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38 #include <sys/queue.h>
40 #include <rte_interrupts.h>
42 #include <rte_debug.h>
44 #include <rte_ether.h>
45 #include <rte_ethdev.h>
47 #include "ixgbe_logs.h"
48 #include "ixgbe/ixgbe_api.h"
49 #include "ixgbe/ixgbe_common.h"
50 #include "ixgbe_ethdev.h"
52 /* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */
53 #define FDIRCTRL_PBALLOC_MASK 0x03
55 /* For calculating memory required for FDIR filters */
56 #define PBALLOC_SIZE_SHIFT 15
58 /* Number of bits used to mask bucket hash for different pballoc sizes */
59 #define PERFECT_BUCKET_64KB_HASH_MASK 0x07FF /* 11 bits */
60 #define PERFECT_BUCKET_128KB_HASH_MASK 0x0FFF /* 12 bits */
61 #define PERFECT_BUCKET_256KB_HASH_MASK 0x1FFF /* 13 bits */
62 #define SIG_BUCKET_64KB_HASH_MASK 0x1FFF /* 13 bits */
63 #define SIG_BUCKET_128KB_HASH_MASK 0x3FFF /* 14 bits */
64 #define SIG_BUCKET_256KB_HASH_MASK 0x7FFF /* 15 bits */
65 #define IXGBE_DEFAULT_FLEXBYTES_OFFSET 12 /* default flexbytes offset in bytes */
66 #define IXGBE_FDIR_MAX_FLEX_LEN 2 /* len in bytes of flexbytes */
67 #define IXGBE_MAX_FLX_SOURCE_OFF 62
68 #define IXGBE_FDIRCTRL_FLEX_MASK (0x1F << IXGBE_FDIRCTRL_FLEX_SHIFT)
69 #define IXGBE_FDIRCMD_CMD_INTERVAL_US 10
71 #define IXGBE_FDIR_FLOW_TYPES ( \
72 (1 << RTE_ETH_FLOW_TYPE_UDPV4) | \
73 (1 << RTE_ETH_FLOW_TYPE_TCPV4) | \
74 (1 << RTE_ETH_FLOW_TYPE_SCTPV4) | \
75 (1 << RTE_ETH_FLOW_TYPE_IPV4_OTHER) | \
76 (1 << RTE_ETH_FLOW_TYPE_UDPV6) | \
77 (1 << RTE_ETH_FLOW_TYPE_TCPV6) | \
78 (1 << RTE_ETH_FLOW_TYPE_SCTPV6) | \
79 (1 << RTE_ETH_FLOW_TYPE_IPV6_OTHER))
81 #define IPV6_ADDR_TO_MASK(ipaddr, ipv6m) do { \
82 uint8_t ipv6_addr[16]; \
84 rte_memcpy(ipv6_addr, (ipaddr), sizeof(ipv6_addr));\
86 for (i = 0; i < sizeof(ipv6_addr); i++) { \
87 if (ipv6_addr[i] == UINT8_MAX) \
89 else if (ipv6_addr[i] != 0) { \
90 PMD_DRV_LOG(ERR, " invalid IPv6 address mask."); \
96 #define IPV6_MASK_TO_ADDR(ipv6m, ipaddr) do { \
97 uint8_t ipv6_addr[16]; \
99 for (i = 0; i < sizeof(ipv6_addr); i++) { \
100 if ((ipv6m) & (1 << i)) \
101 ipv6_addr[i] = UINT8_MAX; \
105 rte_memcpy((ipaddr), ipv6_addr, sizeof(ipv6_addr));\
108 static int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash);
109 static int fdir_set_input_mask_82599(struct rte_eth_dev *dev,
110 const struct rte_eth_fdir_masks *input_mask);
111 static int ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
112 const struct rte_eth_fdir_flex_conf *conf);
113 static int fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl);
114 static int ixgbe_fdir_filter_to_atr_input(
115 const struct rte_eth_fdir_filter *fdir_filter,
116 union ixgbe_atr_input *input);
117 static uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
119 static uint32_t atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
120 enum rte_fdir_pballoc_type pballoc);
121 static uint32_t atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
122 enum rte_fdir_pballoc_type pballoc);
123 static int fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
124 union ixgbe_atr_input *input, uint8_t queue,
125 uint32_t fdircmd, uint32_t fdirhash);
126 static int fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
127 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
129 static int ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
130 const struct rte_eth_fdir_filter *fdir_filter,
134 * This function is based on ixgbe_fdir_enable_82599() in ixgbe/ixgbe_82599.c.
135 * It adds extra configuration of fdirctrl that is common for all filter types.
137 * Initialize Flow Director control registers
138 * @hw: pointer to hardware structure
139 * @fdirctrl: value to write to flow director control register
142 fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl)
146 PMD_INIT_FUNC_TRACE();
148 /* Prime the keys for hashing */
149 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
150 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
153 * Continue setup of fdirctrl register bits:
154 * Set the maximum length per hash bucket to 0xA filters
155 * Send interrupt when 64 filters are left
157 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
158 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
161 * Poll init-done after we write the register. Estimated times:
162 * 10G: PBALLOC = 11b, timing is 60us
163 * 1G: PBALLOC = 11b, timing is 600us
164 * 100M: PBALLOC = 11b, timing is 6ms
166 * Multiple these timings by 4 if under full Rx load
168 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
169 * 1 msec per poll time. If we're at line rate and drop to 100M, then
170 * this might not finish in our poll time, but we can live with that
173 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
174 IXGBE_WRITE_FLUSH(hw);
175 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
176 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
177 IXGBE_FDIRCTRL_INIT_DONE)
182 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
183 PMD_INIT_LOG(ERR, "Flow Director poll time exceeded "
191 * Set appropriate bits in fdirctrl for: variable reporting levels, moving
192 * flexbytes matching field, and drop queue (only for perfect matching mode).
195 configure_fdir_flags(const struct rte_fdir_conf *conf, uint32_t *fdirctrl)
199 switch (conf->pballoc) {
200 case RTE_FDIR_PBALLOC_64K:
201 /* 8k - 1 signature filters */
202 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
204 case RTE_FDIR_PBALLOC_128K:
205 /* 16k - 1 signature filters */
206 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
208 case RTE_FDIR_PBALLOC_256K:
209 /* 32k - 1 signature filters */
210 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
214 PMD_INIT_LOG(ERR, "Invalid fdir_conf->pballoc value");
218 /* status flags: write hash & swindex in the rx descriptor */
219 switch (conf->status) {
220 case RTE_FDIR_NO_REPORT_STATUS:
221 /* do nothing, default mode */
223 case RTE_FDIR_REPORT_STATUS:
224 /* report status when the packet matches a fdir rule */
225 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
227 case RTE_FDIR_REPORT_STATUS_ALWAYS:
228 /* always report status */
229 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS;
233 PMD_INIT_LOG(ERR, "Invalid fdir_conf->status value");
237 *fdirctrl |= (IXGBE_DEFAULT_FLEXBYTES_OFFSET / sizeof(uint16_t)) <<
238 IXGBE_FDIRCTRL_FLEX_SHIFT;
240 if (conf->mode == RTE_FDIR_MODE_PERFECT) {
241 *fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
242 *fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
245 * Continue setup of fdirctrl register bits:
246 * Set the maximum length per hash bucket to 0xA filters
247 * Send interrupt when 64 filters are left
249 *fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
250 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
256 * Reverse the bits in FDIR registers that store 2 x 16 bit masks.
258 * @hi_dword: Bits 31:16 mask to be bit swapped.
259 * @lo_dword: Bits 15:0 mask to be bit swapped.
261 * Flow director uses several registers to store 2 x 16 bit masks with the
262 * bits reversed such as FDIRTCPM, FDIRUDPM. The LS bit of the
263 * mask affects the MS bit/byte of the target. This function reverses the
264 * bits in these masks.
266 static inline uint32_t
267 reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)
269 uint32_t mask = hi_dword << 16;
271 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
272 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
273 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
274 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
278 * This is based on ixgbe_fdir_set_input_mask_82599() in ixgbe/ixgbe_82599.c,
279 * but makes use of the rte_fdir_masks structure to see which bits to set.
282 fdir_set_input_mask_82599(struct rte_eth_dev *dev,
283 const struct rte_eth_fdir_masks *input_mask)
285 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
286 struct ixgbe_hw_fdir_info *info =
287 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
289 * mask VM pool and DIPv6 since there are currently not supported
290 * mask FLEX byte, it will be set in flex_conf
292 uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 | IXGBE_FDIRM_FLEX;
293 uint32_t fdirtcpm; /* TCP source and destination port masks. */
294 uint32_t fdiripv6m; /* IPv6 source and destination masks. */
295 uint16_t dst_ipv6m = 0;
296 uint16_t src_ipv6m = 0;
298 PMD_INIT_FUNC_TRACE();
301 * Program the relevant mask registers. If src/dst_port or src/dst_addr
302 * are zero, then assume a full mask for that field. Also assume that
303 * a VLAN of 0 is unspecified, so mask that out as well. L4type
304 * cannot be masked out in this implementation.
306 if (input_mask->dst_port_mask == 0 && input_mask->src_port_mask == 0)
307 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
308 fdirm |= IXGBE_FDIRM_L4P;
310 if (input_mask->vlan_tci_mask == 0x0FFF)
311 /* mask VLAN Priority */
312 fdirm |= IXGBE_FDIRM_VLANP;
313 else if (input_mask->vlan_tci_mask == 0xE000)
315 fdirm |= IXGBE_FDIRM_VLANID;
316 else if (input_mask->vlan_tci_mask == 0)
317 /* mask VLAN ID and Priority */
318 fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
319 else if (input_mask->vlan_tci_mask != 0xEFFF) {
320 PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
323 info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
325 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
327 /* store the TCP/UDP port masks, bit reversed from port layout */
328 fdirtcpm = reverse_fdir_bitmasks(input_mask->dst_port_mask,
329 input_mask->src_port_mask);
331 /* write both the same so that UDP and TCP use the same mask */
332 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
333 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
334 info->mask.src_port_mask = input_mask->src_port_mask;
335 info->mask.dst_port_mask = input_mask->dst_port_mask;
337 /* Store source and destination IPv4 masks (big-endian) */
338 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, ~(input_mask->ipv4_mask.src_ip));
339 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, ~(input_mask->ipv4_mask.dst_ip));
340 info->mask.src_ipv4_mask = input_mask->ipv4_mask.src_ip;
341 info->mask.dst_ipv4_mask = input_mask->ipv4_mask.dst_ip;
343 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE) {
345 * IPv6 mask is only meaningful in signature mode
346 * Store source and destination IPv6 masks (bit reversed)
348 IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.src_ip, src_ipv6m);
349 IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.dst_ip, dst_ipv6m);
350 fdiripv6m = (dst_ipv6m << 16) | src_ipv6m;
352 IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m);
353 info->mask.src_ipv6_mask = src_ipv6m;
354 info->mask.dst_ipv6_mask = dst_ipv6m;
357 return IXGBE_SUCCESS;
361 * ixgbe_check_fdir_flex_conf -check if the flex payload and mask configuration
362 * arguments are valid
365 ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
366 const struct rte_eth_fdir_flex_conf *conf)
368 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
369 struct ixgbe_hw_fdir_info *info =
370 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
371 const struct rte_eth_flex_payload_cfg *flex_cfg;
372 const struct rte_eth_fdir_flex_mask *flex_mask;
373 uint32_t fdirctrl, fdirm;
374 uint16_t flexbytes = 0;
377 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
378 fdirm = IXGBE_READ_REG(hw, IXGBE_FDIRM);
381 PMD_DRV_LOG(INFO, "NULL pointer.");
385 for (i = 0; i < conf->nb_payloads; i++) {
386 flex_cfg = &conf->flex_set[i];
387 if (flex_cfg->type != RTE_ETH_RAW_PAYLOAD) {
388 PMD_DRV_LOG(ERR, "unsupported payload type.");
391 if (((flex_cfg->src_offset[0] & 0x1) == 0) &&
392 (flex_cfg->src_offset[1] == flex_cfg->src_offset[0] + 1) &&
393 (flex_cfg->src_offset[0] <= IXGBE_MAX_FLX_SOURCE_OFF)) {
394 fdirctrl &= ~IXGBE_FDIRCTRL_FLEX_MASK;
395 fdirctrl |= (flex_cfg->src_offset[0] / sizeof(uint16_t)) <<
396 IXGBE_FDIRCTRL_FLEX_SHIFT;
398 PMD_DRV_LOG(ERR, "invalid flexbytes arguments.");
403 for (i = 0; i < conf->nb_flexmasks; i++) {
404 flex_mask = &conf->flex_mask[i];
405 if (flex_mask->flow_type != RTE_ETH_FLOW_TYPE_RAW) {
406 PMD_DRV_LOG(ERR, "unsupported flow type.");
409 flexbytes = (uint16_t)(((flex_mask->mask[0] << 8) & 0xFF00) |
410 ((flex_mask->mask[1]) & 0xFF));
411 if (flexbytes == UINT16_MAX)
412 fdirm &= ~IXGBE_FDIRM_FLEX;
413 else if (flexbytes != 0) {
414 /* IXGBE_FDIRM_FLEX is set by default when set mask */
415 PMD_DRV_LOG(ERR, " invalid flexbytes mask arguments.");
419 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
420 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
421 info->mask.flex_bytes_mask = flexbytes ? UINT16_MAX : 0;
422 info->flex_bytes_offset = (uint8_t)((fdirctrl &
423 IXGBE_FDIRCTRL_FLEX_MASK) >>
424 IXGBE_FDIRCTRL_FLEX_SHIFT);
429 ixgbe_fdir_configure(struct rte_eth_dev *dev)
431 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
433 uint32_t fdirctrl, pbsize;
436 PMD_INIT_FUNC_TRACE();
438 if (hw->mac.type != ixgbe_mac_82599EB &&
439 hw->mac.type != ixgbe_mac_X540 &&
440 hw->mac.type != ixgbe_mac_X550 &&
441 hw->mac.type != ixgbe_mac_X550EM_x)
444 err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
449 * Before enabling Flow Director, the Rx Packet Buffer size
450 * must be reduced. The new value is the current size minus
451 * flow director memory usage size.
453 pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
454 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
455 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
458 * The defaults in the HW for RX PB 1-7 are not zero and so should be
459 * intialized to zero for non DCB mode otherwise actual total RX PB
460 * would be bigger than programmed and filter space would run into
463 for (i = 1; i < 8; i++)
464 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
466 err = fdir_set_input_mask_82599(dev, &dev->data->dev_conf.fdir_conf.mask);
468 PMD_INIT_LOG(ERR, " Error on setting FD mask");
471 err = ixgbe_set_fdir_flex_conf(dev,
472 &dev->data->dev_conf.fdir_conf.flex_conf);
474 PMD_INIT_LOG(ERR, " Error on setting FD flexible arguments.");
478 err = fdir_enable_82599(hw, fdirctrl);
480 PMD_INIT_LOG(ERR, " Error on enabling FD.");
487 * Convert DPDK rte_eth_fdir_filter struct to ixgbe_atr_input union that is used
488 * by the IXGBE driver code.
491 ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,
492 union ixgbe_atr_input *input)
494 input->formatted.vlan_id = fdir_filter->input.flow_ext.vlan_tci;
495 input->formatted.flex_bytes = (uint16_t)(
496 (fdir_filter->input.flow_ext.flexbytes[1] << 8 & 0xFF00) |
497 (fdir_filter->input.flow_ext.flexbytes[0] & 0xFF));
499 switch (fdir_filter->input.flow_type) {
500 case RTE_ETH_FLOW_TYPE_UDPV4:
501 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
503 case RTE_ETH_FLOW_TYPE_TCPV4:
504 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
506 case RTE_ETH_FLOW_TYPE_SCTPV4:
507 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
509 case RTE_ETH_FLOW_TYPE_IPV4_OTHER:
510 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
512 case RTE_ETH_FLOW_TYPE_UDPV6:
513 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV6;
515 case RTE_ETH_FLOW_TYPE_TCPV6:
516 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
518 case RTE_ETH_FLOW_TYPE_SCTPV6:
519 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV6;
521 case RTE_ETH_FLOW_TYPE_IPV6_OTHER:
522 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV6;
525 PMD_DRV_LOG(ERR, " Error on flow_type input");
529 switch (fdir_filter->input.flow_type) {
530 case RTE_ETH_FLOW_TYPE_UDPV4:
531 case RTE_ETH_FLOW_TYPE_TCPV4:
532 input->formatted.src_port =
533 fdir_filter->input.flow.udp4_flow.src_port;
534 input->formatted.dst_port =
535 fdir_filter->input.flow.udp4_flow.dst_port;
536 /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
537 case RTE_ETH_FLOW_TYPE_SCTPV4:
538 case RTE_ETH_FLOW_TYPE_IPV4_OTHER:
539 input->formatted.src_ip[0] =
540 fdir_filter->input.flow.ip4_flow.src_ip;
541 input->formatted.dst_ip[0] =
542 fdir_filter->input.flow.ip4_flow.dst_ip;
545 case RTE_ETH_FLOW_TYPE_UDPV6:
546 case RTE_ETH_FLOW_TYPE_TCPV6:
547 input->formatted.src_port =
548 fdir_filter->input.flow.udp6_flow.src_port;
549 input->formatted.dst_port =
550 fdir_filter->input.flow.udp6_flow.dst_port;
551 /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
552 case RTE_ETH_FLOW_TYPE_SCTPV6:
553 case RTE_ETH_FLOW_TYPE_IPV6_OTHER:
554 rte_memcpy(input->formatted.src_ip,
555 fdir_filter->input.flow.ipv6_flow.src_ip,
556 sizeof(input->formatted.src_ip));
557 rte_memcpy(input->formatted.dst_ip,
558 fdir_filter->input.flow.ipv6_flow.dst_ip,
559 sizeof(input->formatted.dst_ip));
562 PMD_DRV_LOG(ERR, " Error on flow_type input");
570 * The below function is taken from the FreeBSD IXGBE drivers release
571 * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK
572 * before returning, as the signature hash can use 16bits.
574 * The newer driver has optimised functions for calculating bucket and
575 * signature hashes. However they don't support IPv6 type packets for signature
576 * filters so are not used here.
578 * Note that the bkt_hash field in the ixgbe_atr_input structure is also never
581 * Compute the hashes for SW ATR
582 * @stream: input bitstream to compute the hash on
583 * @key: 32-bit hash key
586 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
590 * The algorithm is as follows:
591 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
592 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
593 * and A[n] x B[n] is bitwise AND between same length strings
595 * K[n] is 16 bits, defined as:
596 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
597 * for n modulo 32 < 15, K[n] =
598 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
600 * S[n] is 16 bits, defined as:
601 * for n >= 15, S[n] = S[n:n - 15]
602 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
604 * To simplify for programming, the algorithm is implemented
605 * in software this way:
607 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
609 * for (i = 0; i < 352; i+=32)
610 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
612 * lo_hash_dword[15:0] ^= Stream[15:0];
613 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
614 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
616 * hi_hash_dword[31:0] ^= Stream[351:320];
619 * hash[15:0] ^= Stream[15:0];
621 * for (i = 0; i < 16; i++) {
623 * hash[15:0] ^= lo_hash_dword[(i+15):i];
625 * hash[15:0] ^= hi_hash_dword[(i+15):i];
629 __be32 common_hash_dword = 0;
630 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
634 /* record the flow_vm_vlan bits as they are a key part to the hash */
635 flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
637 /* generate common hash dword */
638 for (i = 1; i <= 13; i++)
639 common_hash_dword ^= atr_input->dword_stream[i];
641 hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
643 /* low dword is word swapped version of common */
644 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
646 /* apply flow ID/VM pool/VLAN ID bits to hash words */
647 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
649 /* Process bits 0 and 16 */
650 if (key & 0x0001) hash_result ^= lo_hash_dword;
651 if (key & 0x00010000) hash_result ^= hi_hash_dword;
654 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
655 * delay this because bit 0 of the stream should not be processed
656 * so we do not add the vlan until after bit 0 was processed
658 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
661 /* process the remaining 30 bits in the key 2 bits at a time */
662 for (i = 15; i; i-- ) {
663 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
664 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
671 atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
672 enum rte_fdir_pballoc_type pballoc)
674 if (pballoc == RTE_FDIR_PBALLOC_256K)
675 return ixgbe_atr_compute_hash_82599(input,
676 IXGBE_ATR_BUCKET_HASH_KEY) &
677 PERFECT_BUCKET_256KB_HASH_MASK;
678 else if (pballoc == RTE_FDIR_PBALLOC_128K)
679 return ixgbe_atr_compute_hash_82599(input,
680 IXGBE_ATR_BUCKET_HASH_KEY) &
681 PERFECT_BUCKET_128KB_HASH_MASK;
683 return ixgbe_atr_compute_hash_82599(input,
684 IXGBE_ATR_BUCKET_HASH_KEY) &
685 PERFECT_BUCKET_64KB_HASH_MASK;
689 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
690 * @hw: pointer to hardware structure
693 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, uint32_t *fdircmd)
697 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
698 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
699 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
701 rte_delay_us(IXGBE_FDIRCMD_CMD_INTERVAL_US);
708 * Calculate the hash value needed for signature-match filters. In the FreeBSD
709 * driver, this is done by the optimised function
710 * ixgbe_atr_compute_sig_hash_82599(). However that can't be used here as it
711 * doesn't support calculating a hash for an IPv6 filter.
714 atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
715 enum rte_fdir_pballoc_type pballoc)
717 uint32_t bucket_hash, sig_hash;
719 if (pballoc == RTE_FDIR_PBALLOC_256K)
720 bucket_hash = ixgbe_atr_compute_hash_82599(input,
721 IXGBE_ATR_BUCKET_HASH_KEY) &
722 SIG_BUCKET_256KB_HASH_MASK;
723 else if (pballoc == RTE_FDIR_PBALLOC_128K)
724 bucket_hash = ixgbe_atr_compute_hash_82599(input,
725 IXGBE_ATR_BUCKET_HASH_KEY) &
726 SIG_BUCKET_128KB_HASH_MASK;
728 bucket_hash = ixgbe_atr_compute_hash_82599(input,
729 IXGBE_ATR_BUCKET_HASH_KEY) &
730 SIG_BUCKET_64KB_HASH_MASK;
732 sig_hash = ixgbe_atr_compute_hash_82599(input,
733 IXGBE_ATR_SIGNATURE_HASH_KEY);
735 return (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash;
739 * This is based on ixgbe_fdir_write_perfect_filter_82599() in
740 * ixgbe/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register
741 * added, and IPv6 support also added. The hash value is also pre-calculated
742 * as the pballoc value is needed to do it.
745 fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
746 union ixgbe_atr_input *input, uint8_t queue,
747 uint32_t fdircmd, uint32_t fdirhash)
749 uint32_t fdirport, fdirvlan;
752 /* record the IPv4 address (big-endian) */
753 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
754 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
756 /* record source and destination port (little-endian)*/
757 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
758 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
759 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
760 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
762 /* record vlan (little-endian) and flex_bytes(big-endian) */
763 fdirvlan = input->formatted.flex_bytes;
764 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
765 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
766 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
768 /* configure FDIRHASH register */
769 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
772 * flush all previous writes to make certain registers are
773 * programmed prior to issuing the command
775 IXGBE_WRITE_FLUSH(hw);
777 /* configure FDIRCMD register */
778 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
779 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
780 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
781 fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
782 fdircmd |= (uint32_t)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
784 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
786 PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
788 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
790 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
796 * This function is based on ixgbe_atr_add_signature_filter_82599() in
797 * ixgbe/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports
798 * setting extra fields in the FDIRCMD register, and removes the code that was
799 * verifying the flow_type field. According to the documentation, a flow type of
800 * 00 (i.e. not TCP, UDP, or SCTP) is not supported, however it appears to
803 * Adds a signature hash filter
804 * @hw: pointer to hardware structure
805 * @input: unique input dword
806 * @queue: queue index to direct traffic to
807 * @fdircmd: any extra flags to set in fdircmd register
808 * @fdirhash: pre-calculated hash value for the filter
811 fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
812 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
817 PMD_INIT_FUNC_TRACE();
819 /* configure FDIRCMD register */
820 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
821 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
822 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
823 fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
825 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
826 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
828 PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
830 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
832 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
838 * This is based on ixgbe_fdir_erase_perfect_filter_82599() in
839 * ixgbe/ixgbe_82599.c. It is modified to take in the hash as a parameter so
840 * that it can be used for removing signature and perfect filters.
843 fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash)
845 uint32_t fdircmd = 0;
848 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
850 /* flush hash to HW */
851 IXGBE_WRITE_FLUSH(hw);
853 /* Query if filter is present */
854 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
856 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
858 PMD_INIT_LOG(ERR, "Timeout querying for flow director filter.");
862 /* if filter exists in hardware then remove it */
863 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
864 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
865 IXGBE_WRITE_FLUSH(hw);
866 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
867 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
869 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
871 PMD_INIT_LOG(ERR, "Timeout erasing flow director filter.");
877 * ixgbe_add_del_fdir_filter - add or remove a flow diretor filter.
878 * @dev: pointer to the structure rte_eth_dev
879 * @fdir_filter: fdir filter entry
880 * @del: 1 - delete, 0 - add
881 * @update: 1 - update
884 ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
885 const struct rte_eth_fdir_filter *fdir_filter,
889 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
890 uint32_t fdircmd_flags;
892 union ixgbe_atr_input input;
894 bool is_perfect = FALSE;
897 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_NONE)
900 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
903 memset(&input, 0, sizeof(input));
905 err = ixgbe_fdir_filter_to_atr_input(fdir_filter, &input);
910 if (input.formatted.flow_type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
911 PMD_DRV_LOG(ERR, "IPv6 is not supported in"
915 fdirhash = atr_compute_perfect_hash_82599(&input,
916 dev->data->dev_conf.fdir_conf.pballoc);
917 fdirhash |= fdir_filter->soft_id <<
918 IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
920 fdirhash = atr_compute_sig_hash_82599(&input,
921 dev->data->dev_conf.fdir_conf.pballoc);
924 err = fdir_erase_filter_82599(hw, fdirhash);
926 PMD_DRV_LOG(ERR, "Fail to delete FDIR filter!");
928 PMD_DRV_LOG(DEBUG, "Success to delete FDIR filter!");
931 /* add or update an fdir filter*/
932 fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
933 if (fdir_filter->action.behavior == RTE_ETH_FDIR_REJECT) {
935 queue = dev->data->dev_conf.fdir_conf.drop_queue;
936 fdircmd_flags |= IXGBE_FDIRCMD_DROP;
938 PMD_DRV_LOG(ERR, "Drop option is not supported in"
942 } else if (fdir_filter->action.rx_queue < IXGBE_MAX_RX_QUEUE_NUM)
943 queue = (uint8_t)fdir_filter->action.rx_queue;
948 err = fdir_write_perfect_filter_82599(hw, &input, queue,
949 fdircmd_flags, fdirhash);
951 err = fdir_add_signature_filter_82599(hw, &input, queue,
952 fdircmd_flags, fdirhash);
955 PMD_DRV_LOG(ERR, "Fail to add FDIR filter!");
957 PMD_DRV_LOG(DEBUG, "Success to add FDIR filter");
963 ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir *fdir)
965 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
966 struct ixgbe_hw_fdir_info *info =
967 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
970 if (hw->mac.type != ixgbe_mac_82599EB &&
971 hw->mac.type != ixgbe_mac_X540 &&
972 hw->mac.type != ixgbe_mac_X550 &&
973 hw->mac.type != ixgbe_mac_X550EM_x)
976 /* Get the information from registers */
977 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE);
978 info->collision = (uint16_t)((reg & IXGBE_FDIRFREE_COLL_MASK) >>
979 IXGBE_FDIRFREE_COLL_SHIFT);
980 info->free = (uint16_t)((reg & IXGBE_FDIRFREE_FREE_MASK) >>
981 IXGBE_FDIRFREE_FREE_SHIFT);
983 reg = IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
984 info->maxhash = (uint16_t)((reg & IXGBE_FDIRLEN_MAXHASH_MASK) >>
985 IXGBE_FDIRLEN_MAXHASH_SHIFT);
986 info->maxlen = (uint8_t)((reg & IXGBE_FDIRLEN_MAXLEN_MASK) >>
987 IXGBE_FDIRLEN_MAXLEN_SHIFT);
989 reg = IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
990 info->remove += (reg & IXGBE_FDIRUSTAT_REMOVE_MASK) >>
991 IXGBE_FDIRUSTAT_REMOVE_SHIFT;
992 info->add += (reg & IXGBE_FDIRUSTAT_ADD_MASK) >>
993 IXGBE_FDIRUSTAT_ADD_SHIFT;
995 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT) & 0xFFFF;
996 info->f_remove += (reg & IXGBE_FDIRFSTAT_FREMOVE_MASK) >>
997 IXGBE_FDIRFSTAT_FREMOVE_SHIFT;
998 info->f_add += (reg & IXGBE_FDIRFSTAT_FADD_MASK) >>
999 IXGBE_FDIRFSTAT_FADD_SHIFT;
1001 /* Copy the new information in the fdir parameter */
1002 fdir->collision = info->collision;
1003 fdir->free = info->free;
1004 fdir->maxhash = info->maxhash;
1005 fdir->maxlen = info->maxlen;
1006 fdir->remove = info->remove;
1007 fdir->add = info->add;
1008 fdir->f_remove = info->f_remove;
1009 fdir->f_add = info->f_add;
1013 * ixgbe_fdir_ctrl_func - deal with all operations on flow director.
1014 * @dev: pointer to the structure rte_eth_dev
1015 * @filter_op:operation will be taken
1016 * @arg: a pointer to specific structure corresponding to the filter_op
1019 ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
1020 enum rte_filter_op filter_op, void *arg)
1022 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1025 if (hw->mac.type != ixgbe_mac_82599EB &&
1026 hw->mac.type != ixgbe_mac_X540 &&
1027 hw->mac.type != ixgbe_mac_X550 &&
1028 hw->mac.type != ixgbe_mac_X550EM_x)
1031 if (filter_op == RTE_ETH_FILTER_NOP)
1034 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1037 switch (filter_op) {
1038 case RTE_ETH_FILTER_ADD:
1039 ret = ixgbe_add_del_fdir_filter(dev,
1040 (struct rte_eth_fdir_filter *)arg, FALSE, FALSE);
1042 case RTE_ETH_FILTER_UPDATE:
1043 ret = ixgbe_add_del_fdir_filter(dev,
1044 (struct rte_eth_fdir_filter *)arg, FALSE, TRUE);
1046 case RTE_ETH_FILTER_DELETE:
1047 ret = ixgbe_add_del_fdir_filter(dev,
1048 (struct rte_eth_fdir_filter *)arg, TRUE, FALSE);
1051 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);