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38 #include <sys/queue.h>
40 #include <rte_interrupts.h>
42 #include <rte_debug.h>
44 #include <rte_ether.h>
45 #include <rte_ethdev.h>
47 #include "ixgbe_logs.h"
48 #include "ixgbe/ixgbe_api.h"
49 #include "ixgbe/ixgbe_common.h"
50 #include "ixgbe_ethdev.h"
52 /* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */
53 #define FDIRCTRL_PBALLOC_MASK 0x03
55 /* For calculating memory required for FDIR filters */
56 #define PBALLOC_SIZE_SHIFT 15
58 /* Number of bits used to mask bucket hash for different pballoc sizes */
59 #define PERFECT_BUCKET_64KB_HASH_MASK 0x07FF /* 11 bits */
60 #define PERFECT_BUCKET_128KB_HASH_MASK 0x0FFF /* 12 bits */
61 #define PERFECT_BUCKET_256KB_HASH_MASK 0x1FFF /* 13 bits */
62 #define SIG_BUCKET_64KB_HASH_MASK 0x1FFF /* 13 bits */
63 #define SIG_BUCKET_128KB_HASH_MASK 0x3FFF /* 14 bits */
64 #define SIG_BUCKET_256KB_HASH_MASK 0x7FFF /* 15 bits */
67 * This function is based on ixgbe_fdir_enable_82599() in ixgbe/ixgbe_82599.c.
68 * It adds extra configuration of fdirctrl that is common for all filter types.
70 * Initialize Flow Director control registers
71 * @hw: pointer to hardware structure
72 * @fdirctrl: value to write to flow director control register
74 static void fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
78 PMD_INIT_FUNC_TRACE();
80 /* Prime the keys for hashing */
81 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
82 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
85 * Continue setup of fdirctrl register bits:
86 * Set the maximum length per hash bucket to 0xA filters
87 * Send interrupt when 64 filters are left
89 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
90 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
93 * Poll init-done after we write the register. Estimated times:
94 * 10G: PBALLOC = 11b, timing is 60us
95 * 1G: PBALLOC = 11b, timing is 600us
96 * 100M: PBALLOC = 11b, timing is 6ms
98 * Multiple these timings by 4 if under full Rx load
100 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
101 * 1 msec per poll time. If we're at line rate and drop to 100M, then
102 * this might not finish in our poll time, but we can live with that
105 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
106 IXGBE_WRITE_FLUSH(hw);
107 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
108 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
109 IXGBE_FDIRCTRL_INIT_DONE)
114 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
115 PMD_INIT_LOG(WARNING, "Flow Director poll time exceeded!\n");
119 * Set appropriate bits in fdirctrl for: variable reporting levels, moving
120 * flexbytes matching field, and drop queue (only for perfect matching mode).
123 configure_fdir_flags(struct rte_fdir_conf *conf, uint32_t *fdirctrl)
127 switch (conf->pballoc) {
128 case RTE_FDIR_PBALLOC_64K:
129 /* 8k - 1 signature filters */
130 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
132 case RTE_FDIR_PBALLOC_128K:
133 /* 16k - 1 signature filters */
134 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
136 case RTE_FDIR_PBALLOC_256K:
137 /* 32k - 1 signature filters */
138 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
142 PMD_INIT_LOG(ERR, "Invalid fdir_conf->pballoc value");
146 /* status flags: write hash & swindex in the rx descriptor */
147 switch (conf->status) {
148 case RTE_FDIR_NO_REPORT_STATUS:
149 /* do nothing, default mode */
151 case RTE_FDIR_REPORT_STATUS:
152 /* report status when the packet matches a fdir rule */
153 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
155 case RTE_FDIR_REPORT_STATUS_ALWAYS:
156 /* always report status */
157 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS;
161 PMD_INIT_LOG(ERR, "Invalid fdir_conf->status value");
165 *fdirctrl |= (conf->flexbytes_offset << IXGBE_FDIRCTRL_FLEX_SHIFT);
167 if (conf->mode == RTE_FDIR_MODE_PERFECT) {
168 *fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
169 *fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
176 ixgbe_fdir_configure(struct rte_eth_dev *dev)
178 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
180 uint32_t fdirctrl, pbsize;
183 PMD_INIT_FUNC_TRACE();
185 if (hw->mac.type != ixgbe_mac_82599EB && hw->mac.type !=ixgbe_mac_X540)
188 err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
193 * Before enabling Flow Director, the Rx Packet Buffer size
194 * must be reduced. The new value is the current size minus
195 * flow director memory usage size.
197 pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
198 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
199 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
202 * The defaults in the HW for RX PB 1-7 are not zero and so should be
203 * intialized to zero for non DCB mode otherwise actual total RX PB
204 * would be bigger than programmed and filter space would run into
207 for (i = 1; i < 8; i++)
208 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
210 fdir_enable_82599(hw, fdirctrl);
215 * The below function is taken from the FreeBSD IXGBE drivers release
216 * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK
217 * before returning, as the signature hash can use 16bits.
219 * The newer driver has optimised functions for calculating bucket and
220 * signature hashes. However they don't support IPv6 type packets for signature
221 * filters so are not used here.
223 * Note that the bkt_hash field in the ixgbe_atr_input structure is also never
226 * Compute the hashes for SW ATR
227 * @stream: input bitstream to compute the hash on
228 * @key: 32-bit hash key
231 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
235 * The algorithm is as follows:
236 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
237 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
238 * and A[n] x B[n] is bitwise AND between same length strings
240 * K[n] is 16 bits, defined as:
241 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
242 * for n modulo 32 < 15, K[n] =
243 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
245 * S[n] is 16 bits, defined as:
246 * for n >= 15, S[n] = S[n:n - 15]
247 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
249 * To simplify for programming, the algorithm is implemented
250 * in software this way:
252 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
254 * for (i = 0; i < 352; i+=32)
255 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
257 * lo_hash_dword[15:0] ^= Stream[15:0];
258 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
259 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
261 * hi_hash_dword[31:0] ^= Stream[351:320];
264 * hash[15:0] ^= Stream[15:0];
266 * for (i = 0; i < 16; i++) {
268 * hash[15:0] ^= lo_hash_dword[(i+15):i];
270 * hash[15:0] ^= hi_hash_dword[(i+15):i];
274 __be32 common_hash_dword = 0;
275 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
279 /* record the flow_vm_vlan bits as they are a key part to the hash */
280 flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
282 /* generate common hash dword */
283 for (i = 1; i <= 13; i++)
284 common_hash_dword ^= atr_input->dword_stream[i];
286 hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
288 /* low dword is word swapped version of common */
289 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
291 /* apply flow ID/VM pool/VLAN ID bits to hash words */
292 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
294 /* Process bits 0 and 16 */
295 if (key & 0x0001) hash_result ^= lo_hash_dword;
296 if (key & 0x00010000) hash_result ^= hi_hash_dword;
299 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
300 * delay this because bit 0 of the stream should not be processed
301 * so we do not add the vlan until after bit 0 was processed
303 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
306 /* process the remaining 30 bits in the key 2 bits at a time */
307 for (i = 15; i; i-- ) {
308 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
309 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
316 * Calculate the hash value needed for signature-match filters. In the FreeBSD
317 * driver, this is done by the optimised function
318 * ixgbe_atr_compute_sig_hash_82599(). However that can't be used here as it
319 * doesn't support calculating a hash for an IPv6 filter.
322 atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
323 enum rte_fdir_pballoc_type pballoc)
325 uint32_t bucket_hash, sig_hash;
327 if (pballoc == RTE_FDIR_PBALLOC_256K)
328 bucket_hash = ixgbe_atr_compute_hash_82599(input,
329 IXGBE_ATR_BUCKET_HASH_KEY) &
330 SIG_BUCKET_256KB_HASH_MASK;
331 else if (pballoc == RTE_FDIR_PBALLOC_128K)
332 bucket_hash = ixgbe_atr_compute_hash_82599(input,
333 IXGBE_ATR_BUCKET_HASH_KEY) &
334 SIG_BUCKET_128KB_HASH_MASK;
336 bucket_hash = ixgbe_atr_compute_hash_82599(input,
337 IXGBE_ATR_BUCKET_HASH_KEY) &
338 SIG_BUCKET_64KB_HASH_MASK;
340 sig_hash = ixgbe_atr_compute_hash_82599(input,
341 IXGBE_ATR_SIGNATURE_HASH_KEY);
343 return (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash;
347 * This function is based on ixgbe_atr_add_signature_filter_82599() in
348 * ixgbe/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports
349 * setting extra fields in the FDIRCMD register, and removes the code that was
350 * verifying the flow_type field. According to the documentation, a flow type of
351 * 00 (i.e. not TCP, UDP, or SCTP) is not supported, however it appears to
354 * Adds a signature hash filter
355 * @hw: pointer to hardware structure
356 * @input: unique input dword
357 * @queue: queue index to direct traffic to
358 * @fdircmd: any extra flags to set in fdircmd register
359 * @fdirhash: pre-calculated hash value for the filter
362 fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
363 union ixgbe_atr_input *input, u8 queue, u32 fdircmd,
368 PMD_INIT_FUNC_TRACE();
370 /* configure FDIRCMD register */
371 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
372 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
373 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
374 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
377 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
378 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
380 fdirhashcmd = (u64)fdircmd << 32;
381 fdirhashcmd |= fdirhash;
382 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
384 PMD_INIT_LOG(DEBUG, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
388 * Convert DPDK rte_fdir_filter struct to ixgbe_atr_input union that is used
389 * by the IXGBE driver code.
392 fdir_filter_to_atr_input(struct rte_fdir_filter *fdir_filter,
393 union ixgbe_atr_input *input)
395 if ((fdir_filter->l4type == RTE_FDIR_L4TYPE_SCTP ||
396 fdir_filter->l4type == RTE_FDIR_L4TYPE_NONE) &&
397 (fdir_filter->port_src || fdir_filter->port_dst)) {
398 PMD_INIT_LOG(ERR, "Invalid fdir_filter");
402 memset(input, 0, sizeof(*input));
404 input->formatted.vlan_id = fdir_filter->vlan_id;
405 input->formatted.src_port = fdir_filter->port_src;
406 input->formatted.dst_port = fdir_filter->port_dst;
407 input->formatted.flex_bytes = fdir_filter->flex_bytes;
409 switch (fdir_filter->l4type) {
410 case RTE_FDIR_L4TYPE_TCP:
411 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
413 case RTE_FDIR_L4TYPE_UDP:
414 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
416 case RTE_FDIR_L4TYPE_SCTP:
417 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
419 case RTE_FDIR_L4TYPE_NONE:
420 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
423 PMD_INIT_LOG(ERR, " Error on l4type input");
427 if (fdir_filter->iptype == RTE_FDIR_IPTYPE_IPV6) {
428 input->formatted.flow_type |= IXGBE_ATR_L4TYPE_IPV6_MASK;
430 input->formatted.src_ip[0] = fdir_filter->ip_src.ipv6_addr[0];
431 input->formatted.src_ip[1] = fdir_filter->ip_src.ipv6_addr[1];
432 input->formatted.src_ip[2] = fdir_filter->ip_src.ipv6_addr[2];
433 input->formatted.src_ip[3] = fdir_filter->ip_src.ipv6_addr[3];
435 input->formatted.dst_ip[0] = fdir_filter->ip_dst.ipv6_addr[0];
436 input->formatted.dst_ip[1] = fdir_filter->ip_dst.ipv6_addr[1];
437 input->formatted.dst_ip[2] = fdir_filter->ip_dst.ipv6_addr[2];
438 input->formatted.dst_ip[3] = fdir_filter->ip_dst.ipv6_addr[3];
441 input->formatted.src_ip[0] = fdir_filter->ip_src.ipv4_addr;
442 input->formatted.dst_ip[0] = fdir_filter->ip_dst.ipv4_addr;
449 * Adds or updates a signature filter.
451 * dev: ethernet device to add filter to
452 * fdir_filter: filter details
453 * queue: queue index to direct traffic to
454 * update: 0 to add a new filter, otherwise update existing.
457 fdir_add_update_signature_filter(struct rte_eth_dev *dev,
458 struct rte_fdir_filter *fdir_filter, uint8_t queue, int update)
460 struct ixgbe_hw *hw= IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
461 uint32_t fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
463 union ixgbe_atr_input input;
466 if (hw->mac.type != ixgbe_mac_82599EB && hw->mac.type !=ixgbe_mac_X540)
469 err = fdir_filter_to_atr_input(fdir_filter, &input);
473 fdirhash = atr_compute_sig_hash_82599(&input,
474 dev->data->dev_conf.fdir_conf.pballoc);
475 fdir_add_signature_filter_82599(hw, &input, queue, fdircmd_flags,
481 ixgbe_fdir_add_signature_filter(struct rte_eth_dev *dev,
482 struct rte_fdir_filter *fdir_filter, uint8_t queue)
484 PMD_INIT_FUNC_TRACE();
485 return fdir_add_update_signature_filter(dev, fdir_filter, queue, 0);
489 ixgbe_fdir_update_signature_filter(struct rte_eth_dev *dev,
490 struct rte_fdir_filter *fdir_filter, uint8_t queue)
492 PMD_INIT_FUNC_TRACE();
493 return fdir_add_update_signature_filter(dev, fdir_filter, queue, 1);
497 * This is based on ixgbe_fdir_erase_perfect_filter_82599() in
498 * ixgbe/ixgbe_82599.c. It is modified to take in the hash as a parameter so
499 * that it can be used for removing signature and perfect filters.
502 fdir_erase_filter_82599(struct ixgbe_hw *hw,
503 __rte_unused union ixgbe_atr_input *input, uint32_t fdirhash)
509 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
511 /* flush hash to HW */
512 IXGBE_WRITE_FLUSH(hw);
514 /* Query if filter is present */
515 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
517 for (retry_count = 10; retry_count; retry_count--) {
518 /* allow 10us for query to process */
520 /* verify query completed successfully */
521 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
522 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
527 PMD_INIT_LOG(ERR, "Timeout querying for flow director filter");
531 /* if filter exists in hardware then remove it */
532 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
533 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
534 IXGBE_WRITE_FLUSH(hw);
535 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
536 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
543 ixgbe_fdir_remove_signature_filter(struct rte_eth_dev *dev,
544 struct rte_fdir_filter *fdir_filter)
546 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
547 union ixgbe_atr_input input;
550 PMD_INIT_FUNC_TRACE();
552 if (hw->mac.type != ixgbe_mac_82599EB && hw->mac.type !=ixgbe_mac_X540)
555 err = fdir_filter_to_atr_input(fdir_filter, &input);
559 return fdir_erase_filter_82599(hw, &input,
560 atr_compute_sig_hash_82599(&input,
561 dev->data->dev_conf.fdir_conf.pballoc));
565 * Reverse the bits in FDIR registers that store 2 x 16 bit masks.
567 * @hi_dword: Bits 31:16 mask to be bit swapped.
568 * @lo_dword: Bits 15:0 mask to be bit swapped.
570 * Flow director uses several registers to store 2 x 16 bit masks with the
571 * bits reversed such as FDIRTCPM, FDIRUDPM and FDIRIP6M. The LS bit of the
572 * mask affects the MS bit/byte of the target. This function reverses the
573 * bits in these masks.
576 reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)
578 u32 mask = hi_dword << 16;
580 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
581 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
582 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
583 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
587 * This macro exists in ixgbe/ixgbe_82599.c, however in that file it reverses
588 * the bytes, and then reverses them again. So here it does nothing.
590 #define IXGBE_WRITE_REG_BE32 IXGBE_WRITE_REG
593 * This is based on ixgbe_fdir_set_input_mask_82599() in ixgbe/ixgbe_82599.c,
594 * but makes use of the rte_fdir_masks structure to see which bits to set.
597 fdir_set_input_mask_82599(struct ixgbe_hw *hw,
598 struct rte_fdir_masks *input_mask)
600 /* mask VM pool since it is currently not supported */
601 u32 fdirm = IXGBE_FDIRM_POOL;
602 u32 fdirtcpm; /* TCP source and destination port masks. */
603 u32 fdiripv6m; /* IPv6 source and destination masks. */
605 PMD_INIT_FUNC_TRACE();
608 * Program the relevant mask registers. If src/dst_port or src/dst_addr
609 * are zero, then assume a full mask for that field. Also assume that
610 * a VLAN of 0 is unspecified, so mask that out as well. L4type
611 * cannot be masked out in this implementation.
613 if (input_mask->only_ip_flow) {
614 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
615 fdirm |= IXGBE_FDIRM_L4P;
616 if (input_mask->dst_port_mask || input_mask->src_port_mask) {
617 PMD_INIT_LOG(ERR, " Error on src/dst port mask\n");
622 if (!input_mask->comp_ipv6_dst)
624 fdirm |= IXGBE_FDIRM_DIPv6;
626 if (!input_mask->vlan_id)
628 fdirm |= IXGBE_FDIRM_VLANID;
630 if (!input_mask->vlan_prio)
631 /* mask VLAN priority */
632 fdirm |= IXGBE_FDIRM_VLANP;
634 if (!input_mask->flexbytes)
635 /* Mask Flex Bytes */
636 fdirm |= IXGBE_FDIRM_FLEX;
638 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
640 /* store the TCP/UDP port masks, bit reversed from port layout */
641 fdirtcpm = reverse_fdir_bitmasks(input_mask->dst_port_mask,
642 input_mask->src_port_mask);
644 /* write both the same so that UDP and TCP use the same mask */
645 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
646 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
648 if (!input_mask->set_ipv6_mask) {
649 /* Store source and destination IPv4 masks (big-endian) */
650 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
651 IXGBE_NTOHL(~input_mask->src_ipv4_mask));
652 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
653 IXGBE_NTOHL(~input_mask->dst_ipv4_mask));
656 /* Store source and destination IPv6 masks (bit reversed) */
657 fdiripv6m = reverse_fdir_bitmasks(input_mask->dst_ipv6_mask,
658 input_mask->src_ipv6_mask);
660 IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m);
663 return IXGBE_SUCCESS;
667 ixgbe_fdir_set_masks(struct rte_eth_dev *dev, struct rte_fdir_masks *fdir_masks)
672 PMD_INIT_FUNC_TRACE();
674 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
676 if (hw->mac.type != ixgbe_mac_82599EB && hw->mac.type !=ixgbe_mac_X540)
679 err = ixgbe_reinit_fdir_tables_82599(hw);
681 PMD_INIT_LOG(ERR, "reinit of fdir tables failed");
685 return fdir_set_input_mask_82599(hw, fdir_masks);
689 atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
690 enum rte_fdir_pballoc_type pballoc)
692 if (pballoc == RTE_FDIR_PBALLOC_256K)
693 return ixgbe_atr_compute_hash_82599(input,
694 IXGBE_ATR_BUCKET_HASH_KEY) &
695 PERFECT_BUCKET_256KB_HASH_MASK;
696 else if (pballoc == RTE_FDIR_PBALLOC_128K)
697 return ixgbe_atr_compute_hash_82599(input,
698 IXGBE_ATR_BUCKET_HASH_KEY) &
699 PERFECT_BUCKET_128KB_HASH_MASK;
701 return ixgbe_atr_compute_hash_82599(input,
702 IXGBE_ATR_BUCKET_HASH_KEY) &
703 PERFECT_BUCKET_64KB_HASH_MASK;
707 * This is based on ixgbe_fdir_write_perfect_filter_82599() in
708 * ixgbe/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register
709 * added, and IPv6 support also added. The hash value is also pre-calculated
710 * as the pballoc value is needed to do it.
713 fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, union ixgbe_atr_input *input,
714 uint16_t soft_id, uint8_t queue, uint32_t fdircmd,
717 u32 fdirport, fdirvlan;
719 /* record the source address (big-endian) */
720 if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
721 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), input->formatted.src_ip[0]);
722 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), input->formatted.src_ip[1]);
723 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.src_ip[2]);
724 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[3]);
727 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
730 /* record the first 32 bits of the destination address (big-endian) */
731 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
733 /* record source and destination port (little-endian)*/
734 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
735 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
736 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
737 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
739 /* record vlan (little-endian) and flex_bytes(big-endian) */
740 fdirvlan = input->formatted.flex_bytes;
741 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
742 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
743 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
745 /* configure FDIRHASH register */
746 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
747 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
750 * flush all previous writes to make certain registers are
751 * programmed prior to issuing the command
753 IXGBE_WRITE_FLUSH(hw);
755 /* configure FDIRCMD register */
756 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
757 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
758 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
759 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
760 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
762 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
766 * Adds or updates a perfect filter.
768 * dev: ethernet device to add filter to
769 * fdir_filter: filter details
770 * soft_id: software index for the filters
771 * queue: queue index to direct traffic to
772 * drop: non-zero if packets should be sent to the drop queue
773 * update: 0 to add a new filter, otherwise update existing.
776 fdir_add_update_perfect_filter(struct rte_eth_dev *dev,
777 struct rte_fdir_filter *fdir_filter, uint16_t soft_id,
778 uint8_t queue, int drop, int update)
780 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
781 uint32_t fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
783 union ixgbe_atr_input input;
786 if (hw->mac.type != ixgbe_mac_82599EB && hw->mac.type !=ixgbe_mac_X540)
789 err = fdir_filter_to_atr_input(fdir_filter, &input);
794 queue = dev->data->dev_conf.fdir_conf.drop_queue;
795 fdircmd_flags |= IXGBE_FDIRCMD_DROP;
798 fdirhash = atr_compute_perfect_hash_82599(&input,
799 dev->data->dev_conf.fdir_conf.pballoc);
801 fdir_write_perfect_filter_82599(hw, &input, soft_id, queue,
802 fdircmd_flags, fdirhash);
807 ixgbe_fdir_add_perfect_filter(struct rte_eth_dev *dev,
808 struct rte_fdir_filter *fdir_filter, uint16_t soft_id,
809 uint8_t queue, uint8_t drop)
811 PMD_INIT_FUNC_TRACE();
812 return fdir_add_update_perfect_filter(dev, fdir_filter, soft_id, queue,
817 ixgbe_fdir_update_perfect_filter(struct rte_eth_dev *dev,
818 struct rte_fdir_filter *fdir_filter, uint16_t soft_id,
819 uint8_t queue, uint8_t drop)
821 PMD_INIT_FUNC_TRACE();
822 return fdir_add_update_perfect_filter(dev, fdir_filter, soft_id, queue,
827 ixgbe_fdir_remove_perfect_filter(struct rte_eth_dev *dev,
828 struct rte_fdir_filter *fdir_filter,
831 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
832 union ixgbe_atr_input input;
836 PMD_INIT_FUNC_TRACE();
838 if (hw->mac.type != ixgbe_mac_82599EB && hw->mac.type !=ixgbe_mac_X540)
841 err = fdir_filter_to_atr_input(fdir_filter, &input);
845 /* configure FDIRHASH register */
846 fdirhash = atr_compute_perfect_hash_82599(&input,
847 dev->data->dev_conf.fdir_conf.pballoc);
848 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
850 return fdir_erase_filter_82599(hw, &input, fdirhash);
854 ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir *fdir)
856 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
857 struct ixgbe_hw_fdir_info *info =
858 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
861 if (hw->mac.type != ixgbe_mac_82599EB && hw->mac.type !=ixgbe_mac_X540)
864 /* Get the information from registers */
865 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE);
866 info->collision = (uint16_t)((reg & IXGBE_FDIRFREE_COLL_MASK) >>
867 IXGBE_FDIRFREE_COLL_SHIFT);
868 info->free = (uint16_t)((reg & IXGBE_FDIRFREE_FREE_MASK) >>
869 IXGBE_FDIRFREE_FREE_SHIFT);
871 reg = IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
872 info->maxhash = (uint16_t)((reg & IXGBE_FDIRLEN_MAXHASH_MASK) >>
873 IXGBE_FDIRLEN_MAXHASH_SHIFT);
874 info->maxlen = (uint8_t)((reg & IXGBE_FDIRLEN_MAXLEN_MASK) >>
875 IXGBE_FDIRLEN_MAXLEN_SHIFT);
877 reg = IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
878 info->remove += (reg & IXGBE_FDIRUSTAT_REMOVE_MASK) >>
879 IXGBE_FDIRUSTAT_REMOVE_SHIFT;
880 info->add += (reg & IXGBE_FDIRUSTAT_ADD_MASK) >>
881 IXGBE_FDIRUSTAT_ADD_SHIFT;
883 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT) & 0xFFFF;
884 info->f_remove += (reg & IXGBE_FDIRFSTAT_FREMOVE_MASK) >>
885 IXGBE_FDIRFSTAT_FREMOVE_SHIFT;
886 info->f_add += (reg & IXGBE_FDIRFSTAT_FADD_MASK) >>
887 IXGBE_FDIRFSTAT_FADD_SHIFT;
889 /* Copy the new information in the fdir parameter */
890 fdir->collision = info->collision;
891 fdir->free = info->free;
892 fdir->maxhash = info->maxhash;
893 fdir->maxlen = info->maxlen;
894 fdir->remove = info->remove;
895 fdir->add = info->add;
896 fdir->f_remove = info->f_remove;
897 fdir->f_add = info->f_add;