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38 #include <sys/queue.h>
40 #include <rte_interrupts.h>
42 #include <rte_debug.h>
44 #include <rte_ether.h>
45 #include <rte_ethdev.h>
47 #include "ixgbe_logs.h"
48 #include "ixgbe/ixgbe_api.h"
49 #include "ixgbe/ixgbe_common.h"
50 #include "ixgbe_ethdev.h"
52 /* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */
53 #define FDIRCTRL_PBALLOC_MASK 0x03
55 /* For calculating memory required for FDIR filters */
56 #define PBALLOC_SIZE_SHIFT 15
58 /* Number of bits used to mask bucket hash for different pballoc sizes */
59 #define PERFECT_BUCKET_64KB_HASH_MASK 0x07FF /* 11 bits */
60 #define PERFECT_BUCKET_128KB_HASH_MASK 0x0FFF /* 12 bits */
61 #define PERFECT_BUCKET_256KB_HASH_MASK 0x1FFF /* 13 bits */
62 #define SIG_BUCKET_64KB_HASH_MASK 0x1FFF /* 13 bits */
63 #define SIG_BUCKET_128KB_HASH_MASK 0x3FFF /* 14 bits */
64 #define SIG_BUCKET_256KB_HASH_MASK 0x7FFF /* 15 bits */
67 * This function is based on ixgbe_fdir_enable_82599() in ixgbe/ixgbe_82599.c.
68 * It adds extra configuration of fdirctrl that is common for all filter types.
70 * Initialize Flow Director control registers
71 * @hw: pointer to hardware structure
72 * @fdirctrl: value to write to flow director control register
74 static void fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
78 PMD_INIT_FUNC_TRACE();
80 /* Prime the keys for hashing */
81 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
82 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
85 * Continue setup of fdirctrl register bits:
86 * Set the maximum length per hash bucket to 0xA filters
87 * Send interrupt when 64 filters are left
89 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
90 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
93 * Poll init-done after we write the register. Estimated times:
94 * 10G: PBALLOC = 11b, timing is 60us
95 * 1G: PBALLOC = 11b, timing is 600us
96 * 100M: PBALLOC = 11b, timing is 6ms
98 * Multiple these timings by 4 if under full Rx load
100 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
101 * 1 msec per poll time. If we're at line rate and drop to 100M, then
102 * this might not finish in our poll time, but we can live with that
105 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
106 IXGBE_WRITE_FLUSH(hw);
107 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
108 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
109 IXGBE_FDIRCTRL_INIT_DONE)
114 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
115 PMD_INIT_LOG(WARNING, "Flow Director poll time exceeded!");
119 * Set appropriate bits in fdirctrl for: variable reporting levels, moving
120 * flexbytes matching field, and drop queue (only for perfect matching mode).
123 configure_fdir_flags(struct rte_fdir_conf *conf, uint32_t *fdirctrl)
127 switch (conf->pballoc) {
128 case RTE_FDIR_PBALLOC_64K:
129 /* 8k - 1 signature filters */
130 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
132 case RTE_FDIR_PBALLOC_128K:
133 /* 16k - 1 signature filters */
134 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
136 case RTE_FDIR_PBALLOC_256K:
137 /* 32k - 1 signature filters */
138 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
142 PMD_INIT_LOG(ERR, "Invalid fdir_conf->pballoc value");
146 /* status flags: write hash & swindex in the rx descriptor */
147 switch (conf->status) {
148 case RTE_FDIR_NO_REPORT_STATUS:
149 /* do nothing, default mode */
151 case RTE_FDIR_REPORT_STATUS:
152 /* report status when the packet matches a fdir rule */
153 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
155 case RTE_FDIR_REPORT_STATUS_ALWAYS:
156 /* always report status */
157 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS;
161 PMD_INIT_LOG(ERR, "Invalid fdir_conf->status value");
165 *fdirctrl |= (conf->flexbytes_offset << IXGBE_FDIRCTRL_FLEX_SHIFT);
167 if (conf->mode == RTE_FDIR_MODE_PERFECT) {
168 *fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
169 *fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
176 ixgbe_fdir_configure(struct rte_eth_dev *dev)
178 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
180 uint32_t fdirctrl, pbsize;
183 PMD_INIT_FUNC_TRACE();
185 if (hw->mac.type != ixgbe_mac_82599EB &&
186 hw->mac.type != ixgbe_mac_X540 &&
187 hw->mac.type != ixgbe_mac_X550 &&
188 hw->mac.type != ixgbe_mac_X550EM_x)
191 err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
196 * Before enabling Flow Director, the Rx Packet Buffer size
197 * must be reduced. The new value is the current size minus
198 * flow director memory usage size.
200 pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
201 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
202 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
205 * The defaults in the HW for RX PB 1-7 are not zero and so should be
206 * intialized to zero for non DCB mode otherwise actual total RX PB
207 * would be bigger than programmed and filter space would run into
210 for (i = 1; i < 8; i++)
211 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
213 fdir_enable_82599(hw, fdirctrl);
218 * The below function is taken from the FreeBSD IXGBE drivers release
219 * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK
220 * before returning, as the signature hash can use 16bits.
222 * The newer driver has optimised functions for calculating bucket and
223 * signature hashes. However they don't support IPv6 type packets for signature
224 * filters so are not used here.
226 * Note that the bkt_hash field in the ixgbe_atr_input structure is also never
229 * Compute the hashes for SW ATR
230 * @stream: input bitstream to compute the hash on
231 * @key: 32-bit hash key
234 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
238 * The algorithm is as follows:
239 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
240 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
241 * and A[n] x B[n] is bitwise AND between same length strings
243 * K[n] is 16 bits, defined as:
244 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
245 * for n modulo 32 < 15, K[n] =
246 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
248 * S[n] is 16 bits, defined as:
249 * for n >= 15, S[n] = S[n:n - 15]
250 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
252 * To simplify for programming, the algorithm is implemented
253 * in software this way:
255 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
257 * for (i = 0; i < 352; i+=32)
258 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
260 * lo_hash_dword[15:0] ^= Stream[15:0];
261 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
262 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
264 * hi_hash_dword[31:0] ^= Stream[351:320];
267 * hash[15:0] ^= Stream[15:0];
269 * for (i = 0; i < 16; i++) {
271 * hash[15:0] ^= lo_hash_dword[(i+15):i];
273 * hash[15:0] ^= hi_hash_dword[(i+15):i];
277 __be32 common_hash_dword = 0;
278 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
282 /* record the flow_vm_vlan bits as they are a key part to the hash */
283 flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
285 /* generate common hash dword */
286 for (i = 1; i <= 13; i++)
287 common_hash_dword ^= atr_input->dword_stream[i];
289 hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
291 /* low dword is word swapped version of common */
292 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
294 /* apply flow ID/VM pool/VLAN ID bits to hash words */
295 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
297 /* Process bits 0 and 16 */
298 if (key & 0x0001) hash_result ^= lo_hash_dword;
299 if (key & 0x00010000) hash_result ^= hi_hash_dword;
302 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
303 * delay this because bit 0 of the stream should not be processed
304 * so we do not add the vlan until after bit 0 was processed
306 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
309 /* process the remaining 30 bits in the key 2 bits at a time */
310 for (i = 15; i; i-- ) {
311 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
312 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
319 * Calculate the hash value needed for signature-match filters. In the FreeBSD
320 * driver, this is done by the optimised function
321 * ixgbe_atr_compute_sig_hash_82599(). However that can't be used here as it
322 * doesn't support calculating a hash for an IPv6 filter.
325 atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
326 enum rte_fdir_pballoc_type pballoc)
328 uint32_t bucket_hash, sig_hash;
330 if (pballoc == RTE_FDIR_PBALLOC_256K)
331 bucket_hash = ixgbe_atr_compute_hash_82599(input,
332 IXGBE_ATR_BUCKET_HASH_KEY) &
333 SIG_BUCKET_256KB_HASH_MASK;
334 else if (pballoc == RTE_FDIR_PBALLOC_128K)
335 bucket_hash = ixgbe_atr_compute_hash_82599(input,
336 IXGBE_ATR_BUCKET_HASH_KEY) &
337 SIG_BUCKET_128KB_HASH_MASK;
339 bucket_hash = ixgbe_atr_compute_hash_82599(input,
340 IXGBE_ATR_BUCKET_HASH_KEY) &
341 SIG_BUCKET_64KB_HASH_MASK;
343 sig_hash = ixgbe_atr_compute_hash_82599(input,
344 IXGBE_ATR_SIGNATURE_HASH_KEY);
346 return (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash;
350 * This function is based on ixgbe_atr_add_signature_filter_82599() in
351 * ixgbe/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports
352 * setting extra fields in the FDIRCMD register, and removes the code that was
353 * verifying the flow_type field. According to the documentation, a flow type of
354 * 00 (i.e. not TCP, UDP, or SCTP) is not supported, however it appears to
357 * Adds a signature hash filter
358 * @hw: pointer to hardware structure
359 * @input: unique input dword
360 * @queue: queue index to direct traffic to
361 * @fdircmd: any extra flags to set in fdircmd register
362 * @fdirhash: pre-calculated hash value for the filter
365 fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
366 union ixgbe_atr_input *input, u8 queue, u32 fdircmd,
371 PMD_INIT_FUNC_TRACE();
373 /* configure FDIRCMD register */
374 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
375 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
376 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
377 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
380 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
381 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
383 fdirhashcmd = (u64)fdircmd << 32;
384 fdirhashcmd |= fdirhash;
385 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
387 PMD_INIT_LOG(DEBUG, "Tx Queue=%x hash=%x", queue, (u32)fdirhashcmd);
391 * Convert DPDK rte_fdir_filter struct to ixgbe_atr_input union that is used
392 * by the IXGBE driver code.
395 fdir_filter_to_atr_input(struct rte_fdir_filter *fdir_filter,
396 union ixgbe_atr_input *input)
398 if ((fdir_filter->l4type == RTE_FDIR_L4TYPE_SCTP ||
399 fdir_filter->l4type == RTE_FDIR_L4TYPE_NONE) &&
400 (fdir_filter->port_src || fdir_filter->port_dst)) {
401 PMD_INIT_LOG(ERR, "Invalid fdir_filter");
405 memset(input, 0, sizeof(*input));
407 input->formatted.vlan_id = fdir_filter->vlan_id;
408 input->formatted.src_port = fdir_filter->port_src;
409 input->formatted.dst_port = fdir_filter->port_dst;
410 input->formatted.flex_bytes = fdir_filter->flex_bytes;
412 switch (fdir_filter->l4type) {
413 case RTE_FDIR_L4TYPE_TCP:
414 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
416 case RTE_FDIR_L4TYPE_UDP:
417 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
419 case RTE_FDIR_L4TYPE_SCTP:
420 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
422 case RTE_FDIR_L4TYPE_NONE:
423 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
426 PMD_INIT_LOG(ERR, " Error on l4type input");
430 if (fdir_filter->iptype == RTE_FDIR_IPTYPE_IPV6) {
431 input->formatted.flow_type |= IXGBE_ATR_L4TYPE_IPV6_MASK;
433 input->formatted.src_ip[0] = fdir_filter->ip_src.ipv6_addr[0];
434 input->formatted.src_ip[1] = fdir_filter->ip_src.ipv6_addr[1];
435 input->formatted.src_ip[2] = fdir_filter->ip_src.ipv6_addr[2];
436 input->formatted.src_ip[3] = fdir_filter->ip_src.ipv6_addr[3];
438 input->formatted.dst_ip[0] = fdir_filter->ip_dst.ipv6_addr[0];
439 input->formatted.dst_ip[1] = fdir_filter->ip_dst.ipv6_addr[1];
440 input->formatted.dst_ip[2] = fdir_filter->ip_dst.ipv6_addr[2];
441 input->formatted.dst_ip[3] = fdir_filter->ip_dst.ipv6_addr[3];
444 input->formatted.src_ip[0] = fdir_filter->ip_src.ipv4_addr;
445 input->formatted.dst_ip[0] = fdir_filter->ip_dst.ipv4_addr;
452 * Adds or updates a signature filter.
454 * dev: ethernet device to add filter to
455 * fdir_filter: filter details
456 * queue: queue index to direct traffic to
457 * update: 0 to add a new filter, otherwise update existing.
460 fdir_add_update_signature_filter(struct rte_eth_dev *dev,
461 struct rte_fdir_filter *fdir_filter, uint8_t queue, int update)
463 struct ixgbe_hw *hw= IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
464 uint32_t fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
466 union ixgbe_atr_input input;
469 if (hw->mac.type != ixgbe_mac_82599EB &&
470 hw->mac.type != ixgbe_mac_X540 &&
471 hw->mac.type != ixgbe_mac_X550 &&
472 hw->mac.type != ixgbe_mac_X550EM_x)
475 err = fdir_filter_to_atr_input(fdir_filter, &input);
479 fdirhash = atr_compute_sig_hash_82599(&input,
480 dev->data->dev_conf.fdir_conf.pballoc);
481 fdir_add_signature_filter_82599(hw, &input, queue, fdircmd_flags,
487 ixgbe_fdir_add_signature_filter(struct rte_eth_dev *dev,
488 struct rte_fdir_filter *fdir_filter, uint8_t queue)
490 PMD_INIT_FUNC_TRACE();
491 return fdir_add_update_signature_filter(dev, fdir_filter, queue, 0);
495 ixgbe_fdir_update_signature_filter(struct rte_eth_dev *dev,
496 struct rte_fdir_filter *fdir_filter, uint8_t queue)
498 PMD_INIT_FUNC_TRACE();
499 return fdir_add_update_signature_filter(dev, fdir_filter, queue, 1);
503 * This is based on ixgbe_fdir_erase_perfect_filter_82599() in
504 * ixgbe/ixgbe_82599.c. It is modified to take in the hash as a parameter so
505 * that it can be used for removing signature and perfect filters.
508 fdir_erase_filter_82599(struct ixgbe_hw *hw,
509 __rte_unused union ixgbe_atr_input *input, uint32_t fdirhash)
515 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
517 /* flush hash to HW */
518 IXGBE_WRITE_FLUSH(hw);
520 /* Query if filter is present */
521 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
523 for (retry_count = 10; retry_count; retry_count--) {
524 /* allow 10us for query to process */
526 /* verify query completed successfully */
527 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
528 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
533 PMD_INIT_LOG(ERR, "Timeout querying for flow director filter");
537 /* if filter exists in hardware then remove it */
538 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
539 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
540 IXGBE_WRITE_FLUSH(hw);
541 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
542 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
549 ixgbe_fdir_remove_signature_filter(struct rte_eth_dev *dev,
550 struct rte_fdir_filter *fdir_filter)
552 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
553 union ixgbe_atr_input input;
556 PMD_INIT_FUNC_TRACE();
558 if (hw->mac.type != ixgbe_mac_82599EB &&
559 hw->mac.type != ixgbe_mac_X540 &&
560 hw->mac.type != ixgbe_mac_X550 &&
561 hw->mac.type != ixgbe_mac_X550EM_x)
564 err = fdir_filter_to_atr_input(fdir_filter, &input);
568 return fdir_erase_filter_82599(hw, &input,
569 atr_compute_sig_hash_82599(&input,
570 dev->data->dev_conf.fdir_conf.pballoc));
574 * Reverse the bits in FDIR registers that store 2 x 16 bit masks.
576 * @hi_dword: Bits 31:16 mask to be bit swapped.
577 * @lo_dword: Bits 15:0 mask to be bit swapped.
579 * Flow director uses several registers to store 2 x 16 bit masks with the
580 * bits reversed such as FDIRTCPM, FDIRUDPM and FDIRIP6M. The LS bit of the
581 * mask affects the MS bit/byte of the target. This function reverses the
582 * bits in these masks.
585 reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)
587 u32 mask = hi_dword << 16;
589 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
590 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
591 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
592 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
596 * This macro exists in ixgbe/ixgbe_82599.c, however in that file it reverses
597 * the bytes, and then reverses them again. So here it does nothing.
599 #define IXGBE_WRITE_REG_BE32 IXGBE_WRITE_REG
602 * This is based on ixgbe_fdir_set_input_mask_82599() in ixgbe/ixgbe_82599.c,
603 * but makes use of the rte_fdir_masks structure to see which bits to set.
606 fdir_set_input_mask_82599(struct ixgbe_hw *hw,
607 struct rte_fdir_masks *input_mask)
609 /* mask VM pool since it is currently not supported */
610 u32 fdirm = IXGBE_FDIRM_POOL;
611 u32 fdirtcpm; /* TCP source and destination port masks. */
612 u32 fdiripv6m; /* IPv6 source and destination masks. */
614 PMD_INIT_FUNC_TRACE();
617 * Program the relevant mask registers. If src/dst_port or src/dst_addr
618 * are zero, then assume a full mask for that field. Also assume that
619 * a VLAN of 0 is unspecified, so mask that out as well. L4type
620 * cannot be masked out in this implementation.
622 if (input_mask->only_ip_flow) {
623 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
624 fdirm |= IXGBE_FDIRM_L4P;
625 if (input_mask->dst_port_mask || input_mask->src_port_mask) {
626 PMD_INIT_LOG(ERR, " Error on src/dst port mask");
631 if (!input_mask->comp_ipv6_dst)
633 fdirm |= IXGBE_FDIRM_DIPv6;
635 if (!input_mask->vlan_id)
637 fdirm |= IXGBE_FDIRM_VLANID;
639 if (!input_mask->vlan_prio)
640 /* mask VLAN priority */
641 fdirm |= IXGBE_FDIRM_VLANP;
643 if (!input_mask->flexbytes)
644 /* Mask Flex Bytes */
645 fdirm |= IXGBE_FDIRM_FLEX;
647 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
649 /* store the TCP/UDP port masks, bit reversed from port layout */
650 fdirtcpm = reverse_fdir_bitmasks(input_mask->dst_port_mask,
651 input_mask->src_port_mask);
653 /* write both the same so that UDP and TCP use the same mask */
654 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
655 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
657 if (!input_mask->set_ipv6_mask) {
658 /* Store source and destination IPv4 masks (big-endian) */
659 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
660 IXGBE_NTOHL(~input_mask->src_ipv4_mask));
661 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
662 IXGBE_NTOHL(~input_mask->dst_ipv4_mask));
665 /* Store source and destination IPv6 masks (bit reversed) */
666 fdiripv6m = reverse_fdir_bitmasks(input_mask->dst_ipv6_mask,
667 input_mask->src_ipv6_mask);
669 IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m);
672 return IXGBE_SUCCESS;
676 ixgbe_fdir_set_masks(struct rte_eth_dev *dev, struct rte_fdir_masks *fdir_masks)
681 PMD_INIT_FUNC_TRACE();
683 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
685 if (hw->mac.type != ixgbe_mac_82599EB &&
686 hw->mac.type != ixgbe_mac_X540 &&
687 hw->mac.type != ixgbe_mac_X550 &&
688 hw->mac.type != ixgbe_mac_X550EM_x)
691 err = ixgbe_reinit_fdir_tables_82599(hw);
693 PMD_INIT_LOG(ERR, "reinit of fdir tables failed");
697 return fdir_set_input_mask_82599(hw, fdir_masks);
701 atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
702 enum rte_fdir_pballoc_type pballoc)
704 if (pballoc == RTE_FDIR_PBALLOC_256K)
705 return ixgbe_atr_compute_hash_82599(input,
706 IXGBE_ATR_BUCKET_HASH_KEY) &
707 PERFECT_BUCKET_256KB_HASH_MASK;
708 else if (pballoc == RTE_FDIR_PBALLOC_128K)
709 return ixgbe_atr_compute_hash_82599(input,
710 IXGBE_ATR_BUCKET_HASH_KEY) &
711 PERFECT_BUCKET_128KB_HASH_MASK;
713 return ixgbe_atr_compute_hash_82599(input,
714 IXGBE_ATR_BUCKET_HASH_KEY) &
715 PERFECT_BUCKET_64KB_HASH_MASK;
719 * This is based on ixgbe_fdir_write_perfect_filter_82599() in
720 * ixgbe/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register
721 * added, and IPv6 support also added. The hash value is also pre-calculated
722 * as the pballoc value is needed to do it.
725 fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, union ixgbe_atr_input *input,
726 uint16_t soft_id, uint8_t queue, uint32_t fdircmd,
729 u32 fdirport, fdirvlan;
731 /* record the source address (big-endian) */
732 if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
733 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), input->formatted.src_ip[0]);
734 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), input->formatted.src_ip[1]);
735 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.src_ip[2]);
736 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[3]);
739 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
742 /* record the first 32 bits of the destination address (big-endian) */
743 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
745 /* record source and destination port (little-endian)*/
746 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
747 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
748 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
749 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
751 /* record vlan (little-endian) and flex_bytes(big-endian) */
752 fdirvlan = input->formatted.flex_bytes;
753 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
754 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
755 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
757 /* configure FDIRHASH register */
758 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
759 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
762 * flush all previous writes to make certain registers are
763 * programmed prior to issuing the command
765 IXGBE_WRITE_FLUSH(hw);
767 /* configure FDIRCMD register */
768 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
769 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
770 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
771 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
772 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
774 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
778 * Adds or updates a perfect filter.
780 * dev: ethernet device to add filter to
781 * fdir_filter: filter details
782 * soft_id: software index for the filters
783 * queue: queue index to direct traffic to
784 * drop: non-zero if packets should be sent to the drop queue
785 * update: 0 to add a new filter, otherwise update existing.
788 fdir_add_update_perfect_filter(struct rte_eth_dev *dev,
789 struct rte_fdir_filter *fdir_filter, uint16_t soft_id,
790 uint8_t queue, int drop, int update)
792 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
793 uint32_t fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
795 union ixgbe_atr_input input;
798 if (hw->mac.type != ixgbe_mac_82599EB &&
799 hw->mac.type != ixgbe_mac_X540 &&
800 hw->mac.type != ixgbe_mac_X550 &&
801 hw->mac.type != ixgbe_mac_X550EM_x)
804 err = fdir_filter_to_atr_input(fdir_filter, &input);
809 queue = dev->data->dev_conf.fdir_conf.drop_queue;
810 fdircmd_flags |= IXGBE_FDIRCMD_DROP;
813 fdirhash = atr_compute_perfect_hash_82599(&input,
814 dev->data->dev_conf.fdir_conf.pballoc);
816 fdir_write_perfect_filter_82599(hw, &input, soft_id, queue,
817 fdircmd_flags, fdirhash);
822 ixgbe_fdir_add_perfect_filter(struct rte_eth_dev *dev,
823 struct rte_fdir_filter *fdir_filter, uint16_t soft_id,
824 uint8_t queue, uint8_t drop)
826 PMD_INIT_FUNC_TRACE();
827 return fdir_add_update_perfect_filter(dev, fdir_filter, soft_id, queue,
832 ixgbe_fdir_update_perfect_filter(struct rte_eth_dev *dev,
833 struct rte_fdir_filter *fdir_filter, uint16_t soft_id,
834 uint8_t queue, uint8_t drop)
836 PMD_INIT_FUNC_TRACE();
837 return fdir_add_update_perfect_filter(dev, fdir_filter, soft_id, queue,
842 ixgbe_fdir_remove_perfect_filter(struct rte_eth_dev *dev,
843 struct rte_fdir_filter *fdir_filter,
846 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
847 union ixgbe_atr_input input;
851 PMD_INIT_FUNC_TRACE();
853 if (hw->mac.type != ixgbe_mac_82599EB &&
854 hw->mac.type != ixgbe_mac_X540 &&
855 hw->mac.type != ixgbe_mac_X550 &&
856 hw->mac.type != ixgbe_mac_X550EM_x)
859 err = fdir_filter_to_atr_input(fdir_filter, &input);
863 /* configure FDIRHASH register */
864 fdirhash = atr_compute_perfect_hash_82599(&input,
865 dev->data->dev_conf.fdir_conf.pballoc);
866 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
868 return fdir_erase_filter_82599(hw, &input, fdirhash);
872 ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir *fdir)
874 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
875 struct ixgbe_hw_fdir_info *info =
876 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
879 if (hw->mac.type != ixgbe_mac_82599EB &&
880 hw->mac.type != ixgbe_mac_X540 &&
881 hw->mac.type != ixgbe_mac_X550 &&
882 hw->mac.type != ixgbe_mac_X550EM_x)
885 /* Get the information from registers */
886 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE);
887 info->collision = (uint16_t)((reg & IXGBE_FDIRFREE_COLL_MASK) >>
888 IXGBE_FDIRFREE_COLL_SHIFT);
889 info->free = (uint16_t)((reg & IXGBE_FDIRFREE_FREE_MASK) >>
890 IXGBE_FDIRFREE_FREE_SHIFT);
892 reg = IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
893 info->maxhash = (uint16_t)((reg & IXGBE_FDIRLEN_MAXHASH_MASK) >>
894 IXGBE_FDIRLEN_MAXHASH_SHIFT);
895 info->maxlen = (uint8_t)((reg & IXGBE_FDIRLEN_MAXLEN_MASK) >>
896 IXGBE_FDIRLEN_MAXLEN_SHIFT);
898 reg = IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
899 info->remove += (reg & IXGBE_FDIRUSTAT_REMOVE_MASK) >>
900 IXGBE_FDIRUSTAT_REMOVE_SHIFT;
901 info->add += (reg & IXGBE_FDIRUSTAT_ADD_MASK) >>
902 IXGBE_FDIRUSTAT_ADD_SHIFT;
904 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT) & 0xFFFF;
905 info->f_remove += (reg & IXGBE_FDIRFSTAT_FREMOVE_MASK) >>
906 IXGBE_FDIRFSTAT_FREMOVE_SHIFT;
907 info->f_add += (reg & IXGBE_FDIRFSTAT_FADD_MASK) >>
908 IXGBE_FDIRFSTAT_FADD_SHIFT;
910 /* Copy the new information in the fdir parameter */
911 fdir->collision = info->collision;
912 fdir->free = info->free;
913 fdir->maxhash = info->maxhash;
914 fdir->maxlen = info->maxlen;
915 fdir->remove = info->remove;
916 fdir->add = info->add;
917 fdir->f_remove = info->f_remove;
918 fdir->f_add = info->f_add;