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38 #include <sys/queue.h>
40 #include <rte_interrupts.h>
42 #include <rte_debug.h>
44 #include <rte_ether.h>
45 #include <rte_ethdev.h>
47 #include "ixgbe_logs.h"
48 #include "ixgbe/ixgbe_api.h"
49 #include "ixgbe/ixgbe_common.h"
50 #include "ixgbe_ethdev.h"
52 /* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */
53 #define FDIRCTRL_PBALLOC_MASK 0x03
55 /* For calculating memory required for FDIR filters */
56 #define PBALLOC_SIZE_SHIFT 15
58 /* Number of bits used to mask bucket hash for different pballoc sizes */
59 #define PERFECT_BUCKET_64KB_HASH_MASK 0x07FF /* 11 bits */
60 #define PERFECT_BUCKET_128KB_HASH_MASK 0x0FFF /* 12 bits */
61 #define PERFECT_BUCKET_256KB_HASH_MASK 0x1FFF /* 13 bits */
62 #define SIG_BUCKET_64KB_HASH_MASK 0x1FFF /* 13 bits */
63 #define SIG_BUCKET_128KB_HASH_MASK 0x3FFF /* 14 bits */
64 #define SIG_BUCKET_256KB_HASH_MASK 0x7FFF /* 15 bits */
65 #define IXGBE_FDIRCMD_CMD_INTERVAL_US 10
67 static int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash);
68 static int ixgbe_fdir_filter_to_atr_input(
69 const struct rte_eth_fdir_filter *fdir_filter,
70 union ixgbe_atr_input *input);
71 static uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
73 static uint32_t atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
74 enum rte_fdir_pballoc_type pballoc);
75 static uint32_t atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
76 enum rte_fdir_pballoc_type pballoc);
77 static int fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
78 union ixgbe_atr_input *input, uint8_t queue,
79 uint32_t fdircmd, uint32_t fdirhash);
80 static int fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
81 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
83 static int ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
84 const struct rte_eth_fdir_filter *fdir_filter,
88 * This function is based on ixgbe_fdir_enable_82599() in ixgbe/ixgbe_82599.c.
89 * It adds extra configuration of fdirctrl that is common for all filter types.
91 * Initialize Flow Director control registers
92 * @hw: pointer to hardware structure
93 * @fdirctrl: value to write to flow director control register
95 static void fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
99 PMD_INIT_FUNC_TRACE();
101 /* Prime the keys for hashing */
102 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
103 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
106 * Continue setup of fdirctrl register bits:
107 * Set the maximum length per hash bucket to 0xA filters
108 * Send interrupt when 64 filters are left
110 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
111 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
114 * Poll init-done after we write the register. Estimated times:
115 * 10G: PBALLOC = 11b, timing is 60us
116 * 1G: PBALLOC = 11b, timing is 600us
117 * 100M: PBALLOC = 11b, timing is 6ms
119 * Multiple these timings by 4 if under full Rx load
121 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
122 * 1 msec per poll time. If we're at line rate and drop to 100M, then
123 * this might not finish in our poll time, but we can live with that
126 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
127 IXGBE_WRITE_FLUSH(hw);
128 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
129 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
130 IXGBE_FDIRCTRL_INIT_DONE)
135 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
136 PMD_INIT_LOG(WARNING, "Flow Director poll time exceeded!");
140 * Set appropriate bits in fdirctrl for: variable reporting levels, moving
141 * flexbytes matching field, and drop queue (only for perfect matching mode).
144 configure_fdir_flags(struct rte_fdir_conf *conf, uint32_t *fdirctrl)
148 switch (conf->pballoc) {
149 case RTE_FDIR_PBALLOC_64K:
150 /* 8k - 1 signature filters */
151 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
153 case RTE_FDIR_PBALLOC_128K:
154 /* 16k - 1 signature filters */
155 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
157 case RTE_FDIR_PBALLOC_256K:
158 /* 32k - 1 signature filters */
159 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
163 PMD_INIT_LOG(ERR, "Invalid fdir_conf->pballoc value");
167 /* status flags: write hash & swindex in the rx descriptor */
168 switch (conf->status) {
169 case RTE_FDIR_NO_REPORT_STATUS:
170 /* do nothing, default mode */
172 case RTE_FDIR_REPORT_STATUS:
173 /* report status when the packet matches a fdir rule */
174 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
176 case RTE_FDIR_REPORT_STATUS_ALWAYS:
177 /* always report status */
178 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS;
182 PMD_INIT_LOG(ERR, "Invalid fdir_conf->status value");
186 *fdirctrl |= (conf->flexbytes_offset << IXGBE_FDIRCTRL_FLEX_SHIFT);
188 if (conf->mode == RTE_FDIR_MODE_PERFECT) {
189 *fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
190 *fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
197 ixgbe_fdir_configure(struct rte_eth_dev *dev)
199 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
201 uint32_t fdirctrl, pbsize;
204 PMD_INIT_FUNC_TRACE();
206 if (hw->mac.type != ixgbe_mac_82599EB &&
207 hw->mac.type != ixgbe_mac_X540 &&
208 hw->mac.type != ixgbe_mac_X550 &&
209 hw->mac.type != ixgbe_mac_X550EM_x)
212 err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
217 * Before enabling Flow Director, the Rx Packet Buffer size
218 * must be reduced. The new value is the current size minus
219 * flow director memory usage size.
221 pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
222 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
223 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
226 * The defaults in the HW for RX PB 1-7 are not zero and so should be
227 * intialized to zero for non DCB mode otherwise actual total RX PB
228 * would be bigger than programmed and filter space would run into
231 for (i = 1; i < 8; i++)
232 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
234 fdir_enable_82599(hw, fdirctrl);
239 * Reverse the bits in FDIR registers that store 2 x 16 bit masks.
241 * @hi_dword: Bits 31:16 mask to be bit swapped.
242 * @lo_dword: Bits 15:0 mask to be bit swapped.
244 * Flow director uses several registers to store 2 x 16 bit masks with the
245 * bits reversed such as FDIRTCPM, FDIRUDPM and FDIRIP6M. The LS bit of the
246 * mask affects the MS bit/byte of the target. This function reverses the
247 * bits in these masks.
250 reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)
252 u32 mask = hi_dword << 16;
254 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
255 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
256 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
257 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
261 * This macro exists in ixgbe/ixgbe_82599.c, however in that file it reverses
262 * the bytes, and then reverses them again. So here it does nothing.
264 #define IXGBE_WRITE_REG_BE32 IXGBE_WRITE_REG
267 * This is based on ixgbe_fdir_set_input_mask_82599() in ixgbe/ixgbe_82599.c,
268 * but makes use of the rte_fdir_masks structure to see which bits to set.
271 fdir_set_input_mask_82599(struct ixgbe_hw *hw,
272 struct rte_fdir_masks *input_mask)
274 /* mask VM pool since it is currently not supported */
275 u32 fdirm = IXGBE_FDIRM_POOL;
276 u32 fdirtcpm; /* TCP source and destination port masks. */
277 u32 fdiripv6m; /* IPv6 source and destination masks. */
279 PMD_INIT_FUNC_TRACE();
282 * Program the relevant mask registers. If src/dst_port or src/dst_addr
283 * are zero, then assume a full mask for that field. Also assume that
284 * a VLAN of 0 is unspecified, so mask that out as well. L4type
285 * cannot be masked out in this implementation.
287 if (input_mask->only_ip_flow) {
288 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
289 fdirm |= IXGBE_FDIRM_L4P;
290 if (input_mask->dst_port_mask || input_mask->src_port_mask) {
291 PMD_INIT_LOG(ERR, " Error on src/dst port mask");
296 if (!input_mask->comp_ipv6_dst)
298 fdirm |= IXGBE_FDIRM_DIPv6;
300 if (!input_mask->vlan_id)
302 fdirm |= IXGBE_FDIRM_VLANID;
304 if (!input_mask->vlan_prio)
305 /* mask VLAN priority */
306 fdirm |= IXGBE_FDIRM_VLANP;
308 if (!input_mask->flexbytes)
309 /* Mask Flex Bytes */
310 fdirm |= IXGBE_FDIRM_FLEX;
312 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
314 /* store the TCP/UDP port masks, bit reversed from port layout */
315 fdirtcpm = reverse_fdir_bitmasks(input_mask->dst_port_mask,
316 input_mask->src_port_mask);
318 /* write both the same so that UDP and TCP use the same mask */
319 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
320 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
322 if (!input_mask->set_ipv6_mask) {
323 /* Store source and destination IPv4 masks (big-endian) */
324 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
325 IXGBE_NTOHL(~input_mask->src_ipv4_mask));
326 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
327 IXGBE_NTOHL(~input_mask->dst_ipv4_mask));
329 /* Store source and destination IPv6 masks (bit reversed) */
330 fdiripv6m = reverse_fdir_bitmasks(input_mask->dst_ipv6_mask,
331 input_mask->src_ipv6_mask);
333 IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m);
336 return IXGBE_SUCCESS;
340 ixgbe_fdir_set_masks(struct rte_eth_dev *dev, struct rte_fdir_masks *fdir_masks)
345 PMD_INIT_FUNC_TRACE();
347 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
349 if (hw->mac.type != ixgbe_mac_82599EB &&
350 hw->mac.type != ixgbe_mac_X540 &&
351 hw->mac.type != ixgbe_mac_X550 &&
352 hw->mac.type != ixgbe_mac_X550EM_x)
355 err = ixgbe_reinit_fdir_tables_82599(hw);
357 PMD_INIT_LOG(ERR, "reinit of fdir tables failed");
361 return fdir_set_input_mask_82599(hw, fdir_masks);
365 * Convert DPDK rte_eth_fdir_filter struct to ixgbe_atr_input union that is used
366 * by the IXGBE driver code.
369 ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,
370 union ixgbe_atr_input *input)
372 input->formatted.vlan_id = fdir_filter->input.flow_ext.vlan_tci;
373 input->formatted.flex_bytes = (uint16_t)(
374 (fdir_filter->input.flow_ext.flexbytes[1] << 8 & 0xFF00) |
375 (fdir_filter->input.flow_ext.flexbytes[0] & 0xFF));
377 switch (fdir_filter->input.flow_type) {
378 case RTE_ETH_FLOW_TYPE_UDPV4:
379 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
381 case RTE_ETH_FLOW_TYPE_TCPV4:
382 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
384 case RTE_ETH_FLOW_TYPE_SCTPV4:
385 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
387 case RTE_ETH_FLOW_TYPE_IPV4_OTHER:
388 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
390 case RTE_ETH_FLOW_TYPE_UDPV6:
391 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV6;
393 case RTE_ETH_FLOW_TYPE_TCPV6:
394 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
396 case RTE_ETH_FLOW_TYPE_SCTPV6:
397 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV6;
399 case RTE_ETH_FLOW_TYPE_IPV6_OTHER:
400 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV6;
403 PMD_DRV_LOG(ERR, " Error on flow_type input");
407 switch (fdir_filter->input.flow_type) {
408 case RTE_ETH_FLOW_TYPE_UDPV4:
409 case RTE_ETH_FLOW_TYPE_TCPV4:
410 input->formatted.src_port =
411 fdir_filter->input.flow.udp4_flow.src_port;
412 input->formatted.dst_port =
413 fdir_filter->input.flow.udp4_flow.dst_port;
414 /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
415 case RTE_ETH_FLOW_TYPE_SCTPV4:
416 case RTE_ETH_FLOW_TYPE_IPV4_OTHER:
417 input->formatted.src_ip[0] =
418 fdir_filter->input.flow.ip4_flow.src_ip;
419 input->formatted.dst_ip[0] =
420 fdir_filter->input.flow.ip4_flow.dst_ip;
423 case RTE_ETH_FLOW_TYPE_UDPV6:
424 case RTE_ETH_FLOW_TYPE_TCPV6:
425 input->formatted.src_port =
426 fdir_filter->input.flow.udp6_flow.src_port;
427 input->formatted.dst_port =
428 fdir_filter->input.flow.udp6_flow.dst_port;
429 /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
430 case RTE_ETH_FLOW_TYPE_SCTPV6:
431 case RTE_ETH_FLOW_TYPE_IPV6_OTHER:
432 rte_memcpy(input->formatted.src_ip,
433 fdir_filter->input.flow.ipv6_flow.src_ip,
434 sizeof(input->formatted.src_ip));
435 rte_memcpy(input->formatted.dst_ip,
436 fdir_filter->input.flow.ipv6_flow.dst_ip,
437 sizeof(input->formatted.dst_ip));
440 PMD_DRV_LOG(ERR, " Error on flow_type input");
448 * The below function is taken from the FreeBSD IXGBE drivers release
449 * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK
450 * before returning, as the signature hash can use 16bits.
452 * The newer driver has optimised functions for calculating bucket and
453 * signature hashes. However they don't support IPv6 type packets for signature
454 * filters so are not used here.
456 * Note that the bkt_hash field in the ixgbe_atr_input structure is also never
459 * Compute the hashes for SW ATR
460 * @stream: input bitstream to compute the hash on
461 * @key: 32-bit hash key
464 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
468 * The algorithm is as follows:
469 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
470 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
471 * and A[n] x B[n] is bitwise AND between same length strings
473 * K[n] is 16 bits, defined as:
474 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
475 * for n modulo 32 < 15, K[n] =
476 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
478 * S[n] is 16 bits, defined as:
479 * for n >= 15, S[n] = S[n:n - 15]
480 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
482 * To simplify for programming, the algorithm is implemented
483 * in software this way:
485 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
487 * for (i = 0; i < 352; i+=32)
488 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
490 * lo_hash_dword[15:0] ^= Stream[15:0];
491 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
492 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
494 * hi_hash_dword[31:0] ^= Stream[351:320];
497 * hash[15:0] ^= Stream[15:0];
499 * for (i = 0; i < 16; i++) {
501 * hash[15:0] ^= lo_hash_dword[(i+15):i];
503 * hash[15:0] ^= hi_hash_dword[(i+15):i];
507 __be32 common_hash_dword = 0;
508 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
512 /* record the flow_vm_vlan bits as they are a key part to the hash */
513 flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
515 /* generate common hash dword */
516 for (i = 1; i <= 13; i++)
517 common_hash_dword ^= atr_input->dword_stream[i];
519 hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
521 /* low dword is word swapped version of common */
522 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
524 /* apply flow ID/VM pool/VLAN ID bits to hash words */
525 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
527 /* Process bits 0 and 16 */
528 if (key & 0x0001) hash_result ^= lo_hash_dword;
529 if (key & 0x00010000) hash_result ^= hi_hash_dword;
532 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
533 * delay this because bit 0 of the stream should not be processed
534 * so we do not add the vlan until after bit 0 was processed
536 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
539 /* process the remaining 30 bits in the key 2 bits at a time */
540 for (i = 15; i; i-- ) {
541 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
542 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
549 atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
550 enum rte_fdir_pballoc_type pballoc)
552 if (pballoc == RTE_FDIR_PBALLOC_256K)
553 return ixgbe_atr_compute_hash_82599(input,
554 IXGBE_ATR_BUCKET_HASH_KEY) &
555 PERFECT_BUCKET_256KB_HASH_MASK;
556 else if (pballoc == RTE_FDIR_PBALLOC_128K)
557 return ixgbe_atr_compute_hash_82599(input,
558 IXGBE_ATR_BUCKET_HASH_KEY) &
559 PERFECT_BUCKET_128KB_HASH_MASK;
561 return ixgbe_atr_compute_hash_82599(input,
562 IXGBE_ATR_BUCKET_HASH_KEY) &
563 PERFECT_BUCKET_64KB_HASH_MASK;
567 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
568 * @hw: pointer to hardware structure
571 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, uint32_t *fdircmd)
575 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
576 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
577 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
579 rte_delay_us(IXGBE_FDIRCMD_CMD_INTERVAL_US);
586 * Calculate the hash value needed for signature-match filters. In the FreeBSD
587 * driver, this is done by the optimised function
588 * ixgbe_atr_compute_sig_hash_82599(). However that can't be used here as it
589 * doesn't support calculating a hash for an IPv6 filter.
592 atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
593 enum rte_fdir_pballoc_type pballoc)
595 uint32_t bucket_hash, sig_hash;
597 if (pballoc == RTE_FDIR_PBALLOC_256K)
598 bucket_hash = ixgbe_atr_compute_hash_82599(input,
599 IXGBE_ATR_BUCKET_HASH_KEY) &
600 SIG_BUCKET_256KB_HASH_MASK;
601 else if (pballoc == RTE_FDIR_PBALLOC_128K)
602 bucket_hash = ixgbe_atr_compute_hash_82599(input,
603 IXGBE_ATR_BUCKET_HASH_KEY) &
604 SIG_BUCKET_128KB_HASH_MASK;
606 bucket_hash = ixgbe_atr_compute_hash_82599(input,
607 IXGBE_ATR_BUCKET_HASH_KEY) &
608 SIG_BUCKET_64KB_HASH_MASK;
610 sig_hash = ixgbe_atr_compute_hash_82599(input,
611 IXGBE_ATR_SIGNATURE_HASH_KEY);
613 return (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash;
617 * This is based on ixgbe_fdir_write_perfect_filter_82599() in
618 * ixgbe/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register
619 * added, and IPv6 support also added. The hash value is also pre-calculated
620 * as the pballoc value is needed to do it.
623 fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
624 union ixgbe_atr_input *input, uint8_t queue,
625 uint32_t fdircmd, uint32_t fdirhash)
627 uint32_t fdirport, fdirvlan;
630 /* record the IPv4 address (big-endian) */
631 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
632 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
634 /* record source and destination port (little-endian)*/
635 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
636 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
637 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
638 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
640 /* record vlan (little-endian) and flex_bytes(big-endian) */
641 fdirvlan = input->formatted.flex_bytes;
642 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
643 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
644 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
646 /* configure FDIRHASH register */
647 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
650 * flush all previous writes to make certain registers are
651 * programmed prior to issuing the command
653 IXGBE_WRITE_FLUSH(hw);
655 /* configure FDIRCMD register */
656 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
657 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
658 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
659 fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
660 fdircmd |= (uint32_t)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
662 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
664 PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
666 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
668 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
674 * This function is based on ixgbe_atr_add_signature_filter_82599() in
675 * ixgbe/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports
676 * setting extra fields in the FDIRCMD register, and removes the code that was
677 * verifying the flow_type field. According to the documentation, a flow type of
678 * 00 (i.e. not TCP, UDP, or SCTP) is not supported, however it appears to
681 * Adds a signature hash filter
682 * @hw: pointer to hardware structure
683 * @input: unique input dword
684 * @queue: queue index to direct traffic to
685 * @fdircmd: any extra flags to set in fdircmd register
686 * @fdirhash: pre-calculated hash value for the filter
689 fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
690 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
695 PMD_INIT_FUNC_TRACE();
697 /* configure FDIRCMD register */
698 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
699 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
700 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
701 fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
703 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
704 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
706 PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
708 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
710 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
716 * This is based on ixgbe_fdir_erase_perfect_filter_82599() in
717 * ixgbe/ixgbe_82599.c. It is modified to take in the hash as a parameter so
718 * that it can be used for removing signature and perfect filters.
721 fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash)
723 uint32_t fdircmd = 0;
726 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
728 /* flush hash to HW */
729 IXGBE_WRITE_FLUSH(hw);
731 /* Query if filter is present */
732 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
734 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
736 PMD_INIT_LOG(ERR, "Timeout querying for flow director filter.");
740 /* if filter exists in hardware then remove it */
741 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
742 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
743 IXGBE_WRITE_FLUSH(hw);
744 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
745 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
747 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
749 PMD_INIT_LOG(ERR, "Timeout erasing flow director filter.");
755 * ixgbe_add_del_fdir_filter - add or remove a flow diretor filter.
756 * @dev: pointer to the structure rte_eth_dev
757 * @fdir_filter: fdir filter entry
758 * @del: 1 - delete, 0 - add
759 * @update: 1 - update
762 ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
763 const struct rte_eth_fdir_filter *fdir_filter,
767 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
768 uint32_t fdircmd_flags;
770 union ixgbe_atr_input input;
772 bool is_perfect = FALSE;
775 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_NONE)
778 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
781 memset(&input, 0, sizeof(input));
783 err = ixgbe_fdir_filter_to_atr_input(fdir_filter, &input);
788 if (input.formatted.flow_type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
789 PMD_DRV_LOG(ERR, "IPv6 is not supported in"
793 fdirhash = atr_compute_perfect_hash_82599(&input,
794 dev->data->dev_conf.fdir_conf.pballoc);
795 fdirhash |= fdir_filter->soft_id <<
796 IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
798 fdirhash = atr_compute_sig_hash_82599(&input,
799 dev->data->dev_conf.fdir_conf.pballoc);
802 err = fdir_erase_filter_82599(hw, fdirhash);
804 PMD_DRV_LOG(ERR, "Fail to delete FDIR filter!");
806 PMD_DRV_LOG(DEBUG, "Success to delete FDIR filter!");
809 /* add or update an fdir filter*/
810 fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
811 if (fdir_filter->action.behavior == RTE_ETH_FDIR_REJECT) {
813 queue = dev->data->dev_conf.fdir_conf.drop_queue;
814 fdircmd_flags |= IXGBE_FDIRCMD_DROP;
816 PMD_DRV_LOG(ERR, "Drop option is not supported in"
820 } else if (fdir_filter->action.rx_queue < IXGBE_MAX_RX_QUEUE_NUM)
821 queue = (uint8_t)fdir_filter->action.rx_queue;
826 err = fdir_write_perfect_filter_82599(hw, &input, queue,
827 fdircmd_flags, fdirhash);
829 err = fdir_add_signature_filter_82599(hw, &input, queue,
830 fdircmd_flags, fdirhash);
833 PMD_DRV_LOG(ERR, "Fail to add FDIR filter!");
835 PMD_DRV_LOG(DEBUG, "Success to add FDIR filter");
841 ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir *fdir)
843 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
844 struct ixgbe_hw_fdir_info *info =
845 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
848 if (hw->mac.type != ixgbe_mac_82599EB &&
849 hw->mac.type != ixgbe_mac_X540 &&
850 hw->mac.type != ixgbe_mac_X550 &&
851 hw->mac.type != ixgbe_mac_X550EM_x)
854 /* Get the information from registers */
855 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE);
856 info->collision = (uint16_t)((reg & IXGBE_FDIRFREE_COLL_MASK) >>
857 IXGBE_FDIRFREE_COLL_SHIFT);
858 info->free = (uint16_t)((reg & IXGBE_FDIRFREE_FREE_MASK) >>
859 IXGBE_FDIRFREE_FREE_SHIFT);
861 reg = IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
862 info->maxhash = (uint16_t)((reg & IXGBE_FDIRLEN_MAXHASH_MASK) >>
863 IXGBE_FDIRLEN_MAXHASH_SHIFT);
864 info->maxlen = (uint8_t)((reg & IXGBE_FDIRLEN_MAXLEN_MASK) >>
865 IXGBE_FDIRLEN_MAXLEN_SHIFT);
867 reg = IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
868 info->remove += (reg & IXGBE_FDIRUSTAT_REMOVE_MASK) >>
869 IXGBE_FDIRUSTAT_REMOVE_SHIFT;
870 info->add += (reg & IXGBE_FDIRUSTAT_ADD_MASK) >>
871 IXGBE_FDIRUSTAT_ADD_SHIFT;
873 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT) & 0xFFFF;
874 info->f_remove += (reg & IXGBE_FDIRFSTAT_FREMOVE_MASK) >>
875 IXGBE_FDIRFSTAT_FREMOVE_SHIFT;
876 info->f_add += (reg & IXGBE_FDIRFSTAT_FADD_MASK) >>
877 IXGBE_FDIRFSTAT_FADD_SHIFT;
879 /* Copy the new information in the fdir parameter */
880 fdir->collision = info->collision;
881 fdir->free = info->free;
882 fdir->maxhash = info->maxhash;
883 fdir->maxlen = info->maxlen;
884 fdir->remove = info->remove;
885 fdir->add = info->add;
886 fdir->f_remove = info->f_remove;
887 fdir->f_add = info->f_add;
891 * ixgbe_fdir_ctrl_func - deal with all operations on flow director.
892 * @dev: pointer to the structure rte_eth_dev
893 * @filter_op:operation will be taken
894 * @arg: a pointer to specific structure corresponding to the filter_op
897 ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
898 enum rte_filter_op filter_op, void *arg)
900 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
903 if (hw->mac.type != ixgbe_mac_82599EB &&
904 hw->mac.type != ixgbe_mac_X540 &&
905 hw->mac.type != ixgbe_mac_X550 &&
906 hw->mac.type != ixgbe_mac_X550EM_x)
909 if (filter_op == RTE_ETH_FILTER_NOP)
912 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
916 case RTE_ETH_FILTER_ADD:
917 ret = ixgbe_add_del_fdir_filter(dev,
918 (struct rte_eth_fdir_filter *)arg, FALSE, FALSE);
920 case RTE_ETH_FILTER_UPDATE:
921 ret = ixgbe_add_del_fdir_filter(dev,
922 (struct rte_eth_fdir_filter *)arg, FALSE, TRUE);
924 case RTE_ETH_FILTER_DELETE:
925 ret = ixgbe_add_del_fdir_filter(dev,
926 (struct rte_eth_fdir_filter *)arg, TRUE, FALSE);
929 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);