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42 #include <rte_interrupts.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memcpy.h>
49 #include <rte_malloc.h>
50 #include <rte_random.h>
52 #include "ixgbe/ixgbe_common.h"
53 #include "ixgbe_ethdev.h"
55 #define IXGBE_MAX_VFTA (128)
58 void eth_random_addr(uint8_t *addr)
60 uint64_t rand = rte_rand();
61 uint8_t *p = (uint8_t*)&rand;
63 rte_memcpy(addr, p, ETHER_ADDR_LEN);
64 addr[0] &= 0xfe; /* clear multicast bit */
65 addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
68 static inline uint16_t
69 dev_num_vf(struct rte_eth_dev *eth_dev)
71 return eth_dev->pci_dev->max_vfs;
75 int ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
77 unsigned char vf_mac_addr[ETHER_ADDR_LEN];
78 struct ixgbe_vf_info *vfinfo =
79 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
82 for (vfn = 0; vfn < vf_num; vfn++) {
83 eth_random_addr(vf_mac_addr);
84 /* keep the random address as default */
85 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
93 ixgbe_mb_intr_setup(struct rte_eth_dev *dev)
95 struct ixgbe_interrupt *intr =
96 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
98 intr->mask |= IXGBE_EICR_MAILBOX;
103 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev)
105 struct ixgbe_vf_info **vfinfo =
106 IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
107 struct ixgbe_hw *hw =
108 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
112 PMD_INIT_FUNC_TRACE();
114 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
115 if (0 == (vf_num = dev_num_vf(eth_dev)))
118 *vfinfo = rte_zmalloc("vf_info", sizeof(struct ixgbe_vf_info) * vf_num, 0);
120 rte_panic("Cannot allocate memory for private VF data\n");
122 if (vf_num >= ETH_32_POOLS) {
124 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS;
125 } else if (vf_num >= ETH_16_POOLS) {
127 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS;
130 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS;
133 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
134 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
135 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
137 ixgbe_vf_perm_addr_gen(eth_dev, vf_num);
139 /* init_mailbox_params */
140 hw->mbx.ops.init_params(hw);
142 /* set mb interrupt mask */
143 ixgbe_mb_intr_setup(eth_dev);
148 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev)
150 uint32_t vtctl, fcrth;
151 uint32_t vfre_slot, vfre_offset;
153 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
154 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
155 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
156 uint32_t gpie, gcr_ext;
160 if (0 == (vf_num = dev_num_vf(eth_dev)))
163 /* enable VMDq and set the default pool for PF */
164 vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
165 vtctl |= IXGBE_VMD_CTL_VMDQ_EN;
166 vtctl &= ~IXGBE_VT_CTL_POOL_MASK;
167 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
168 << IXGBE_VT_CTL_POOL_SHIFT;
169 vtctl |= IXGBE_VT_CTL_REPLEN;
170 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
172 vfre_offset = vf_num & VFRE_MASK;
173 vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0;
175 /* Enable pools reserved to PF only */
176 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0) << vfre_offset);
177 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1);
178 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0) << vfre_offset);
179 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1);
181 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
182 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
184 /* clear VMDq map to perment rar 0 */
185 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
187 /* clear VMDq map to scan rar 127 */
188 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0);
189 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0);
191 /* set VMDq map to default PF pool */
192 hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);
195 * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode
197 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
198 gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK;
200 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
201 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
202 gpie |= IXGBE_GPIE_MSIX_MODE;
204 switch (RTE_ETH_DEV_SRIOV(eth_dev).active) {
206 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
207 gpie |= IXGBE_GPIE_VTMODE_64;
210 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32;
211 gpie |= IXGBE_GPIE_VTMODE_32;
214 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_16;
215 gpie |= IXGBE_GPIE_VTMODE_16;
219 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
220 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
223 * enable vlan filtering and allow all vlan tags through
225 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
226 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
227 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
229 /* VFTA - enable all vlan filters */
230 for (i = 0; i < IXGBE_MAX_VFTA; i++) {
231 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
234 /* Enable MAC Anti-Spoofing */
235 hw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num);
237 /* set flow control threshold to max to avoid tx switch hang */
238 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
239 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
240 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
241 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
248 set_rx_mode(struct rte_eth_dev *dev)
250 struct rte_eth_dev_data *dev_data =
251 (struct rte_eth_dev_data*)dev->data->dev_private;
252 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
253 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
254 uint16_t vfn = dev_num_vf(dev);
256 /* Check for Promiscuous and All Multicast modes */
257 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
259 /* set all bits that we expect to always be set */
260 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
261 fctrl |= IXGBE_FCTRL_BAM;
263 /* clear the bits we are changing the status of */
264 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
266 if (dev_data->promiscuous) {
267 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
268 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
269 /* don't hardware filter vlans in promisc mode */
270 ixgbe_vlan_hw_filter_disable(dev);
272 if (dev_data->all_multicast) {
273 fctrl |= IXGBE_FCTRL_MPE;
274 vmolr |= IXGBE_VMOLR_MPE;
276 vmolr |= IXGBE_VMOLR_ROMPE;
278 ixgbe_vlan_hw_filter_enable(dev);
281 if (hw->mac.type != ixgbe_mac_82598EB) {
282 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) &
283 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
285 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr);
288 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
290 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
291 ixgbe_vlan_hw_strip_enable_all(dev);
293 ixgbe_vlan_hw_strip_disable_all(dev);
297 ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
299 struct ixgbe_hw *hw =
300 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
301 struct ixgbe_vf_info *vfinfo =
302 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
303 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
304 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
306 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_ROMPE |
307 IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
308 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
310 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0);
312 /* reset multicast table array for vf */
313 vfinfo[vf].num_vf_mc_hashes = 0;
318 hw->mac.ops.clear_rar(hw, rar_entry);
322 ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
324 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
326 uint32_t reg_offset, vf_shift;
327 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
328 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
330 vf_shift = vf & VFRE_MASK;
331 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0;
333 /* enable transmit and receive for vf */
334 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
335 reg |= (reg | (1 << vf_shift));
336 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);
338 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
339 reg |= (reg | (1 << vf_shift));
340 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
342 /* Enable counting of spoofed packets in the SSVPC register */
343 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
344 reg |= (1 << vf_shift);
345 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
347 ixgbe_vf_reset_event(dev, vf);
351 ixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
353 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
354 struct ixgbe_vf_info *vfinfo =
355 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
356 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
357 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
358 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
360 ixgbe_vf_reset_msg(dev, vf);
362 hw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV);
364 /* reply to reset with ack and vf mac address */
365 msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK;
366 rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);
368 * Piggyback the multicast filter type so VF can compute the
371 msgbuf[3] = hw->mac.mc_filter_type;
372 ixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf);
378 ixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
380 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
381 struct ixgbe_vf_info *vfinfo =
382 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
383 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
384 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
386 if (is_valid_assigned_ether_addr((struct ether_addr*)new_mac)) {
387 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
388 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV);
394 ixgbe_vf_set_multicast(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
396 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
397 struct ixgbe_vf_info *vfinfo =
398 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
399 int nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
400 IXGBE_VT_MSGINFO_SHIFT;
401 uint16_t *hash_list = (uint16_t *)&msgbuf[1];
404 const uint32_t IXGBE_MTA_INDEX_MASK = 0x7F;
405 const uint32_t IXGBE_MTA_BIT_SHIFT = 5;
406 const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1;
410 /* only so many hash values supported */
411 nb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES);
413 /* store the mc entries */
414 vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries;
415 for (i = 0; i < nb_entries; i++) {
416 vfinfo->vf_mc_hashes[i] = hash_list[i];
419 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
420 mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT)
421 & IXGBE_MTA_INDEX_MASK;
422 mta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK;
423 reg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx));
424 reg_val |= (1 << mta_shift);
425 IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val);
432 ixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
435 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
436 struct ixgbe_vf_info *vfinfo =
437 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
439 add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK)
440 >> IXGBE_VT_MSGINFO_SHIFT;
441 vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);
444 vfinfo[vf].vlan_count++;
445 else if (vfinfo[vf].vlan_count)
446 vfinfo[vf].vlan_count--;
447 return hw->mac.ops.set_vfta(hw, vid, vf, (bool)add);
451 ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
453 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
454 uint32_t new_mtu = msgbuf[1];
456 int max_frame = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
458 /* Only X540 supports jumbo frames in IOV mode */
459 if (hw->mac.type != ixgbe_mac_X540)
462 if ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
465 max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) &
466 IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT;
467 if (max_frs < new_mtu) {
468 max_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT;
469 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs);
476 ixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
478 uint16_t mbx_size = IXGBE_VFMAILBOX_SIZE;
479 uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE];
481 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
483 retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf);
485 RTE_LOG(ERR, PMD, "Error mbx recv msg from VF %d\n", vf);
489 /* do nothing with the message already been processed */
490 if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK))
493 /* flush the ack before we write any messages back */
494 IXGBE_WRITE_FLUSH(hw);
496 /* perform VF reset */
497 if (msgbuf[0] == IXGBE_VF_RESET) {
498 return ixgbe_vf_reset(dev, vf, msgbuf);
501 /* check & process VF to PF mailbox message */
502 switch ((msgbuf[0] & 0xFFFF)) {
503 case IXGBE_VF_SET_MAC_ADDR:
504 retval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf);
506 case IXGBE_VF_SET_MULTICAST:
507 retval = ixgbe_vf_set_multicast(dev, vf, msgbuf);
509 case IXGBE_VF_SET_LPE:
510 retval = ixgbe_set_vf_lpe(dev, vf, msgbuf);
512 case IXGBE_VF_SET_VLAN:
513 retval = ixgbe_vf_set_vlan(dev, vf, msgbuf);
516 RTE_LOG(DEBUG, PMD, "Unhandled Msg %8.8x\n", (unsigned) msgbuf[0]);
517 retval = IXGBE_ERR_MBX;
521 /* response the VF according to the message process result */
523 msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;
525 msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK;
527 msgbuf[0] |= IXGBE_VT_MSGTYPE_CTS;
529 ixgbe_write_mbx(hw, msgbuf, 1, vf);
535 ixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
537 uint32_t msg = IXGBE_VT_MSGTYPE_NACK;
538 struct ixgbe_hw *hw =
539 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
541 ixgbe_write_mbx(hw, &msg, 1, vf);
544 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev)
547 struct ixgbe_hw *hw =
548 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
550 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
551 /* check & process vf function level reset */
552 if (!ixgbe_check_for_rst(hw, vf))
553 ixgbe_vf_reset_event(eth_dev, vf);
555 /* check & process vf mailbox messages */
556 if (!ixgbe_check_for_msg(hw, vf))
557 ixgbe_rcv_msg_from_vf(eth_dev, vf);
559 /* check & process acks from vf */
560 if (!ixgbe_check_for_ack(hw, vf))
561 ixgbe_rcv_ack_from_vf(eth_dev, vf);