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42 #include <rte_interrupts.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memcpy.h>
49 #include <rte_malloc.h>
50 #include <rte_random.h>
52 #include "ixgbe/ixgbe_common.h"
53 #include "ixgbe_ethdev.h"
55 #define IXGBE_MAX_VFTA (128)
58 void eth_random_addr(uint8_t *addr)
60 uint64_t rand = rte_rand();
61 uint8_t *p = (uint8_t*)&rand;
63 rte_memcpy(addr, p, ETHER_ADDR_LEN);
64 addr[0] &= 0xfe; /* clear multicast bit */
65 addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
68 static inline uint16_t
69 dev_num_vf(struct rte_eth_dev *eth_dev)
71 return eth_dev->pci_dev->max_vfs;
75 int ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
77 unsigned char vf_mac_addr[ETHER_ADDR_LEN];
78 struct ixgbe_vf_info *vfinfo =
79 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
82 for (vfn = 0; vfn < vf_num; vfn++) {
83 eth_random_addr(vf_mac_addr);
84 /* keep the random address as default */
85 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
93 ixgbe_mb_intr_setup(struct rte_eth_dev *dev)
95 struct ixgbe_interrupt *intr =
96 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
98 intr->mask |= IXGBE_EICR_MAILBOX;
103 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev)
105 struct ixgbe_vf_info **vfinfo =
106 IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
107 struct ixgbe_mirror_info *mirror_info =
108 IXGBE_DEV_PRIVATE_TO_PFDATA(eth_dev->data->dev_private);
109 struct ixgbe_uta_info *uta_info =
110 IXGBE_DEV_PRIVATE_TO_UTA(eth_dev->data->dev_private);
111 struct ixgbe_hw *hw =
112 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
116 PMD_INIT_FUNC_TRACE();
118 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
119 if (0 == (vf_num = dev_num_vf(eth_dev)))
122 *vfinfo = rte_zmalloc("vf_info", sizeof(struct ixgbe_vf_info) * vf_num, 0);
124 rte_panic("Cannot allocate memory for private VF data\n");
126 memset(mirror_info,0,sizeof(struct ixgbe_mirror_info));
127 memset(uta_info,0,sizeof(struct ixgbe_uta_info));
128 hw->mac.mc_filter_type = 0;
130 if (vf_num >= ETH_32_POOLS) {
132 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS;
133 } else if (vf_num >= ETH_16_POOLS) {
135 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS;
138 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS;
141 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
142 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
143 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
145 ixgbe_vf_perm_addr_gen(eth_dev, vf_num);
147 /* init_mailbox_params */
148 hw->mbx.ops.init_params(hw);
150 /* set mb interrupt mask */
151 ixgbe_mb_intr_setup(eth_dev);
156 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev)
158 uint32_t vtctl, fcrth;
159 uint32_t vfre_slot, vfre_offset;
161 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
162 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
163 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
164 uint32_t gpie, gcr_ext;
168 if (0 == (vf_num = dev_num_vf(eth_dev)))
171 /* enable VMDq and set the default pool for PF */
172 vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
173 vtctl |= IXGBE_VMD_CTL_VMDQ_EN;
174 vtctl &= ~IXGBE_VT_CTL_POOL_MASK;
175 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
176 << IXGBE_VT_CTL_POOL_SHIFT;
177 vtctl |= IXGBE_VT_CTL_REPLEN;
178 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
180 vfre_offset = vf_num & VFRE_MASK;
181 vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0;
183 /* Enable pools reserved to PF only */
184 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0) << vfre_offset);
185 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1);
186 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0) << vfre_offset);
187 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1);
189 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
190 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
192 /* clear VMDq map to perment rar 0 */
193 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
195 /* clear VMDq map to scan rar 127 */
196 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0);
197 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0);
199 /* set VMDq map to default PF pool */
200 hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);
203 * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode
205 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
206 gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK;
208 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
209 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
210 gpie |= IXGBE_GPIE_MSIX_MODE;
212 switch (RTE_ETH_DEV_SRIOV(eth_dev).active) {
214 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
215 gpie |= IXGBE_GPIE_VTMODE_64;
218 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32;
219 gpie |= IXGBE_GPIE_VTMODE_32;
222 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_16;
223 gpie |= IXGBE_GPIE_VTMODE_16;
227 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
228 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
231 * enable vlan filtering and allow all vlan tags through
233 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
234 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
235 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
237 /* VFTA - enable all vlan filters */
238 for (i = 0; i < IXGBE_MAX_VFTA; i++) {
239 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
242 /* Enable MAC Anti-Spoofing */
243 hw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num);
245 /* set flow control threshold to max to avoid tx switch hang */
246 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
247 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
248 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
249 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
256 set_rx_mode(struct rte_eth_dev *dev)
258 struct rte_eth_dev_data *dev_data =
259 (struct rte_eth_dev_data*)dev->data->dev_private;
260 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
261 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
262 uint16_t vfn = dev_num_vf(dev);
264 /* Check for Promiscuous and All Multicast modes */
265 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
267 /* set all bits that we expect to always be set */
268 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
269 fctrl |= IXGBE_FCTRL_BAM;
271 /* clear the bits we are changing the status of */
272 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
274 if (dev_data->promiscuous) {
275 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
276 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
278 if (dev_data->all_multicast) {
279 fctrl |= IXGBE_FCTRL_MPE;
280 vmolr |= IXGBE_VMOLR_MPE;
282 vmolr |= IXGBE_VMOLR_ROMPE;
286 if (hw->mac.type != ixgbe_mac_82598EB) {
287 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) &
288 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
290 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr);
293 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
295 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
296 ixgbe_vlan_hw_strip_enable_all(dev);
298 ixgbe_vlan_hw_strip_disable_all(dev);
302 ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
304 struct ixgbe_hw *hw =
305 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
306 struct ixgbe_vf_info *vfinfo =
307 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
308 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
309 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
311 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_ROMPE |
312 IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
313 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
315 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0);
317 /* reset multicast table array for vf */
318 vfinfo[vf].num_vf_mc_hashes = 0;
323 hw->mac.ops.clear_rar(hw, rar_entry);
327 ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
329 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
331 uint32_t reg_offset, vf_shift;
332 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
333 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
335 vf_shift = vf & VFRE_MASK;
336 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0;
338 /* enable transmit and receive for vf */
339 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
340 reg |= (reg | (1 << vf_shift));
341 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);
343 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
344 reg |= (reg | (1 << vf_shift));
345 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
347 /* Enable counting of spoofed packets in the SSVPC register */
348 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
349 reg |= (1 << vf_shift);
350 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
352 ixgbe_vf_reset_event(dev, vf);
356 ixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
358 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
359 struct ixgbe_vf_info *vfinfo =
360 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
361 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
362 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
363 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
365 ixgbe_vf_reset_msg(dev, vf);
367 hw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV);
369 /* reply to reset with ack and vf mac address */
370 msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK;
371 rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);
373 * Piggyback the multicast filter type so VF can compute the
376 msgbuf[3] = hw->mac.mc_filter_type;
377 ixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf);
383 ixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
385 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
386 struct ixgbe_vf_info *vfinfo =
387 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
388 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
389 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
391 if (is_valid_assigned_ether_addr((struct ether_addr*)new_mac)) {
392 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
393 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV);
399 ixgbe_vf_set_multicast(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
401 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
402 struct ixgbe_vf_info *vfinfo =
403 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
404 int nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
405 IXGBE_VT_MSGINFO_SHIFT;
406 uint16_t *hash_list = (uint16_t *)&msgbuf[1];
409 const uint32_t IXGBE_MTA_INDEX_MASK = 0x7F;
410 const uint32_t IXGBE_MTA_BIT_SHIFT = 5;
411 const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1;
415 /* only so many hash values supported */
416 nb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES);
418 /* store the mc entries */
419 vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries;
420 for (i = 0; i < nb_entries; i++) {
421 vfinfo->vf_mc_hashes[i] = hash_list[i];
424 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
425 mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT)
426 & IXGBE_MTA_INDEX_MASK;
427 mta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK;
428 reg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx));
429 reg_val |= (1 << mta_shift);
430 IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val);
437 ixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
440 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
441 struct ixgbe_vf_info *vfinfo =
442 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
444 add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK)
445 >> IXGBE_VT_MSGINFO_SHIFT;
446 vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);
449 vfinfo[vf].vlan_count++;
450 else if (vfinfo[vf].vlan_count)
451 vfinfo[vf].vlan_count--;
452 return hw->mac.ops.set_vfta(hw, vid, vf, (bool)add);
456 ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
458 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
459 uint32_t new_mtu = msgbuf[1];
461 int max_frame = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
463 /* Only X540 supports jumbo frames in IOV mode */
464 if (hw->mac.type != ixgbe_mac_X540)
467 if ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
470 max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) &
471 IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT;
472 if (max_frs < new_mtu) {
473 max_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT;
474 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs);
481 ixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
483 uint16_t mbx_size = IXGBE_VFMAILBOX_SIZE;
484 uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE];
486 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
488 retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf);
490 RTE_LOG(ERR, PMD, "Error mbx recv msg from VF %d\n", vf);
494 /* do nothing with the message already been processed */
495 if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK))
498 /* flush the ack before we write any messages back */
499 IXGBE_WRITE_FLUSH(hw);
501 /* perform VF reset */
502 if (msgbuf[0] == IXGBE_VF_RESET) {
503 return ixgbe_vf_reset(dev, vf, msgbuf);
506 /* check & process VF to PF mailbox message */
507 switch ((msgbuf[0] & 0xFFFF)) {
508 case IXGBE_VF_SET_MAC_ADDR:
509 retval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf);
511 case IXGBE_VF_SET_MULTICAST:
512 retval = ixgbe_vf_set_multicast(dev, vf, msgbuf);
514 case IXGBE_VF_SET_LPE:
515 retval = ixgbe_set_vf_lpe(dev, vf, msgbuf);
517 case IXGBE_VF_SET_VLAN:
518 retval = ixgbe_vf_set_vlan(dev, vf, msgbuf);
521 RTE_LOG(DEBUG, PMD, "Unhandled Msg %8.8x\n", (unsigned) msgbuf[0]);
522 retval = IXGBE_ERR_MBX;
526 /* response the VF according to the message process result */
528 msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;
530 msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK;
532 msgbuf[0] |= IXGBE_VT_MSGTYPE_CTS;
534 ixgbe_write_mbx(hw, msgbuf, 1, vf);
540 ixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
542 uint32_t msg = IXGBE_VT_MSGTYPE_NACK;
543 struct ixgbe_hw *hw =
544 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
546 ixgbe_write_mbx(hw, &msg, 1, vf);
549 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev)
552 struct ixgbe_hw *hw =
553 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
555 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
556 /* check & process vf function level reset */
557 if (!ixgbe_check_for_rst(hw, vf))
558 ixgbe_vf_reset_event(eth_dev, vf);
560 /* check & process vf mailbox messages */
561 if (!ixgbe_check_for_msg(hw, vf))
562 ixgbe_rcv_msg_from_vf(eth_dev, vf);
564 /* check & process acks from vf */
565 if (!ixgbe_check_for_ack(hw, vf))
566 ixgbe_rcv_ack_from_vf(eth_dev, vf);