4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
47 #include <rte_cycles.h>
49 #include <rte_debug.h>
50 #include <rte_interrupts.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_launch.h>
55 #include <rte_tailq.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
80 #include "ixgbe_rxtx.h"
82 #define IXGBE_RSS_OFFLOAD_ALL ( \
88 ETH_RSS_IPV6_TCP_EX | \
93 static inline struct rte_mbuf *
94 rte_rxmbuf_alloc(struct rte_mempool *mp)
98 m = __rte_mbuf_raw_alloc(mp);
99 __rte_mbuf_sanity_check_raw(m, 0);
105 #define RTE_PMD_USE_PREFETCH
108 #ifdef RTE_PMD_USE_PREFETCH
110 * Prefetch a cache line into all cache levels.
112 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
114 #define rte_ixgbe_prefetch(p) do {} while(0)
117 /*********************************************************************
121 **********************************************************************/
124 * Check for descriptors with their DD bit set and free mbufs.
125 * Return the total number of buffers freed.
127 static inline int __attribute__((always_inline))
128 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
130 struct igb_tx_entry *txep;
134 /* check DD bit on threshold descriptor */
135 status = txq->tx_ring[txq->tx_next_dd].wb.status;
136 if (! (status & IXGBE_ADVTXD_STAT_DD))
140 * first buffer to free from S/W ring is at index
141 * tx_next_dd - (tx_rs_thresh-1)
143 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
145 /* prefetch the mbufs that are about to be freed */
146 for (i = 0; i < txq->tx_rs_thresh; ++i)
147 rte_prefetch0((txep + i)->mbuf);
149 /* free buffers one at a time */
150 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
151 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
152 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
156 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
157 rte_pktmbuf_free_seg(txep->mbuf);
162 /* buffers were freed, update counters */
163 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
164 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
165 if (txq->tx_next_dd >= txq->nb_tx_desc)
166 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
168 return txq->tx_rs_thresh;
171 /* Populate 4 descriptors with data from 4 mbufs */
173 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
175 uint64_t buf_dma_addr;
179 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
180 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
181 pkt_len = (*pkts)->data_len;
183 /* write data to descriptor */
184 txdp->read.buffer_addr = buf_dma_addr;
185 txdp->read.cmd_type_len =
186 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
187 txdp->read.olinfo_status =
188 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
192 /* Populate 1 descriptor with data from 1 mbuf */
194 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
196 uint64_t buf_dma_addr;
199 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
200 pkt_len = (*pkts)->data_len;
202 /* write data to descriptor */
203 txdp->read.buffer_addr = buf_dma_addr;
204 txdp->read.cmd_type_len =
205 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
206 txdp->read.olinfo_status =
207 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
211 * Fill H/W descriptor ring with mbuf data.
212 * Copy mbuf pointers to the S/W ring.
215 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
218 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
219 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
220 const int N_PER_LOOP = 4;
221 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
222 int mainpart, leftover;
226 * Process most of the packets in chunks of N pkts. Any
227 * leftover packets will get processed one at a time.
229 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
230 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
231 for (i = 0; i < mainpart; i += N_PER_LOOP) {
232 /* Copy N mbuf pointers to the S/W ring */
233 for (j = 0; j < N_PER_LOOP; ++j) {
234 (txep + i + j)->mbuf = *(pkts + i + j);
236 tx4(txdp + i, pkts + i);
239 if (unlikely(leftover > 0)) {
240 for (i = 0; i < leftover; ++i) {
241 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
242 tx1(txdp + mainpart + i, pkts + mainpart + i);
247 static inline uint16_t
248 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
251 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
252 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
256 * Begin scanning the H/W ring for done descriptors when the
257 * number of available descriptors drops below tx_free_thresh. For
258 * each done descriptor, free the associated buffer.
260 if (txq->nb_tx_free < txq->tx_free_thresh)
261 ixgbe_tx_free_bufs(txq);
263 /* Only use descriptors that are available */
264 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
265 if (unlikely(nb_pkts == 0))
268 /* Use exactly nb_pkts descriptors */
269 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
272 * At this point, we know there are enough descriptors in the
273 * ring to transmit all the packets. This assumes that each
274 * mbuf contains a single segment, and that no new offloads
275 * are expected, which would require a new context descriptor.
279 * See if we're going to wrap-around. If so, handle the top
280 * of the descriptor ring first, then do the bottom. If not,
281 * the processing looks just like the "bottom" part anyway...
283 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
284 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
285 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
288 * We know that the last descriptor in the ring will need to
289 * have its RS bit set because tx_rs_thresh has to be
290 * a divisor of the ring size
292 tx_r[txq->tx_next_rs].read.cmd_type_len |=
293 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
294 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
299 /* Fill H/W descriptor ring with mbuf data */
300 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
301 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
304 * Determine if RS bit should be set
305 * This is what we actually want:
306 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
307 * but instead of subtracting 1 and doing >=, we can just do
308 * greater than without subtracting.
310 if (txq->tx_tail > txq->tx_next_rs) {
311 tx_r[txq->tx_next_rs].read.cmd_type_len |=
312 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
313 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
315 if (txq->tx_next_rs >= txq->nb_tx_desc)
316 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
320 * Check for wrap-around. This would only happen if we used
321 * up to the last descriptor in the ring, no more, no less.
323 if (txq->tx_tail >= txq->nb_tx_desc)
326 /* update tail pointer */
328 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
334 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
339 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
340 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
341 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
343 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
347 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
348 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
349 nb_tx = (uint16_t)(nb_tx + ret);
350 nb_pkts = (uint16_t)(nb_pkts - ret);
359 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
360 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
361 uint64_t ol_flags, uint32_t vlan_macip_lens)
363 uint32_t type_tucmd_mlhl;
364 uint32_t mss_l4len_idx;
368 ctx_idx = txq->ctx_curr;
372 if (ol_flags & PKT_TX_VLAN_PKT) {
373 cmp_mask |= TX_VLAN_CMP_MASK;
376 if (ol_flags & PKT_TX_IP_CKSUM) {
377 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
378 cmp_mask |= TX_MAC_LEN_CMP_MASK;
381 /* Specify which HW CTX to upload. */
382 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
383 switch (ol_flags & PKT_TX_L4_MASK) {
384 case PKT_TX_UDP_CKSUM:
385 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
386 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
387 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
388 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
390 case PKT_TX_TCP_CKSUM:
391 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
392 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
393 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
394 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
396 case PKT_TX_SCTP_CKSUM:
397 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
398 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
399 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
400 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
403 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
404 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
408 txq->ctx_cache[ctx_idx].flags = ol_flags;
409 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
410 txq->ctx_cache[ctx_idx].vlan_macip_lens.data =
411 vlan_macip_lens & cmp_mask;
413 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
414 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
415 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
416 ctx_txd->seqnum_seed = 0;
420 * Check which hardware context can be used. Use the existing match
421 * or create a new context descriptor.
423 static inline uint32_t
424 what_advctx_update(struct igb_tx_queue *txq, uint64_t flags,
425 uint32_t vlan_macip_lens)
427 /* If match with the current used context */
428 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
429 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
430 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
431 return txq->ctx_curr;
434 /* What if match with the next context */
436 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
437 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
438 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
439 return txq->ctx_curr;
442 /* Mismatch, use the previous context */
443 return (IXGBE_CTX_NUM);
446 static inline uint32_t
447 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
449 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
450 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
453 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
454 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
458 static inline uint32_t
459 tx_desc_vlan_flags_to_cmdtype(uint64_t ol_flags)
461 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
462 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
465 /* Default RS bit threshold values */
466 #ifndef DEFAULT_TX_RS_THRESH
467 #define DEFAULT_TX_RS_THRESH 32
469 #ifndef DEFAULT_TX_FREE_THRESH
470 #define DEFAULT_TX_FREE_THRESH 32
473 /* Reset transmit descriptors after they have been used */
475 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
477 struct igb_tx_entry *sw_ring = txq->sw_ring;
478 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
479 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
480 uint16_t nb_tx_desc = txq->nb_tx_desc;
481 uint16_t desc_to_clean_to;
482 uint16_t nb_tx_to_clean;
484 /* Determine the last descriptor needing to be cleaned */
485 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
486 if (desc_to_clean_to >= nb_tx_desc)
487 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
489 /* Check to make sure the last descriptor to clean is done */
490 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
491 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
493 PMD_TX_FREE_LOG(DEBUG,
494 "TX descriptor %4u is not done"
495 "(port=%d queue=%d)",
497 txq->port_id, txq->queue_id);
498 /* Failed to clean any descriptors, better luck next time */
502 /* Figure out how many descriptors will be cleaned */
503 if (last_desc_cleaned > desc_to_clean_to)
504 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
507 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
510 PMD_TX_FREE_LOG(DEBUG,
511 "Cleaning %4u TX descriptors: %4u to %4u "
512 "(port=%d queue=%d)",
513 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
514 txq->port_id, txq->queue_id);
517 * The last descriptor to clean is done, so that means all the
518 * descriptors from the last descriptor that was cleaned
519 * up to the last descriptor with the RS bit set
520 * are done. Only reset the threshold descriptor.
522 txr[desc_to_clean_to].wb.status = 0;
524 /* Update the txq to reflect the last descriptor that was cleaned */
525 txq->last_desc_cleaned = desc_to_clean_to;
526 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
533 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
536 struct igb_tx_queue *txq;
537 struct igb_tx_entry *sw_ring;
538 struct igb_tx_entry *txe, *txn;
539 volatile union ixgbe_adv_tx_desc *txr;
540 volatile union ixgbe_adv_tx_desc *txd;
541 struct rte_mbuf *tx_pkt;
542 struct rte_mbuf *m_seg;
543 union ixgbe_vlan_macip vlan_macip_lens;
544 uint64_t buf_dma_addr;
545 uint32_t olinfo_status;
546 uint32_t cmd_type_len;
559 sw_ring = txq->sw_ring;
561 tx_id = txq->tx_tail;
562 txe = &sw_ring[tx_id];
564 /* Determine if the descriptor ring needs to be cleaned. */
565 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
566 ixgbe_xmit_cleanup(txq);
570 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
573 pkt_len = tx_pkt->pkt_len;
575 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
578 * Determine how many (if any) context descriptors
579 * are needed for offload functionality.
581 ol_flags = tx_pkt->ol_flags;
582 vlan_macip_lens.f.vlan_tci = tx_pkt->vlan_tci;
583 vlan_macip_lens.f.l2_l3_len = tx_pkt->l2_l3_len;
585 /* If hardware offload required */
586 tx_ol_req = ol_flags & PKT_TX_OFFLOAD_MASK;
588 /* If new context need be built or reuse the exist ctx. */
589 ctx = what_advctx_update(txq, tx_ol_req,
590 vlan_macip_lens.data);
591 /* Only allocate context descriptor if required*/
592 new_ctx = (ctx == IXGBE_CTX_NUM);
597 * Keep track of how many descriptors are used this loop
598 * This will always be the number of segments + the number of
599 * Context descriptors required to transmit the packet
601 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
604 * The number of descriptors that must be allocated for a
605 * packet is the number of segments of that packet, plus 1
606 * Context Descriptor for the hardware offload, if any.
607 * Determine the last TX descriptor to allocate in the TX ring
608 * for the packet, starting from the current position (tx_id)
611 tx_last = (uint16_t) (tx_id + nb_used - 1);
614 if (tx_last >= txq->nb_tx_desc)
615 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
617 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
618 " tx_first=%u tx_last=%u\n",
619 (unsigned) txq->port_id,
620 (unsigned) txq->queue_id,
626 * Make sure there are enough TX descriptors available to
627 * transmit the entire packet.
628 * nb_used better be less than or equal to txq->tx_rs_thresh
630 if (nb_used > txq->nb_tx_free) {
631 PMD_TX_FREE_LOG(DEBUG,
632 "Not enough free TX descriptors "
633 "nb_used=%4u nb_free=%4u "
634 "(port=%d queue=%d)",
635 nb_used, txq->nb_tx_free,
636 txq->port_id, txq->queue_id);
638 if (ixgbe_xmit_cleanup(txq) != 0) {
639 /* Could not clean any descriptors */
645 /* nb_used better be <= txq->tx_rs_thresh */
646 if (unlikely(nb_used > txq->tx_rs_thresh)) {
647 PMD_TX_FREE_LOG(DEBUG,
648 "The number of descriptors needed to "
649 "transmit the packet exceeds the "
650 "RS bit threshold. This will impact "
652 "nb_used=%4u nb_free=%4u "
654 "(port=%d queue=%d)",
655 nb_used, txq->nb_tx_free,
657 txq->port_id, txq->queue_id);
659 * Loop here until there are enough TX
660 * descriptors or until the ring cannot be
663 while (nb_used > txq->nb_tx_free) {
664 if (ixgbe_xmit_cleanup(txq) != 0) {
666 * Could not clean any
678 * By now there are enough free TX descriptors to transmit
683 * Set common flags of all TX Data Descriptors.
685 * The following bits must be set in all Data Descriptors:
686 * - IXGBE_ADVTXD_DTYP_DATA
687 * - IXGBE_ADVTXD_DCMD_DEXT
689 * The following bits must be set in the first Data Descriptor
690 * and are ignored in the other ones:
691 * - IXGBE_ADVTXD_DCMD_IFCS
692 * - IXGBE_ADVTXD_MAC_1588
693 * - IXGBE_ADVTXD_DCMD_VLE
695 * The following bits must only be set in the last Data
697 * - IXGBE_TXD_CMD_EOP
699 * The following bits can be set in any Data Descriptor, but
700 * are only set in the last Data Descriptor:
703 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
704 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
705 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
706 #ifdef RTE_LIBRTE_IEEE1588
707 if (ol_flags & PKT_TX_IEEE1588_TMST)
708 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
713 * Setup the TX Advanced Context Descriptor if required
716 volatile struct ixgbe_adv_tx_context_desc *
719 ctx_txd = (volatile struct
720 ixgbe_adv_tx_context_desc *)
723 txn = &sw_ring[txe->next_id];
724 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
726 if (txe->mbuf != NULL) {
727 rte_pktmbuf_free_seg(txe->mbuf);
731 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
732 vlan_macip_lens.data);
734 txe->last_id = tx_last;
735 tx_id = txe->next_id;
740 * Setup the TX Advanced Data Descriptor,
741 * This path will go through
742 * whatever new/reuse the context descriptor
744 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
745 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
746 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
752 txn = &sw_ring[txe->next_id];
754 if (txe->mbuf != NULL)
755 rte_pktmbuf_free_seg(txe->mbuf);
759 * Set up Transmit Data Descriptor.
761 slen = m_seg->data_len;
762 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
763 txd->read.buffer_addr =
764 rte_cpu_to_le_64(buf_dma_addr);
765 txd->read.cmd_type_len =
766 rte_cpu_to_le_32(cmd_type_len | slen);
767 txd->read.olinfo_status =
768 rte_cpu_to_le_32(olinfo_status);
769 txe->last_id = tx_last;
770 tx_id = txe->next_id;
773 } while (m_seg != NULL);
776 * The last packet data descriptor needs End Of Packet (EOP)
778 cmd_type_len |= IXGBE_TXD_CMD_EOP;
779 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
780 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
782 /* Set RS bit only on threshold packets' last descriptor */
783 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
784 PMD_TX_FREE_LOG(DEBUG,
785 "Setting RS bit on TXD id="
786 "%4u (port=%d queue=%d)",
787 tx_last, txq->port_id, txq->queue_id);
789 cmd_type_len |= IXGBE_TXD_CMD_RS;
791 /* Update txq RS bit counters */
794 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
800 * Set the Transmit Descriptor Tail (TDT)
802 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
803 (unsigned) txq->port_id, (unsigned) txq->queue_id,
804 (unsigned) tx_id, (unsigned) nb_tx);
805 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
806 txq->tx_tail = tx_id;
811 /*********************************************************************
815 **********************************************************************/
816 static inline uint64_t
817 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
821 static uint64_t ip_pkt_types_map[16] = {
822 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
823 PKT_RX_IPV6_HDR, 0, 0, 0,
824 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
825 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
828 static uint64_t ip_rss_types_map[16] = {
829 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
830 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
831 PKT_RX_RSS_HASH, 0, 0, 0,
832 0, 0, 0, PKT_RX_FDIR,
835 #ifdef RTE_LIBRTE_IEEE1588
836 static uint32_t ip_pkt_etqf_map[8] = {
837 0, 0, 0, PKT_RX_IEEE1588_PTP,
841 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
842 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
843 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
845 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
846 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
849 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
852 static inline uint64_t
853 rx_desc_status_to_pkt_flags(uint32_t rx_status)
858 * Check if VLAN present only.
859 * Do not check whether L3/L4 rx checksum done by NIC or not,
860 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
862 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
864 #ifdef RTE_LIBRTE_IEEE1588
865 if (rx_status & IXGBE_RXD_STAT_TMST)
866 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
871 static inline uint64_t
872 rx_desc_error_to_pkt_flags(uint32_t rx_status)
875 * Bit 31: IPE, IPv4 checksum error
876 * Bit 30: L4I, L4I integrity error
878 static uint64_t error_to_pkt_flags_map[4] = {
879 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
880 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
882 return error_to_pkt_flags_map[(rx_status >>
883 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
886 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
888 * LOOK_AHEAD defines how many desc statuses to check beyond the
889 * current descriptor.
890 * It must be a pound define for optimal performance.
891 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
892 * function only works with LOOK_AHEAD=8.
895 #if (LOOK_AHEAD != 8)
896 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
899 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
901 volatile union ixgbe_adv_rx_desc *rxdp;
902 struct igb_rx_entry *rxep;
905 int s[LOOK_AHEAD], nb_dd;
909 /* get references to current descriptor and S/W ring entry */
910 rxdp = &rxq->rx_ring[rxq->rx_tail];
911 rxep = &rxq->sw_ring[rxq->rx_tail];
913 /* check to make sure there is at least 1 packet to receive */
914 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
918 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
919 * reference packets that are ready to be received.
921 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
922 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
924 /* Read desc statuses backwards to avoid race condition */
925 for (j = LOOK_AHEAD-1; j >= 0; --j)
926 s[j] = rxdp[j].wb.upper.status_error;
928 /* Compute how many status bits were set */
930 for (j = 0; j < LOOK_AHEAD; ++j)
931 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
935 /* Translate descriptor info to mbuf format */
936 for (j = 0; j < nb_dd; ++j) {
938 pkt_len = (uint16_t)(rxdp[j].wb.upper.length -
940 mb->data_len = pkt_len;
941 mb->pkt_len = pkt_len;
942 mb->vlan_tci = rxdp[j].wb.upper.vlan;
943 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
945 /* convert descriptor fields to rte mbuf flags */
946 mb->ol_flags = rx_desc_hlen_type_rss_to_pkt_flags(
947 rxdp[j].wb.lower.lo_dword.data);
948 /* reuse status field from scan list */
949 mb->ol_flags = mb->ol_flags |
950 rx_desc_status_to_pkt_flags(s[j]);
951 mb->ol_flags = mb->ol_flags |
952 rx_desc_error_to_pkt_flags(s[j]);
955 /* Move mbuf pointers from the S/W ring to the stage */
956 for (j = 0; j < LOOK_AHEAD; ++j) {
957 rxq->rx_stage[i + j] = rxep[j].mbuf;
960 /* stop if all requested packets could not be received */
961 if (nb_dd != LOOK_AHEAD)
965 /* clear software ring entries so we can cleanup correctly */
966 for (i = 0; i < nb_rx; ++i) {
967 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
975 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
977 volatile union ixgbe_adv_rx_desc *rxdp;
978 struct igb_rx_entry *rxep;
984 /* allocate buffers in bulk directly into the S/W ring */
985 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
986 (rxq->rx_free_thresh - 1));
987 rxep = &rxq->sw_ring[alloc_idx];
988 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
989 rxq->rx_free_thresh);
990 if (unlikely(diag != 0))
993 rxdp = &rxq->rx_ring[alloc_idx];
994 for (i = 0; i < rxq->rx_free_thresh; ++i) {
995 /* populate the static rte mbuf fields */
997 rte_mbuf_refcnt_set(mb, 1);
999 mb->data_off = RTE_PKTMBUF_HEADROOM;
1001 mb->port = rxq->port_id;
1003 /* populate the descriptors */
1004 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1005 rxdp[i].read.hdr_addr = dma_addr;
1006 rxdp[i].read.pkt_addr = dma_addr;
1009 /* update tail pointer */
1011 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1013 /* update state of internal queue structure */
1014 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1015 rxq->rx_free_thresh);
1016 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1017 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1023 static inline uint16_t
1024 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1027 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1030 /* how many packets are ready to return? */
1031 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1033 /* copy mbuf pointers to the application's packet list */
1034 for (i = 0; i < nb_pkts; ++i)
1035 rx_pkts[i] = stage[i];
1037 /* update internal queue state */
1038 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1039 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1044 static inline uint16_t
1045 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1048 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1051 /* Any previously recv'd pkts will be returned from the Rx stage */
1052 if (rxq->rx_nb_avail)
1053 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1055 /* Scan the H/W ring for packets to receive */
1056 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1058 /* update internal queue state */
1059 rxq->rx_next_avail = 0;
1060 rxq->rx_nb_avail = nb_rx;
1061 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1063 /* if required, allocate new buffers to replenish descriptors */
1064 if (rxq->rx_tail > rxq->rx_free_trigger) {
1065 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1067 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1068 "queue_id=%u\n", (unsigned) rxq->port_id,
1069 (unsigned) rxq->queue_id);
1071 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1072 rxq->rx_free_thresh;
1075 * Need to rewind any previous receives if we cannot
1076 * allocate new buffers to replenish the old ones.
1078 rxq->rx_nb_avail = 0;
1079 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1080 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1081 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1087 if (rxq->rx_tail >= rxq->nb_rx_desc)
1090 /* received any packets this loop? */
1091 if (rxq->rx_nb_avail)
1092 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1097 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1099 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1104 if (unlikely(nb_pkts == 0))
1107 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1108 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1110 /* request is relatively large, chunk it up */
1114 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1115 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1116 nb_rx = (uint16_t)(nb_rx + ret);
1117 nb_pkts = (uint16_t)(nb_pkts - ret);
1124 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1127 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1130 struct igb_rx_queue *rxq;
1131 volatile union ixgbe_adv_rx_desc *rx_ring;
1132 volatile union ixgbe_adv_rx_desc *rxdp;
1133 struct igb_rx_entry *sw_ring;
1134 struct igb_rx_entry *rxe;
1135 struct rte_mbuf *rxm;
1136 struct rte_mbuf *nmb;
1137 union ixgbe_adv_rx_desc rxd;
1140 uint32_t hlen_type_rss;
1150 rx_id = rxq->rx_tail;
1151 rx_ring = rxq->rx_ring;
1152 sw_ring = rxq->sw_ring;
1153 while (nb_rx < nb_pkts) {
1155 * The order of operations here is important as the DD status
1156 * bit must not be read after any other descriptor fields.
1157 * rx_ring and rxdp are pointing to volatile data so the order
1158 * of accesses cannot be reordered by the compiler. If they were
1159 * not volatile, they could be reordered which could lead to
1160 * using invalid descriptor fields when read from rxd.
1162 rxdp = &rx_ring[rx_id];
1163 staterr = rxdp->wb.upper.status_error;
1164 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1171 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1172 * is likely to be invalid and to be dropped by the various
1173 * validation checks performed by the network stack.
1175 * Allocate a new mbuf to replenish the RX ring descriptor.
1176 * If the allocation fails:
1177 * - arrange for that RX descriptor to be the first one
1178 * being parsed the next time the receive function is
1179 * invoked [on the same queue].
1181 * - Stop parsing the RX ring and return immediately.
1183 * This policy do not drop the packet received in the RX
1184 * descriptor for which the allocation of a new mbuf failed.
1185 * Thus, it allows that packet to be later retrieved if
1186 * mbuf have been freed in the mean time.
1187 * As a side effect, holding RX descriptors instead of
1188 * systematically giving them back to the NIC may lead to
1189 * RX ring exhaustion situations.
1190 * However, the NIC can gracefully prevent such situations
1191 * to happen by sending specific "back-pressure" flow control
1192 * frames to its peer(s).
1194 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1195 "ext_err_stat=0x%08x pkt_len=%u\n",
1196 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1197 (unsigned) rx_id, (unsigned) staterr,
1198 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1200 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1202 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1203 "queue_id=%u\n", (unsigned) rxq->port_id,
1204 (unsigned) rxq->queue_id);
1205 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1210 rxe = &sw_ring[rx_id];
1212 if (rx_id == rxq->nb_rx_desc)
1215 /* Prefetch next mbuf while processing current one. */
1216 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1219 * When next RX descriptor is on a cache-line boundary,
1220 * prefetch the next 4 RX descriptors and the next 8 pointers
1223 if ((rx_id & 0x3) == 0) {
1224 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1225 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1231 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1232 rxdp->read.hdr_addr = dma_addr;
1233 rxdp->read.pkt_addr = dma_addr;
1236 * Initialize the returned mbuf.
1237 * 1) setup generic mbuf fields:
1238 * - number of segments,
1241 * - RX port identifier.
1242 * 2) integrate hardware offload data, if any:
1243 * - RSS flag & hash,
1244 * - IP checksum flag,
1245 * - VLAN TCI, if any,
1248 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1250 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1251 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1254 rxm->pkt_len = pkt_len;
1255 rxm->data_len = pkt_len;
1256 rxm->port = rxq->port_id;
1258 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1259 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1260 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1262 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1263 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1264 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1265 rxm->ol_flags = pkt_flags;
1267 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1268 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1269 else if (pkt_flags & PKT_RX_FDIR) {
1270 rxm->hash.fdir.hash =
1271 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1272 & IXGBE_ATR_HASH_MASK);
1273 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1276 * Store the mbuf address into the next entry of the array
1277 * of returned packets.
1279 rx_pkts[nb_rx++] = rxm;
1281 rxq->rx_tail = rx_id;
1284 * If the number of free RX descriptors is greater than the RX free
1285 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1287 * Update the RDT with the value of the last processed RX descriptor
1288 * minus 1, to guarantee that the RDT register is never equal to the
1289 * RDH register, which creates a "full" ring situtation from the
1290 * hardware point of view...
1292 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1293 if (nb_hold > rxq->rx_free_thresh) {
1294 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1295 "nb_hold=%u nb_rx=%u\n",
1296 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1297 (unsigned) rx_id, (unsigned) nb_hold,
1299 rx_id = (uint16_t) ((rx_id == 0) ?
1300 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1301 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1304 rxq->nb_rx_hold = nb_hold;
1309 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1312 struct igb_rx_queue *rxq;
1313 volatile union ixgbe_adv_rx_desc *rx_ring;
1314 volatile union ixgbe_adv_rx_desc *rxdp;
1315 struct igb_rx_entry *sw_ring;
1316 struct igb_rx_entry *rxe;
1317 struct rte_mbuf *first_seg;
1318 struct rte_mbuf *last_seg;
1319 struct rte_mbuf *rxm;
1320 struct rte_mbuf *nmb;
1321 union ixgbe_adv_rx_desc rxd;
1322 uint64_t dma; /* Physical address of mbuf data buffer */
1324 uint32_t hlen_type_rss;
1334 rx_id = rxq->rx_tail;
1335 rx_ring = rxq->rx_ring;
1336 sw_ring = rxq->sw_ring;
1339 * Retrieve RX context of current packet, if any.
1341 first_seg = rxq->pkt_first_seg;
1342 last_seg = rxq->pkt_last_seg;
1344 while (nb_rx < nb_pkts) {
1347 * The order of operations here is important as the DD status
1348 * bit must not be read after any other descriptor fields.
1349 * rx_ring and rxdp are pointing to volatile data so the order
1350 * of accesses cannot be reordered by the compiler. If they were
1351 * not volatile, they could be reordered which could lead to
1352 * using invalid descriptor fields when read from rxd.
1354 rxdp = &rx_ring[rx_id];
1355 staterr = rxdp->wb.upper.status_error;
1356 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1363 * Allocate a new mbuf to replenish the RX ring descriptor.
1364 * If the allocation fails:
1365 * - arrange for that RX descriptor to be the first one
1366 * being parsed the next time the receive function is
1367 * invoked [on the same queue].
1369 * - Stop parsing the RX ring and return immediately.
1371 * This policy does not drop the packet received in the RX
1372 * descriptor for which the allocation of a new mbuf failed.
1373 * Thus, it allows that packet to be later retrieved if
1374 * mbuf have been freed in the mean time.
1375 * As a side effect, holding RX descriptors instead of
1376 * systematically giving them back to the NIC may lead to
1377 * RX ring exhaustion situations.
1378 * However, the NIC can gracefully prevent such situations
1379 * to happen by sending specific "back-pressure" flow control
1380 * frames to its peer(s).
1382 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
1383 "staterr=0x%x data_len=%u\n",
1384 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1385 (unsigned) rx_id, (unsigned) staterr,
1386 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1388 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1390 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1391 "queue_id=%u\n", (unsigned) rxq->port_id,
1392 (unsigned) rxq->queue_id);
1393 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1398 rxe = &sw_ring[rx_id];
1400 if (rx_id == rxq->nb_rx_desc)
1403 /* Prefetch next mbuf while processing current one. */
1404 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1407 * When next RX descriptor is on a cache-line boundary,
1408 * prefetch the next 4 RX descriptors and the next 8 pointers
1411 if ((rx_id & 0x3) == 0) {
1412 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1413 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1417 * Update RX descriptor with the physical address of the new
1418 * data buffer of the new allocated mbuf.
1422 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1423 rxdp->read.hdr_addr = dma;
1424 rxdp->read.pkt_addr = dma;
1427 * Set data length & data buffer address of mbuf.
1429 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1430 rxm->data_len = data_len;
1431 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1434 * If this is the first buffer of the received packet,
1435 * set the pointer to the first mbuf of the packet and
1436 * initialize its context.
1437 * Otherwise, update the total length and the number of segments
1438 * of the current scattered packet, and update the pointer to
1439 * the last mbuf of the current packet.
1441 if (first_seg == NULL) {
1443 first_seg->pkt_len = data_len;
1444 first_seg->nb_segs = 1;
1446 first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
1448 first_seg->nb_segs++;
1449 last_seg->next = rxm;
1453 * If this is not the last buffer of the received packet,
1454 * update the pointer to the last mbuf of the current scattered
1455 * packet and continue to parse the RX ring.
1457 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1463 * This is the last buffer of the received packet.
1464 * If the CRC is not stripped by the hardware:
1465 * - Subtract the CRC length from the total packet length.
1466 * - If the last buffer only contains the whole CRC or a part
1467 * of it, free the mbuf associated to the last buffer.
1468 * If part of the CRC is also contained in the previous
1469 * mbuf, subtract the length of that CRC part from the
1470 * data length of the previous mbuf.
1473 if (unlikely(rxq->crc_len > 0)) {
1474 first_seg->pkt_len -= ETHER_CRC_LEN;
1475 if (data_len <= ETHER_CRC_LEN) {
1476 rte_pktmbuf_free_seg(rxm);
1477 first_seg->nb_segs--;
1478 last_seg->data_len = (uint16_t)
1479 (last_seg->data_len -
1480 (ETHER_CRC_LEN - data_len));
1481 last_seg->next = NULL;
1484 (uint16_t) (data_len - ETHER_CRC_LEN);
1488 * Initialize the first mbuf of the returned packet:
1489 * - RX port identifier,
1490 * - hardware offload data, if any:
1491 * - RSS flag & hash,
1492 * - IP checksum flag,
1493 * - VLAN TCI, if any,
1496 first_seg->port = rxq->port_id;
1499 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1500 * set in the pkt_flags field.
1502 first_seg->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1503 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1504 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1505 pkt_flags = (uint16_t)(pkt_flags |
1506 rx_desc_status_to_pkt_flags(staterr));
1507 pkt_flags = (uint16_t)(pkt_flags |
1508 rx_desc_error_to_pkt_flags(staterr));
1509 first_seg->ol_flags = pkt_flags;
1511 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1512 first_seg->hash.rss = rxd.wb.lower.hi_dword.rss;
1513 else if (pkt_flags & PKT_RX_FDIR) {
1514 first_seg->hash.fdir.hash =
1515 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1516 & IXGBE_ATR_HASH_MASK);
1517 first_seg->hash.fdir.id =
1518 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1521 /* Prefetch data of first segment, if configured to do so. */
1522 rte_packet_prefetch((char *)first_seg->buf_addr +
1523 first_seg->data_off);
1526 * Store the mbuf address into the next entry of the array
1527 * of returned packets.
1529 rx_pkts[nb_rx++] = first_seg;
1532 * Setup receipt context for a new packet.
1538 * Record index of the next RX descriptor to probe.
1540 rxq->rx_tail = rx_id;
1543 * Save receive context.
1545 rxq->pkt_first_seg = first_seg;
1546 rxq->pkt_last_seg = last_seg;
1549 * If the number of free RX descriptors is greater than the RX free
1550 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1552 * Update the RDT with the value of the last processed RX descriptor
1553 * minus 1, to guarantee that the RDT register is never equal to the
1554 * RDH register, which creates a "full" ring situtation from the
1555 * hardware point of view...
1557 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1558 if (nb_hold > rxq->rx_free_thresh) {
1559 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1560 "nb_hold=%u nb_rx=%u\n",
1561 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1562 (unsigned) rx_id, (unsigned) nb_hold,
1564 rx_id = (uint16_t) ((rx_id == 0) ?
1565 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1566 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1569 rxq->nb_rx_hold = nb_hold;
1573 /*********************************************************************
1575 * Queue management functions
1577 **********************************************************************/
1580 * Rings setup and release.
1582 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1583 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1584 * also optimize cache line size effect. H/W supports up to cache line size 128.
1586 #define IXGBE_ALIGN 128
1589 * Maximum number of Ring Descriptors.
1591 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1592 * descriptors should meet the following condition:
1593 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1595 #define IXGBE_MIN_RING_DESC 32
1596 #define IXGBE_MAX_RING_DESC 4096
1599 * Create memzone for HW rings. malloc can't be used as the physical address is
1600 * needed. If the memzone is already created, then this function returns a ptr
1603 static const struct rte_memzone *
1604 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1605 uint16_t queue_id, uint32_t ring_size, int socket_id)
1607 char z_name[RTE_MEMZONE_NAMESIZE];
1608 const struct rte_memzone *mz;
1610 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1611 dev->driver->pci_drv.name, ring_name,
1612 dev->data->port_id, queue_id);
1614 mz = rte_memzone_lookup(z_name);
1618 #ifdef RTE_LIBRTE_XEN_DOM0
1619 return rte_memzone_reserve_bounded(z_name, ring_size,
1620 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1622 return rte_memzone_reserve_aligned(z_name, ring_size,
1623 socket_id, 0, IXGBE_ALIGN);
1628 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1632 if (txq->sw_ring != NULL) {
1633 for (i = 0; i < txq->nb_tx_desc; i++) {
1634 if (txq->sw_ring[i].mbuf != NULL) {
1635 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1636 txq->sw_ring[i].mbuf = NULL;
1643 ixgbe_tx_free_swring(struct igb_tx_queue *txq)
1646 txq->sw_ring != NULL)
1647 rte_free(txq->sw_ring);
1651 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1653 if (txq != NULL && txq->ops != NULL) {
1654 txq->ops->release_mbufs(txq);
1655 txq->ops->free_swring(txq);
1661 ixgbe_dev_tx_queue_release(void *txq)
1663 ixgbe_tx_queue_release(txq);
1666 /* (Re)set dynamic igb_tx_queue fields to defaults */
1668 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1670 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1672 struct igb_tx_entry *txe = txq->sw_ring;
1675 /* Zero out HW ring memory */
1676 for (i = 0; i < txq->nb_tx_desc; i++) {
1677 txq->tx_ring[i] = zeroed_desc;
1680 /* Initialize SW ring entries */
1681 prev = (uint16_t) (txq->nb_tx_desc - 1);
1682 for (i = 0; i < txq->nb_tx_desc; i++) {
1683 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1684 txd->wb.status = IXGBE_TXD_STAT_DD;
1687 txe[prev].next_id = i;
1691 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1692 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1695 txq->nb_tx_used = 0;
1697 * Always allow 1 descriptor to be un-allocated to avoid
1698 * a H/W race condition
1700 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1701 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1703 memset((void*)&txq->ctx_cache, 0,
1704 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1707 static struct ixgbe_txq_ops def_txq_ops = {
1708 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1709 .free_swring = ixgbe_tx_free_swring,
1710 .reset = ixgbe_reset_tx_queue,
1714 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1717 unsigned int socket_id,
1718 const struct rte_eth_txconf *tx_conf)
1720 const struct rte_memzone *tz;
1721 struct igb_tx_queue *txq;
1722 struct ixgbe_hw *hw;
1723 uint16_t tx_rs_thresh, tx_free_thresh;
1725 PMD_INIT_FUNC_TRACE();
1726 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1729 * Validate number of transmit descriptors.
1730 * It must not exceed hardware maximum, and must be multiple
1733 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1734 (nb_desc > IXGBE_MAX_RING_DESC) ||
1735 (nb_desc < IXGBE_MIN_RING_DESC)) {
1740 * The following two parameters control the setting of the RS bit on
1741 * transmit descriptors.
1742 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1743 * descriptors have been used.
1744 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1745 * descriptors are used or if the number of descriptors required
1746 * to transmit a packet is greater than the number of free TX
1748 * The following constraints must be satisfied:
1749 * tx_rs_thresh must be greater than 0.
1750 * tx_rs_thresh must be less than the size of the ring minus 2.
1751 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1752 * tx_rs_thresh must be a divisor of the ring size.
1753 * tx_free_thresh must be greater than 0.
1754 * tx_free_thresh must be less than the size of the ring minus 3.
1755 * One descriptor in the TX ring is used as a sentinel to avoid a
1756 * H/W race condition, hence the maximum threshold constraints.
1757 * When set to zero use default values.
1759 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1760 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1761 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1762 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1763 if (tx_rs_thresh >= (nb_desc - 2)) {
1764 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the number "
1765 "of TX descriptors minus 2. (tx_rs_thresh=%u port=%d "
1766 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1767 (int)dev->data->port_id, (int)queue_idx);
1770 if (tx_free_thresh >= (nb_desc - 3)) {
1771 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the "
1772 "tx_free_thresh must be less than the number of TX "
1773 "descriptors minus 3. (tx_free_thresh=%u port=%d "
1774 "queue=%d)\n", (unsigned int)tx_free_thresh,
1775 (int)dev->data->port_id, (int)queue_idx);
1778 if (tx_rs_thresh > tx_free_thresh) {
1779 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than or equal to "
1780 "tx_free_thresh. (tx_free_thresh=%u tx_rs_thresh=%u "
1781 "port=%d queue=%d)\n", (unsigned int)tx_free_thresh,
1782 (unsigned int)tx_rs_thresh, (int)dev->data->port_id,
1786 if ((nb_desc % tx_rs_thresh) != 0) {
1787 RTE_LOG(ERR, PMD, "tx_rs_thresh must be a divisor of the "
1788 "number of TX descriptors. (tx_rs_thresh=%u port=%d "
1789 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1790 (int)dev->data->port_id, (int)queue_idx);
1795 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1796 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1797 * by the NIC and all descriptors are written back after the NIC
1798 * accumulates WTHRESH descriptors.
1800 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1801 RTE_LOG(ERR, PMD, "TX WTHRESH must be set to 0 if "
1802 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1803 "port=%d queue=%d)\n", (unsigned int)tx_rs_thresh,
1804 (int)dev->data->port_id, (int)queue_idx);
1808 /* Free memory prior to re-allocation if needed... */
1809 if (dev->data->tx_queues[queue_idx] != NULL) {
1810 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1811 dev->data->tx_queues[queue_idx] = NULL;
1814 /* First allocate the tx queue data structure */
1815 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct igb_tx_queue),
1816 CACHE_LINE_SIZE, socket_id);
1821 * Allocate TX ring hardware descriptors. A memzone large enough to
1822 * handle the maximum ring size is allocated in order to allow for
1823 * resizing in later calls to the queue setup function.
1825 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1826 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1829 ixgbe_tx_queue_release(txq);
1833 txq->nb_tx_desc = nb_desc;
1834 txq->tx_rs_thresh = tx_rs_thresh;
1835 txq->tx_free_thresh = tx_free_thresh;
1836 txq->pthresh = tx_conf->tx_thresh.pthresh;
1837 txq->hthresh = tx_conf->tx_thresh.hthresh;
1838 txq->wthresh = tx_conf->tx_thresh.wthresh;
1839 txq->queue_id = queue_idx;
1840 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1841 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1842 txq->port_id = dev->data->port_id;
1843 txq->txq_flags = tx_conf->txq_flags;
1844 txq->ops = &def_txq_ops;
1845 txq->start_tx_per_q = tx_conf->start_tx_per_q;
1848 * Modification to set VFTDT for virtual function if vf is detected
1850 if (hw->mac.type == ixgbe_mac_82599_vf)
1851 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1853 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1854 #ifndef RTE_LIBRTE_XEN_DOM0
1855 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1857 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1859 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1861 /* Allocate software ring */
1862 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1863 sizeof(struct igb_tx_entry) * nb_desc,
1864 CACHE_LINE_SIZE, socket_id);
1865 if (txq->sw_ring == NULL) {
1866 ixgbe_tx_queue_release(txq);
1869 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1870 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1872 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1873 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
1874 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1875 PMD_INIT_LOG(INFO, "Using simple tx code path\n");
1876 #ifdef RTE_IXGBE_INC_VECTOR
1877 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1878 ixgbe_txq_vec_setup(txq, socket_id) == 0) {
1879 PMD_INIT_LOG(INFO, "Vector tx enabled.\n");
1880 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1884 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1886 PMD_INIT_LOG(INFO, "Using full-featured tx code path\n");
1887 PMD_INIT_LOG(INFO, " - txq_flags = %lx [IXGBE_SIMPLE_FLAGS=%lx]\n", (long unsigned)txq->txq_flags, (long unsigned)IXGBE_SIMPLE_FLAGS);
1888 PMD_INIT_LOG(INFO, " - tx_rs_thresh = %lu [RTE_PMD_IXGBE_TX_MAX_BURST=%lu]\n", (long unsigned)txq->tx_rs_thresh, (long unsigned)RTE_PMD_IXGBE_TX_MAX_BURST);
1889 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1892 txq->ops->reset(txq);
1894 dev->data->tx_queues[queue_idx] = txq;
1901 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1905 if (rxq->sw_ring != NULL) {
1906 for (i = 0; i < rxq->nb_rx_desc; i++) {
1907 if (rxq->sw_ring[i].mbuf != NULL) {
1908 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1909 rxq->sw_ring[i].mbuf = NULL;
1912 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1913 if (rxq->rx_nb_avail) {
1914 for (i = 0; i < rxq->rx_nb_avail; ++i) {
1915 struct rte_mbuf *mb;
1916 mb = rxq->rx_stage[rxq->rx_next_avail + i];
1917 rte_pktmbuf_free_seg(mb);
1919 rxq->rx_nb_avail = 0;
1926 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
1929 ixgbe_rx_queue_release_mbufs(rxq);
1930 rte_free(rxq->sw_ring);
1936 ixgbe_dev_rx_queue_release(void *rxq)
1938 ixgbe_rx_queue_release(rxq);
1942 * Check if Rx Burst Bulk Alloc function can be used.
1944 * 0: the preconditions are satisfied and the bulk allocation function
1946 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
1947 * function must be used.
1950 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1951 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
1953 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct igb_rx_queue *rxq)
1959 * Make sure the following pre-conditions are satisfied:
1960 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
1961 * rxq->rx_free_thresh < rxq->nb_rx_desc
1962 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
1963 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
1964 * Scattered packets are not supported. This should be checked
1965 * outside of this function.
1967 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1968 if (! (rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST))
1970 else if (! (rxq->rx_free_thresh < rxq->nb_rx_desc))
1972 else if (! ((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0))
1974 else if (! (rxq->nb_rx_desc <
1975 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST)))
1984 /* Reset dynamic igb_rx_queue fields back to defaults */
1986 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
1988 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
1994 * By default, the Rx queue setup function allocates enough memory for
1995 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
1996 * extra memory at the end of the descriptor ring to be zero'd out. A
1997 * pre-condition for using the Rx burst bulk alloc function is that the
1998 * number of descriptors is less than or equal to
1999 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2000 * constraints here to see if we need to zero out memory after the end
2001 * of the H/W descriptor ring.
2003 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2004 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2005 /* zero out extra memory */
2006 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2009 /* do not zero out extra memory */
2010 len = rxq->nb_rx_desc;
2013 * Zero out HW ring memory. Zero out extra memory at the end of
2014 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2015 * reads extra memory as zeros.
2017 for (i = 0; i < len; i++) {
2018 rxq->rx_ring[i] = zeroed_desc;
2021 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2023 * initialize extra software ring entries. Space for these extra
2024 * entries is always allocated
2026 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2027 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2028 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2031 rxq->rx_nb_avail = 0;
2032 rxq->rx_next_avail = 0;
2033 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2034 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2036 rxq->nb_rx_hold = 0;
2037 rxq->pkt_first_seg = NULL;
2038 rxq->pkt_last_seg = NULL;
2042 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2045 unsigned int socket_id,
2046 const struct rte_eth_rxconf *rx_conf,
2047 struct rte_mempool *mp)
2049 const struct rte_memzone *rz;
2050 struct igb_rx_queue *rxq;
2051 struct ixgbe_hw *hw;
2052 int use_def_burst_func = 1;
2055 PMD_INIT_FUNC_TRACE();
2056 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2059 * Validate number of receive descriptors.
2060 * It must not exceed hardware maximum, and must be multiple
2063 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2064 (nb_desc > IXGBE_MAX_RING_DESC) ||
2065 (nb_desc < IXGBE_MIN_RING_DESC)) {
2069 /* Free memory prior to re-allocation if needed... */
2070 if (dev->data->rx_queues[queue_idx] != NULL) {
2071 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2072 dev->data->rx_queues[queue_idx] = NULL;
2075 /* First allocate the rx queue data structure */
2076 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct igb_rx_queue),
2077 CACHE_LINE_SIZE, socket_id);
2081 rxq->nb_rx_desc = nb_desc;
2082 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2083 rxq->queue_id = queue_idx;
2084 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2085 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2086 rxq->port_id = dev->data->port_id;
2087 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2089 rxq->drop_en = rx_conf->rx_drop_en;
2090 rxq->start_rx_per_q = rx_conf->start_rx_per_q;
2093 * Allocate RX ring hardware descriptors. A memzone large enough to
2094 * handle the maximum ring size is allocated in order to allow for
2095 * resizing in later calls to the queue setup function.
2097 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2098 RX_RING_SZ, socket_id);
2100 ixgbe_rx_queue_release(rxq);
2105 * Zero init all the descriptors in the ring.
2107 memset (rz->addr, 0, RX_RING_SZ);
2110 * Modified to setup VFRDT for Virtual Function
2112 if (hw->mac.type == ixgbe_mac_82599_vf) {
2114 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2116 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2120 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2122 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2124 #ifndef RTE_LIBRTE_XEN_DOM0
2125 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2127 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2129 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2132 * Allocate software ring. Allow for space at the end of the
2133 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2134 * function does not access an invalid memory region.
2136 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2137 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2141 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2142 sizeof(struct igb_rx_entry) * len,
2143 CACHE_LINE_SIZE, socket_id);
2144 if (rxq->sw_ring == NULL) {
2145 ixgbe_rx_queue_release(rxq);
2148 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
2149 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2152 * Certain constraints must be met in order to use the bulk buffer
2153 * allocation Rx burst function.
2155 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2157 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2158 if (!use_def_burst_func && !dev->data->scattered_rx) {
2159 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2160 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2161 "satisfied. Rx Burst Bulk Alloc function will be "
2162 "used on port=%d, queue=%d.\n",
2163 rxq->port_id, rxq->queue_id);
2164 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2165 #ifdef RTE_IXGBE_INC_VECTOR
2166 if (!ixgbe_rx_vec_condition_check(dev)) {
2167 PMD_INIT_LOG(INFO, "Vector rx enabled, please make "
2168 "sure RX burst size no less than 32.\n");
2169 ixgbe_rxq_vec_setup(rxq, socket_id);
2170 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
2175 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2176 "are not satisfied, Scattered Rx is requested, "
2177 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2178 "enabled (port=%d, queue=%d).\n",
2179 rxq->port_id, rxq->queue_id);
2181 dev->data->rx_queues[queue_idx] = rxq;
2183 ixgbe_reset_rx_queue(rxq);
2189 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2191 #define IXGBE_RXQ_SCAN_INTERVAL 4
2192 volatile union ixgbe_adv_rx_desc *rxdp;
2193 struct igb_rx_queue *rxq;
2196 if (rx_queue_id >= dev->data->nb_rx_queues) {
2197 PMD_RX_LOG(ERR, "Invalid RX queue id=%d\n", rx_queue_id);
2201 rxq = dev->data->rx_queues[rx_queue_id];
2202 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2204 while ((desc < rxq->nb_rx_desc) &&
2205 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2206 desc += IXGBE_RXQ_SCAN_INTERVAL;
2207 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2208 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2209 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2210 desc - rxq->nb_rx_desc]);
2217 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2219 volatile union ixgbe_adv_rx_desc *rxdp;
2220 struct igb_rx_queue *rxq = rx_queue;
2223 if (unlikely(offset >= rxq->nb_rx_desc))
2225 desc = rxq->rx_tail + offset;
2226 if (desc >= rxq->nb_rx_desc)
2227 desc -= rxq->nb_rx_desc;
2229 rxdp = &rxq->rx_ring[desc];
2230 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2234 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2238 PMD_INIT_FUNC_TRACE();
2240 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2241 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2243 txq->ops->release_mbufs(txq);
2244 txq->ops->reset(txq);
2248 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2249 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2251 ixgbe_rx_queue_release_mbufs(rxq);
2252 ixgbe_reset_rx_queue(rxq);
2257 /*********************************************************************
2259 * Device RX/TX init functions
2261 **********************************************************************/
2264 * Receive Side Scaling (RSS)
2265 * See section 7.1.2.8 in the following document:
2266 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2269 * The source and destination IP addresses of the IP header and the source
2270 * and destination ports of TCP/UDP headers, if any, of received packets are
2271 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2272 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2273 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2274 * RSS output index which is used as the RX queue index where to store the
2276 * The following output is supplied in the RX write-back descriptor:
2277 * - 32-bit result of the Microsoft RSS hash function,
2278 * - 4-bit RSS type field.
2282 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2283 * Used as the default key.
2285 static uint8_t rss_intel_key[40] = {
2286 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2287 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2288 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2289 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2290 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2294 ixgbe_rss_disable(struct rte_eth_dev *dev)
2296 struct ixgbe_hw *hw;
2299 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2300 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2301 mrqc &= ~IXGBE_MRQC_RSSEN;
2302 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2306 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2314 hash_key = rss_conf->rss_key;
2315 if (hash_key != NULL) {
2316 /* Fill in RSS hash key */
2317 for (i = 0; i < 10; i++) {
2318 rss_key = hash_key[(i * 4)];
2319 rss_key |= hash_key[(i * 4) + 1] << 8;
2320 rss_key |= hash_key[(i * 4) + 2] << 16;
2321 rss_key |= hash_key[(i * 4) + 3] << 24;
2322 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2326 /* Set configured hashing protocols in MRQC register */
2327 rss_hf = rss_conf->rss_hf;
2328 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2329 if (rss_hf & ETH_RSS_IPV4)
2330 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2331 if (rss_hf & ETH_RSS_IPV4_TCP)
2332 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2333 if (rss_hf & ETH_RSS_IPV6)
2334 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2335 if (rss_hf & ETH_RSS_IPV6_EX)
2336 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2337 if (rss_hf & ETH_RSS_IPV6_TCP)
2338 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2339 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2340 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2341 if (rss_hf & ETH_RSS_IPV4_UDP)
2342 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2343 if (rss_hf & ETH_RSS_IPV6_UDP)
2344 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2345 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2346 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2347 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2351 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2352 struct rte_eth_rss_conf *rss_conf)
2354 struct ixgbe_hw *hw;
2358 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2361 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2362 * "RSS enabling cannot be done dynamically while it must be
2363 * preceded by a software reset"
2364 * Before changing anything, first check that the update RSS operation
2365 * does not attempt to disable RSS, if RSS was enabled at
2366 * initialization time, or does not attempt to enable RSS, if RSS was
2367 * disabled at initialization time.
2369 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2370 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2371 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2372 if (rss_hf != 0) /* Enable RSS */
2374 return 0; /* Nothing to do */
2377 if (rss_hf == 0) /* Disable RSS */
2379 ixgbe_hw_rss_hash_set(hw, rss_conf);
2384 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2385 struct rte_eth_rss_conf *rss_conf)
2387 struct ixgbe_hw *hw;
2394 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2395 hash_key = rss_conf->rss_key;
2396 if (hash_key != NULL) {
2397 /* Return RSS hash key */
2398 for (i = 0; i < 10; i++) {
2399 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2400 hash_key[(i * 4)] = rss_key & 0x000000FF;
2401 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2402 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2403 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2407 /* Get RSS functions configured in MRQC register */
2408 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2409 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2410 rss_conf->rss_hf = 0;
2414 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2415 rss_hf |= ETH_RSS_IPV4;
2416 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2417 rss_hf |= ETH_RSS_IPV4_TCP;
2418 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2419 rss_hf |= ETH_RSS_IPV6;
2420 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2421 rss_hf |= ETH_RSS_IPV6_EX;
2422 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2423 rss_hf |= ETH_RSS_IPV6_TCP;
2424 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2425 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2426 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2427 rss_hf |= ETH_RSS_IPV4_UDP;
2428 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2429 rss_hf |= ETH_RSS_IPV6_UDP;
2430 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2431 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2432 rss_conf->rss_hf = rss_hf;
2437 ixgbe_rss_configure(struct rte_eth_dev *dev)
2439 struct rte_eth_rss_conf rss_conf;
2440 struct ixgbe_hw *hw;
2445 PMD_INIT_FUNC_TRACE();
2446 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2449 * Fill in redirection table
2450 * The byte-swap is needed because NIC registers are in
2451 * little-endian order.
2454 for (i = 0, j = 0; i < 128; i++, j++) {
2455 if (j == dev->data->nb_rx_queues)
2457 reta = (reta << 8) | j;
2459 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2464 * Configure the RSS key and the RSS protocols used to compute
2465 * the RSS hash of input packets.
2467 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2468 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2469 ixgbe_rss_disable(dev);
2472 if (rss_conf.rss_key == NULL)
2473 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2474 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2477 #define NUM_VFTA_REGISTERS 128
2478 #define NIC_RX_BUFFER_SIZE 0x200
2481 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2483 struct rte_eth_vmdq_dcb_conf *cfg;
2484 struct ixgbe_hw *hw;
2485 enum rte_eth_nb_pools num_pools;
2486 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2488 uint8_t nb_tcs; /* number of traffic classes */
2491 PMD_INIT_FUNC_TRACE();
2492 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2493 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2494 num_pools = cfg->nb_queue_pools;
2495 /* Check we have a valid number of pools */
2496 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2497 ixgbe_rss_disable(dev);
2500 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2501 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2505 * split rx buffer up into sections, each for 1 traffic class
2507 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2508 for (i = 0 ; i < nb_tcs; i++) {
2509 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2510 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2511 /* clear 10 bits. */
2512 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2513 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2515 /* zero alloc all unused TCs */
2516 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2517 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2518 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2519 /* clear 10 bits. */
2520 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2523 /* MRQC: enable vmdq and dcb */
2524 mrqc = ((num_pools == ETH_16_POOLS) ? \
2525 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2526 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2528 /* PFVTCTL: turn on virtualisation and set the default pool */
2529 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2530 if (cfg->enable_default_pool) {
2531 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2533 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2536 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2538 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2540 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2542 * mapping is done with 3 bits per priority,
2543 * so shift by i*3 each time
2545 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2547 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2549 /* RTRPCS: DCB related */
2550 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2552 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2553 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2554 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2555 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2557 /* VFTA - enable all vlan filters */
2558 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2559 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2562 /* VFRE: pool enabling for receive - 16 or 32 */
2563 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2564 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2567 * MPSAR - allow pools to read specific mac addresses
2568 * In this case, all pools should be able to read from mac addr 0
2570 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2571 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2573 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2574 for (i = 0; i < cfg->nb_pool_maps; i++) {
2575 /* set vlan id in VF register and set the valid bit */
2576 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2577 (cfg->pool_map[i].vlan_id & 0xFFF)));
2579 * Put the allowed pools in VFB reg. As we only have 16 or 32
2580 * pools, we only need to use the first half of the register
2583 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2588 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2589 * @hw: pointer to hardware structure
2590 * @dcb_config: pointer to ixgbe_dcb_config structure
2593 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2594 struct ixgbe_dcb_config *dcb_config)
2599 PMD_INIT_FUNC_TRACE();
2600 if (hw->mac.type != ixgbe_mac_82598EB) {
2601 /* Disable the Tx desc arbiter so that MTQC can be changed */
2602 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2603 reg |= IXGBE_RTTDCS_ARBDIS;
2604 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2606 /* Enable DCB for Tx with 8 TCs */
2607 if (dcb_config->num_tcs.pg_tcs == 8) {
2608 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2611 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2613 if (dcb_config->vt_mode)
2614 reg |= IXGBE_MTQC_VT_ENA;
2615 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2617 /* Disable drop for all queues */
2618 for (q = 0; q < 128; q++)
2619 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2620 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2622 /* Enable the Tx desc arbiter */
2623 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2624 reg &= ~IXGBE_RTTDCS_ARBDIS;
2625 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2627 /* Enable Security TX Buffer IFG for DCB */
2628 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2629 reg |= IXGBE_SECTX_DCB;
2630 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2636 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2637 * @dev: pointer to rte_eth_dev structure
2638 * @dcb_config: pointer to ixgbe_dcb_config structure
2641 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2642 struct ixgbe_dcb_config *dcb_config)
2644 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2645 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2646 struct ixgbe_hw *hw =
2647 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2649 PMD_INIT_FUNC_TRACE();
2650 if (hw->mac.type != ixgbe_mac_82598EB)
2651 /*PF VF Transmit Enable*/
2652 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2653 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2655 /*Configure general DCB TX parameters*/
2656 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2661 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2662 struct ixgbe_dcb_config *dcb_config)
2664 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2665 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2666 struct ixgbe_dcb_tc_config *tc;
2669 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2670 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2671 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2672 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2675 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2676 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2678 /* User Priority to Traffic Class mapping */
2679 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2680 j = vmdq_rx_conf->dcb_queue[i];
2681 tc = &dcb_config->tc_config[j];
2682 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2688 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2689 struct ixgbe_dcb_config *dcb_config)
2691 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2692 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2693 struct ixgbe_dcb_tc_config *tc;
2696 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2697 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2698 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2699 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2702 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2703 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2706 /* User Priority to Traffic Class mapping */
2707 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2708 j = vmdq_tx_conf->dcb_queue[i];
2709 tc = &dcb_config->tc_config[j];
2710 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2717 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2718 struct ixgbe_dcb_config *dcb_config)
2720 struct rte_eth_dcb_rx_conf *rx_conf =
2721 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2722 struct ixgbe_dcb_tc_config *tc;
2725 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2726 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2728 /* User Priority to Traffic Class mapping */
2729 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2730 j = rx_conf->dcb_queue[i];
2731 tc = &dcb_config->tc_config[j];
2732 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2738 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2739 struct ixgbe_dcb_config *dcb_config)
2741 struct rte_eth_dcb_tx_conf *tx_conf =
2742 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2743 struct ixgbe_dcb_tc_config *tc;
2746 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2747 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2749 /* User Priority to Traffic Class mapping */
2750 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2751 j = tx_conf->dcb_queue[i];
2752 tc = &dcb_config->tc_config[j];
2753 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2759 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2760 * @hw: pointer to hardware structure
2761 * @dcb_config: pointer to ixgbe_dcb_config structure
2764 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2765 struct ixgbe_dcb_config *dcb_config)
2771 PMD_INIT_FUNC_TRACE();
2773 * Disable the arbiter before changing parameters
2774 * (always enable recycle mode; WSP)
2776 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2777 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2779 if (hw->mac.type != ixgbe_mac_82598EB) {
2780 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2781 if (dcb_config->num_tcs.pg_tcs == 4) {
2782 if (dcb_config->vt_mode)
2783 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2784 IXGBE_MRQC_VMDQRT4TCEN;
2786 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2787 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2791 if (dcb_config->num_tcs.pg_tcs == 8) {
2792 if (dcb_config->vt_mode)
2793 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2794 IXGBE_MRQC_VMDQRT8TCEN;
2796 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2797 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2802 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2805 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2806 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2807 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2808 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2810 /* VFTA - enable all vlan filters */
2811 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2812 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2816 * Configure Rx packet plane (recycle mode; WSP) and
2819 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2820 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2826 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2827 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2829 switch (hw->mac.type) {
2830 case ixgbe_mac_82598EB:
2831 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2833 case ixgbe_mac_82599EB:
2834 case ixgbe_mac_X540:
2835 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2844 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2845 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2847 switch (hw->mac.type) {
2848 case ixgbe_mac_82598EB:
2849 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2850 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2852 case ixgbe_mac_82599EB:
2853 case ixgbe_mac_X540:
2854 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2855 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2862 #define DCB_RX_CONFIG 1
2863 #define DCB_TX_CONFIG 1
2864 #define DCB_TX_PB 1024
2866 * ixgbe_dcb_hw_configure - Enable DCB and configure
2867 * general DCB in VT mode and non-VT mode parameters
2868 * @dev: pointer to rte_eth_dev structure
2869 * @dcb_config: pointer to ixgbe_dcb_config structure
2872 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2873 struct ixgbe_dcb_config *dcb_config)
2876 uint8_t i,pfc_en,nb_tcs;
2878 uint8_t config_dcb_rx = 0;
2879 uint8_t config_dcb_tx = 0;
2880 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2881 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2882 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2883 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2884 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2885 struct ixgbe_dcb_tc_config *tc;
2886 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2887 struct ixgbe_hw *hw =
2888 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2890 switch(dev->data->dev_conf.rxmode.mq_mode){
2891 case ETH_MQ_RX_VMDQ_DCB:
2892 dcb_config->vt_mode = true;
2893 if (hw->mac.type != ixgbe_mac_82598EB) {
2894 config_dcb_rx = DCB_RX_CONFIG;
2896 *get dcb and VT rx configuration parameters
2899 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2900 /*Configure general VMDQ and DCB RX parameters*/
2901 ixgbe_vmdq_dcb_configure(dev);
2905 dcb_config->vt_mode = false;
2906 config_dcb_rx = DCB_RX_CONFIG;
2907 /* Get dcb TX configuration parameters from rte_eth_conf */
2908 ixgbe_dcb_rx_config(dev,dcb_config);
2909 /*Configure general DCB RX parameters*/
2910 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2913 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration\n");
2916 switch (dev->data->dev_conf.txmode.mq_mode) {
2917 case ETH_MQ_TX_VMDQ_DCB:
2918 dcb_config->vt_mode = true;
2919 config_dcb_tx = DCB_TX_CONFIG;
2920 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2921 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2922 /*Configure general VMDQ and DCB TX parameters*/
2923 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2927 dcb_config->vt_mode = false;
2928 config_dcb_tx = DCB_TX_CONFIG;
2929 /*get DCB TX configuration parameters from rte_eth_conf*/
2930 ixgbe_dcb_tx_config(dev,dcb_config);
2931 /*Configure general DCB TX parameters*/
2932 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2935 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration\n");
2939 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2941 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2942 if(nb_tcs == ETH_4_TCS) {
2943 /* Avoid un-configured priority mapping to TC0 */
2945 uint8_t mask = 0xFF;
2946 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
2947 mask = (uint8_t)(mask & (~ (1 << map[i])));
2948 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
2949 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
2953 /* Re-configure 4 TCs BW */
2954 for (i = 0; i < nb_tcs; i++) {
2955 tc = &dcb_config->tc_config[i];
2956 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
2957 (uint8_t)(100 / nb_tcs);
2958 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
2959 (uint8_t)(100 / nb_tcs);
2961 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2962 tc = &dcb_config->tc_config[i];
2963 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
2964 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
2969 /* Set RX buffer size */
2970 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2971 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
2972 for (i = 0 ; i < nb_tcs; i++) {
2973 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2975 /* zero alloc all unused TCs */
2976 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2977 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
2981 /* Only support an equally distributed Tx packet buffer strategy. */
2982 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
2983 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
2984 for (i = 0; i < nb_tcs; i++) {
2985 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
2986 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
2988 /* Clear unused TCs, if any, to zero buffer size*/
2989 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2990 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
2991 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
2995 /*Calculates traffic class credits*/
2996 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2997 IXGBE_DCB_TX_CONFIG);
2998 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2999 IXGBE_DCB_RX_CONFIG);
3002 /* Unpack CEE standard containers */
3003 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3004 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3005 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3006 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3007 /* Configure PG(ETS) RX */
3008 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3012 /* Unpack CEE standard containers */
3013 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3014 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3015 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3016 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3017 /* Configure PG(ETS) TX */
3018 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3021 /*Configure queue statistics registers*/
3022 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3024 /* Check if the PFC is supported */
3025 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3026 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3027 for (i = 0; i < nb_tcs; i++) {
3029 * If the TC count is 8,and the default high_water is 48,
3030 * the low_water is 16 as default.
3032 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3033 hw->fc.low_water[i] = pbsize / 4;
3034 /* Enable pfc for this TC */
3035 tc = &dcb_config->tc_config[i];
3036 tc->pfc = ixgbe_dcb_pfc_enabled;
3038 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3039 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3041 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3048 * ixgbe_configure_dcb - Configure DCB Hardware
3049 * @dev: pointer to rte_eth_dev
3051 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3053 struct ixgbe_dcb_config *dcb_cfg =
3054 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3055 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3057 PMD_INIT_FUNC_TRACE();
3059 /* check support mq_mode for DCB */
3060 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3061 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3064 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3067 /** Configure DCB hardware **/
3068 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3074 * VMDq only support for 10 GbE NIC.
3077 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3079 struct rte_eth_vmdq_rx_conf *cfg;
3080 struct ixgbe_hw *hw;
3081 enum rte_eth_nb_pools num_pools;
3082 uint32_t mrqc, vt_ctl, vlanctrl;
3085 PMD_INIT_FUNC_TRACE();
3086 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3087 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3088 num_pools = cfg->nb_queue_pools;
3090 ixgbe_rss_disable(dev);
3092 /* MRQC: enable vmdq */
3093 mrqc = IXGBE_MRQC_VMDQEN;
3094 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3096 /* PFVTCTL: turn on virtualisation and set the default pool */
3097 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3098 if (cfg->enable_default_pool)
3099 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3101 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3103 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3105 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3106 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3107 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3108 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3110 /* VFTA - enable all vlan filters */
3111 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3112 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3114 /* VFRE: pool enabling for receive - 64 */
3115 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3116 if (num_pools == ETH_64_POOLS)
3117 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3120 * MPSAR - allow pools to read specific mac addresses
3121 * In this case, all pools should be able to read from mac addr 0
3123 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3124 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3126 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3127 for (i = 0; i < cfg->nb_pool_maps; i++) {
3128 /* set vlan id in VF register and set the valid bit */
3129 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3130 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3132 * Put the allowed pools in VFB reg. As we only have 16 or 64
3133 * pools, we only need to use the first half of the register
3136 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3137 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3138 (cfg->pool_map[i].pools & UINT32_MAX));
3140 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3141 ((cfg->pool_map[i].pools >> 32) \
3146 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3147 if (cfg->enable_loop_back) {
3148 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3149 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3150 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3153 IXGBE_WRITE_FLUSH(hw);
3157 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3158 * @hw: pointer to hardware structure
3161 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3166 PMD_INIT_FUNC_TRACE();
3167 /*PF VF Transmit Enable*/
3168 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3169 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3171 /* Disable the Tx desc arbiter so that MTQC can be changed */
3172 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3173 reg |= IXGBE_RTTDCS_ARBDIS;
3174 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3176 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3177 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3179 /* Disable drop for all queues */
3180 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3181 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3182 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3184 /* Enable the Tx desc arbiter */
3185 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3186 reg &= ~IXGBE_RTTDCS_ARBDIS;
3187 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3189 IXGBE_WRITE_FLUSH(hw);
3195 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
3197 struct igb_rx_entry *rxe = rxq->sw_ring;
3201 /* Initialize software ring entries */
3202 for (i = 0; i < rxq->nb_rx_desc; i++) {
3203 volatile union ixgbe_adv_rx_desc *rxd;
3204 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3206 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u\n",
3207 (unsigned) rxq->queue_id);
3211 rte_mbuf_refcnt_set(mbuf, 1);
3213 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3215 mbuf->port = rxq->port_id;
3218 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3219 rxd = &rxq->rx_ring[i];
3220 rxd->read.hdr_addr = dma_addr;
3221 rxd->read.pkt_addr = dma_addr;
3229 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3231 struct ixgbe_hw *hw =
3232 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3234 if (hw->mac.type == ixgbe_mac_82598EB)
3237 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3239 * SRIOV inactive scheme
3240 * any DCB/RSS w/o VMDq multi-queue setting
3242 switch (dev->data->dev_conf.rxmode.mq_mode) {
3244 ixgbe_rss_configure(dev);
3247 case ETH_MQ_RX_VMDQ_DCB:
3248 ixgbe_vmdq_dcb_configure(dev);
3251 case ETH_MQ_RX_VMDQ_ONLY:
3252 ixgbe_vmdq_rx_hw_configure(dev);
3255 case ETH_MQ_RX_NONE:
3256 /* if mq_mode is none, disable rss mode.*/
3257 default: ixgbe_rss_disable(dev);
3260 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3262 * SRIOV active scheme
3263 * FIXME if support DCB/RSS together with VMDq & SRIOV
3266 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQEN);
3270 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT4TCEN);
3274 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT8TCEN);
3277 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3285 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3287 struct ixgbe_hw *hw =
3288 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3292 if (hw->mac.type == ixgbe_mac_82598EB)
3295 /* disable arbiter before setting MTQC */
3296 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3297 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3298 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3300 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3302 * SRIOV inactive scheme
3303 * any DCB w/o VMDq multi-queue setting
3305 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3306 ixgbe_vmdq_tx_hw_configure(hw);
3308 mtqc = IXGBE_MTQC_64Q_1PB;
3309 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3312 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3315 * SRIOV active scheme
3316 * FIXME if support DCB together with VMDq & SRIOV
3319 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3322 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3325 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3329 mtqc = IXGBE_MTQC_64Q_1PB;
3330 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3332 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3335 /* re-enable arbiter */
3336 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3337 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3343 * Initializes Receive Unit.
3346 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3348 struct ixgbe_hw *hw;
3349 struct igb_rx_queue *rxq;
3350 struct rte_pktmbuf_pool_private *mbp_priv;
3362 PMD_INIT_FUNC_TRACE();
3363 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3366 * Make sure receives are disabled while setting
3367 * up the RX context (registers, descriptor rings, etc.).
3369 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3370 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3372 /* Enable receipt of broadcasted frames */
3373 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3374 fctrl |= IXGBE_FCTRL_BAM;
3375 fctrl |= IXGBE_FCTRL_DPF;
3376 fctrl |= IXGBE_FCTRL_PMCF;
3377 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3380 * Configure CRC stripping, if any.
3382 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3383 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3384 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3386 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3389 * Configure jumbo frame support, if any.
3391 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3392 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3393 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3394 maxfrs &= 0x0000FFFF;
3395 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3396 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3398 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3401 * If loopback mode is configured for 82599, set LPBK bit.
3403 if (hw->mac.type == ixgbe_mac_82599EB &&
3404 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3405 hlreg0 |= IXGBE_HLREG0_LPBK;
3407 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3409 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3411 /* Setup RX queues */
3412 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3413 rxq = dev->data->rx_queues[i];
3416 * Reset crc_len in case it was changed after queue setup by a
3417 * call to configure.
3419 rxq->crc_len = (uint8_t)
3420 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3423 /* Setup the Base and Length of the Rx Descriptor Rings */
3424 bus_addr = rxq->rx_ring_phys_addr;
3425 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3426 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3427 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3428 (uint32_t)(bus_addr >> 32));
3429 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3430 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3431 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3432 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3434 /* Configure the SRRCTL register */
3435 #ifdef RTE_HEADER_SPLIT_ENABLE
3437 * Configure Header Split
3439 if (dev->data->dev_conf.rxmode.header_split) {
3440 if (hw->mac.type == ixgbe_mac_82599EB) {
3441 /* Must setup the PSRTYPE register */
3443 psrtype = IXGBE_PSRTYPE_TCPHDR |
3444 IXGBE_PSRTYPE_UDPHDR |
3445 IXGBE_PSRTYPE_IPV4HDR |
3446 IXGBE_PSRTYPE_IPV6HDR;
3447 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3449 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3450 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3451 IXGBE_SRRCTL_BSIZEHDR_MASK);
3452 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3455 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3457 /* Set if packets are dropped when no descriptors available */
3459 srrctl |= IXGBE_SRRCTL_DROP_EN;
3462 * Configure the RX buffer size in the BSIZEPACKET field of
3463 * the SRRCTL register of the queue.
3464 * The value is in 1 KB resolution. Valid values can be from
3467 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3468 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3469 RTE_PKTMBUF_HEADROOM);
3470 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3471 IXGBE_SRRCTL_BSIZEPKT_MASK);
3472 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3474 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3475 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3477 /* It adds dual VLAN length for supporting dual VLAN */
3478 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3479 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3480 dev->data->scattered_rx = 1;
3481 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3485 if (dev->data->dev_conf.rxmode.enable_scatter) {
3486 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3487 dev->data->scattered_rx = 1;
3491 * Device configured with multiple RX queues.
3493 ixgbe_dev_mq_rx_configure(dev);
3496 * Setup the Checksum Register.
3497 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3498 * Enable IP/L4 checkum computation by hardware if requested to do so.
3500 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3501 rxcsum |= IXGBE_RXCSUM_PCSD;
3502 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3503 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3505 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3507 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3509 if (hw->mac.type == ixgbe_mac_82599EB) {
3510 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3511 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3512 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3514 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3515 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3516 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3523 * Initializes Transmit Unit.
3526 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3528 struct ixgbe_hw *hw;
3529 struct igb_tx_queue *txq;
3535 PMD_INIT_FUNC_TRACE();
3536 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3538 /* Enable TX CRC (checksum offload requirement) */
3539 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3540 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
3541 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3543 /* Setup the Base and Length of the Tx Descriptor Rings */
3544 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3545 txq = dev->data->tx_queues[i];
3547 bus_addr = txq->tx_ring_phys_addr;
3548 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3549 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3550 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3551 (uint32_t)(bus_addr >> 32));
3552 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3553 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3554 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3555 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3556 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3559 * Disable Tx Head Writeback RO bit, since this hoses
3560 * bookkeeping if things aren't delivered in order.
3562 switch (hw->mac.type) {
3563 case ixgbe_mac_82598EB:
3564 txctrl = IXGBE_READ_REG(hw,
3565 IXGBE_DCA_TXCTRL(txq->reg_idx));
3566 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3567 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3571 case ixgbe_mac_82599EB:
3572 case ixgbe_mac_X540:
3574 txctrl = IXGBE_READ_REG(hw,
3575 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3576 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3577 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3583 /* Device configured with multiple TX queues. */
3584 ixgbe_dev_mq_tx_configure(dev);
3588 * Set up link for 82599 loopback mode Tx->Rx.
3591 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3593 DEBUGFUNC("ixgbe_setup_loopback_link_82599");
3595 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3596 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3598 PMD_INIT_LOG(ERR, "Could not enable loopback mode\n");
3607 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3608 ixgbe_reset_pipeline_82599(hw);
3610 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3616 * Start Transmit and Receive Units.
3619 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3621 struct ixgbe_hw *hw;
3622 struct igb_tx_queue *txq;
3623 struct igb_rx_queue *rxq;
3629 PMD_INIT_FUNC_TRACE();
3630 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3632 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3633 txq = dev->data->tx_queues[i];
3634 /* Setup Transmit Threshold Registers */
3635 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3636 txdctl |= txq->pthresh & 0x7F;
3637 txdctl |= ((txq->hthresh & 0x7F) << 8);
3638 txdctl |= ((txq->wthresh & 0x7F) << 16);
3639 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3642 if (hw->mac.type != ixgbe_mac_82598EB) {
3643 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3644 dmatxctl |= IXGBE_DMATXCTL_TE;
3645 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3648 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3649 txq = dev->data->tx_queues[i];
3650 if (!txq->start_tx_per_q)
3651 ixgbe_dev_tx_queue_start(dev, i);
3654 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3655 rxq = dev->data->rx_queues[i];
3656 if (!rxq->start_rx_per_q)
3657 ixgbe_dev_rx_queue_start(dev, i);
3660 /* Enable Receive engine */
3661 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3662 if (hw->mac.type == ixgbe_mac_82598EB)
3663 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3664 rxctrl |= IXGBE_RXCTRL_RXEN;
3665 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3667 /* If loopback mode is enabled for 82599, set up the link accordingly */
3668 if (hw->mac.type == ixgbe_mac_82599EB &&
3669 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3670 ixgbe_setup_loopback_link_82599(hw);
3675 * Start Receive Units for specified queue.
3678 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3680 struct ixgbe_hw *hw;
3681 struct igb_rx_queue *rxq;
3685 PMD_INIT_FUNC_TRACE();
3686 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3688 if (rx_queue_id < dev->data->nb_rx_queues) {
3689 rxq = dev->data->rx_queues[rx_queue_id];
3691 /* Allocate buffers for descriptor rings */
3692 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
3694 "Could not alloc mbuf for queue:%d\n",
3698 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3699 rxdctl |= IXGBE_RXDCTL_ENABLE;
3700 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3702 /* Wait until RX Enable ready */
3703 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3706 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3707 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3709 PMD_INIT_LOG(ERR, "Could not enable "
3710 "Rx Queue %d\n", rx_queue_id);
3712 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3713 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3721 * Stop Receive Units for specified queue.
3724 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3726 struct ixgbe_hw *hw;
3727 struct igb_rx_queue *rxq;
3731 PMD_INIT_FUNC_TRACE();
3732 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3734 if (rx_queue_id < dev->data->nb_rx_queues) {
3735 rxq = dev->data->rx_queues[rx_queue_id];
3737 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3738 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3739 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3741 /* Wait until RX Enable ready */
3742 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3745 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3746 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
3748 PMD_INIT_LOG(ERR, "Could not disable "
3749 "Rx Queue %d\n", rx_queue_id);
3751 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3753 ixgbe_rx_queue_release_mbufs(rxq);
3754 ixgbe_reset_rx_queue(rxq);
3763 * Start Transmit Units for specified queue.
3766 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3768 struct ixgbe_hw *hw;
3769 struct igb_tx_queue *txq;
3773 PMD_INIT_FUNC_TRACE();
3774 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3776 if (tx_queue_id < dev->data->nb_tx_queues) {
3777 txq = dev->data->tx_queues[tx_queue_id];
3778 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3779 txdctl |= IXGBE_TXDCTL_ENABLE;
3780 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3782 /* Wait until TX Enable ready */
3783 if (hw->mac.type == ixgbe_mac_82599EB) {
3784 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3787 txdctl = IXGBE_READ_REG(hw,
3788 IXGBE_TXDCTL(txq->reg_idx));
3789 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3791 PMD_INIT_LOG(ERR, "Could not enable "
3792 "Tx Queue %d\n", tx_queue_id);
3795 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3796 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3804 * Stop Transmit Units for specified queue.
3807 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3809 struct ixgbe_hw *hw;
3810 struct igb_tx_queue *txq;
3812 uint32_t txtdh, txtdt;
3815 PMD_INIT_FUNC_TRACE();
3816 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3818 if (tx_queue_id < dev->data->nb_tx_queues) {
3819 txq = dev->data->tx_queues[tx_queue_id];
3821 /* Wait until TX queue is empty */
3822 if (hw->mac.type == ixgbe_mac_82599EB) {
3823 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3825 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3826 txtdh = IXGBE_READ_REG(hw,
3827 IXGBE_TDH(txq->reg_idx));
3828 txtdt = IXGBE_READ_REG(hw,
3829 IXGBE_TDT(txq->reg_idx));
3830 } while (--poll_ms && (txtdh != txtdt));
3833 "Tx Queue %d is not empty when stopping.\n",
3837 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3838 txdctl &= ~IXGBE_TXDCTL_ENABLE;
3839 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3841 /* Wait until TX Enable ready */
3842 if (hw->mac.type == ixgbe_mac_82599EB) {
3843 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3846 txdctl = IXGBE_READ_REG(hw,
3847 IXGBE_TXDCTL(txq->reg_idx));
3848 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
3850 PMD_INIT_LOG(ERR, "Could not disable "
3851 "Tx Queue %d\n", tx_queue_id);
3854 if (txq->ops != NULL) {
3855 txq->ops->release_mbufs(txq);
3856 txq->ops->reset(txq);
3865 * [VF] Initializes Receive Unit.
3868 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3870 struct ixgbe_hw *hw;
3871 struct igb_rx_queue *rxq;
3872 struct rte_pktmbuf_pool_private *mbp_priv;
3879 PMD_INIT_FUNC_TRACE();
3880 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3883 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
3884 * disables the VF receipt of packets if the PF MTU is > 1500.
3885 * This is done to deal with 82599 limitations that imposes
3886 * the PF and all VFs to share the same MTU.
3887 * Then, the PF driver enables again the VF receipt of packet when
3888 * the VF driver issues a IXGBE_VF_SET_LPE request.
3889 * In the meantime, the VF device cannot be used, even if the VF driver
3890 * and the Guest VM network stack are ready to accept packets with a
3891 * size up to the PF MTU.
3892 * As a work-around to this PF behaviour, force the call to
3893 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
3894 * VF packets received can work in all cases.
3896 ixgbevf_rlpml_set_vf(hw,
3897 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
3899 /* Setup RX queues */
3900 dev->rx_pkt_burst = ixgbe_recv_pkts;
3901 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3902 rxq = dev->data->rx_queues[i];
3904 /* Allocate buffers for descriptor rings */
3905 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3909 /* Setup the Base and Length of the Rx Descriptor Rings */
3910 bus_addr = rxq->rx_ring_phys_addr;
3912 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3913 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3914 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3915 (uint32_t)(bus_addr >> 32));
3916 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3917 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3918 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3919 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3922 /* Configure the SRRCTL register */
3923 #ifdef RTE_HEADER_SPLIT_ENABLE
3925 * Configure Header Split
3927 if (dev->data->dev_conf.rxmode.header_split) {
3929 /* Must setup the PSRTYPE register */
3931 psrtype = IXGBE_PSRTYPE_TCPHDR |
3932 IXGBE_PSRTYPE_UDPHDR |
3933 IXGBE_PSRTYPE_IPV4HDR |
3934 IXGBE_PSRTYPE_IPV6HDR;
3936 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
3938 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3939 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3940 IXGBE_SRRCTL_BSIZEHDR_MASK);
3941 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3944 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3946 /* Set if packets are dropped when no descriptors available */
3948 srrctl |= IXGBE_SRRCTL_DROP_EN;
3951 * Configure the RX buffer size in the BSIZEPACKET field of
3952 * the SRRCTL register of the queue.
3953 * The value is in 1 KB resolution. Valid values can be from
3956 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3957 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3958 RTE_PKTMBUF_HEADROOM);
3959 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3960 IXGBE_SRRCTL_BSIZEPKT_MASK);
3963 * VF modification to write virtual function SRRCTL register
3965 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
3967 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3968 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3970 /* It adds dual VLAN length for supporting dual VLAN */
3971 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3972 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
3973 dev->data->scattered_rx = 1;
3974 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3978 if (dev->data->dev_conf.rxmode.enable_scatter) {
3979 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3980 dev->data->scattered_rx = 1;
3987 * [VF] Initializes Transmit Unit.
3990 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
3992 struct ixgbe_hw *hw;
3993 struct igb_tx_queue *txq;
3998 PMD_INIT_FUNC_TRACE();
3999 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4001 /* Setup the Base and Length of the Tx Descriptor Rings */
4002 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4003 txq = dev->data->tx_queues[i];
4004 bus_addr = txq->tx_ring_phys_addr;
4005 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4006 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4007 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4008 (uint32_t)(bus_addr >> 32));
4009 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4010 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4011 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4012 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4013 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4016 * Disable Tx Head Writeback RO bit, since this hoses
4017 * bookkeeping if things aren't delivered in order.
4019 txctrl = IXGBE_READ_REG(hw,
4020 IXGBE_VFDCA_TXCTRL(i));
4021 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4022 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4028 * [VF] Start Transmit and Receive Units.
4031 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4033 struct ixgbe_hw *hw;
4034 struct igb_tx_queue *txq;
4035 struct igb_rx_queue *rxq;
4041 PMD_INIT_FUNC_TRACE();
4042 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4044 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4045 txq = dev->data->tx_queues[i];
4046 /* Setup Transmit Threshold Registers */
4047 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4048 txdctl |= txq->pthresh & 0x7F;
4049 txdctl |= ((txq->hthresh & 0x7F) << 8);
4050 txdctl |= ((txq->wthresh & 0x7F) << 16);
4051 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4054 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4056 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4057 txdctl |= IXGBE_TXDCTL_ENABLE;
4058 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4061 /* Wait until TX Enable ready */
4064 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4065 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4067 PMD_INIT_LOG(ERR, "Could not enable "
4068 "Tx Queue %d\n", i);
4070 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4072 rxq = dev->data->rx_queues[i];
4074 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4075 rxdctl |= IXGBE_RXDCTL_ENABLE;
4076 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4078 /* Wait until RX Enable ready */
4082 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4083 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4085 PMD_INIT_LOG(ERR, "Could not enable "
4086 "Rx Queue %d\n", i);
4088 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);