4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5 * Copyright 2014 6WIND S.A.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * * Neither the name of Intel Corporation nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
46 #include <rte_byteorder.h>
47 #include <rte_common.h>
48 #include <rte_cycles.h>
50 #include <rte_debug.h>
51 #include <rte_interrupts.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_launch.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
75 #include "ixgbe_logs.h"
76 #include "ixgbe/ixgbe_api.h"
77 #include "ixgbe/ixgbe_vf.h"
78 #include "ixgbe_ethdev.h"
79 #include "ixgbe/ixgbe_dcb.h"
80 #include "ixgbe/ixgbe_common.h"
81 #include "ixgbe_rxtx.h"
83 /* Bit Mask to indicate what bits required for building TX context */
84 #define IXGBE_TX_OFFLOAD_MASK ( \
90 static inline struct rte_mbuf *
91 rte_rxmbuf_alloc(struct rte_mempool *mp)
95 m = __rte_mbuf_raw_alloc(mp);
96 __rte_mbuf_sanity_check_raw(m, 0);
102 #define RTE_PMD_USE_PREFETCH
105 #ifdef RTE_PMD_USE_PREFETCH
107 * Prefetch a cache line into all cache levels.
109 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
111 #define rte_ixgbe_prefetch(p) do {} while(0)
114 /*********************************************************************
118 **********************************************************************/
121 * Check for descriptors with their DD bit set and free mbufs.
122 * Return the total number of buffers freed.
124 static inline int __attribute__((always_inline))
125 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
127 struct ixgbe_tx_entry *txep;
131 /* check DD bit on threshold descriptor */
132 status = txq->tx_ring[txq->tx_next_dd].wb.status;
133 if (! (status & IXGBE_ADVTXD_STAT_DD))
137 * first buffer to free from S/W ring is at index
138 * tx_next_dd - (tx_rs_thresh-1)
140 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
142 /* free buffers one at a time */
143 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
144 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
145 txep->mbuf->next = NULL;
146 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
150 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
151 rte_pktmbuf_free_seg(txep->mbuf);
156 /* buffers were freed, update counters */
157 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
158 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
159 if (txq->tx_next_dd >= txq->nb_tx_desc)
160 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
162 return txq->tx_rs_thresh;
165 /* Populate 4 descriptors with data from 4 mbufs */
167 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
169 uint64_t buf_dma_addr;
173 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
174 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
175 pkt_len = (*pkts)->data_len;
177 /* write data to descriptor */
178 txdp->read.buffer_addr = buf_dma_addr;
179 txdp->read.cmd_type_len =
180 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
181 txdp->read.olinfo_status =
182 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
183 rte_prefetch0(&(*pkts)->pool);
187 /* Populate 1 descriptor with data from 1 mbuf */
189 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
191 uint64_t buf_dma_addr;
194 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
195 pkt_len = (*pkts)->data_len;
197 /* write data to descriptor */
198 txdp->read.buffer_addr = buf_dma_addr;
199 txdp->read.cmd_type_len =
200 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
201 txdp->read.olinfo_status =
202 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
203 rte_prefetch0(&(*pkts)->pool);
207 * Fill H/W descriptor ring with mbuf data.
208 * Copy mbuf pointers to the S/W ring.
211 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
214 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
215 struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
216 const int N_PER_LOOP = 4;
217 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
218 int mainpart, leftover;
222 * Process most of the packets in chunks of N pkts. Any
223 * leftover packets will get processed one at a time.
225 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
226 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
227 for (i = 0; i < mainpart; i += N_PER_LOOP) {
228 /* Copy N mbuf pointers to the S/W ring */
229 for (j = 0; j < N_PER_LOOP; ++j) {
230 (txep + i + j)->mbuf = *(pkts + i + j);
232 tx4(txdp + i, pkts + i);
235 if (unlikely(leftover > 0)) {
236 for (i = 0; i < leftover; ++i) {
237 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
238 tx1(txdp + mainpart + i, pkts + mainpart + i);
243 static inline uint16_t
244 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
247 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
248 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
252 * Begin scanning the H/W ring for done descriptors when the
253 * number of available descriptors drops below tx_free_thresh. For
254 * each done descriptor, free the associated buffer.
256 if (txq->nb_tx_free < txq->tx_free_thresh)
257 ixgbe_tx_free_bufs(txq);
259 /* Only use descriptors that are available */
260 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
261 if (unlikely(nb_pkts == 0))
264 /* Use exactly nb_pkts descriptors */
265 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
268 * At this point, we know there are enough descriptors in the
269 * ring to transmit all the packets. This assumes that each
270 * mbuf contains a single segment, and that no new offloads
271 * are expected, which would require a new context descriptor.
275 * See if we're going to wrap-around. If so, handle the top
276 * of the descriptor ring first, then do the bottom. If not,
277 * the processing looks just like the "bottom" part anyway...
279 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
280 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
281 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
284 * We know that the last descriptor in the ring will need to
285 * have its RS bit set because tx_rs_thresh has to be
286 * a divisor of the ring size
288 tx_r[txq->tx_next_rs].read.cmd_type_len |=
289 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
290 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
295 /* Fill H/W descriptor ring with mbuf data */
296 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
297 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
300 * Determine if RS bit should be set
301 * This is what we actually want:
302 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
303 * but instead of subtracting 1 and doing >=, we can just do
304 * greater than without subtracting.
306 if (txq->tx_tail > txq->tx_next_rs) {
307 tx_r[txq->tx_next_rs].read.cmd_type_len |=
308 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
309 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
311 if (txq->tx_next_rs >= txq->nb_tx_desc)
312 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
316 * Check for wrap-around. This would only happen if we used
317 * up to the last descriptor in the ring, no more, no less.
319 if (txq->tx_tail >= txq->nb_tx_desc)
322 /* update tail pointer */
324 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
330 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
335 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
336 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
337 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
339 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
343 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
344 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
345 nb_tx = (uint16_t)(nb_tx + ret);
346 nb_pkts = (uint16_t)(nb_pkts - ret);
355 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
356 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
357 uint64_t ol_flags, union ixgbe_tx_offload tx_offload)
359 uint32_t type_tucmd_mlhl;
360 uint32_t mss_l4len_idx = 0;
362 uint32_t vlan_macip_lens;
363 union ixgbe_tx_offload tx_offload_mask;
365 ctx_idx = txq->ctx_curr;
366 tx_offload_mask.data = 0;
369 /* Specify which HW CTX to upload. */
370 mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
372 if (ol_flags & PKT_TX_VLAN_PKT) {
373 tx_offload_mask.vlan_tci |= ~0;
376 /* check if TCP segmentation required for this packet */
377 if (ol_flags & PKT_TX_TCP_SEG) {
378 /* implies IP cksum and TCP cksum */
379 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
380 IXGBE_ADVTXD_TUCMD_L4T_TCP |
381 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
383 tx_offload_mask.l2_len |= ~0;
384 tx_offload_mask.l3_len |= ~0;
385 tx_offload_mask.l4_len |= ~0;
386 tx_offload_mask.tso_segsz |= ~0;
387 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
388 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
389 } else { /* no TSO, check if hardware checksum is needed */
390 if (ol_flags & PKT_TX_IP_CKSUM) {
391 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
392 tx_offload_mask.l2_len |= ~0;
393 tx_offload_mask.l3_len |= ~0;
396 switch (ol_flags & PKT_TX_L4_MASK) {
397 case PKT_TX_UDP_CKSUM:
398 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
399 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
400 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
401 tx_offload_mask.l2_len |= ~0;
402 tx_offload_mask.l3_len |= ~0;
404 case PKT_TX_TCP_CKSUM:
405 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
406 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
407 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
408 tx_offload_mask.l2_len |= ~0;
409 tx_offload_mask.l3_len |= ~0;
410 tx_offload_mask.l4_len |= ~0;
412 case PKT_TX_SCTP_CKSUM:
413 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
414 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
415 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
416 tx_offload_mask.l2_len |= ~0;
417 tx_offload_mask.l3_len |= ~0;
420 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
421 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
426 txq->ctx_cache[ctx_idx].flags = ol_flags;
427 txq->ctx_cache[ctx_idx].tx_offload.data =
428 tx_offload_mask.data & tx_offload.data;
429 txq->ctx_cache[ctx_idx].tx_offload_mask = tx_offload_mask;
431 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
432 vlan_macip_lens = tx_offload.l3_len;
433 vlan_macip_lens |= (tx_offload.l2_len << IXGBE_ADVTXD_MACLEN_SHIFT);
434 vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
435 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
436 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
437 ctx_txd->seqnum_seed = 0;
441 * Check which hardware context can be used. Use the existing match
442 * or create a new context descriptor.
444 static inline uint32_t
445 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
446 union ixgbe_tx_offload tx_offload)
448 /* If match with the current used context */
449 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
450 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
451 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
452 return txq->ctx_curr;
455 /* What if match with the next context */
457 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
458 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
459 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
460 return txq->ctx_curr;
463 /* Mismatch, use the previous context */
464 return (IXGBE_CTX_NUM);
467 static inline uint32_t
468 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
471 if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
472 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
473 if (ol_flags & PKT_TX_IP_CKSUM)
474 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
475 if (ol_flags & PKT_TX_TCP_SEG)
476 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
480 static inline uint32_t
481 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
483 uint32_t cmdtype = 0;
484 if (ol_flags & PKT_TX_VLAN_PKT)
485 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
486 if (ol_flags & PKT_TX_TCP_SEG)
487 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
491 /* Default RS bit threshold values */
492 #ifndef DEFAULT_TX_RS_THRESH
493 #define DEFAULT_TX_RS_THRESH 32
495 #ifndef DEFAULT_TX_FREE_THRESH
496 #define DEFAULT_TX_FREE_THRESH 32
499 /* Reset transmit descriptors after they have been used */
501 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
503 struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
504 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
505 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
506 uint16_t nb_tx_desc = txq->nb_tx_desc;
507 uint16_t desc_to_clean_to;
508 uint16_t nb_tx_to_clean;
510 /* Determine the last descriptor needing to be cleaned */
511 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
512 if (desc_to_clean_to >= nb_tx_desc)
513 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
515 /* Check to make sure the last descriptor to clean is done */
516 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
517 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
519 PMD_TX_FREE_LOG(DEBUG,
520 "TX descriptor %4u is not done"
521 "(port=%d queue=%d)",
523 txq->port_id, txq->queue_id);
524 /* Failed to clean any descriptors, better luck next time */
528 /* Figure out how many descriptors will be cleaned */
529 if (last_desc_cleaned > desc_to_clean_to)
530 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
533 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
536 PMD_TX_FREE_LOG(DEBUG,
537 "Cleaning %4u TX descriptors: %4u to %4u "
538 "(port=%d queue=%d)",
539 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
540 txq->port_id, txq->queue_id);
543 * The last descriptor to clean is done, so that means all the
544 * descriptors from the last descriptor that was cleaned
545 * up to the last descriptor with the RS bit set
546 * are done. Only reset the threshold descriptor.
548 txr[desc_to_clean_to].wb.status = 0;
550 /* Update the txq to reflect the last descriptor that was cleaned */
551 txq->last_desc_cleaned = desc_to_clean_to;
552 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
559 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
562 struct ixgbe_tx_queue *txq;
563 struct ixgbe_tx_entry *sw_ring;
564 struct ixgbe_tx_entry *txe, *txn;
565 volatile union ixgbe_adv_tx_desc *txr;
566 volatile union ixgbe_adv_tx_desc *txd;
567 struct rte_mbuf *tx_pkt;
568 struct rte_mbuf *m_seg;
569 uint64_t buf_dma_addr;
570 uint32_t olinfo_status;
571 uint32_t cmd_type_len;
582 union ixgbe_tx_offload tx_offload = {0};
585 sw_ring = txq->sw_ring;
587 tx_id = txq->tx_tail;
588 txe = &sw_ring[tx_id];
590 /* Determine if the descriptor ring needs to be cleaned. */
591 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
592 ixgbe_xmit_cleanup(txq);
595 rte_prefetch0(&txe->mbuf->pool);
598 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
601 pkt_len = tx_pkt->pkt_len;
604 * Determine how many (if any) context descriptors
605 * are needed for offload functionality.
607 ol_flags = tx_pkt->ol_flags;
609 /* If hardware offload required */
610 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
612 tx_offload.l2_len = tx_pkt->l2_len;
613 tx_offload.l3_len = tx_pkt->l3_len;
614 tx_offload.l4_len = tx_pkt->l4_len;
615 tx_offload.vlan_tci = tx_pkt->vlan_tci;
616 tx_offload.tso_segsz = tx_pkt->tso_segsz;
618 /* If new context need be built or reuse the exist ctx. */
619 ctx = what_advctx_update(txq, tx_ol_req,
621 /* Only allocate context descriptor if required*/
622 new_ctx = (ctx == IXGBE_CTX_NUM);
627 * Keep track of how many descriptors are used this loop
628 * This will always be the number of segments + the number of
629 * Context descriptors required to transmit the packet
631 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
634 * The number of descriptors that must be allocated for a
635 * packet is the number of segments of that packet, plus 1
636 * Context Descriptor for the hardware offload, if any.
637 * Determine the last TX descriptor to allocate in the TX ring
638 * for the packet, starting from the current position (tx_id)
641 tx_last = (uint16_t) (tx_id + nb_used - 1);
644 if (tx_last >= txq->nb_tx_desc)
645 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
647 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
648 " tx_first=%u tx_last=%u",
649 (unsigned) txq->port_id,
650 (unsigned) txq->queue_id,
656 * Make sure there are enough TX descriptors available to
657 * transmit the entire packet.
658 * nb_used better be less than or equal to txq->tx_rs_thresh
660 if (nb_used > txq->nb_tx_free) {
661 PMD_TX_FREE_LOG(DEBUG,
662 "Not enough free TX descriptors "
663 "nb_used=%4u nb_free=%4u "
664 "(port=%d queue=%d)",
665 nb_used, txq->nb_tx_free,
666 txq->port_id, txq->queue_id);
668 if (ixgbe_xmit_cleanup(txq) != 0) {
669 /* Could not clean any descriptors */
675 /* nb_used better be <= txq->tx_rs_thresh */
676 if (unlikely(nb_used > txq->tx_rs_thresh)) {
677 PMD_TX_FREE_LOG(DEBUG,
678 "The number of descriptors needed to "
679 "transmit the packet exceeds the "
680 "RS bit threshold. This will impact "
682 "nb_used=%4u nb_free=%4u "
684 "(port=%d queue=%d)",
685 nb_used, txq->nb_tx_free,
687 txq->port_id, txq->queue_id);
689 * Loop here until there are enough TX
690 * descriptors or until the ring cannot be
693 while (nb_used > txq->nb_tx_free) {
694 if (ixgbe_xmit_cleanup(txq) != 0) {
696 * Could not clean any
708 * By now there are enough free TX descriptors to transmit
713 * Set common flags of all TX Data Descriptors.
715 * The following bits must be set in all Data Descriptors:
716 * - IXGBE_ADVTXD_DTYP_DATA
717 * - IXGBE_ADVTXD_DCMD_DEXT
719 * The following bits must be set in the first Data Descriptor
720 * and are ignored in the other ones:
721 * - IXGBE_ADVTXD_DCMD_IFCS
722 * - IXGBE_ADVTXD_MAC_1588
723 * - IXGBE_ADVTXD_DCMD_VLE
725 * The following bits must only be set in the last Data
727 * - IXGBE_TXD_CMD_EOP
729 * The following bits can be set in any Data Descriptor, but
730 * are only set in the last Data Descriptor:
733 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
734 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
736 #ifdef RTE_LIBRTE_IEEE1588
737 if (ol_flags & PKT_TX_IEEE1588_TMST)
738 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
744 if (ol_flags & PKT_TX_TCP_SEG) {
745 /* when TSO is on, paylen in descriptor is the
746 * not the packet len but the tcp payload len */
747 pkt_len -= (tx_offload.l2_len +
748 tx_offload.l3_len + tx_offload.l4_len);
752 * Setup the TX Advanced Context Descriptor if required
755 volatile struct ixgbe_adv_tx_context_desc *
758 ctx_txd = (volatile struct
759 ixgbe_adv_tx_context_desc *)
762 txn = &sw_ring[txe->next_id];
763 rte_prefetch0(&txn->mbuf->pool);
765 if (txe->mbuf != NULL) {
766 rte_pktmbuf_free_seg(txe->mbuf);
770 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
773 txe->last_id = tx_last;
774 tx_id = txe->next_id;
779 * Setup the TX Advanced Data Descriptor,
780 * This path will go through
781 * whatever new/reuse the context descriptor
783 cmd_type_len |= tx_desc_ol_flags_to_cmdtype(ol_flags);
784 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
785 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
788 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
793 txn = &sw_ring[txe->next_id];
794 rte_prefetch0(&txn->mbuf->pool);
796 if (txe->mbuf != NULL)
797 rte_pktmbuf_free_seg(txe->mbuf);
801 * Set up Transmit Data Descriptor.
803 slen = m_seg->data_len;
804 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
805 txd->read.buffer_addr =
806 rte_cpu_to_le_64(buf_dma_addr);
807 txd->read.cmd_type_len =
808 rte_cpu_to_le_32(cmd_type_len | slen);
809 txd->read.olinfo_status =
810 rte_cpu_to_le_32(olinfo_status);
811 txe->last_id = tx_last;
812 tx_id = txe->next_id;
815 } while (m_seg != NULL);
818 * The last packet data descriptor needs End Of Packet (EOP)
820 cmd_type_len |= IXGBE_TXD_CMD_EOP;
821 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
822 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
824 /* Set RS bit only on threshold packets' last descriptor */
825 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
826 PMD_TX_FREE_LOG(DEBUG,
827 "Setting RS bit on TXD id="
828 "%4u (port=%d queue=%d)",
829 tx_last, txq->port_id, txq->queue_id);
831 cmd_type_len |= IXGBE_TXD_CMD_RS;
833 /* Update txq RS bit counters */
836 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
842 * Set the Transmit Descriptor Tail (TDT)
844 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
845 (unsigned) txq->port_id, (unsigned) txq->queue_id,
846 (unsigned) tx_id, (unsigned) nb_tx);
847 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
848 txq->tx_tail = tx_id;
853 /*********************************************************************
857 **********************************************************************/
858 static inline uint64_t
859 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
863 static const uint64_t ip_pkt_types_map[16] = {
864 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
865 PKT_RX_IPV6_HDR, 0, 0, 0,
866 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
867 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
870 static const uint64_t ip_rss_types_map[16] = {
871 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
872 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
873 PKT_RX_RSS_HASH, 0, 0, 0,
874 0, 0, 0, PKT_RX_FDIR,
877 #ifdef RTE_LIBRTE_IEEE1588
878 static uint64_t ip_pkt_etqf_map[8] = {
879 0, 0, 0, PKT_RX_IEEE1588_PTP,
883 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
884 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
885 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
887 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
888 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
891 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
894 static inline uint64_t
895 rx_desc_status_to_pkt_flags(uint32_t rx_status)
900 * Check if VLAN present only.
901 * Do not check whether L3/L4 rx checksum done by NIC or not,
902 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
904 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
906 #ifdef RTE_LIBRTE_IEEE1588
907 if (rx_status & IXGBE_RXD_STAT_TMST)
908 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
913 static inline uint64_t
914 rx_desc_error_to_pkt_flags(uint32_t rx_status)
917 * Bit 31: IPE, IPv4 checksum error
918 * Bit 30: L4I, L4I integrity error
920 static uint64_t error_to_pkt_flags_map[4] = {
921 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
922 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
924 return error_to_pkt_flags_map[(rx_status >>
925 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
928 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
930 * LOOK_AHEAD defines how many desc statuses to check beyond the
931 * current descriptor.
932 * It must be a pound define for optimal performance.
933 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
934 * function only works with LOOK_AHEAD=8.
937 #if (LOOK_AHEAD != 8)
938 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
941 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
943 volatile union ixgbe_adv_rx_desc *rxdp;
944 struct ixgbe_rx_entry *rxep;
948 int s[LOOK_AHEAD], nb_dd;
952 /* get references to current descriptor and S/W ring entry */
953 rxdp = &rxq->rx_ring[rxq->rx_tail];
954 rxep = &rxq->sw_ring[rxq->rx_tail];
956 /* check to make sure there is at least 1 packet to receive */
957 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
961 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
962 * reference packets that are ready to be received.
964 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
965 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
967 /* Read desc statuses backwards to avoid race condition */
968 for (j = LOOK_AHEAD-1; j >= 0; --j)
969 s[j] = rxdp[j].wb.upper.status_error;
971 /* Compute how many status bits were set */
973 for (j = 0; j < LOOK_AHEAD; ++j)
974 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
978 /* Translate descriptor info to mbuf format */
979 for (j = 0; j < nb_dd; ++j) {
981 pkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len);
982 mb->data_len = pkt_len;
983 mb->pkt_len = pkt_len;
984 mb->vlan_tci = rxdp[j].wb.upper.vlan;
985 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
987 /* convert descriptor fields to rte mbuf flags */
988 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(
989 rxdp[j].wb.lower.lo_dword.data);
990 /* reuse status field from scan list */
991 pkt_flags |= rx_desc_status_to_pkt_flags(s[j]);
992 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
993 mb->ol_flags = pkt_flags;
995 if (likely(pkt_flags & PKT_RX_RSS_HASH))
996 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
997 else if (pkt_flags & PKT_RX_FDIR) {
999 (uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum)
1000 & IXGBE_ATR_HASH_MASK);
1001 mb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id;
1005 /* Move mbuf pointers from the S/W ring to the stage */
1006 for (j = 0; j < LOOK_AHEAD; ++j) {
1007 rxq->rx_stage[i + j] = rxep[j].mbuf;
1010 /* stop if all requested packets could not be received */
1011 if (nb_dd != LOOK_AHEAD)
1015 /* clear software ring entries so we can cleanup correctly */
1016 for (i = 0; i < nb_rx; ++i) {
1017 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1025 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)
1027 volatile union ixgbe_adv_rx_desc *rxdp;
1028 struct ixgbe_rx_entry *rxep;
1029 struct rte_mbuf *mb;
1034 /* allocate buffers in bulk directly into the S/W ring */
1035 alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1036 rxep = &rxq->sw_ring[alloc_idx];
1037 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1038 rxq->rx_free_thresh);
1039 if (unlikely(diag != 0))
1042 rxdp = &rxq->rx_ring[alloc_idx];
1043 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1044 /* populate the static rte mbuf fields */
1049 mb->port = rxq->port_id;
1052 rte_mbuf_refcnt_set(mb, 1);
1053 mb->data_off = RTE_PKTMBUF_HEADROOM;
1055 /* populate the descriptors */
1056 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
1057 rxdp[i].read.hdr_addr = dma_addr;
1058 rxdp[i].read.pkt_addr = dma_addr;
1061 /* update state of internal queue structure */
1062 rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
1063 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1064 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1070 static inline uint16_t
1071 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1074 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1077 /* how many packets are ready to return? */
1078 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1080 /* copy mbuf pointers to the application's packet list */
1081 for (i = 0; i < nb_pkts; ++i)
1082 rx_pkts[i] = stage[i];
1084 /* update internal queue state */
1085 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1086 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1091 static inline uint16_t
1092 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1095 struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1098 /* Any previously recv'd pkts will be returned from the Rx stage */
1099 if (rxq->rx_nb_avail)
1100 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1102 /* Scan the H/W ring for packets to receive */
1103 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1105 /* update internal queue state */
1106 rxq->rx_next_avail = 0;
1107 rxq->rx_nb_avail = nb_rx;
1108 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1110 /* if required, allocate new buffers to replenish descriptors */
1111 if (rxq->rx_tail > rxq->rx_free_trigger) {
1112 uint16_t cur_free_trigger = rxq->rx_free_trigger;
1114 if (ixgbe_rx_alloc_bufs(rxq, true) != 0) {
1116 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1117 "queue_id=%u", (unsigned) rxq->port_id,
1118 (unsigned) rxq->queue_id);
1120 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1121 rxq->rx_free_thresh;
1124 * Need to rewind any previous receives if we cannot
1125 * allocate new buffers to replenish the old ones.
1127 rxq->rx_nb_avail = 0;
1128 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1129 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1130 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1135 /* update tail pointer */
1137 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, cur_free_trigger);
1140 if (rxq->rx_tail >= rxq->nb_rx_desc)
1143 /* received any packets this loop? */
1144 if (rxq->rx_nb_avail)
1145 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1150 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1152 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1157 if (unlikely(nb_pkts == 0))
1160 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1161 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1163 /* request is relatively large, chunk it up */
1167 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1168 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1169 nb_rx = (uint16_t)(nb_rx + ret);
1170 nb_pkts = (uint16_t)(nb_pkts - ret);
1180 /* Stub to avoid extra ifdefs */
1182 ixgbe_recv_pkts_bulk_alloc(__rte_unused void *rx_queue,
1183 __rte_unused struct rte_mbuf **rx_pkts, __rte_unused uint16_t nb_pkts)
1189 ixgbe_rx_alloc_bufs(__rte_unused struct ixgbe_rx_queue *rxq,
1190 __rte_unused bool reset_mbuf)
1194 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1197 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1200 struct ixgbe_rx_queue *rxq;
1201 volatile union ixgbe_adv_rx_desc *rx_ring;
1202 volatile union ixgbe_adv_rx_desc *rxdp;
1203 struct ixgbe_rx_entry *sw_ring;
1204 struct ixgbe_rx_entry *rxe;
1205 struct rte_mbuf *rxm;
1206 struct rte_mbuf *nmb;
1207 union ixgbe_adv_rx_desc rxd;
1210 uint32_t hlen_type_rss;
1220 rx_id = rxq->rx_tail;
1221 rx_ring = rxq->rx_ring;
1222 sw_ring = rxq->sw_ring;
1223 while (nb_rx < nb_pkts) {
1225 * The order of operations here is important as the DD status
1226 * bit must not be read after any other descriptor fields.
1227 * rx_ring and rxdp are pointing to volatile data so the order
1228 * of accesses cannot be reordered by the compiler. If they were
1229 * not volatile, they could be reordered which could lead to
1230 * using invalid descriptor fields when read from rxd.
1232 rxdp = &rx_ring[rx_id];
1233 staterr = rxdp->wb.upper.status_error;
1234 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1241 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1242 * is likely to be invalid and to be dropped by the various
1243 * validation checks performed by the network stack.
1245 * Allocate a new mbuf to replenish the RX ring descriptor.
1246 * If the allocation fails:
1247 * - arrange for that RX descriptor to be the first one
1248 * being parsed the next time the receive function is
1249 * invoked [on the same queue].
1251 * - Stop parsing the RX ring and return immediately.
1253 * This policy do not drop the packet received in the RX
1254 * descriptor for which the allocation of a new mbuf failed.
1255 * Thus, it allows that packet to be later retrieved if
1256 * mbuf have been freed in the mean time.
1257 * As a side effect, holding RX descriptors instead of
1258 * systematically giving them back to the NIC may lead to
1259 * RX ring exhaustion situations.
1260 * However, the NIC can gracefully prevent such situations
1261 * to happen by sending specific "back-pressure" flow control
1262 * frames to its peer(s).
1264 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1265 "ext_err_stat=0x%08x pkt_len=%u",
1266 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1267 (unsigned) rx_id, (unsigned) staterr,
1268 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1270 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1272 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1273 "queue_id=%u", (unsigned) rxq->port_id,
1274 (unsigned) rxq->queue_id);
1275 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1280 rxe = &sw_ring[rx_id];
1282 if (rx_id == rxq->nb_rx_desc)
1285 /* Prefetch next mbuf while processing current one. */
1286 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1289 * When next RX descriptor is on a cache-line boundary,
1290 * prefetch the next 4 RX descriptors and the next 8 pointers
1293 if ((rx_id & 0x3) == 0) {
1294 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1295 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1301 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1302 rxdp->read.hdr_addr = dma_addr;
1303 rxdp->read.pkt_addr = dma_addr;
1306 * Initialize the returned mbuf.
1307 * 1) setup generic mbuf fields:
1308 * - number of segments,
1311 * - RX port identifier.
1312 * 2) integrate hardware offload data, if any:
1313 * - RSS flag & hash,
1314 * - IP checksum flag,
1315 * - VLAN TCI, if any,
1318 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1320 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1321 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1324 rxm->pkt_len = pkt_len;
1325 rxm->data_len = pkt_len;
1326 rxm->port = rxq->port_id;
1328 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1329 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1330 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1332 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1333 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1334 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1335 rxm->ol_flags = pkt_flags;
1337 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1338 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1339 else if (pkt_flags & PKT_RX_FDIR) {
1340 rxm->hash.fdir.hash =
1341 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1342 & IXGBE_ATR_HASH_MASK);
1343 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1346 * Store the mbuf address into the next entry of the array
1347 * of returned packets.
1349 rx_pkts[nb_rx++] = rxm;
1351 rxq->rx_tail = rx_id;
1354 * If the number of free RX descriptors is greater than the RX free
1355 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1357 * Update the RDT with the value of the last processed RX descriptor
1358 * minus 1, to guarantee that the RDT register is never equal to the
1359 * RDH register, which creates a "full" ring situtation from the
1360 * hardware point of view...
1362 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1363 if (nb_hold > rxq->rx_free_thresh) {
1364 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1365 "nb_hold=%u nb_rx=%u",
1366 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1367 (unsigned) rx_id, (unsigned) nb_hold,
1369 rx_id = (uint16_t) ((rx_id == 0) ?
1370 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1371 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1374 rxq->nb_rx_hold = nb_hold;
1379 * Detect an RSC descriptor.
1381 static inline uint32_t
1382 ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
1384 return (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &
1385 IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
1389 * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
1391 * Fill the following info in the HEAD buffer of the Rx cluster:
1392 * - RX port identifier
1393 * - hardware offload data, if any:
1395 * - IP checksum flag
1396 * - VLAN TCI, if any
1398 * @head HEAD of the packet cluster
1399 * @desc HW descriptor to get data from
1400 * @port_id Port ID of the Rx queue
1403 ixgbe_fill_cluster_head_buf(
1404 struct rte_mbuf *head,
1405 union ixgbe_adv_rx_desc *desc,
1409 uint32_t hlen_type_rss;
1412 head->port = port_id;
1415 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1416 * set in the pkt_flags field.
1418 head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1419 hlen_type_rss = rte_le_to_cpu_32(desc->wb.lower.lo_dword.data);
1420 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1421 pkt_flags |= rx_desc_status_to_pkt_flags(staterr);
1422 pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1423 head->ol_flags = pkt_flags;
1425 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1426 head->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);
1427 else if (pkt_flags & PKT_RX_FDIR) {
1428 head->hash.fdir.hash =
1429 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)
1430 & IXGBE_ATR_HASH_MASK;
1431 head->hash.fdir.id =
1432 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);
1437 * ixgbe_recv_pkts_lro - receive handler for and LRO case.
1439 * @rx_queue Rx queue handle
1440 * @rx_pkts table of received packets
1441 * @nb_pkts size of rx_pkts table
1442 * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling
1444 * Handles the Rx HW ring completions when RSC feature is configured. Uses an
1445 * additional ring of ixgbe_rsc_entry's that will hold the relevant RSC info.
1447 * We use the same logic as in Linux and in FreeBSD ixgbe drivers:
1448 * 1) When non-EOP RSC completion arrives:
1449 * a) Update the HEAD of the current RSC aggregation cluster with the new
1450 * segment's data length.
1451 * b) Set the "next" pointer of the current segment to point to the segment
1452 * at the NEXTP index.
1453 * c) Pass the HEAD of RSC aggregation cluster on to the next NEXTP entry
1454 * in the sw_rsc_ring.
1455 * 2) When EOP arrives we just update the cluster's total length and offload
1456 * flags and deliver the cluster up to the upper layers. In our case - put it
1457 * in the rx_pkts table.
1459 * Returns the number of received packets/clusters (according to the "bulk
1460 * receive" interface).
1462 static inline uint16_t
1463 ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
1466 struct ixgbe_rx_queue *rxq = rx_queue;
1467 volatile union ixgbe_adv_rx_desc *rx_ring = rxq->rx_ring;
1468 struct ixgbe_rx_entry *sw_ring = rxq->sw_ring;
1469 struct ixgbe_rsc_entry *sw_rsc_ring = rxq->sw_rsc_ring;
1470 uint16_t rx_id = rxq->rx_tail;
1472 uint16_t nb_hold = rxq->nb_rx_hold;
1473 uint16_t prev_id = rxq->rx_tail;
1475 while (nb_rx < nb_pkts) {
1477 struct ixgbe_rx_entry *rxe;
1478 struct ixgbe_rsc_entry *rsc_entry;
1479 struct ixgbe_rsc_entry *next_rsc_entry;
1480 struct ixgbe_rx_entry *next_rxe;
1481 struct rte_mbuf *first_seg;
1482 struct rte_mbuf *rxm;
1483 struct rte_mbuf *nmb;
1484 union ixgbe_adv_rx_desc rxd;
1487 volatile union ixgbe_adv_rx_desc *rxdp;
1492 * The code in this whole file uses the volatile pointer to
1493 * ensure the read ordering of the status and the rest of the
1494 * descriptor fields (on the compiler level only!!!). This is so
1495 * UGLY - why not to just use the compiler barrier instead? DPDK
1496 * even has the rte_compiler_barrier() for that.
1498 * But most importantly this is just wrong because this doesn't
1499 * ensure memory ordering in a general case at all. For
1500 * instance, DPDK is supposed to work on Power CPUs where
1501 * compiler barrier may just not be enough!
1503 * I tried to write only this function properly to have a
1504 * starting point (as a part of an LRO/RSC series) but the
1505 * compiler cursed at me when I tried to cast away the
1506 * "volatile" from rx_ring (yes, it's volatile too!!!). So, I'm
1507 * keeping it the way it is for now.
1509 * The code in this file is broken in so many other places and
1510 * will just not work on a big endian CPU anyway therefore the
1511 * lines below will have to be revisited together with the rest
1515 * - Get rid of "volatile" crap and let the compiler do its
1517 * - Use the proper memory barrier (rte_rmb()) to ensure the
1518 * memory ordering below.
1520 rxdp = &rx_ring[rx_id];
1521 staterr = rte_le_to_cpu_32(rxdp->wb.upper.status_error);
1523 if (!(staterr & IXGBE_RXDADV_STAT_DD))
1528 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1529 "staterr=0x%x data_len=%u",
1530 rxq->port_id, rxq->queue_id, rx_id, staterr,
1531 rte_le_to_cpu_16(rxd.wb.upper.length));
1534 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1536 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed "
1537 "port_id=%u queue_id=%u",
1538 rxq->port_id, rxq->queue_id);
1540 rte_eth_devices[rxq->port_id].data->
1541 rx_mbuf_alloc_failed++;
1544 } else if (nb_hold > rxq->rx_free_thresh) {
1545 uint16_t next_rdt = rxq->rx_free_trigger;
1547 if (!ixgbe_rx_alloc_bufs(rxq, false)) {
1549 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr,
1551 nb_hold -= rxq->rx_free_thresh;
1553 PMD_RX_LOG(DEBUG, "RX bulk alloc failed "
1554 "port_id=%u queue_id=%u",
1555 rxq->port_id, rxq->queue_id);
1557 rte_eth_devices[rxq->port_id].data->
1558 rx_mbuf_alloc_failed++;
1564 rxe = &sw_ring[rx_id];
1565 eop = staterr & IXGBE_RXDADV_STAT_EOP;
1567 next_id = rx_id + 1;
1568 if (next_id == rxq->nb_rx_desc)
1571 /* Prefetch next mbuf while processing current one. */
1572 rte_ixgbe_prefetch(sw_ring[next_id].mbuf);
1575 * When next RX descriptor is on a cache-line boundary,
1576 * prefetch the next 4 RX descriptors and the next 4 pointers
1579 if ((next_id & 0x3) == 0) {
1580 rte_ixgbe_prefetch(&rx_ring[next_id]);
1581 rte_ixgbe_prefetch(&sw_ring[next_id]);
1588 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1590 * Update RX descriptor with the physical address of the
1591 * new data buffer of the new allocated mbuf.
1595 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1596 rxdp->read.hdr_addr = dma;
1597 rxdp->read.pkt_addr = dma;
1602 * Set data length & data buffer address of mbuf.
1604 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1605 rxm->data_len = data_len;
1610 * Get next descriptor index:
1611 * - For RSC it's in the NEXTP field.
1612 * - For a scattered packet - it's just a following
1615 if (ixgbe_rsc_count(&rxd))
1617 (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1618 IXGBE_RXDADV_NEXTP_SHIFT;
1622 next_rsc_entry = &sw_rsc_ring[nextp_id];
1623 next_rxe = &sw_ring[nextp_id];
1624 rte_ixgbe_prefetch(next_rxe);
1627 rsc_entry = &sw_rsc_ring[rx_id];
1628 first_seg = rsc_entry->fbuf;
1629 rsc_entry->fbuf = NULL;
1632 * If this is the first buffer of the received packet,
1633 * set the pointer to the first mbuf of the packet and
1634 * initialize its context.
1635 * Otherwise, update the total length and the number of segments
1636 * of the current scattered packet, and update the pointer to
1637 * the last mbuf of the current packet.
1639 if (first_seg == NULL) {
1641 first_seg->pkt_len = data_len;
1642 first_seg->nb_segs = 1;
1644 first_seg->pkt_len += data_len;
1645 first_seg->nb_segs++;
1652 * If this is not the last buffer of the received packet, update
1653 * the pointer to the first mbuf at the NEXTP entry in the
1654 * sw_rsc_ring and continue to parse the RX ring.
1657 rxm->next = next_rxe->mbuf;
1658 next_rsc_entry->fbuf = first_seg;
1663 * This is the last buffer of the received packet - return
1664 * the current cluster to the user.
1668 /* Initialize the first mbuf of the returned packet */
1669 ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq->port_id,
1672 /* Prefetch data of first segment, if configured to do so. */
1673 rte_packet_prefetch((char *)first_seg->buf_addr +
1674 first_seg->data_off);
1677 * Store the mbuf address into the next entry of the array
1678 * of returned packets.
1680 rx_pkts[nb_rx++] = first_seg;
1684 * Record index of the next RX descriptor to probe.
1686 rxq->rx_tail = rx_id;
1689 * If the number of free RX descriptors is greater than the RX free
1690 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1692 * Update the RDT with the value of the last processed RX descriptor
1693 * minus 1, to guarantee that the RDT register is never equal to the
1694 * RDH register, which creates a "full" ring situtation from the
1695 * hardware point of view...
1697 if (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {
1698 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1699 "nb_hold=%u nb_rx=%u",
1700 rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
1703 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, prev_id);
1707 rxq->nb_rx_hold = nb_hold;
1712 ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1715 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, false);
1719 ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1722 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, true);
1726 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1729 struct ixgbe_rx_queue *rxq;
1730 volatile union ixgbe_adv_rx_desc *rx_ring;
1731 volatile union ixgbe_adv_rx_desc *rxdp;
1732 struct ixgbe_rx_entry *sw_ring;
1733 struct ixgbe_rx_entry *rxe;
1734 struct rte_mbuf *first_seg;
1735 struct rte_mbuf *last_seg;
1736 struct rte_mbuf *rxm;
1737 struct rte_mbuf *nmb;
1738 union ixgbe_adv_rx_desc rxd;
1739 uint64_t dma; /* Physical address of mbuf data buffer */
1749 rx_id = rxq->rx_tail;
1750 rx_ring = rxq->rx_ring;
1751 sw_ring = rxq->sw_ring;
1754 * Retrieve RX context of current packet, if any.
1756 first_seg = rxq->pkt_first_seg;
1757 last_seg = rxq->pkt_last_seg;
1759 while (nb_rx < nb_pkts) {
1762 * The order of operations here is important as the DD status
1763 * bit must not be read after any other descriptor fields.
1764 * rx_ring and rxdp are pointing to volatile data so the order
1765 * of accesses cannot be reordered by the compiler. If they were
1766 * not volatile, they could be reordered which could lead to
1767 * using invalid descriptor fields when read from rxd.
1769 rxdp = &rx_ring[rx_id];
1770 staterr = rxdp->wb.upper.status_error;
1771 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1778 * Allocate a new mbuf to replenish the RX ring descriptor.
1779 * If the allocation fails:
1780 * - arrange for that RX descriptor to be the first one
1781 * being parsed the next time the receive function is
1782 * invoked [on the same queue].
1784 * - Stop parsing the RX ring and return immediately.
1786 * This policy does not drop the packet received in the RX
1787 * descriptor for which the allocation of a new mbuf failed.
1788 * Thus, it allows that packet to be later retrieved if
1789 * mbuf have been freed in the mean time.
1790 * As a side effect, holding RX descriptors instead of
1791 * systematically giving them back to the NIC may lead to
1792 * RX ring exhaustion situations.
1793 * However, the NIC can gracefully prevent such situations
1794 * to happen by sending specific "back-pressure" flow control
1795 * frames to its peer(s).
1797 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1798 "staterr=0x%x data_len=%u",
1799 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1800 (unsigned) rx_id, (unsigned) staterr,
1801 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1803 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1805 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1806 "queue_id=%u", (unsigned) rxq->port_id,
1807 (unsigned) rxq->queue_id);
1808 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1813 rxe = &sw_ring[rx_id];
1815 if (rx_id == rxq->nb_rx_desc)
1818 /* Prefetch next mbuf while processing current one. */
1819 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1822 * When next RX descriptor is on a cache-line boundary,
1823 * prefetch the next 4 RX descriptors and the next 8 pointers
1826 if ((rx_id & 0x3) == 0) {
1827 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1828 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1832 * Update RX descriptor with the physical address of the new
1833 * data buffer of the new allocated mbuf.
1837 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1838 rxdp->read.hdr_addr = dma;
1839 rxdp->read.pkt_addr = dma;
1842 * Set data length & data buffer address of mbuf.
1844 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1845 rxm->data_len = data_len;
1846 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1849 * If this is the first buffer of the received packet,
1850 * set the pointer to the first mbuf of the packet and
1851 * initialize its context.
1852 * Otherwise, update the total length and the number of segments
1853 * of the current scattered packet, and update the pointer to
1854 * the last mbuf of the current packet.
1856 if (first_seg == NULL) {
1858 first_seg->pkt_len = data_len;
1859 first_seg->nb_segs = 1;
1861 first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
1863 first_seg->nb_segs++;
1864 last_seg->next = rxm;
1868 * If this is not the last buffer of the received packet,
1869 * update the pointer to the last mbuf of the current scattered
1870 * packet and continue to parse the RX ring.
1872 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1878 * This is the last buffer of the received packet.
1879 * If the CRC is not stripped by the hardware:
1880 * - Subtract the CRC length from the total packet length.
1881 * - If the last buffer only contains the whole CRC or a part
1882 * of it, free the mbuf associated to the last buffer.
1883 * If part of the CRC is also contained in the previous
1884 * mbuf, subtract the length of that CRC part from the
1885 * data length of the previous mbuf.
1888 if (unlikely(rxq->crc_len > 0)) {
1889 first_seg->pkt_len -= ETHER_CRC_LEN;
1890 if (data_len <= ETHER_CRC_LEN) {
1891 rte_pktmbuf_free_seg(rxm);
1892 first_seg->nb_segs--;
1893 last_seg->data_len = (uint16_t)
1894 (last_seg->data_len -
1895 (ETHER_CRC_LEN - data_len));
1896 last_seg->next = NULL;
1899 (uint16_t) (data_len - ETHER_CRC_LEN);
1902 /* Initialize the first mbuf of the returned packet */
1903 ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq->port_id,
1906 /* Prefetch data of first segment, if configured to do so. */
1907 rte_packet_prefetch((char *)first_seg->buf_addr +
1908 first_seg->data_off);
1911 * Store the mbuf address into the next entry of the array
1912 * of returned packets.
1914 rx_pkts[nb_rx++] = first_seg;
1917 * Setup receipt context for a new packet.
1923 * Record index of the next RX descriptor to probe.
1925 rxq->rx_tail = rx_id;
1928 * Save receive context.
1930 rxq->pkt_first_seg = first_seg;
1931 rxq->pkt_last_seg = last_seg;
1934 * If the number of free RX descriptors is greater than the RX free
1935 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1937 * Update the RDT with the value of the last processed RX descriptor
1938 * minus 1, to guarantee that the RDT register is never equal to the
1939 * RDH register, which creates a "full" ring situtation from the
1940 * hardware point of view...
1942 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1943 if (nb_hold > rxq->rx_free_thresh) {
1944 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1945 "nb_hold=%u nb_rx=%u",
1946 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1947 (unsigned) rx_id, (unsigned) nb_hold,
1949 rx_id = (uint16_t) ((rx_id == 0) ?
1950 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1951 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1954 rxq->nb_rx_hold = nb_hold;
1958 /*********************************************************************
1960 * Queue management functions
1962 **********************************************************************/
1965 * Rings setup and release.
1967 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1968 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1969 * also optimize cache line size effect. H/W supports up to cache line size 128.
1971 #define IXGBE_ALIGN 128
1974 * Maximum number of Ring Descriptors.
1976 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1977 * descriptors should meet the following condition:
1978 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1980 #define IXGBE_MIN_RING_DESC 32
1981 #define IXGBE_MAX_RING_DESC 4096
1984 * Create memzone for HW rings. malloc can't be used as the physical address is
1985 * needed. If the memzone is already created, then this function returns a ptr
1988 static const struct rte_memzone *
1989 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1990 uint16_t queue_id, uint32_t ring_size, int socket_id)
1992 char z_name[RTE_MEMZONE_NAMESIZE];
1993 const struct rte_memzone *mz;
1995 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1996 dev->driver->pci_drv.name, ring_name,
1997 dev->data->port_id, queue_id);
1999 mz = rte_memzone_lookup(z_name);
2003 #ifdef RTE_LIBRTE_XEN_DOM0
2004 return rte_memzone_reserve_bounded(z_name, ring_size,
2005 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
2007 return rte_memzone_reserve_aligned(z_name, ring_size,
2008 socket_id, 0, IXGBE_ALIGN);
2013 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
2017 if (txq->sw_ring != NULL) {
2018 for (i = 0; i < txq->nb_tx_desc; i++) {
2019 if (txq->sw_ring[i].mbuf != NULL) {
2020 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2021 txq->sw_ring[i].mbuf = NULL;
2028 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
2031 txq->sw_ring != NULL)
2032 rte_free(txq->sw_ring);
2036 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
2038 if (txq != NULL && txq->ops != NULL) {
2039 txq->ops->release_mbufs(txq);
2040 txq->ops->free_swring(txq);
2046 ixgbe_dev_tx_queue_release(void *txq)
2048 ixgbe_tx_queue_release(txq);
2051 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
2053 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
2055 static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
2056 struct ixgbe_tx_entry *txe = txq->sw_ring;
2059 /* Zero out HW ring memory */
2060 for (i = 0; i < txq->nb_tx_desc; i++) {
2061 txq->tx_ring[i] = zeroed_desc;
2064 /* Initialize SW ring entries */
2065 prev = (uint16_t) (txq->nb_tx_desc - 1);
2066 for (i = 0; i < txq->nb_tx_desc; i++) {
2067 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
2068 txd->wb.status = IXGBE_TXD_STAT_DD;
2071 txe[prev].next_id = i;
2075 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2076 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2079 txq->nb_tx_used = 0;
2081 * Always allow 1 descriptor to be un-allocated to avoid
2082 * a H/W race condition
2084 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2085 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2087 memset((void*)&txq->ctx_cache, 0,
2088 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
2091 static const struct ixgbe_txq_ops def_txq_ops = {
2092 .release_mbufs = ixgbe_tx_queue_release_mbufs,
2093 .free_swring = ixgbe_tx_free_swring,
2094 .reset = ixgbe_reset_tx_queue,
2097 /* Takes an ethdev and a queue and sets up the tx function to be used based on
2098 * the queue parameters. Used in tx_queue_setup by primary process and then
2099 * in dev_init by secondary process when attaching to an existing ethdev.
2102 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
2104 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2105 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS)
2106 && (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
2107 PMD_INIT_LOG(INFO, "Using simple tx code path");
2108 #ifdef RTE_IXGBE_INC_VECTOR
2109 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
2110 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
2111 ixgbe_txq_vec_setup(txq) == 0)) {
2112 PMD_INIT_LOG(INFO, "Vector tx enabled.");
2113 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
2116 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
2118 PMD_INIT_LOG(INFO, "Using full-featured tx code path");
2120 " - txq_flags = %lx " "[IXGBE_SIMPLE_FLAGS=%lx]",
2121 (unsigned long)txq->txq_flags,
2122 (unsigned long)IXGBE_SIMPLE_FLAGS);
2124 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
2125 (unsigned long)txq->tx_rs_thresh,
2126 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
2127 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2132 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
2135 unsigned int socket_id,
2136 const struct rte_eth_txconf *tx_conf)
2138 const struct rte_memzone *tz;
2139 struct ixgbe_tx_queue *txq;
2140 struct ixgbe_hw *hw;
2141 uint16_t tx_rs_thresh, tx_free_thresh;
2143 PMD_INIT_FUNC_TRACE();
2144 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2147 * Validate number of transmit descriptors.
2148 * It must not exceed hardware maximum, and must be multiple
2151 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
2152 (nb_desc > IXGBE_MAX_RING_DESC) ||
2153 (nb_desc < IXGBE_MIN_RING_DESC)) {
2158 * The following two parameters control the setting of the RS bit on
2159 * transmit descriptors.
2160 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
2161 * descriptors have been used.
2162 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
2163 * descriptors are used or if the number of descriptors required
2164 * to transmit a packet is greater than the number of free TX
2166 * The following constraints must be satisfied:
2167 * tx_rs_thresh must be greater than 0.
2168 * tx_rs_thresh must be less than the size of the ring minus 2.
2169 * tx_rs_thresh must be less than or equal to tx_free_thresh.
2170 * tx_rs_thresh must be a divisor of the ring size.
2171 * tx_free_thresh must be greater than 0.
2172 * tx_free_thresh must be less than the size of the ring minus 3.
2173 * One descriptor in the TX ring is used as a sentinel to avoid a
2174 * H/W race condition, hence the maximum threshold constraints.
2175 * When set to zero use default values.
2177 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2178 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2179 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2180 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2181 if (tx_rs_thresh >= (nb_desc - 2)) {
2182 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
2183 "of TX descriptors minus 2. (tx_rs_thresh=%u "
2184 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2185 (int)dev->data->port_id, (int)queue_idx);
2188 if (tx_free_thresh >= (nb_desc - 3)) {
2189 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2190 "tx_free_thresh must be less than the number of "
2191 "TX descriptors minus 3. (tx_free_thresh=%u "
2192 "port=%d queue=%d)",
2193 (unsigned int)tx_free_thresh,
2194 (int)dev->data->port_id, (int)queue_idx);
2197 if (tx_rs_thresh > tx_free_thresh) {
2198 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
2199 "tx_free_thresh. (tx_free_thresh=%u "
2200 "tx_rs_thresh=%u port=%d queue=%d)",
2201 (unsigned int)tx_free_thresh,
2202 (unsigned int)tx_rs_thresh,
2203 (int)dev->data->port_id,
2207 if ((nb_desc % tx_rs_thresh) != 0) {
2208 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2209 "number of TX descriptors. (tx_rs_thresh=%u "
2210 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2211 (int)dev->data->port_id, (int)queue_idx);
2216 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
2217 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
2218 * by the NIC and all descriptors are written back after the NIC
2219 * accumulates WTHRESH descriptors.
2221 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2222 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2223 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
2224 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2225 (int)dev->data->port_id, (int)queue_idx);
2229 /* Free memory prior to re-allocation if needed... */
2230 if (dev->data->tx_queues[queue_idx] != NULL) {
2231 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
2232 dev->data->tx_queues[queue_idx] = NULL;
2235 /* First allocate the tx queue data structure */
2236 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
2237 RTE_CACHE_LINE_SIZE, socket_id);
2242 * Allocate TX ring hardware descriptors. A memzone large enough to
2243 * handle the maximum ring size is allocated in order to allow for
2244 * resizing in later calls to the queue setup function.
2246 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
2247 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
2250 ixgbe_tx_queue_release(txq);
2254 txq->nb_tx_desc = nb_desc;
2255 txq->tx_rs_thresh = tx_rs_thresh;
2256 txq->tx_free_thresh = tx_free_thresh;
2257 txq->pthresh = tx_conf->tx_thresh.pthresh;
2258 txq->hthresh = tx_conf->tx_thresh.hthresh;
2259 txq->wthresh = tx_conf->tx_thresh.wthresh;
2260 txq->queue_id = queue_idx;
2261 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2262 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2263 txq->port_id = dev->data->port_id;
2264 txq->txq_flags = tx_conf->txq_flags;
2265 txq->ops = &def_txq_ops;
2266 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2269 * Modification to set VFTDT for virtual function if vf is detected
2271 if (hw->mac.type == ixgbe_mac_82599_vf ||
2272 hw->mac.type == ixgbe_mac_X540_vf ||
2273 hw->mac.type == ixgbe_mac_X550_vf ||
2274 hw->mac.type == ixgbe_mac_X550EM_x_vf)
2275 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
2277 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
2278 #ifndef RTE_LIBRTE_XEN_DOM0
2279 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
2281 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2283 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
2285 /* Allocate software ring */
2286 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
2287 sizeof(struct ixgbe_tx_entry) * nb_desc,
2288 RTE_CACHE_LINE_SIZE, socket_id);
2289 if (txq->sw_ring == NULL) {
2290 ixgbe_tx_queue_release(txq);
2293 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2294 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
2296 /* set up vector or scalar TX function as appropriate */
2297 ixgbe_set_tx_function(dev, txq);
2299 txq->ops->reset(txq);
2301 dev->data->tx_queues[queue_idx] = txq;
2308 * ixgbe_free_rsc_cluster - free the not-yet-completed RSC cluster
2310 * The "next" pointer of the last segment of (not-yet-completed) RSC clusters
2311 * in the sw_rsc_ring is not set to NULL but rather points to the next
2312 * mbuf of this RSC aggregation (that has not been completed yet and still
2313 * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we
2314 * will just free first "nb_segs" segments of the cluster explicitly by calling
2315 * an rte_pktmbuf_free_seg().
2317 * @m RSC cluster head
2320 ixgbe_free_rsc_cluster(struct rte_mbuf *m)
2322 uint8_t i, nb_segs = m->nb_segs;
2323 struct rte_mbuf *next_seg;
2325 for (i = 0; i < nb_segs; i++) {
2327 rte_pktmbuf_free_seg(m);
2333 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
2337 if (rxq->sw_ring != NULL) {
2338 for (i = 0; i < rxq->nb_rx_desc; i++) {
2339 if (rxq->sw_ring[i].mbuf != NULL) {
2340 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2341 rxq->sw_ring[i].mbuf = NULL;
2344 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2345 if (rxq->rx_nb_avail) {
2346 for (i = 0; i < rxq->rx_nb_avail; ++i) {
2347 struct rte_mbuf *mb;
2348 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2349 rte_pktmbuf_free_seg(mb);
2351 rxq->rx_nb_avail = 0;
2356 if (rxq->sw_rsc_ring)
2357 for (i = 0; i < rxq->nb_rx_desc; i++)
2358 if (rxq->sw_rsc_ring[i].fbuf) {
2359 ixgbe_free_rsc_cluster(rxq->sw_rsc_ring[i].fbuf);
2360 rxq->sw_rsc_ring[i].fbuf = NULL;
2365 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2368 ixgbe_rx_queue_release_mbufs(rxq);
2369 rte_free(rxq->sw_ring);
2370 rte_free(rxq->sw_rsc_ring);
2376 ixgbe_dev_rx_queue_release(void *rxq)
2378 ixgbe_rx_queue_release(rxq);
2382 * Check if Rx Burst Bulk Alloc function can be used.
2384 * 0: the preconditions are satisfied and the bulk allocation function
2386 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2387 * function must be used.
2390 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2391 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2393 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct ixgbe_rx_queue *rxq)
2399 * Make sure the following pre-conditions are satisfied:
2400 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2401 * rxq->rx_free_thresh < rxq->nb_rx_desc
2402 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2403 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2404 * Scattered packets are not supported. This should be checked
2405 * outside of this function.
2407 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2408 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2409 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2410 "rxq->rx_free_thresh=%d, "
2411 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2412 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2414 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2415 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2416 "rxq->rx_free_thresh=%d, "
2417 "rxq->nb_rx_desc=%d",
2418 rxq->rx_free_thresh, rxq->nb_rx_desc);
2420 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2421 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2422 "rxq->nb_rx_desc=%d, "
2423 "rxq->rx_free_thresh=%d",
2424 rxq->nb_rx_desc, rxq->rx_free_thresh);
2426 } else if (!(rxq->nb_rx_desc <
2427 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2428 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2429 "rxq->nb_rx_desc=%d, "
2430 "IXGBE_MAX_RING_DESC=%d, "
2431 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2432 rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2433 RTE_PMD_IXGBE_RX_MAX_BURST);
2443 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2445 ixgbe_reset_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_rx_queue *rxq)
2447 static const union ixgbe_adv_rx_desc zeroed_desc = {{0}};
2449 uint16_t len = rxq->nb_rx_desc;
2452 * By default, the Rx queue setup function allocates enough memory for
2453 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2454 * extra memory at the end of the descriptor ring to be zero'd out. A
2455 * pre-condition for using the Rx burst bulk alloc function is that the
2456 * number of descriptors is less than or equal to
2457 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2458 * constraints here to see if we need to zero out memory after the end
2459 * of the H/W descriptor ring.
2461 if (adapter->rx_bulk_alloc_allowed)
2462 /* zero out extra memory */
2463 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2466 * Zero out HW ring memory. Zero out extra memory at the end of
2467 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2468 * reads extra memory as zeros.
2470 for (i = 0; i < len; i++) {
2471 rxq->rx_ring[i] = zeroed_desc;
2474 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2476 * initialize extra software ring entries. Space for these extra
2477 * entries is always allocated
2479 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2480 for (i = rxq->nb_rx_desc; i < len; ++i) {
2481 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2484 rxq->rx_nb_avail = 0;
2485 rxq->rx_next_avail = 0;
2486 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2487 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2489 rxq->nb_rx_hold = 0;
2490 rxq->pkt_first_seg = NULL;
2491 rxq->pkt_last_seg = NULL;
2496 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2499 unsigned int socket_id,
2500 const struct rte_eth_rxconf *rx_conf,
2501 struct rte_mempool *mp)
2503 const struct rte_memzone *rz;
2504 struct ixgbe_rx_queue *rxq;
2505 struct ixgbe_hw *hw;
2507 struct ixgbe_adapter *adapter =
2508 (struct ixgbe_adapter *)dev->data->dev_private;
2509 struct rte_eth_dev_info dev_info = { 0 };
2510 struct rte_eth_rxmode *dev_rx_mode = &dev->data->dev_conf.rxmode;
2511 bool rsc_requested = false;
2513 dev->dev_ops->dev_infos_get(dev, &dev_info);
2514 if ((dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO) &&
2515 dev_rx_mode->enable_lro)
2516 rsc_requested = true;
2518 PMD_INIT_FUNC_TRACE();
2519 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2522 * Validate number of receive descriptors.
2523 * It must not exceed hardware maximum, and must be multiple
2526 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2527 (nb_desc > IXGBE_MAX_RING_DESC) ||
2528 (nb_desc < IXGBE_MIN_RING_DESC)) {
2532 /* Free memory prior to re-allocation if needed... */
2533 if (dev->data->rx_queues[queue_idx] != NULL) {
2534 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2535 dev->data->rx_queues[queue_idx] = NULL;
2538 /* First allocate the rx queue data structure */
2539 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2540 RTE_CACHE_LINE_SIZE, socket_id);
2544 rxq->nb_rx_desc = nb_desc;
2545 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2546 rxq->queue_id = queue_idx;
2547 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2548 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2549 rxq->port_id = dev->data->port_id;
2550 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2552 rxq->drop_en = rx_conf->rx_drop_en;
2553 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2556 * Allocate RX ring hardware descriptors. A memzone large enough to
2557 * handle the maximum ring size is allocated in order to allow for
2558 * resizing in later calls to the queue setup function.
2560 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2561 RX_RING_SZ, socket_id);
2563 ixgbe_rx_queue_release(rxq);
2568 * Zero init all the descriptors in the ring.
2570 memset (rz->addr, 0, RX_RING_SZ);
2573 * Modified to setup VFRDT for Virtual Function
2575 if (hw->mac.type == ixgbe_mac_82599_vf ||
2576 hw->mac.type == ixgbe_mac_X540_vf ||
2577 hw->mac.type == ixgbe_mac_X550_vf ||
2578 hw->mac.type == ixgbe_mac_X550EM_x_vf) {
2580 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2582 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2586 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2588 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2590 #ifndef RTE_LIBRTE_XEN_DOM0
2591 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2593 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2595 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2598 * Certain constraints must be met in order to use the bulk buffer
2599 * allocation Rx burst function. If any of Rx queues doesn't meet them
2600 * the feature should be disabled for the whole port.
2602 if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
2603 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
2604 "preconditions - canceling the feature for "
2605 "the whole port[%d]",
2606 rxq->queue_id, rxq->port_id);
2607 adapter->rx_bulk_alloc_allowed = false;
2611 * Allocate software ring. Allow for space at the end of the
2612 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2613 * function does not access an invalid memory region.
2616 if (adapter->rx_bulk_alloc_allowed)
2617 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2619 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2620 sizeof(struct ixgbe_rx_entry) * len,
2621 RTE_CACHE_LINE_SIZE, socket_id);
2622 if (!rxq->sw_ring) {
2623 ixgbe_rx_queue_release(rxq);
2627 if (rsc_requested) {
2629 rte_zmalloc_socket("rxq->sw_rsc_ring",
2630 sizeof(struct ixgbe_rsc_entry) * len,
2631 RTE_CACHE_LINE_SIZE, socket_id);
2632 if (!rxq->sw_rsc_ring) {
2633 ixgbe_rx_queue_release(rxq);
2637 rxq->sw_rsc_ring = NULL;
2639 PMD_INIT_LOG(DEBUG, "sw_ring=%p sw_rsc_ring=%p hw_ring=%p "
2640 "dma_addr=0x%"PRIx64,
2641 rxq->sw_ring, rxq->sw_rsc_ring, rxq->rx_ring,
2642 rxq->rx_ring_phys_addr);
2644 if (!rte_is_power_of_2(nb_desc)) {
2645 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
2646 "preconditions - canceling the feature for "
2647 "the whole port[%d]",
2648 rxq->queue_id, rxq->port_id);
2649 adapter->rx_vec_allowed = false;
2651 ixgbe_rxq_vec_setup(rxq);
2653 dev->data->rx_queues[queue_idx] = rxq;
2655 ixgbe_reset_rx_queue(adapter, rxq);
2661 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2663 #define IXGBE_RXQ_SCAN_INTERVAL 4
2664 volatile union ixgbe_adv_rx_desc *rxdp;
2665 struct ixgbe_rx_queue *rxq;
2668 if (rx_queue_id >= dev->data->nb_rx_queues) {
2669 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2673 rxq = dev->data->rx_queues[rx_queue_id];
2674 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2676 while ((desc < rxq->nb_rx_desc) &&
2677 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2678 desc += IXGBE_RXQ_SCAN_INTERVAL;
2679 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2680 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2681 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2682 desc - rxq->nb_rx_desc]);
2689 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2691 volatile union ixgbe_adv_rx_desc *rxdp;
2692 struct ixgbe_rx_queue *rxq = rx_queue;
2695 if (unlikely(offset >= rxq->nb_rx_desc))
2697 desc = rxq->rx_tail + offset;
2698 if (desc >= rxq->nb_rx_desc)
2699 desc -= rxq->nb_rx_desc;
2701 rxdp = &rxq->rx_ring[desc];
2702 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2706 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2709 struct ixgbe_adapter *adapter =
2710 (struct ixgbe_adapter *)dev->data->dev_private;
2712 PMD_INIT_FUNC_TRACE();
2714 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2715 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
2717 txq->ops->release_mbufs(txq);
2718 txq->ops->reset(txq);
2722 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2723 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
2725 ixgbe_rx_queue_release_mbufs(rxq);
2726 ixgbe_reset_rx_queue(adapter, rxq);
2731 /*********************************************************************
2733 * Device RX/TX init functions
2735 **********************************************************************/
2738 * Receive Side Scaling (RSS)
2739 * See section 7.1.2.8 in the following document:
2740 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2743 * The source and destination IP addresses of the IP header and the source
2744 * and destination ports of TCP/UDP headers, if any, of received packets are
2745 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2746 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2747 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2748 * RSS output index which is used as the RX queue index where to store the
2750 * The following output is supplied in the RX write-back descriptor:
2751 * - 32-bit result of the Microsoft RSS hash function,
2752 * - 4-bit RSS type field.
2756 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2757 * Used as the default key.
2759 static uint8_t rss_intel_key[40] = {
2760 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2761 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2762 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2763 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2764 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2768 ixgbe_rss_disable(struct rte_eth_dev *dev)
2770 struct ixgbe_hw *hw;
2773 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2774 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2775 mrqc &= ~IXGBE_MRQC_RSSEN;
2776 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2780 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2788 hash_key = rss_conf->rss_key;
2789 if (hash_key != NULL) {
2790 /* Fill in RSS hash key */
2791 for (i = 0; i < 10; i++) {
2792 rss_key = hash_key[(i * 4)];
2793 rss_key |= hash_key[(i * 4) + 1] << 8;
2794 rss_key |= hash_key[(i * 4) + 2] << 16;
2795 rss_key |= hash_key[(i * 4) + 3] << 24;
2796 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2800 /* Set configured hashing protocols in MRQC register */
2801 rss_hf = rss_conf->rss_hf;
2802 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2803 if (rss_hf & ETH_RSS_IPV4)
2804 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2805 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2806 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2807 if (rss_hf & ETH_RSS_IPV6)
2808 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2809 if (rss_hf & ETH_RSS_IPV6_EX)
2810 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2811 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2812 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2813 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2814 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2815 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2816 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2817 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2818 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2819 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2820 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2821 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2825 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2826 struct rte_eth_rss_conf *rss_conf)
2828 struct ixgbe_hw *hw;
2832 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2835 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2836 * "RSS enabling cannot be done dynamically while it must be
2837 * preceded by a software reset"
2838 * Before changing anything, first check that the update RSS operation
2839 * does not attempt to disable RSS, if RSS was enabled at
2840 * initialization time, or does not attempt to enable RSS, if RSS was
2841 * disabled at initialization time.
2843 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2844 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2845 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2846 if (rss_hf != 0) /* Enable RSS */
2848 return 0; /* Nothing to do */
2851 if (rss_hf == 0) /* Disable RSS */
2853 ixgbe_hw_rss_hash_set(hw, rss_conf);
2858 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2859 struct rte_eth_rss_conf *rss_conf)
2861 struct ixgbe_hw *hw;
2868 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2869 hash_key = rss_conf->rss_key;
2870 if (hash_key != NULL) {
2871 /* Return RSS hash key */
2872 for (i = 0; i < 10; i++) {
2873 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2874 hash_key[(i * 4)] = rss_key & 0x000000FF;
2875 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2876 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2877 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2881 /* Get RSS functions configured in MRQC register */
2882 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2883 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2884 rss_conf->rss_hf = 0;
2888 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2889 rss_hf |= ETH_RSS_IPV4;
2890 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2891 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2892 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2893 rss_hf |= ETH_RSS_IPV6;
2894 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2895 rss_hf |= ETH_RSS_IPV6_EX;
2896 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2897 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2898 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2899 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2900 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2901 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2902 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2903 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2904 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2905 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2906 rss_conf->rss_hf = rss_hf;
2911 ixgbe_rss_configure(struct rte_eth_dev *dev)
2913 struct rte_eth_rss_conf rss_conf;
2914 struct ixgbe_hw *hw;
2919 PMD_INIT_FUNC_TRACE();
2920 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2923 * Fill in redirection table
2924 * The byte-swap is needed because NIC registers are in
2925 * little-endian order.
2928 for (i = 0, j = 0; i < 128; i++, j++) {
2929 if (j == dev->data->nb_rx_queues)
2931 reta = (reta << 8) | j;
2933 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2938 * Configure the RSS key and the RSS protocols used to compute
2939 * the RSS hash of input packets.
2941 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2942 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2943 ixgbe_rss_disable(dev);
2946 if (rss_conf.rss_key == NULL)
2947 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2948 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2951 #define NUM_VFTA_REGISTERS 128
2952 #define NIC_RX_BUFFER_SIZE 0x200
2955 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2957 struct rte_eth_vmdq_dcb_conf *cfg;
2958 struct ixgbe_hw *hw;
2959 enum rte_eth_nb_pools num_pools;
2960 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2962 uint8_t nb_tcs; /* number of traffic classes */
2965 PMD_INIT_FUNC_TRACE();
2966 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2967 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2968 num_pools = cfg->nb_queue_pools;
2969 /* Check we have a valid number of pools */
2970 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2971 ixgbe_rss_disable(dev);
2974 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2975 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2979 * split rx buffer up into sections, each for 1 traffic class
2981 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2982 for (i = 0 ; i < nb_tcs; i++) {
2983 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2984 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2985 /* clear 10 bits. */
2986 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2987 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2989 /* zero alloc all unused TCs */
2990 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2991 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2992 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2993 /* clear 10 bits. */
2994 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2997 /* MRQC: enable vmdq and dcb */
2998 mrqc = ((num_pools == ETH_16_POOLS) ? \
2999 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
3000 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3002 /* PFVTCTL: turn on virtualisation and set the default pool */
3003 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3004 if (cfg->enable_default_pool) {
3005 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3007 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3010 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3012 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
3014 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
3016 * mapping is done with 3 bits per priority,
3017 * so shift by i*3 each time
3019 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
3021 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
3023 /* RTRPCS: DCB related */
3024 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
3026 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3027 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3028 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3029 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3031 /* VFTA - enable all vlan filters */
3032 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3033 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3036 /* VFRE: pool enabling for receive - 16 or 32 */
3037 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
3038 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3041 * MPSAR - allow pools to read specific mac addresses
3042 * In this case, all pools should be able to read from mac addr 0
3044 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
3045 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
3047 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3048 for (i = 0; i < cfg->nb_pool_maps; i++) {
3049 /* set vlan id in VF register and set the valid bit */
3050 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3051 (cfg->pool_map[i].vlan_id & 0xFFF)));
3053 * Put the allowed pools in VFB reg. As we only have 16 or 32
3054 * pools, we only need to use the first half of the register
3057 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
3062 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
3063 * @hw: pointer to hardware structure
3064 * @dcb_config: pointer to ixgbe_dcb_config structure
3067 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
3068 struct ixgbe_dcb_config *dcb_config)
3073 PMD_INIT_FUNC_TRACE();
3074 if (hw->mac.type != ixgbe_mac_82598EB) {
3075 /* Disable the Tx desc arbiter so that MTQC can be changed */
3076 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3077 reg |= IXGBE_RTTDCS_ARBDIS;
3078 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3080 /* Enable DCB for Tx with 8 TCs */
3081 if (dcb_config->num_tcs.pg_tcs == 8) {
3082 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3085 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3087 if (dcb_config->vt_mode)
3088 reg |= IXGBE_MTQC_VT_ENA;
3089 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3091 /* Disable drop for all queues */
3092 for (q = 0; q < 128; q++)
3093 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3094 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3096 /* Enable the Tx desc arbiter */
3097 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3098 reg &= ~IXGBE_RTTDCS_ARBDIS;
3099 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3101 /* Enable Security TX Buffer IFG for DCB */
3102 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3103 reg |= IXGBE_SECTX_DCB;
3104 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
3110 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
3111 * @dev: pointer to rte_eth_dev structure
3112 * @dcb_config: pointer to ixgbe_dcb_config structure
3115 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
3116 struct ixgbe_dcb_config *dcb_config)
3118 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3119 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3120 struct ixgbe_hw *hw =
3121 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3123 PMD_INIT_FUNC_TRACE();
3124 if (hw->mac.type != ixgbe_mac_82598EB)
3125 /*PF VF Transmit Enable*/
3126 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
3127 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3129 /*Configure general DCB TX parameters*/
3130 ixgbe_dcb_tx_hw_config(hw,dcb_config);
3135 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
3136 struct ixgbe_dcb_config *dcb_config)
3138 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
3139 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3140 struct ixgbe_dcb_tc_config *tc;
3143 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3144 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
3145 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3146 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3149 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3150 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3152 /* User Priority to Traffic Class mapping */
3153 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3154 j = vmdq_rx_conf->dcb_queue[i];
3155 tc = &dcb_config->tc_config[j];
3156 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
3162 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
3163 struct ixgbe_dcb_config *dcb_config)
3165 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3166 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3167 struct ixgbe_dcb_tc_config *tc;
3170 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3171 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
3172 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3173 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3176 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3177 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3180 /* User Priority to Traffic Class mapping */
3181 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3182 j = vmdq_tx_conf->dcb_queue[i];
3183 tc = &dcb_config->tc_config[j];
3184 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
3191 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
3192 struct ixgbe_dcb_config *dcb_config)
3194 struct rte_eth_dcb_rx_conf *rx_conf =
3195 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
3196 struct ixgbe_dcb_tc_config *tc;
3199 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
3200 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
3202 /* User Priority to Traffic Class mapping */
3203 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3204 j = rx_conf->dcb_queue[i];
3205 tc = &dcb_config->tc_config[j];
3206 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
3212 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
3213 struct ixgbe_dcb_config *dcb_config)
3215 struct rte_eth_dcb_tx_conf *tx_conf =
3216 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
3217 struct ixgbe_dcb_tc_config *tc;
3220 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
3221 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
3223 /* User Priority to Traffic Class mapping */
3224 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3225 j = tx_conf->dcb_queue[i];
3226 tc = &dcb_config->tc_config[j];
3227 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
3233 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
3234 * @hw: pointer to hardware structure
3235 * @dcb_config: pointer to ixgbe_dcb_config structure
3238 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
3239 struct ixgbe_dcb_config *dcb_config)
3245 PMD_INIT_FUNC_TRACE();
3247 * Disable the arbiter before changing parameters
3248 * (always enable recycle mode; WSP)
3250 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
3251 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3253 if (hw->mac.type != ixgbe_mac_82598EB) {
3254 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
3255 if (dcb_config->num_tcs.pg_tcs == 4) {
3256 if (dcb_config->vt_mode)
3257 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3258 IXGBE_MRQC_VMDQRT4TCEN;
3260 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3261 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3265 if (dcb_config->num_tcs.pg_tcs == 8) {
3266 if (dcb_config->vt_mode)
3267 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3268 IXGBE_MRQC_VMDQRT8TCEN;
3270 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3271 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3276 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
3279 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3280 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3281 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3282 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3284 /* VFTA - enable all vlan filters */
3285 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3286 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3290 * Configure Rx packet plane (recycle mode; WSP) and
3293 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
3294 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3300 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
3301 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3303 switch (hw->mac.type) {
3304 case ixgbe_mac_82598EB:
3305 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
3307 case ixgbe_mac_82599EB:
3308 case ixgbe_mac_X540:
3309 case ixgbe_mac_X550:
3310 case ixgbe_mac_X550EM_x:
3311 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
3320 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
3321 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3323 switch (hw->mac.type) {
3324 case ixgbe_mac_82598EB:
3325 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
3326 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
3328 case ixgbe_mac_82599EB:
3329 case ixgbe_mac_X540:
3330 case ixgbe_mac_X550:
3331 case ixgbe_mac_X550EM_x:
3332 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
3333 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
3340 #define DCB_RX_CONFIG 1
3341 #define DCB_TX_CONFIG 1
3342 #define DCB_TX_PB 1024
3344 * ixgbe_dcb_hw_configure - Enable DCB and configure
3345 * general DCB in VT mode and non-VT mode parameters
3346 * @dev: pointer to rte_eth_dev structure
3347 * @dcb_config: pointer to ixgbe_dcb_config structure
3350 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
3351 struct ixgbe_dcb_config *dcb_config)
3354 uint8_t i,pfc_en,nb_tcs;
3356 uint8_t config_dcb_rx = 0;
3357 uint8_t config_dcb_tx = 0;
3358 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3359 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3360 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3361 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3362 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3363 struct ixgbe_dcb_tc_config *tc;
3364 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3365 struct ixgbe_hw *hw =
3366 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3368 switch(dev->data->dev_conf.rxmode.mq_mode){
3369 case ETH_MQ_RX_VMDQ_DCB:
3370 dcb_config->vt_mode = true;
3371 if (hw->mac.type != ixgbe_mac_82598EB) {
3372 config_dcb_rx = DCB_RX_CONFIG;
3374 *get dcb and VT rx configuration parameters
3377 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
3378 /*Configure general VMDQ and DCB RX parameters*/
3379 ixgbe_vmdq_dcb_configure(dev);
3383 dcb_config->vt_mode = false;
3384 config_dcb_rx = DCB_RX_CONFIG;
3385 /* Get dcb TX configuration parameters from rte_eth_conf */
3386 ixgbe_dcb_rx_config(dev,dcb_config);
3387 /*Configure general DCB RX parameters*/
3388 ixgbe_dcb_rx_hw_config(hw, dcb_config);
3391 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3394 switch (dev->data->dev_conf.txmode.mq_mode) {
3395 case ETH_MQ_TX_VMDQ_DCB:
3396 dcb_config->vt_mode = true;
3397 config_dcb_tx = DCB_TX_CONFIG;
3398 /* get DCB and VT TX configuration parameters from rte_eth_conf */
3399 ixgbe_dcb_vt_tx_config(dev,dcb_config);
3400 /*Configure general VMDQ and DCB TX parameters*/
3401 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
3405 dcb_config->vt_mode = false;
3406 config_dcb_tx = DCB_TX_CONFIG;
3407 /*get DCB TX configuration parameters from rte_eth_conf*/
3408 ixgbe_dcb_tx_config(dev,dcb_config);
3409 /*Configure general DCB TX parameters*/
3410 ixgbe_dcb_tx_hw_config(hw, dcb_config);
3413 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3417 nb_tcs = dcb_config->num_tcs.pfc_tcs;
3419 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3420 if(nb_tcs == ETH_4_TCS) {
3421 /* Avoid un-configured priority mapping to TC0 */
3423 uint8_t mask = 0xFF;
3424 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3425 mask = (uint8_t)(mask & (~ (1 << map[i])));
3426 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3427 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3431 /* Re-configure 4 TCs BW */
3432 for (i = 0; i < nb_tcs; i++) {
3433 tc = &dcb_config->tc_config[i];
3434 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3435 (uint8_t)(100 / nb_tcs);
3436 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3437 (uint8_t)(100 / nb_tcs);
3439 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3440 tc = &dcb_config->tc_config[i];
3441 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3442 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3447 /* Set RX buffer size */
3448 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3449 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3450 for (i = 0 ; i < nb_tcs; i++) {
3451 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3453 /* zero alloc all unused TCs */
3454 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3455 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3459 /* Only support an equally distributed Tx packet buffer strategy. */
3460 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3461 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3462 for (i = 0; i < nb_tcs; i++) {
3463 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3464 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3466 /* Clear unused TCs, if any, to zero buffer size*/
3467 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3468 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3469 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3473 /*Calculates traffic class credits*/
3474 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3475 IXGBE_DCB_TX_CONFIG);
3476 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3477 IXGBE_DCB_RX_CONFIG);
3480 /* Unpack CEE standard containers */
3481 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3482 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3483 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3484 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3485 /* Configure PG(ETS) RX */
3486 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3490 /* Unpack CEE standard containers */
3491 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3492 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3493 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3494 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3495 /* Configure PG(ETS) TX */
3496 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3499 /*Configure queue statistics registers*/
3500 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3502 /* Check if the PFC is supported */
3503 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3504 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3505 for (i = 0; i < nb_tcs; i++) {
3507 * If the TC count is 8,and the default high_water is 48,
3508 * the low_water is 16 as default.
3510 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3511 hw->fc.low_water[i] = pbsize / 4;
3512 /* Enable pfc for this TC */
3513 tc = &dcb_config->tc_config[i];
3514 tc->pfc = ixgbe_dcb_pfc_enabled;
3516 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3517 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3519 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3526 * ixgbe_configure_dcb - Configure DCB Hardware
3527 * @dev: pointer to rte_eth_dev
3529 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3531 struct ixgbe_dcb_config *dcb_cfg =
3532 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3533 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3535 PMD_INIT_FUNC_TRACE();
3537 /* check support mq_mode for DCB */
3538 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3539 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3542 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3545 /** Configure DCB hardware **/
3546 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3552 * VMDq only support for 10 GbE NIC.
3555 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3557 struct rte_eth_vmdq_rx_conf *cfg;
3558 struct ixgbe_hw *hw;
3559 enum rte_eth_nb_pools num_pools;
3560 uint32_t mrqc, vt_ctl, vlanctrl;
3564 PMD_INIT_FUNC_TRACE();
3565 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3566 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3567 num_pools = cfg->nb_queue_pools;
3569 ixgbe_rss_disable(dev);
3571 /* MRQC: enable vmdq */
3572 mrqc = IXGBE_MRQC_VMDQEN;
3573 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3575 /* PFVTCTL: turn on virtualisation and set the default pool */
3576 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3577 if (cfg->enable_default_pool)
3578 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3580 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3582 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3584 for (i = 0; i < (int)num_pools; i++) {
3585 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
3586 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
3589 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3590 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3591 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3592 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3594 /* VFTA - enable all vlan filters */
3595 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3596 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3598 /* VFRE: pool enabling for receive - 64 */
3599 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3600 if (num_pools == ETH_64_POOLS)
3601 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3604 * MPSAR - allow pools to read specific mac addresses
3605 * In this case, all pools should be able to read from mac addr 0
3607 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3608 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3610 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3611 for (i = 0; i < cfg->nb_pool_maps; i++) {
3612 /* set vlan id in VF register and set the valid bit */
3613 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3614 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3616 * Put the allowed pools in VFB reg. As we only have 16 or 64
3617 * pools, we only need to use the first half of the register
3620 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3621 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3622 (cfg->pool_map[i].pools & UINT32_MAX));
3624 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3625 ((cfg->pool_map[i].pools >> 32) \
3630 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3631 if (cfg->enable_loop_back) {
3632 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3633 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3634 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3637 IXGBE_WRITE_FLUSH(hw);
3641 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3642 * @hw: pointer to hardware structure
3645 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3650 PMD_INIT_FUNC_TRACE();
3651 /*PF VF Transmit Enable*/
3652 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3653 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3655 /* Disable the Tx desc arbiter so that MTQC can be changed */
3656 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3657 reg |= IXGBE_RTTDCS_ARBDIS;
3658 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3660 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3661 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3663 /* Disable drop for all queues */
3664 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3665 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3666 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3668 /* Enable the Tx desc arbiter */
3669 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3670 reg &= ~IXGBE_RTTDCS_ARBDIS;
3671 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3673 IXGBE_WRITE_FLUSH(hw);
3679 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
3681 struct ixgbe_rx_entry *rxe = rxq->sw_ring;
3685 /* Initialize software ring entries */
3686 for (i = 0; i < rxq->nb_rx_desc; i++) {
3687 volatile union ixgbe_adv_rx_desc *rxd;
3688 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3690 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3691 (unsigned) rxq->queue_id);
3695 rte_mbuf_refcnt_set(mbuf, 1);
3697 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3699 mbuf->port = rxq->port_id;
3702 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3703 rxd = &rxq->rx_ring[i];
3704 rxd->read.hdr_addr = dma_addr;
3705 rxd->read.pkt_addr = dma_addr;
3713 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
3715 struct ixgbe_hw *hw;
3718 ixgbe_rss_configure(dev);
3720 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3722 /* MRQC: enable VF RSS */
3723 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
3724 mrqc &= ~IXGBE_MRQC_MRQE_MASK;
3725 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3727 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
3731 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
3735 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
3739 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3745 ixgbe_config_vf_default(struct rte_eth_dev *dev)
3747 struct ixgbe_hw *hw =
3748 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3750 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3752 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3757 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3758 IXGBE_MRQC_VMDQRT4TCEN);
3762 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3763 IXGBE_MRQC_VMDQRT8TCEN);
3767 "invalid pool number in IOV mode");
3774 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3776 struct ixgbe_hw *hw =
3777 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3779 if (hw->mac.type == ixgbe_mac_82598EB)
3782 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3784 * SRIOV inactive scheme
3785 * any DCB/RSS w/o VMDq multi-queue setting
3787 switch (dev->data->dev_conf.rxmode.mq_mode) {
3789 ixgbe_rss_configure(dev);
3792 case ETH_MQ_RX_VMDQ_DCB:
3793 ixgbe_vmdq_dcb_configure(dev);
3796 case ETH_MQ_RX_VMDQ_ONLY:
3797 ixgbe_vmdq_rx_hw_configure(dev);
3800 case ETH_MQ_RX_NONE:
3801 /* if mq_mode is none, disable rss mode.*/
3802 default: ixgbe_rss_disable(dev);
3806 * SRIOV active scheme
3807 * Support RSS together with VMDq & SRIOV
3809 switch (dev->data->dev_conf.rxmode.mq_mode) {
3811 case ETH_MQ_RX_VMDQ_RSS:
3812 ixgbe_config_vf_rss(dev);
3815 /* FIXME if support DCB/RSS together with VMDq & SRIOV */
3816 case ETH_MQ_RX_VMDQ_DCB:
3817 case ETH_MQ_RX_VMDQ_DCB_RSS:
3819 "Could not support DCB with VMDq & SRIOV");
3822 ixgbe_config_vf_default(dev);
3831 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3833 struct ixgbe_hw *hw =
3834 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3838 if (hw->mac.type == ixgbe_mac_82598EB)
3841 /* disable arbiter before setting MTQC */
3842 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3843 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3844 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3846 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3848 * SRIOV inactive scheme
3849 * any DCB w/o VMDq multi-queue setting
3851 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3852 ixgbe_vmdq_tx_hw_configure(hw);
3854 mtqc = IXGBE_MTQC_64Q_1PB;
3855 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3858 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3861 * SRIOV active scheme
3862 * FIXME if support DCB together with VMDq & SRIOV
3865 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3868 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3871 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3875 mtqc = IXGBE_MTQC_64Q_1PB;
3876 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3878 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3881 /* re-enable arbiter */
3882 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3883 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3889 * ixgbe_get_rscctl_maxdesc - Calculate the RSCCTL[n].MAXDESC for PF
3891 * Return the RSCCTL[n].MAXDESC for 82599 and x540 PF devices according to the
3892 * spec rev. 3.0 chapter 8.2.3.8.13.
3894 * @pool Memory pool of the Rx queue
3896 static inline uint32_t
3897 ixgbe_get_rscctl_maxdesc(struct rte_mempool *pool)
3899 struct rte_pktmbuf_pool_private *mp_priv = rte_mempool_get_priv(pool);
3901 /* MAXDESC * SRRCTL.BSIZEPKT must not exceed 64 KB minus one */
3904 (mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);
3907 return IXGBE_RSCCTL_MAXDESC_16;
3908 else if (maxdesc >= 8)
3909 return IXGBE_RSCCTL_MAXDESC_8;
3910 else if (maxdesc >= 4)
3911 return IXGBE_RSCCTL_MAXDESC_4;
3913 return IXGBE_RSCCTL_MAXDESC_1;
3917 * ixgbe_set_ivar - Setup the correct IVAR register for a particular MSIX
3920 * (Taken from FreeBSD tree)
3921 * (yes this is all very magic and confusing :)
3924 * @entry the register array entry
3925 * @vector the MSIX vector for this queue
3929 ixgbe_set_ivar(struct rte_eth_dev *dev, u8 entry, u8 vector, s8 type)
3931 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3934 vector |= IXGBE_IVAR_ALLOC_VAL;
3936 switch (hw->mac.type) {
3938 case ixgbe_mac_82598EB:
3940 entry = IXGBE_IVAR_OTHER_CAUSES_INDEX;
3942 entry += (type * 64);
3943 index = (entry >> 2) & 0x1F;
3944 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
3945 ivar &= ~(0xFF << (8 * (entry & 0x3)));
3946 ivar |= (vector << (8 * (entry & 0x3)));
3947 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
3950 case ixgbe_mac_82599EB:
3951 case ixgbe_mac_X540:
3952 if (type == -1) { /* MISC IVAR */
3953 index = (entry & 1) * 8;
3954 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
3955 ivar &= ~(0xFF << index);
3956 ivar |= (vector << index);
3957 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
3958 } else { /* RX/TX IVARS */
3959 index = (16 * (entry & 1)) + (8 * type);
3960 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
3961 ivar &= ~(0xFF << index);
3962 ivar |= (vector << index);
3963 IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
3973 void ixgbe_set_rx_function(struct rte_eth_dev *dev)
3975 struct ixgbe_adapter *adapter =
3976 (struct ixgbe_adapter *)dev->data->dev_private;
3979 * In order to allow Vector Rx there are a few configuration
3980 * conditions to be met and Rx Bulk Allocation should be allowed.
3982 if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
3983 !adapter->rx_bulk_alloc_allowed) {
3984 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
3985 "preconditions or RTE_IXGBE_INC_VECTOR is "
3987 dev->data->port_id);
3989 adapter->rx_vec_allowed = false;
3993 * Initialize the appropriate LRO callback.
3995 * If all queues satisfy the bulk allocation preconditions
3996 * (hw->rx_bulk_alloc_allowed is TRUE) then we may use bulk allocation.
3997 * Otherwise use a single allocation version.
3999 if (dev->data->lro) {
4000 if (adapter->rx_bulk_alloc_allowed) {
4001 PMD_INIT_LOG(INFO, "LRO is requested. Using a bulk "
4002 "allocation version");
4003 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
4005 PMD_INIT_LOG(INFO, "LRO is requested. Using a single "
4006 "allocation version");
4007 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
4009 } else if (dev->data->scattered_rx) {
4011 * Set the non-LRO scattered callback: there are Vector and
4012 * single allocation versions.
4014 if (adapter->rx_vec_allowed) {
4015 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
4016 "callback (port=%d).",
4017 dev->data->port_id);
4019 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4021 PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector) "
4022 "Scattered Rx callback "
4024 dev->data->port_id);
4026 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
4029 * Below we set "simple" callbacks according to port/queues parameters.
4030 * If parameters allow we are going to choose between the following
4034 * - Single buffer allocation (the simplest one)
4036 } else if (adapter->rx_vec_allowed) {
4037 PMD_INIT_LOG(INFO, "Vector rx enabled, please make sure RX "
4038 "burst size no less than 32.");
4040 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
4041 } else if (adapter->rx_bulk_alloc_allowed) {
4042 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
4043 "satisfied. Rx Burst Bulk Alloc function "
4044 "will be used on port=%d.",
4045 dev->data->port_id);
4047 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
4049 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
4050 "satisfied, or Scattered Rx is requested, "
4051 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC "
4052 "is not enabled (port=%d).",
4053 dev->data->port_id);
4055 dev->rx_pkt_burst = ixgbe_recv_pkts;
4060 * ixgbe_set_rsc - configure RSC related port HW registers
4062 * Configures the port's RSC related registers according to the 4.6.7.2 chapter
4063 * of 82599 Spec (x540 configuration is virtually the same).
4067 * Returns 0 in case of success or a non-zero error code
4070 ixgbe_set_rsc(struct rte_eth_dev *dev)
4072 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4073 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4074 struct rte_eth_dev_info dev_info = { 0 };
4075 bool rsc_capable = false;
4080 dev->dev_ops->dev_infos_get(dev, &dev_info);
4081 if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)
4084 if (!rsc_capable && rx_conf->enable_lro) {
4085 PMD_INIT_LOG(CRIT, "LRO is requested on HW that doesn't "
4090 /* RSC global configuration (chapter 4.6.7.2.1 of 82599 Spec) */
4092 if (!rx_conf->hw_strip_crc && rx_conf->enable_lro) {
4094 * According to chapter of 4.6.7.2.1 of the Spec Rev.
4095 * 3.0 RSC configuration requires HW CRC stripping being
4096 * enabled. If user requested both HW CRC stripping off
4097 * and RSC on - return an error.
4099 PMD_INIT_LOG(CRIT, "LRO can't be enabled when HW CRC "
4104 /* RFCTL configuration */
4106 uint32_t rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4107 if (rx_conf->enable_lro)
4109 * Since NFS packets coalescing is not supported - clear
4110 * RFCTL.NFSW_DIS and RFCTL.NFSR_DIS when RSC is
4113 rfctl &= ~(IXGBE_RFCTL_RSC_DIS | IXGBE_RFCTL_NFSW_DIS |
4114 IXGBE_RFCTL_NFSR_DIS);
4116 rfctl |= IXGBE_RFCTL_RSC_DIS;
4118 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4121 /* If LRO hasn't been requested - we are done here. */
4122 if (!rx_conf->enable_lro)
4125 /* Set RDRXCTL.RSCACKC bit */
4126 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4127 rdrxctl |= IXGBE_RDRXCTL_RSCACKC;
4128 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4130 /* Per-queue RSC configuration (chapter 4.6.7.2.2 of 82599 Spec) */
4131 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4132 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4134 IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxq->reg_idx));
4136 IXGBE_READ_REG(hw, IXGBE_RSCCTL(rxq->reg_idx));
4138 IXGBE_READ_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx));
4140 IXGBE_READ_REG(hw, IXGBE_EITR(rxq->reg_idx));
4143 * ixgbe PMD doesn't support header-split at the moment.
4145 * Following the 4.6.7.2.1 chapter of the 82599/x540
4146 * Spec if RSC is enabled the SRRCTL[n].BSIZEHEADER
4147 * should be configured even if header split is not
4148 * enabled. We will configure it 128 bytes following the
4149 * recommendation in the spec.
4151 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
4152 srrctl |= (128 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4153 IXGBE_SRRCTL_BSIZEHDR_MASK;
4156 * TODO: Consider setting the Receive Descriptor Minimum
4157 * Threshold Size for an RSC case. This is not an obviously
4158 * beneficiary option but the one worth considering...
4161 rscctl |= IXGBE_RSCCTL_RSCEN;
4162 rscctl |= ixgbe_get_rscctl_maxdesc(rxq->mb_pool);
4163 psrtype |= IXGBE_PSRTYPE_TCPHDR;
4166 * RSC: Set ITR interval corresponding to 2K ints/s.
4168 * Full-sized RSC aggregations for a 10Gb/s link will
4169 * arrive at about 20K aggregation/s rate.
4171 * 2K inst/s rate will make only 10% of the
4172 * aggregations to be closed due to the interrupt timer
4173 * expiration for a streaming at wire-speed case.
4175 * For a sparse streaming case this setting will yield
4176 * at most 500us latency for a single RSC aggregation.
4178 eitr &= ~IXGBE_EITR_ITR_INT_MASK;
4179 eitr |= IXGBE_EITR_INTERVAL_US(500) | IXGBE_EITR_CNT_WDIS;
4181 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4182 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);
4183 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4184 IXGBE_WRITE_REG(hw, IXGBE_EITR(rxq->reg_idx), eitr);
4187 * RSC requires the mapping of the queue to the
4190 ixgbe_set_ivar(dev, rxq->reg_idx, i, 0);
4197 PMD_INIT_LOG(INFO, "enabling LRO mode");
4203 * Initializes Receive Unit.
4206 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
4208 struct ixgbe_hw *hw;
4209 struct ixgbe_rx_queue *rxq;
4220 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4223 PMD_INIT_FUNC_TRACE();
4224 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4227 * Make sure receives are disabled while setting
4228 * up the RX context (registers, descriptor rings, etc.).
4230 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4231 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4233 /* Enable receipt of broadcasted frames */
4234 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4235 fctrl |= IXGBE_FCTRL_BAM;
4236 fctrl |= IXGBE_FCTRL_DPF;
4237 fctrl |= IXGBE_FCTRL_PMCF;
4238 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4241 * Configure CRC stripping, if any.
4243 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4244 if (rx_conf->hw_strip_crc)
4245 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
4247 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
4250 * Configure jumbo frame support, if any.
4252 if (rx_conf->jumbo_frame == 1) {
4253 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4254 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4255 maxfrs &= 0x0000FFFF;
4256 maxfrs |= (rx_conf->max_rx_pkt_len << 16);
4257 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4259 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4262 * If loopback mode is configured for 82599, set LPBK bit.
4264 if (hw->mac.type == ixgbe_mac_82599EB &&
4265 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4266 hlreg0 |= IXGBE_HLREG0_LPBK;
4268 hlreg0 &= ~IXGBE_HLREG0_LPBK;
4270 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4272 /* Setup RX queues */
4273 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4274 rxq = dev->data->rx_queues[i];
4277 * Reset crc_len in case it was changed after queue setup by a
4278 * call to configure.
4280 rxq->crc_len = rx_conf->hw_strip_crc ? 0 : ETHER_CRC_LEN;
4282 /* Setup the Base and Length of the Rx Descriptor Rings */
4283 bus_addr = rxq->rx_ring_phys_addr;
4284 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
4285 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4286 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
4287 (uint32_t)(bus_addr >> 32));
4288 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
4289 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4290 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4291 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
4293 /* Configure the SRRCTL register */
4294 #ifdef RTE_HEADER_SPLIT_ENABLE
4296 * Configure Header Split
4298 if (rx_conf->header_split) {
4299 if (hw->mac.type == ixgbe_mac_82599EB) {
4300 /* Must setup the PSRTYPE register */
4302 psrtype = IXGBE_PSRTYPE_TCPHDR |
4303 IXGBE_PSRTYPE_UDPHDR |
4304 IXGBE_PSRTYPE_IPV4HDR |
4305 IXGBE_PSRTYPE_IPV6HDR;
4306 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4308 srrctl = ((rx_conf->split_hdr_size <<
4309 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4310 IXGBE_SRRCTL_BSIZEHDR_MASK);
4311 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4314 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4316 /* Set if packets are dropped when no descriptors available */
4318 srrctl |= IXGBE_SRRCTL_DROP_EN;
4321 * Configure the RX buffer size in the BSIZEPACKET field of
4322 * the SRRCTL register of the queue.
4323 * The value is in 1 KB resolution. Valid values can be from
4326 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4327 RTE_PKTMBUF_HEADROOM);
4328 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4329 IXGBE_SRRCTL_BSIZEPKT_MASK);
4331 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4333 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4334 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4336 /* It adds dual VLAN length for supporting dual VLAN */
4337 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4338 2 * IXGBE_VLAN_TAG_SIZE > buf_size)
4339 dev->data->scattered_rx = 1;
4342 if (rx_conf->enable_scatter)
4343 dev->data->scattered_rx = 1;
4346 * Device configured with multiple RX queues.
4348 ixgbe_dev_mq_rx_configure(dev);
4351 * Setup the Checksum Register.
4352 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
4353 * Enable IP/L4 checkum computation by hardware if requested to do so.
4355 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
4356 rxcsum |= IXGBE_RXCSUM_PCSD;
4357 if (rx_conf->hw_ip_checksum)
4358 rxcsum |= IXGBE_RXCSUM_IPPCSE;
4360 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
4362 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
4364 if (hw->mac.type == ixgbe_mac_82599EB ||
4365 hw->mac.type == ixgbe_mac_X540) {
4366 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4367 if (rx_conf->hw_strip_crc)
4368 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4370 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
4371 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4372 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4375 rc = ixgbe_set_rsc(dev);
4379 ixgbe_set_rx_function(dev);
4385 * Initializes Transmit Unit.
4388 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
4390 struct ixgbe_hw *hw;
4391 struct ixgbe_tx_queue *txq;
4397 PMD_INIT_FUNC_TRACE();
4398 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4400 /* Enable TX CRC (checksum offload requirement) and hw padding
4401 * (TSO requirement) */
4402 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4403 hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
4404 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4406 /* Setup the Base and Length of the Tx Descriptor Rings */
4407 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4408 txq = dev->data->tx_queues[i];
4410 bus_addr = txq->tx_ring_phys_addr;
4411 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
4412 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4413 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
4414 (uint32_t)(bus_addr >> 32));
4415 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
4416 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4417 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4418 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4419 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4422 * Disable Tx Head Writeback RO bit, since this hoses
4423 * bookkeeping if things aren't delivered in order.
4425 switch (hw->mac.type) {
4426 case ixgbe_mac_82598EB:
4427 txctrl = IXGBE_READ_REG(hw,
4428 IXGBE_DCA_TXCTRL(txq->reg_idx));
4429 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4430 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
4434 case ixgbe_mac_82599EB:
4435 case ixgbe_mac_X540:
4436 case ixgbe_mac_X550:
4437 case ixgbe_mac_X550EM_x:
4439 txctrl = IXGBE_READ_REG(hw,
4440 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
4441 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4442 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
4448 /* Device configured with multiple TX queues. */
4449 ixgbe_dev_mq_tx_configure(dev);
4453 * Set up link for 82599 loopback mode Tx->Rx.
4456 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
4458 PMD_INIT_FUNC_TRACE();
4460 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
4461 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
4463 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
4472 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
4473 ixgbe_reset_pipeline_82599(hw);
4475 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
4481 * Start Transmit and Receive Units.
4484 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
4486 struct ixgbe_hw *hw;
4487 struct ixgbe_tx_queue *txq;
4488 struct ixgbe_rx_queue *rxq;
4495 PMD_INIT_FUNC_TRACE();
4496 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4498 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4499 txq = dev->data->tx_queues[i];
4500 /* Setup Transmit Threshold Registers */
4501 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4502 txdctl |= txq->pthresh & 0x7F;
4503 txdctl |= ((txq->hthresh & 0x7F) << 8);
4504 txdctl |= ((txq->wthresh & 0x7F) << 16);
4505 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4508 if (hw->mac.type != ixgbe_mac_82598EB) {
4509 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
4510 dmatxctl |= IXGBE_DMATXCTL_TE;
4511 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
4514 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4515 txq = dev->data->tx_queues[i];
4516 if (!txq->tx_deferred_start) {
4517 ret = ixgbe_dev_tx_queue_start(dev, i);
4523 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4524 rxq = dev->data->rx_queues[i];
4525 if (!rxq->rx_deferred_start) {
4526 ret = ixgbe_dev_rx_queue_start(dev, i);
4532 /* Enable Receive engine */
4533 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4534 if (hw->mac.type == ixgbe_mac_82598EB)
4535 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4536 rxctrl |= IXGBE_RXCTRL_RXEN;
4537 hw->mac.ops.enable_rx_dma(hw, rxctrl);
4539 /* If loopback mode is enabled for 82599, set up the link accordingly */
4540 if (hw->mac.type == ixgbe_mac_82599EB &&
4541 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4542 ixgbe_setup_loopback_link_82599(hw);
4548 * Start Receive Units for specified queue.
4551 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4553 struct ixgbe_hw *hw;
4554 struct ixgbe_rx_queue *rxq;
4558 PMD_INIT_FUNC_TRACE();
4559 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4561 if (rx_queue_id < dev->data->nb_rx_queues) {
4562 rxq = dev->data->rx_queues[rx_queue_id];
4564 /* Allocate buffers for descriptor rings */
4565 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
4566 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
4570 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4571 rxdctl |= IXGBE_RXDCTL_ENABLE;
4572 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
4574 /* Wait until RX Enable ready */
4575 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4578 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4579 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4581 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
4584 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4585 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
4593 * Stop Receive Units for specified queue.
4596 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4598 struct ixgbe_hw *hw;
4599 struct ixgbe_adapter *adapter =
4600 (struct ixgbe_adapter *)dev->data->dev_private;
4601 struct ixgbe_rx_queue *rxq;
4605 PMD_INIT_FUNC_TRACE();
4606 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4608 if (rx_queue_id < dev->data->nb_rx_queues) {
4609 rxq = dev->data->rx_queues[rx_queue_id];
4611 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4612 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
4613 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
4615 /* Wait until RX Enable ready */
4616 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4619 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4620 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
4622 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
4625 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4627 ixgbe_rx_queue_release_mbufs(rxq);
4628 ixgbe_reset_rx_queue(adapter, rxq);
4637 * Start Transmit Units for specified queue.
4640 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4642 struct ixgbe_hw *hw;
4643 struct ixgbe_tx_queue *txq;
4647 PMD_INIT_FUNC_TRACE();
4648 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4650 if (tx_queue_id < dev->data->nb_tx_queues) {
4651 txq = dev->data->tx_queues[tx_queue_id];
4652 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4653 txdctl |= IXGBE_TXDCTL_ENABLE;
4654 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4656 /* Wait until TX Enable ready */
4657 if (hw->mac.type == ixgbe_mac_82599EB) {
4658 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4661 txdctl = IXGBE_READ_REG(hw,
4662 IXGBE_TXDCTL(txq->reg_idx));
4663 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4665 PMD_INIT_LOG(ERR, "Could not enable "
4666 "Tx Queue %d", tx_queue_id);
4669 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4670 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4678 * Stop Transmit Units for specified queue.
4681 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4683 struct ixgbe_hw *hw;
4684 struct ixgbe_tx_queue *txq;
4686 uint32_t txtdh, txtdt;
4689 PMD_INIT_FUNC_TRACE();
4690 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4692 if (tx_queue_id < dev->data->nb_tx_queues) {
4693 txq = dev->data->tx_queues[tx_queue_id];
4695 /* Wait until TX queue is empty */
4696 if (hw->mac.type == ixgbe_mac_82599EB) {
4697 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4699 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4700 txtdh = IXGBE_READ_REG(hw,
4701 IXGBE_TDH(txq->reg_idx));
4702 txtdt = IXGBE_READ_REG(hw,
4703 IXGBE_TDT(txq->reg_idx));
4704 } while (--poll_ms && (txtdh != txtdt));
4706 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
4707 "when stopping.", tx_queue_id);
4710 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4711 txdctl &= ~IXGBE_TXDCTL_ENABLE;
4712 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4714 /* Wait until TX Enable ready */
4715 if (hw->mac.type == ixgbe_mac_82599EB) {
4716 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4719 txdctl = IXGBE_READ_REG(hw,
4720 IXGBE_TXDCTL(txq->reg_idx));
4721 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
4723 PMD_INIT_LOG(ERR, "Could not disable "
4724 "Tx Queue %d", tx_queue_id);
4727 if (txq->ops != NULL) {
4728 txq->ops->release_mbufs(txq);
4729 txq->ops->reset(txq);
4738 * [VF] Initializes Receive Unit.
4741 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
4743 struct ixgbe_hw *hw;
4744 struct ixgbe_rx_queue *rxq;
4746 uint32_t srrctl, psrtype = 0;
4751 PMD_INIT_FUNC_TRACE();
4752 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4754 if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
4755 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4756 "it should be power of 2");
4760 if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
4761 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4762 "it should be equal to or less than %d",
4763 hw->mac.max_rx_queues);
4768 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
4769 * disables the VF receipt of packets if the PF MTU is > 1500.
4770 * This is done to deal with 82599 limitations that imposes
4771 * the PF and all VFs to share the same MTU.
4772 * Then, the PF driver enables again the VF receipt of packet when
4773 * the VF driver issues a IXGBE_VF_SET_LPE request.
4774 * In the meantime, the VF device cannot be used, even if the VF driver
4775 * and the Guest VM network stack are ready to accept packets with a
4776 * size up to the PF MTU.
4777 * As a work-around to this PF behaviour, force the call to
4778 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
4779 * VF packets received can work in all cases.
4781 ixgbevf_rlpml_set_vf(hw,
4782 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
4784 /* Setup RX queues */
4785 dev->rx_pkt_burst = ixgbe_recv_pkts;
4786 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4787 rxq = dev->data->rx_queues[i];
4789 /* Allocate buffers for descriptor rings */
4790 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
4794 /* Setup the Base and Length of the Rx Descriptor Rings */
4795 bus_addr = rxq->rx_ring_phys_addr;
4797 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
4798 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4799 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
4800 (uint32_t)(bus_addr >> 32));
4801 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
4802 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4803 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
4804 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
4807 /* Configure the SRRCTL register */
4808 #ifdef RTE_HEADER_SPLIT_ENABLE
4810 * Configure Header Split
4812 if (dev->data->dev_conf.rxmode.header_split) {
4813 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
4814 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4815 IXGBE_SRRCTL_BSIZEHDR_MASK);
4816 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4819 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4821 /* Set if packets are dropped when no descriptors available */
4823 srrctl |= IXGBE_SRRCTL_DROP_EN;
4826 * Configure the RX buffer size in the BSIZEPACKET field of
4827 * the SRRCTL register of the queue.
4828 * The value is in 1 KB resolution. Valid values can be from
4831 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4832 RTE_PKTMBUF_HEADROOM);
4833 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4834 IXGBE_SRRCTL_BSIZEPKT_MASK);
4837 * VF modification to write virtual function SRRCTL register
4839 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
4841 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4842 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4844 if (dev->data->dev_conf.rxmode.enable_scatter ||
4845 /* It adds dual VLAN length for supporting dual VLAN */
4846 (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4847 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
4848 if (!dev->data->scattered_rx)
4849 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4850 dev->data->scattered_rx = 1;
4851 #ifdef RTE_IXGBE_INC_VECTOR
4852 if (rte_is_power_of_2(rxq->nb_rx_desc))
4854 ixgbe_recv_scattered_pkts_vec;
4857 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
4861 #ifdef RTE_HEADER_SPLIT_ENABLE
4862 if (dev->data->dev_conf.rxmode.header_split)
4863 /* Must setup the PSRTYPE register */
4864 psrtype = IXGBE_PSRTYPE_TCPHDR |
4865 IXGBE_PSRTYPE_UDPHDR |
4866 IXGBE_PSRTYPE_IPV4HDR |
4867 IXGBE_PSRTYPE_IPV6HDR;
4870 /* Set RQPL for VF RSS according to max Rx queue */
4871 psrtype |= (dev->data->nb_rx_queues >> 1) <<
4872 IXGBE_PSRTYPE_RQPL_SHIFT;
4873 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
4879 * [VF] Initializes Transmit Unit.
4882 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4884 struct ixgbe_hw *hw;
4885 struct ixgbe_tx_queue *txq;
4890 PMD_INIT_FUNC_TRACE();
4891 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4893 /* Setup the Base and Length of the Tx Descriptor Rings */
4894 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4895 txq = dev->data->tx_queues[i];
4896 bus_addr = txq->tx_ring_phys_addr;
4897 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4898 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4899 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4900 (uint32_t)(bus_addr >> 32));
4901 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4902 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4903 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4904 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4905 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4908 * Disable Tx Head Writeback RO bit, since this hoses
4909 * bookkeeping if things aren't delivered in order.
4911 txctrl = IXGBE_READ_REG(hw,
4912 IXGBE_VFDCA_TXCTRL(i));
4913 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4914 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4920 * [VF] Start Transmit and Receive Units.
4923 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4925 struct ixgbe_hw *hw;
4926 struct ixgbe_tx_queue *txq;
4927 struct ixgbe_rx_queue *rxq;
4933 PMD_INIT_FUNC_TRACE();
4934 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4936 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4937 txq = dev->data->tx_queues[i];
4938 /* Setup Transmit Threshold Registers */
4939 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4940 txdctl |= txq->pthresh & 0x7F;
4941 txdctl |= ((txq->hthresh & 0x7F) << 8);
4942 txdctl |= ((txq->wthresh & 0x7F) << 16);
4943 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4946 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4948 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4949 txdctl |= IXGBE_TXDCTL_ENABLE;
4950 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4953 /* Wait until TX Enable ready */
4956 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4957 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4959 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
4961 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4963 rxq = dev->data->rx_queues[i];
4965 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4966 rxdctl |= IXGBE_RXDCTL_ENABLE;
4967 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4969 /* Wait until RX Enable ready */
4973 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4974 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4976 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
4978 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
4983 /* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */
4984 int __attribute__((weak))
4985 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
4990 uint16_t __attribute__((weak))
4991 ixgbe_recv_pkts_vec(
4992 void __rte_unused *rx_queue,
4993 struct rte_mbuf __rte_unused **rx_pkts,
4994 uint16_t __rte_unused nb_pkts)
4999 uint16_t __attribute__((weak))
5000 ixgbe_recv_scattered_pkts_vec(
5001 void __rte_unused *rx_queue,
5002 struct rte_mbuf __rte_unused **rx_pkts,
5003 uint16_t __rte_unused nb_pkts)
5008 int __attribute__((weak))
5009 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)