4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5 * Copyright 2014 6WIND S.A.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * * Neither the name of Intel Corporation nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
46 #include <rte_byteorder.h>
47 #include <rte_common.h>
48 #include <rte_cycles.h>
50 #include <rte_debug.h>
51 #include <rte_interrupts.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_launch.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
80 #include "ixgbe_rxtx.h"
82 /* Bit Mask to indicate what bits required for building TX context */
83 #define IXGBE_TX_OFFLOAD_MASK ( \
89 static inline struct rte_mbuf *
90 rte_rxmbuf_alloc(struct rte_mempool *mp)
94 m = __rte_mbuf_raw_alloc(mp);
95 __rte_mbuf_sanity_check_raw(m, 0);
101 #define RTE_PMD_USE_PREFETCH
104 #ifdef RTE_PMD_USE_PREFETCH
106 * Prefetch a cache line into all cache levels.
108 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
110 #define rte_ixgbe_prefetch(p) do {} while(0)
113 /*********************************************************************
117 **********************************************************************/
120 * Check for descriptors with their DD bit set and free mbufs.
121 * Return the total number of buffers freed.
123 static inline int __attribute__((always_inline))
124 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
126 struct ixgbe_tx_entry *txep;
130 /* check DD bit on threshold descriptor */
131 status = txq->tx_ring[txq->tx_next_dd].wb.status;
132 if (! (status & IXGBE_ADVTXD_STAT_DD))
136 * first buffer to free from S/W ring is at index
137 * tx_next_dd - (tx_rs_thresh-1)
139 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
141 /* free buffers one at a time */
142 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
143 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
144 txep->mbuf->next = NULL;
145 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
149 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
150 rte_pktmbuf_free_seg(txep->mbuf);
155 /* buffers were freed, update counters */
156 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
157 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
158 if (txq->tx_next_dd >= txq->nb_tx_desc)
159 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
161 return txq->tx_rs_thresh;
164 /* Populate 4 descriptors with data from 4 mbufs */
166 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
168 uint64_t buf_dma_addr;
172 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
173 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
174 pkt_len = (*pkts)->data_len;
176 /* write data to descriptor */
177 txdp->read.buffer_addr = buf_dma_addr;
178 txdp->read.cmd_type_len =
179 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
180 txdp->read.olinfo_status =
181 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
182 rte_prefetch0(&(*pkts)->pool);
186 /* Populate 1 descriptor with data from 1 mbuf */
188 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
190 uint64_t buf_dma_addr;
193 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
194 pkt_len = (*pkts)->data_len;
196 /* write data to descriptor */
197 txdp->read.buffer_addr = buf_dma_addr;
198 txdp->read.cmd_type_len =
199 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
200 txdp->read.olinfo_status =
201 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
202 rte_prefetch0(&(*pkts)->pool);
206 * Fill H/W descriptor ring with mbuf data.
207 * Copy mbuf pointers to the S/W ring.
210 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
213 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
214 struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
215 const int N_PER_LOOP = 4;
216 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
217 int mainpart, leftover;
221 * Process most of the packets in chunks of N pkts. Any
222 * leftover packets will get processed one at a time.
224 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
225 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
226 for (i = 0; i < mainpart; i += N_PER_LOOP) {
227 /* Copy N mbuf pointers to the S/W ring */
228 for (j = 0; j < N_PER_LOOP; ++j) {
229 (txep + i + j)->mbuf = *(pkts + i + j);
231 tx4(txdp + i, pkts + i);
234 if (unlikely(leftover > 0)) {
235 for (i = 0; i < leftover; ++i) {
236 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
237 tx1(txdp + mainpart + i, pkts + mainpart + i);
242 static inline uint16_t
243 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
246 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
247 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
251 * Begin scanning the H/W ring for done descriptors when the
252 * number of available descriptors drops below tx_free_thresh. For
253 * each done descriptor, free the associated buffer.
255 if (txq->nb_tx_free < txq->tx_free_thresh)
256 ixgbe_tx_free_bufs(txq);
258 /* Only use descriptors that are available */
259 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
260 if (unlikely(nb_pkts == 0))
263 /* Use exactly nb_pkts descriptors */
264 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
267 * At this point, we know there are enough descriptors in the
268 * ring to transmit all the packets. This assumes that each
269 * mbuf contains a single segment, and that no new offloads
270 * are expected, which would require a new context descriptor.
274 * See if we're going to wrap-around. If so, handle the top
275 * of the descriptor ring first, then do the bottom. If not,
276 * the processing looks just like the "bottom" part anyway...
278 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
279 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
280 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
283 * We know that the last descriptor in the ring will need to
284 * have its RS bit set because tx_rs_thresh has to be
285 * a divisor of the ring size
287 tx_r[txq->tx_next_rs].read.cmd_type_len |=
288 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
289 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
294 /* Fill H/W descriptor ring with mbuf data */
295 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
296 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
299 * Determine if RS bit should be set
300 * This is what we actually want:
301 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
302 * but instead of subtracting 1 and doing >=, we can just do
303 * greater than without subtracting.
305 if (txq->tx_tail > txq->tx_next_rs) {
306 tx_r[txq->tx_next_rs].read.cmd_type_len |=
307 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
308 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
310 if (txq->tx_next_rs >= txq->nb_tx_desc)
311 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
315 * Check for wrap-around. This would only happen if we used
316 * up to the last descriptor in the ring, no more, no less.
318 if (txq->tx_tail >= txq->nb_tx_desc)
321 /* update tail pointer */
323 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
329 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
334 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
335 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
336 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
338 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
342 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
343 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
344 nb_tx = (uint16_t)(nb_tx + ret);
345 nb_pkts = (uint16_t)(nb_pkts - ret);
354 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
355 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
356 uint64_t ol_flags, union ixgbe_tx_offload tx_offload)
358 uint32_t type_tucmd_mlhl;
359 uint32_t mss_l4len_idx = 0;
361 uint32_t vlan_macip_lens;
362 union ixgbe_tx_offload tx_offload_mask;
364 ctx_idx = txq->ctx_curr;
365 tx_offload_mask.data = 0;
368 /* Specify which HW CTX to upload. */
369 mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
371 if (ol_flags & PKT_TX_VLAN_PKT) {
372 tx_offload_mask.vlan_tci |= ~0;
375 /* check if TCP segmentation required for this packet */
376 if (ol_flags & PKT_TX_TCP_SEG) {
377 /* implies IP cksum and TCP cksum */
378 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
379 IXGBE_ADVTXD_TUCMD_L4T_TCP |
380 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
382 tx_offload_mask.l2_len |= ~0;
383 tx_offload_mask.l3_len |= ~0;
384 tx_offload_mask.l4_len |= ~0;
385 tx_offload_mask.tso_segsz |= ~0;
386 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
387 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
388 } else { /* no TSO, check if hardware checksum is needed */
389 if (ol_flags & PKT_TX_IP_CKSUM) {
390 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
391 tx_offload_mask.l2_len |= ~0;
392 tx_offload_mask.l3_len |= ~0;
395 switch (ol_flags & PKT_TX_L4_MASK) {
396 case PKT_TX_UDP_CKSUM:
397 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
398 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
399 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
400 tx_offload_mask.l2_len |= ~0;
401 tx_offload_mask.l3_len |= ~0;
403 case PKT_TX_TCP_CKSUM:
404 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
405 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
406 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
407 tx_offload_mask.l2_len |= ~0;
408 tx_offload_mask.l3_len |= ~0;
409 tx_offload_mask.l4_len |= ~0;
411 case PKT_TX_SCTP_CKSUM:
412 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
413 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
414 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
415 tx_offload_mask.l2_len |= ~0;
416 tx_offload_mask.l3_len |= ~0;
419 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
420 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
425 txq->ctx_cache[ctx_idx].flags = ol_flags;
426 txq->ctx_cache[ctx_idx].tx_offload.data =
427 tx_offload_mask.data & tx_offload.data;
428 txq->ctx_cache[ctx_idx].tx_offload_mask = tx_offload_mask;
430 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
431 vlan_macip_lens = tx_offload.l3_len;
432 vlan_macip_lens |= (tx_offload.l2_len << IXGBE_ADVTXD_MACLEN_SHIFT);
433 vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
434 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
435 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
436 ctx_txd->seqnum_seed = 0;
440 * Check which hardware context can be used. Use the existing match
441 * or create a new context descriptor.
443 static inline uint32_t
444 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
445 union ixgbe_tx_offload tx_offload)
447 /* If match with the current used context */
448 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
449 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
450 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
451 return txq->ctx_curr;
454 /* What if match with the next context */
456 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
457 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
458 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
459 return txq->ctx_curr;
462 /* Mismatch, use the previous context */
463 return (IXGBE_CTX_NUM);
466 static inline uint32_t
467 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
470 if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
471 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
472 if (ol_flags & PKT_TX_IP_CKSUM)
473 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
474 if (ol_flags & PKT_TX_TCP_SEG)
475 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
479 static inline uint32_t
480 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
482 uint32_t cmdtype = 0;
483 if (ol_flags & PKT_TX_VLAN_PKT)
484 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
485 if (ol_flags & PKT_TX_TCP_SEG)
486 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
490 /* Default RS bit threshold values */
491 #ifndef DEFAULT_TX_RS_THRESH
492 #define DEFAULT_TX_RS_THRESH 32
494 #ifndef DEFAULT_TX_FREE_THRESH
495 #define DEFAULT_TX_FREE_THRESH 32
498 /* Reset transmit descriptors after they have been used */
500 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
502 struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
503 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
504 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
505 uint16_t nb_tx_desc = txq->nb_tx_desc;
506 uint16_t desc_to_clean_to;
507 uint16_t nb_tx_to_clean;
509 /* Determine the last descriptor needing to be cleaned */
510 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
511 if (desc_to_clean_to >= nb_tx_desc)
512 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
514 /* Check to make sure the last descriptor to clean is done */
515 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
516 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
518 PMD_TX_FREE_LOG(DEBUG,
519 "TX descriptor %4u is not done"
520 "(port=%d queue=%d)",
522 txq->port_id, txq->queue_id);
523 /* Failed to clean any descriptors, better luck next time */
527 /* Figure out how many descriptors will be cleaned */
528 if (last_desc_cleaned > desc_to_clean_to)
529 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
532 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
535 PMD_TX_FREE_LOG(DEBUG,
536 "Cleaning %4u TX descriptors: %4u to %4u "
537 "(port=%d queue=%d)",
538 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
539 txq->port_id, txq->queue_id);
542 * The last descriptor to clean is done, so that means all the
543 * descriptors from the last descriptor that was cleaned
544 * up to the last descriptor with the RS bit set
545 * are done. Only reset the threshold descriptor.
547 txr[desc_to_clean_to].wb.status = 0;
549 /* Update the txq to reflect the last descriptor that was cleaned */
550 txq->last_desc_cleaned = desc_to_clean_to;
551 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
558 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
561 struct ixgbe_tx_queue *txq;
562 struct ixgbe_tx_entry *sw_ring;
563 struct ixgbe_tx_entry *txe, *txn;
564 volatile union ixgbe_adv_tx_desc *txr;
565 volatile union ixgbe_adv_tx_desc *txd;
566 struct rte_mbuf *tx_pkt;
567 struct rte_mbuf *m_seg;
568 uint64_t buf_dma_addr;
569 uint32_t olinfo_status;
570 uint32_t cmd_type_len;
581 union ixgbe_tx_offload tx_offload = { .data = 0 };
584 sw_ring = txq->sw_ring;
586 tx_id = txq->tx_tail;
587 txe = &sw_ring[tx_id];
589 /* Determine if the descriptor ring needs to be cleaned. */
590 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
591 ixgbe_xmit_cleanup(txq);
594 rte_prefetch0(&txe->mbuf->pool);
597 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
600 pkt_len = tx_pkt->pkt_len;
603 * Determine how many (if any) context descriptors
604 * are needed for offload functionality.
606 ol_flags = tx_pkt->ol_flags;
608 /* If hardware offload required */
609 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
611 tx_offload.l2_len = tx_pkt->l2_len;
612 tx_offload.l3_len = tx_pkt->l3_len;
613 tx_offload.l4_len = tx_pkt->l4_len;
614 tx_offload.vlan_tci = tx_pkt->vlan_tci;
615 tx_offload.tso_segsz = tx_pkt->tso_segsz;
617 /* If new context need be built or reuse the exist ctx. */
618 ctx = what_advctx_update(txq, tx_ol_req,
620 /* Only allocate context descriptor if required*/
621 new_ctx = (ctx == IXGBE_CTX_NUM);
626 * Keep track of how many descriptors are used this loop
627 * This will always be the number of segments + the number of
628 * Context descriptors required to transmit the packet
630 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
633 * The number of descriptors that must be allocated for a
634 * packet is the number of segments of that packet, plus 1
635 * Context Descriptor for the hardware offload, if any.
636 * Determine the last TX descriptor to allocate in the TX ring
637 * for the packet, starting from the current position (tx_id)
640 tx_last = (uint16_t) (tx_id + nb_used - 1);
643 if (tx_last >= txq->nb_tx_desc)
644 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
646 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
647 " tx_first=%u tx_last=%u",
648 (unsigned) txq->port_id,
649 (unsigned) txq->queue_id,
655 * Make sure there are enough TX descriptors available to
656 * transmit the entire packet.
657 * nb_used better be less than or equal to txq->tx_rs_thresh
659 if (nb_used > txq->nb_tx_free) {
660 PMD_TX_FREE_LOG(DEBUG,
661 "Not enough free TX descriptors "
662 "nb_used=%4u nb_free=%4u "
663 "(port=%d queue=%d)",
664 nb_used, txq->nb_tx_free,
665 txq->port_id, txq->queue_id);
667 if (ixgbe_xmit_cleanup(txq) != 0) {
668 /* Could not clean any descriptors */
674 /* nb_used better be <= txq->tx_rs_thresh */
675 if (unlikely(nb_used > txq->tx_rs_thresh)) {
676 PMD_TX_FREE_LOG(DEBUG,
677 "The number of descriptors needed to "
678 "transmit the packet exceeds the "
679 "RS bit threshold. This will impact "
681 "nb_used=%4u nb_free=%4u "
683 "(port=%d queue=%d)",
684 nb_used, txq->nb_tx_free,
686 txq->port_id, txq->queue_id);
688 * Loop here until there are enough TX
689 * descriptors or until the ring cannot be
692 while (nb_used > txq->nb_tx_free) {
693 if (ixgbe_xmit_cleanup(txq) != 0) {
695 * Could not clean any
707 * By now there are enough free TX descriptors to transmit
712 * Set common flags of all TX Data Descriptors.
714 * The following bits must be set in all Data Descriptors:
715 * - IXGBE_ADVTXD_DTYP_DATA
716 * - IXGBE_ADVTXD_DCMD_DEXT
718 * The following bits must be set in the first Data Descriptor
719 * and are ignored in the other ones:
720 * - IXGBE_ADVTXD_DCMD_IFCS
721 * - IXGBE_ADVTXD_MAC_1588
722 * - IXGBE_ADVTXD_DCMD_VLE
724 * The following bits must only be set in the last Data
726 * - IXGBE_TXD_CMD_EOP
728 * The following bits can be set in any Data Descriptor, but
729 * are only set in the last Data Descriptor:
732 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
733 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
735 #ifdef RTE_LIBRTE_IEEE1588
736 if (ol_flags & PKT_TX_IEEE1588_TMST)
737 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
743 if (ol_flags & PKT_TX_TCP_SEG) {
744 /* when TSO is on, paylen in descriptor is the
745 * not the packet len but the tcp payload len */
746 pkt_len -= (tx_offload.l2_len +
747 tx_offload.l3_len + tx_offload.l4_len);
751 * Setup the TX Advanced Context Descriptor if required
754 volatile struct ixgbe_adv_tx_context_desc *
757 ctx_txd = (volatile struct
758 ixgbe_adv_tx_context_desc *)
761 txn = &sw_ring[txe->next_id];
762 rte_prefetch0(&txn->mbuf->pool);
764 if (txe->mbuf != NULL) {
765 rte_pktmbuf_free_seg(txe->mbuf);
769 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
772 txe->last_id = tx_last;
773 tx_id = txe->next_id;
778 * Setup the TX Advanced Data Descriptor,
779 * This path will go through
780 * whatever new/reuse the context descriptor
782 cmd_type_len |= tx_desc_ol_flags_to_cmdtype(ol_flags);
783 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
784 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
787 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
792 txn = &sw_ring[txe->next_id];
793 rte_prefetch0(&txn->mbuf->pool);
795 if (txe->mbuf != NULL)
796 rte_pktmbuf_free_seg(txe->mbuf);
800 * Set up Transmit Data Descriptor.
802 slen = m_seg->data_len;
803 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
804 txd->read.buffer_addr =
805 rte_cpu_to_le_64(buf_dma_addr);
806 txd->read.cmd_type_len =
807 rte_cpu_to_le_32(cmd_type_len | slen);
808 txd->read.olinfo_status =
809 rte_cpu_to_le_32(olinfo_status);
810 txe->last_id = tx_last;
811 tx_id = txe->next_id;
814 } while (m_seg != NULL);
817 * The last packet data descriptor needs End Of Packet (EOP)
819 cmd_type_len |= IXGBE_TXD_CMD_EOP;
820 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
821 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
823 /* Set RS bit only on threshold packets' last descriptor */
824 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
825 PMD_TX_FREE_LOG(DEBUG,
826 "Setting RS bit on TXD id="
827 "%4u (port=%d queue=%d)",
828 tx_last, txq->port_id, txq->queue_id);
830 cmd_type_len |= IXGBE_TXD_CMD_RS;
832 /* Update txq RS bit counters */
835 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
841 * Set the Transmit Descriptor Tail (TDT)
843 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
844 (unsigned) txq->port_id, (unsigned) txq->queue_id,
845 (unsigned) tx_id, (unsigned) nb_tx);
846 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
847 txq->tx_tail = tx_id;
852 /*********************************************************************
856 **********************************************************************/
857 static inline uint64_t
858 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
862 static const uint64_t ip_pkt_types_map[16] = {
863 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
864 PKT_RX_IPV6_HDR, 0, 0, 0,
865 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
866 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
869 static const uint64_t ip_rss_types_map[16] = {
870 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
871 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
872 PKT_RX_RSS_HASH, 0, 0, 0,
873 0, 0, 0, PKT_RX_FDIR,
876 #ifdef RTE_LIBRTE_IEEE1588
877 static uint64_t ip_pkt_etqf_map[8] = {
878 0, 0, 0, PKT_RX_IEEE1588_PTP,
882 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
883 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
884 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
886 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
887 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
890 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
893 static inline uint64_t
894 rx_desc_status_to_pkt_flags(uint32_t rx_status)
899 * Check if VLAN present only.
900 * Do not check whether L3/L4 rx checksum done by NIC or not,
901 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
903 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
905 #ifdef RTE_LIBRTE_IEEE1588
906 if (rx_status & IXGBE_RXD_STAT_TMST)
907 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
912 static inline uint64_t
913 rx_desc_error_to_pkt_flags(uint32_t rx_status)
916 * Bit 31: IPE, IPv4 checksum error
917 * Bit 30: L4I, L4I integrity error
919 static uint64_t error_to_pkt_flags_map[4] = {
920 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
921 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
923 return error_to_pkt_flags_map[(rx_status >>
924 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
927 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
929 * LOOK_AHEAD defines how many desc statuses to check beyond the
930 * current descriptor.
931 * It must be a pound define for optimal performance.
932 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
933 * function only works with LOOK_AHEAD=8.
936 #if (LOOK_AHEAD != 8)
937 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
940 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
942 volatile union ixgbe_adv_rx_desc *rxdp;
943 struct ixgbe_rx_entry *rxep;
947 int s[LOOK_AHEAD], nb_dd;
951 /* get references to current descriptor and S/W ring entry */
952 rxdp = &rxq->rx_ring[rxq->rx_tail];
953 rxep = &rxq->sw_ring[rxq->rx_tail];
955 /* check to make sure there is at least 1 packet to receive */
956 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
960 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
961 * reference packets that are ready to be received.
963 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
964 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
966 /* Read desc statuses backwards to avoid race condition */
967 for (j = LOOK_AHEAD-1; j >= 0; --j)
968 s[j] = rxdp[j].wb.upper.status_error;
970 /* Compute how many status bits were set */
972 for (j = 0; j < LOOK_AHEAD; ++j)
973 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
977 /* Translate descriptor info to mbuf format */
978 for (j = 0; j < nb_dd; ++j) {
980 pkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len);
981 mb->data_len = pkt_len;
982 mb->pkt_len = pkt_len;
983 mb->vlan_tci = rxdp[j].wb.upper.vlan;
984 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
986 /* convert descriptor fields to rte mbuf flags */
987 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(
988 rxdp[j].wb.lower.lo_dword.data);
989 /* reuse status field from scan list */
990 pkt_flags |= rx_desc_status_to_pkt_flags(s[j]);
991 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
992 mb->ol_flags = pkt_flags;
994 if (likely(pkt_flags & PKT_RX_RSS_HASH))
995 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
996 else if (pkt_flags & PKT_RX_FDIR) {
998 (uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum)
999 & IXGBE_ATR_HASH_MASK);
1000 mb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id;
1004 /* Move mbuf pointers from the S/W ring to the stage */
1005 for (j = 0; j < LOOK_AHEAD; ++j) {
1006 rxq->rx_stage[i + j] = rxep[j].mbuf;
1009 /* stop if all requested packets could not be received */
1010 if (nb_dd != LOOK_AHEAD)
1014 /* clear software ring entries so we can cleanup correctly */
1015 for (i = 0; i < nb_rx; ++i) {
1016 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1024 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq)
1026 volatile union ixgbe_adv_rx_desc *rxdp;
1027 struct ixgbe_rx_entry *rxep;
1028 struct rte_mbuf *mb;
1033 /* allocate buffers in bulk directly into the S/W ring */
1034 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1035 (rxq->rx_free_thresh - 1));
1036 rxep = &rxq->sw_ring[alloc_idx];
1037 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1038 rxq->rx_free_thresh);
1039 if (unlikely(diag != 0))
1042 rxdp = &rxq->rx_ring[alloc_idx];
1043 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1044 /* populate the static rte mbuf fields */
1046 rte_mbuf_refcnt_set(mb, 1);
1048 mb->data_off = RTE_PKTMBUF_HEADROOM;
1050 mb->port = rxq->port_id;
1052 /* populate the descriptors */
1053 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
1054 rxdp[i].read.hdr_addr = dma_addr;
1055 rxdp[i].read.pkt_addr = dma_addr;
1058 /* update tail pointer */
1060 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1062 /* update state of internal queue structure */
1063 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1064 rxq->rx_free_thresh);
1065 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1066 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1072 static inline uint16_t
1073 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1076 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1079 /* how many packets are ready to return? */
1080 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1082 /* copy mbuf pointers to the application's packet list */
1083 for (i = 0; i < nb_pkts; ++i)
1084 rx_pkts[i] = stage[i];
1086 /* update internal queue state */
1087 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1088 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1093 static inline uint16_t
1094 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1097 struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1100 /* Any previously recv'd pkts will be returned from the Rx stage */
1101 if (rxq->rx_nb_avail)
1102 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1104 /* Scan the H/W ring for packets to receive */
1105 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1107 /* update internal queue state */
1108 rxq->rx_next_avail = 0;
1109 rxq->rx_nb_avail = nb_rx;
1110 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1112 /* if required, allocate new buffers to replenish descriptors */
1113 if (rxq->rx_tail > rxq->rx_free_trigger) {
1114 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1116 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1117 "queue_id=%u", (unsigned) rxq->port_id,
1118 (unsigned) rxq->queue_id);
1120 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1121 rxq->rx_free_thresh;
1124 * Need to rewind any previous receives if we cannot
1125 * allocate new buffers to replenish the old ones.
1127 rxq->rx_nb_avail = 0;
1128 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1129 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1130 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1136 if (rxq->rx_tail >= rxq->nb_rx_desc)
1139 /* received any packets this loop? */
1140 if (rxq->rx_nb_avail)
1141 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1146 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1148 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1153 if (unlikely(nb_pkts == 0))
1156 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1157 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1159 /* request is relatively large, chunk it up */
1163 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1164 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1165 nb_rx = (uint16_t)(nb_rx + ret);
1166 nb_pkts = (uint16_t)(nb_pkts - ret);
1173 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1176 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1179 struct ixgbe_rx_queue *rxq;
1180 volatile union ixgbe_adv_rx_desc *rx_ring;
1181 volatile union ixgbe_adv_rx_desc *rxdp;
1182 struct ixgbe_rx_entry *sw_ring;
1183 struct ixgbe_rx_entry *rxe;
1184 struct rte_mbuf *rxm;
1185 struct rte_mbuf *nmb;
1186 union ixgbe_adv_rx_desc rxd;
1189 uint32_t hlen_type_rss;
1199 rx_id = rxq->rx_tail;
1200 rx_ring = rxq->rx_ring;
1201 sw_ring = rxq->sw_ring;
1202 while (nb_rx < nb_pkts) {
1204 * The order of operations here is important as the DD status
1205 * bit must not be read after any other descriptor fields.
1206 * rx_ring and rxdp are pointing to volatile data so the order
1207 * of accesses cannot be reordered by the compiler. If they were
1208 * not volatile, they could be reordered which could lead to
1209 * using invalid descriptor fields when read from rxd.
1211 rxdp = &rx_ring[rx_id];
1212 staterr = rxdp->wb.upper.status_error;
1213 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1220 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1221 * is likely to be invalid and to be dropped by the various
1222 * validation checks performed by the network stack.
1224 * Allocate a new mbuf to replenish the RX ring descriptor.
1225 * If the allocation fails:
1226 * - arrange for that RX descriptor to be the first one
1227 * being parsed the next time the receive function is
1228 * invoked [on the same queue].
1230 * - Stop parsing the RX ring and return immediately.
1232 * This policy do not drop the packet received in the RX
1233 * descriptor for which the allocation of a new mbuf failed.
1234 * Thus, it allows that packet to be later retrieved if
1235 * mbuf have been freed in the mean time.
1236 * As a side effect, holding RX descriptors instead of
1237 * systematically giving them back to the NIC may lead to
1238 * RX ring exhaustion situations.
1239 * However, the NIC can gracefully prevent such situations
1240 * to happen by sending specific "back-pressure" flow control
1241 * frames to its peer(s).
1243 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1244 "ext_err_stat=0x%08x pkt_len=%u",
1245 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1246 (unsigned) rx_id, (unsigned) staterr,
1247 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1249 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1251 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1252 "queue_id=%u", (unsigned) rxq->port_id,
1253 (unsigned) rxq->queue_id);
1254 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1259 rxe = &sw_ring[rx_id];
1261 if (rx_id == rxq->nb_rx_desc)
1264 /* Prefetch next mbuf while processing current one. */
1265 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1268 * When next RX descriptor is on a cache-line boundary,
1269 * prefetch the next 4 RX descriptors and the next 8 pointers
1272 if ((rx_id & 0x3) == 0) {
1273 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1274 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1280 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1281 rxdp->read.hdr_addr = dma_addr;
1282 rxdp->read.pkt_addr = dma_addr;
1285 * Initialize the returned mbuf.
1286 * 1) setup generic mbuf fields:
1287 * - number of segments,
1290 * - RX port identifier.
1291 * 2) integrate hardware offload data, if any:
1292 * - RSS flag & hash,
1293 * - IP checksum flag,
1294 * - VLAN TCI, if any,
1297 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1299 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1300 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1303 rxm->pkt_len = pkt_len;
1304 rxm->data_len = pkt_len;
1305 rxm->port = rxq->port_id;
1307 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1308 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1309 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1311 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1312 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1313 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1314 rxm->ol_flags = pkt_flags;
1316 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1317 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1318 else if (pkt_flags & PKT_RX_FDIR) {
1319 rxm->hash.fdir.hash =
1320 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1321 & IXGBE_ATR_HASH_MASK);
1322 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1325 * Store the mbuf address into the next entry of the array
1326 * of returned packets.
1328 rx_pkts[nb_rx++] = rxm;
1330 rxq->rx_tail = rx_id;
1333 * If the number of free RX descriptors is greater than the RX free
1334 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1336 * Update the RDT with the value of the last processed RX descriptor
1337 * minus 1, to guarantee that the RDT register is never equal to the
1338 * RDH register, which creates a "full" ring situtation from the
1339 * hardware point of view...
1341 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1342 if (nb_hold > rxq->rx_free_thresh) {
1343 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1344 "nb_hold=%u nb_rx=%u",
1345 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1346 (unsigned) rx_id, (unsigned) nb_hold,
1348 rx_id = (uint16_t) ((rx_id == 0) ?
1349 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1350 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1353 rxq->nb_rx_hold = nb_hold;
1358 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1361 struct ixgbe_rx_queue *rxq;
1362 volatile union ixgbe_adv_rx_desc *rx_ring;
1363 volatile union ixgbe_adv_rx_desc *rxdp;
1364 struct ixgbe_rx_entry *sw_ring;
1365 struct ixgbe_rx_entry *rxe;
1366 struct rte_mbuf *first_seg;
1367 struct rte_mbuf *last_seg;
1368 struct rte_mbuf *rxm;
1369 struct rte_mbuf *nmb;
1370 union ixgbe_adv_rx_desc rxd;
1371 uint64_t dma; /* Physical address of mbuf data buffer */
1373 uint32_t hlen_type_rss;
1383 rx_id = rxq->rx_tail;
1384 rx_ring = rxq->rx_ring;
1385 sw_ring = rxq->sw_ring;
1388 * Retrieve RX context of current packet, if any.
1390 first_seg = rxq->pkt_first_seg;
1391 last_seg = rxq->pkt_last_seg;
1393 while (nb_rx < nb_pkts) {
1396 * The order of operations here is important as the DD status
1397 * bit must not be read after any other descriptor fields.
1398 * rx_ring and rxdp are pointing to volatile data so the order
1399 * of accesses cannot be reordered by the compiler. If they were
1400 * not volatile, they could be reordered which could lead to
1401 * using invalid descriptor fields when read from rxd.
1403 rxdp = &rx_ring[rx_id];
1404 staterr = rxdp->wb.upper.status_error;
1405 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1412 * Allocate a new mbuf to replenish the RX ring descriptor.
1413 * If the allocation fails:
1414 * - arrange for that RX descriptor to be the first one
1415 * being parsed the next time the receive function is
1416 * invoked [on the same queue].
1418 * - Stop parsing the RX ring and return immediately.
1420 * This policy does not drop the packet received in the RX
1421 * descriptor for which the allocation of a new mbuf failed.
1422 * Thus, it allows that packet to be later retrieved if
1423 * mbuf have been freed in the mean time.
1424 * As a side effect, holding RX descriptors instead of
1425 * systematically giving them back to the NIC may lead to
1426 * RX ring exhaustion situations.
1427 * However, the NIC can gracefully prevent such situations
1428 * to happen by sending specific "back-pressure" flow control
1429 * frames to its peer(s).
1431 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1432 "staterr=0x%x data_len=%u",
1433 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1434 (unsigned) rx_id, (unsigned) staterr,
1435 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1437 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1439 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1440 "queue_id=%u", (unsigned) rxq->port_id,
1441 (unsigned) rxq->queue_id);
1442 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1447 rxe = &sw_ring[rx_id];
1449 if (rx_id == rxq->nb_rx_desc)
1452 /* Prefetch next mbuf while processing current one. */
1453 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1456 * When next RX descriptor is on a cache-line boundary,
1457 * prefetch the next 4 RX descriptors and the next 8 pointers
1460 if ((rx_id & 0x3) == 0) {
1461 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1462 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1466 * Update RX descriptor with the physical address of the new
1467 * data buffer of the new allocated mbuf.
1471 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1472 rxdp->read.hdr_addr = dma;
1473 rxdp->read.pkt_addr = dma;
1476 * Set data length & data buffer address of mbuf.
1478 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1479 rxm->data_len = data_len;
1480 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1483 * If this is the first buffer of the received packet,
1484 * set the pointer to the first mbuf of the packet and
1485 * initialize its context.
1486 * Otherwise, update the total length and the number of segments
1487 * of the current scattered packet, and update the pointer to
1488 * the last mbuf of the current packet.
1490 if (first_seg == NULL) {
1492 first_seg->pkt_len = data_len;
1493 first_seg->nb_segs = 1;
1495 first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
1497 first_seg->nb_segs++;
1498 last_seg->next = rxm;
1502 * If this is not the last buffer of the received packet,
1503 * update the pointer to the last mbuf of the current scattered
1504 * packet and continue to parse the RX ring.
1506 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1512 * This is the last buffer of the received packet.
1513 * If the CRC is not stripped by the hardware:
1514 * - Subtract the CRC length from the total packet length.
1515 * - If the last buffer only contains the whole CRC or a part
1516 * of it, free the mbuf associated to the last buffer.
1517 * If part of the CRC is also contained in the previous
1518 * mbuf, subtract the length of that CRC part from the
1519 * data length of the previous mbuf.
1522 if (unlikely(rxq->crc_len > 0)) {
1523 first_seg->pkt_len -= ETHER_CRC_LEN;
1524 if (data_len <= ETHER_CRC_LEN) {
1525 rte_pktmbuf_free_seg(rxm);
1526 first_seg->nb_segs--;
1527 last_seg->data_len = (uint16_t)
1528 (last_seg->data_len -
1529 (ETHER_CRC_LEN - data_len));
1530 last_seg->next = NULL;
1533 (uint16_t) (data_len - ETHER_CRC_LEN);
1537 * Initialize the first mbuf of the returned packet:
1538 * - RX port identifier,
1539 * - hardware offload data, if any:
1540 * - RSS flag & hash,
1541 * - IP checksum flag,
1542 * - VLAN TCI, if any,
1545 first_seg->port = rxq->port_id;
1548 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1549 * set in the pkt_flags field.
1551 first_seg->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1552 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1553 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1554 pkt_flags = (pkt_flags |
1555 rx_desc_status_to_pkt_flags(staterr));
1556 pkt_flags = (pkt_flags |
1557 rx_desc_error_to_pkt_flags(staterr));
1558 first_seg->ol_flags = pkt_flags;
1560 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1561 first_seg->hash.rss =
1562 rte_le_to_cpu_32(rxd.wb.lower.hi_dword.rss);
1563 else if (pkt_flags & PKT_RX_FDIR) {
1564 first_seg->hash.fdir.hash =
1565 rte_le_to_cpu_16(rxd.wb.lower.hi_dword.csum_ip.csum)
1566 & IXGBE_ATR_HASH_MASK;
1567 first_seg->hash.fdir.id =
1568 rte_le_to_cpu_16(rxd.wb.lower.hi_dword.csum_ip.ip_id);
1571 /* Prefetch data of first segment, if configured to do so. */
1572 rte_packet_prefetch((char *)first_seg->buf_addr +
1573 first_seg->data_off);
1576 * Store the mbuf address into the next entry of the array
1577 * of returned packets.
1579 rx_pkts[nb_rx++] = first_seg;
1582 * Setup receipt context for a new packet.
1588 * Record index of the next RX descriptor to probe.
1590 rxq->rx_tail = rx_id;
1593 * Save receive context.
1595 rxq->pkt_first_seg = first_seg;
1596 rxq->pkt_last_seg = last_seg;
1599 * If the number of free RX descriptors is greater than the RX free
1600 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1602 * Update the RDT with the value of the last processed RX descriptor
1603 * minus 1, to guarantee that the RDT register is never equal to the
1604 * RDH register, which creates a "full" ring situtation from the
1605 * hardware point of view...
1607 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1608 if (nb_hold > rxq->rx_free_thresh) {
1609 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1610 "nb_hold=%u nb_rx=%u",
1611 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1612 (unsigned) rx_id, (unsigned) nb_hold,
1614 rx_id = (uint16_t) ((rx_id == 0) ?
1615 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1616 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1619 rxq->nb_rx_hold = nb_hold;
1623 /*********************************************************************
1625 * Queue management functions
1627 **********************************************************************/
1630 * Rings setup and release.
1632 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1633 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1634 * also optimize cache line size effect. H/W supports up to cache line size 128.
1636 #define IXGBE_ALIGN 128
1639 * Maximum number of Ring Descriptors.
1641 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1642 * descriptors should meet the following condition:
1643 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1645 #define IXGBE_MIN_RING_DESC 32
1646 #define IXGBE_MAX_RING_DESC 4096
1649 * Create memzone for HW rings. malloc can't be used as the physical address is
1650 * needed. If the memzone is already created, then this function returns a ptr
1653 static const struct rte_memzone *
1654 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1655 uint16_t queue_id, uint32_t ring_size, int socket_id)
1657 char z_name[RTE_MEMZONE_NAMESIZE];
1658 const struct rte_memzone *mz;
1660 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1661 dev->driver->pci_drv.name, ring_name,
1662 dev->data->port_id, queue_id);
1664 mz = rte_memzone_lookup(z_name);
1668 #ifdef RTE_LIBRTE_XEN_DOM0
1669 return rte_memzone_reserve_bounded(z_name, ring_size,
1670 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1672 return rte_memzone_reserve_aligned(z_name, ring_size,
1673 socket_id, 0, IXGBE_ALIGN);
1678 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
1682 if (txq->sw_ring != NULL) {
1683 for (i = 0; i < txq->nb_tx_desc; i++) {
1684 if (txq->sw_ring[i].mbuf != NULL) {
1685 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1686 txq->sw_ring[i].mbuf = NULL;
1693 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
1696 txq->sw_ring != NULL)
1697 rte_free(txq->sw_ring);
1701 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
1703 if (txq != NULL && txq->ops != NULL) {
1704 txq->ops->release_mbufs(txq);
1705 txq->ops->free_swring(txq);
1711 ixgbe_dev_tx_queue_release(void *txq)
1713 ixgbe_tx_queue_release(txq);
1716 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
1718 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
1720 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1722 struct ixgbe_tx_entry *txe = txq->sw_ring;
1725 /* Zero out HW ring memory */
1726 for (i = 0; i < txq->nb_tx_desc; i++) {
1727 txq->tx_ring[i] = zeroed_desc;
1730 /* Initialize SW ring entries */
1731 prev = (uint16_t) (txq->nb_tx_desc - 1);
1732 for (i = 0; i < txq->nb_tx_desc; i++) {
1733 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1734 txd->wb.status = IXGBE_TXD_STAT_DD;
1737 txe[prev].next_id = i;
1741 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1742 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1745 txq->nb_tx_used = 0;
1747 * Always allow 1 descriptor to be un-allocated to avoid
1748 * a H/W race condition
1750 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1751 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1753 memset((void*)&txq->ctx_cache, 0,
1754 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1757 static const struct ixgbe_txq_ops def_txq_ops = {
1758 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1759 .free_swring = ixgbe_tx_free_swring,
1760 .reset = ixgbe_reset_tx_queue,
1763 /* Takes an ethdev and a queue and sets up the tx function to be used based on
1764 * the queue parameters. Used in tx_queue_setup by primary process and then
1765 * in dev_init by secondary process when attaching to an existing ethdev.
1768 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
1770 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1771 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS)
1772 && (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1773 PMD_INIT_LOG(INFO, "Using simple tx code path");
1774 #ifdef RTE_IXGBE_INC_VECTOR
1775 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1776 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
1777 ixgbe_txq_vec_setup(txq) == 0)) {
1778 PMD_INIT_LOG(INFO, "Vector tx enabled.");
1779 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1782 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1784 PMD_INIT_LOG(INFO, "Using full-featured tx code path");
1786 " - txq_flags = %lx " "[IXGBE_SIMPLE_FLAGS=%lx]",
1787 (unsigned long)txq->txq_flags,
1788 (unsigned long)IXGBE_SIMPLE_FLAGS);
1790 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
1791 (unsigned long)txq->tx_rs_thresh,
1792 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
1793 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1798 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1801 unsigned int socket_id,
1802 const struct rte_eth_txconf *tx_conf)
1804 const struct rte_memzone *tz;
1805 struct ixgbe_tx_queue *txq;
1806 struct ixgbe_hw *hw;
1807 uint16_t tx_rs_thresh, tx_free_thresh;
1809 PMD_INIT_FUNC_TRACE();
1810 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1813 * Validate number of transmit descriptors.
1814 * It must not exceed hardware maximum, and must be multiple
1817 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1818 (nb_desc > IXGBE_MAX_RING_DESC) ||
1819 (nb_desc < IXGBE_MIN_RING_DESC)) {
1824 * The following two parameters control the setting of the RS bit on
1825 * transmit descriptors.
1826 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1827 * descriptors have been used.
1828 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1829 * descriptors are used or if the number of descriptors required
1830 * to transmit a packet is greater than the number of free TX
1832 * The following constraints must be satisfied:
1833 * tx_rs_thresh must be greater than 0.
1834 * tx_rs_thresh must be less than the size of the ring minus 2.
1835 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1836 * tx_rs_thresh must be a divisor of the ring size.
1837 * tx_free_thresh must be greater than 0.
1838 * tx_free_thresh must be less than the size of the ring minus 3.
1839 * One descriptor in the TX ring is used as a sentinel to avoid a
1840 * H/W race condition, hence the maximum threshold constraints.
1841 * When set to zero use default values.
1843 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1844 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1845 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1846 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1847 if (tx_rs_thresh >= (nb_desc - 2)) {
1848 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
1849 "of TX descriptors minus 2. (tx_rs_thresh=%u "
1850 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1851 (int)dev->data->port_id, (int)queue_idx);
1854 if (tx_free_thresh >= (nb_desc - 3)) {
1855 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1856 "tx_free_thresh must be less than the number of "
1857 "TX descriptors minus 3. (tx_free_thresh=%u "
1858 "port=%d queue=%d)",
1859 (unsigned int)tx_free_thresh,
1860 (int)dev->data->port_id, (int)queue_idx);
1863 if (tx_rs_thresh > tx_free_thresh) {
1864 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
1865 "tx_free_thresh. (tx_free_thresh=%u "
1866 "tx_rs_thresh=%u port=%d queue=%d)",
1867 (unsigned int)tx_free_thresh,
1868 (unsigned int)tx_rs_thresh,
1869 (int)dev->data->port_id,
1873 if ((nb_desc % tx_rs_thresh) != 0) {
1874 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1875 "number of TX descriptors. (tx_rs_thresh=%u "
1876 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1877 (int)dev->data->port_id, (int)queue_idx);
1882 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1883 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1884 * by the NIC and all descriptors are written back after the NIC
1885 * accumulates WTHRESH descriptors.
1887 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1888 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1889 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1890 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1891 (int)dev->data->port_id, (int)queue_idx);
1895 /* Free memory prior to re-allocation if needed... */
1896 if (dev->data->tx_queues[queue_idx] != NULL) {
1897 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1898 dev->data->tx_queues[queue_idx] = NULL;
1901 /* First allocate the tx queue data structure */
1902 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
1903 RTE_CACHE_LINE_SIZE, socket_id);
1908 * Allocate TX ring hardware descriptors. A memzone large enough to
1909 * handle the maximum ring size is allocated in order to allow for
1910 * resizing in later calls to the queue setup function.
1912 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1913 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1916 ixgbe_tx_queue_release(txq);
1920 txq->nb_tx_desc = nb_desc;
1921 txq->tx_rs_thresh = tx_rs_thresh;
1922 txq->tx_free_thresh = tx_free_thresh;
1923 txq->pthresh = tx_conf->tx_thresh.pthresh;
1924 txq->hthresh = tx_conf->tx_thresh.hthresh;
1925 txq->wthresh = tx_conf->tx_thresh.wthresh;
1926 txq->queue_id = queue_idx;
1927 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1928 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1929 txq->port_id = dev->data->port_id;
1930 txq->txq_flags = tx_conf->txq_flags;
1931 txq->ops = &def_txq_ops;
1932 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1935 * Modification to set VFTDT for virtual function if vf is detected
1937 if (hw->mac.type == ixgbe_mac_82599_vf ||
1938 hw->mac.type == ixgbe_mac_X540_vf ||
1939 hw->mac.type == ixgbe_mac_X550_vf ||
1940 hw->mac.type == ixgbe_mac_X550EM_x_vf)
1941 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1943 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1944 #ifndef RTE_LIBRTE_XEN_DOM0
1945 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1947 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1949 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1951 /* Allocate software ring */
1952 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1953 sizeof(struct ixgbe_tx_entry) * nb_desc,
1954 RTE_CACHE_LINE_SIZE, socket_id);
1955 if (txq->sw_ring == NULL) {
1956 ixgbe_tx_queue_release(txq);
1959 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1960 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1962 /* set up vector or scalar TX function as appropriate */
1963 ixgbe_set_tx_function(dev, txq);
1965 txq->ops->reset(txq);
1967 dev->data->tx_queues[queue_idx] = txq;
1974 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
1978 if (rxq->sw_ring != NULL) {
1979 for (i = 0; i < rxq->nb_rx_desc; i++) {
1980 if (rxq->sw_ring[i].mbuf != NULL) {
1981 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1982 rxq->sw_ring[i].mbuf = NULL;
1985 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1986 if (rxq->rx_nb_avail) {
1987 for (i = 0; i < rxq->rx_nb_avail; ++i) {
1988 struct rte_mbuf *mb;
1989 mb = rxq->rx_stage[rxq->rx_next_avail + i];
1990 rte_pktmbuf_free_seg(mb);
1992 rxq->rx_nb_avail = 0;
1999 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2002 ixgbe_rx_queue_release_mbufs(rxq);
2003 rte_free(rxq->sw_ring);
2009 ixgbe_dev_rx_queue_release(void *rxq)
2011 ixgbe_rx_queue_release(rxq);
2015 * Check if Rx Burst Bulk Alloc function can be used.
2017 * 0: the preconditions are satisfied and the bulk allocation function
2019 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2020 * function must be used.
2023 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2024 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2026 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct ixgbe_rx_queue *rxq)
2032 * Make sure the following pre-conditions are satisfied:
2033 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2034 * rxq->rx_free_thresh < rxq->nb_rx_desc
2035 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2036 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2037 * Scattered packets are not supported. This should be checked
2038 * outside of this function.
2040 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2041 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2042 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2043 "rxq->rx_free_thresh=%d, "
2044 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2045 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2047 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2048 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2049 "rxq->rx_free_thresh=%d, "
2050 "rxq->nb_rx_desc=%d",
2051 rxq->rx_free_thresh, rxq->nb_rx_desc);
2053 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2054 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2055 "rxq->nb_rx_desc=%d, "
2056 "rxq->rx_free_thresh=%d",
2057 rxq->nb_rx_desc, rxq->rx_free_thresh);
2059 } else if (!(rxq->nb_rx_desc <
2060 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2061 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2062 "rxq->nb_rx_desc=%d, "
2063 "IXGBE_MAX_RING_DESC=%d, "
2064 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2065 rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2066 RTE_PMD_IXGBE_RX_MAX_BURST);
2076 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2078 ixgbe_reset_rx_queue(struct ixgbe_hw *hw, struct ixgbe_rx_queue *rxq)
2080 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
2083 uint16_t len = rxq->nb_rx_desc;
2086 * By default, the Rx queue setup function allocates enough memory for
2087 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2088 * extra memory at the end of the descriptor ring to be zero'd out. A
2089 * pre-condition for using the Rx burst bulk alloc function is that the
2090 * number of descriptors is less than or equal to
2091 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2092 * constraints here to see if we need to zero out memory after the end
2093 * of the H/W descriptor ring.
2095 if (hw->rx_bulk_alloc_allowed)
2096 /* zero out extra memory */
2097 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2100 * Zero out HW ring memory. Zero out extra memory at the end of
2101 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2102 * reads extra memory as zeros.
2104 for (i = 0; i < len; i++) {
2105 rxq->rx_ring[i] = zeroed_desc;
2108 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2110 * initialize extra software ring entries. Space for these extra
2111 * entries is always allocated
2113 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2114 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2115 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2118 rxq->rx_nb_avail = 0;
2119 rxq->rx_next_avail = 0;
2120 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2121 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2123 rxq->nb_rx_hold = 0;
2124 rxq->pkt_first_seg = NULL;
2125 rxq->pkt_last_seg = NULL;
2129 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2132 unsigned int socket_id,
2133 const struct rte_eth_rxconf *rx_conf,
2134 struct rte_mempool *mp)
2136 const struct rte_memzone *rz;
2137 struct ixgbe_rx_queue *rxq;
2138 struct ixgbe_hw *hw;
2141 PMD_INIT_FUNC_TRACE();
2142 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2145 * Validate number of receive descriptors.
2146 * It must not exceed hardware maximum, and must be multiple
2149 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2150 (nb_desc > IXGBE_MAX_RING_DESC) ||
2151 (nb_desc < IXGBE_MIN_RING_DESC)) {
2155 /* Free memory prior to re-allocation if needed... */
2156 if (dev->data->rx_queues[queue_idx] != NULL) {
2157 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2158 dev->data->rx_queues[queue_idx] = NULL;
2161 /* First allocate the rx queue data structure */
2162 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2163 RTE_CACHE_LINE_SIZE, socket_id);
2167 rxq->nb_rx_desc = nb_desc;
2168 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2169 rxq->queue_id = queue_idx;
2170 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2171 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2172 rxq->port_id = dev->data->port_id;
2173 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2175 rxq->drop_en = rx_conf->rx_drop_en;
2176 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2179 * Allocate RX ring hardware descriptors. A memzone large enough to
2180 * handle the maximum ring size is allocated in order to allow for
2181 * resizing in later calls to the queue setup function.
2183 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2184 RX_RING_SZ, socket_id);
2186 ixgbe_rx_queue_release(rxq);
2191 * Zero init all the descriptors in the ring.
2193 memset (rz->addr, 0, RX_RING_SZ);
2196 * Modified to setup VFRDT for Virtual Function
2198 if (hw->mac.type == ixgbe_mac_82599_vf ||
2199 hw->mac.type == ixgbe_mac_X540_vf ||
2200 hw->mac.type == ixgbe_mac_X550_vf ||
2201 hw->mac.type == ixgbe_mac_X550EM_x_vf) {
2203 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2205 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2209 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2211 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2213 #ifndef RTE_LIBRTE_XEN_DOM0
2214 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2216 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2218 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2221 * Certain constraints must be met in order to use the bulk buffer
2222 * allocation Rx burst function. If any of Rx queues doesn't meet them
2223 * the feature should be disabled for the whole port.
2225 if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
2226 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
2227 "preconditions - canceling the feature for "
2228 "the whole port[%d]",
2229 rxq->queue_id, rxq->port_id);
2230 hw->rx_bulk_alloc_allowed = false;
2234 * Allocate software ring. Allow for space at the end of the
2235 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2236 * function does not access an invalid memory region.
2239 if (hw->rx_bulk_alloc_allowed)
2240 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2242 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2243 sizeof(struct ixgbe_rx_entry) * len,
2244 RTE_CACHE_LINE_SIZE, socket_id);
2245 if (rxq->sw_ring == NULL) {
2246 ixgbe_rx_queue_release(rxq);
2249 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2250 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2252 if (!rte_is_power_of_2(nb_desc)) {
2253 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
2254 "preconditions - canceling the feature for "
2255 "the whole port[%d]",
2256 rxq->queue_id, rxq->port_id);
2257 hw->rx_vec_allowed = false;
2259 ixgbe_rxq_vec_setup(rxq);
2261 dev->data->rx_queues[queue_idx] = rxq;
2263 ixgbe_reset_rx_queue(hw, rxq);
2269 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2271 #define IXGBE_RXQ_SCAN_INTERVAL 4
2272 volatile union ixgbe_adv_rx_desc *rxdp;
2273 struct ixgbe_rx_queue *rxq;
2276 if (rx_queue_id >= dev->data->nb_rx_queues) {
2277 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2281 rxq = dev->data->rx_queues[rx_queue_id];
2282 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2284 while ((desc < rxq->nb_rx_desc) &&
2285 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2286 desc += IXGBE_RXQ_SCAN_INTERVAL;
2287 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2288 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2289 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2290 desc - rxq->nb_rx_desc]);
2297 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2299 volatile union ixgbe_adv_rx_desc *rxdp;
2300 struct ixgbe_rx_queue *rxq = rx_queue;
2303 if (unlikely(offset >= rxq->nb_rx_desc))
2305 desc = rxq->rx_tail + offset;
2306 if (desc >= rxq->nb_rx_desc)
2307 desc -= rxq->nb_rx_desc;
2309 rxdp = &rxq->rx_ring[desc];
2310 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2314 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2317 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2319 PMD_INIT_FUNC_TRACE();
2321 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2322 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
2324 txq->ops->release_mbufs(txq);
2325 txq->ops->reset(txq);
2329 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2330 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
2332 ixgbe_rx_queue_release_mbufs(rxq);
2333 ixgbe_reset_rx_queue(hw, rxq);
2338 /*********************************************************************
2340 * Device RX/TX init functions
2342 **********************************************************************/
2345 * Receive Side Scaling (RSS)
2346 * See section 7.1.2.8 in the following document:
2347 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2350 * The source and destination IP addresses of the IP header and the source
2351 * and destination ports of TCP/UDP headers, if any, of received packets are
2352 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2353 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2354 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2355 * RSS output index which is used as the RX queue index where to store the
2357 * The following output is supplied in the RX write-back descriptor:
2358 * - 32-bit result of the Microsoft RSS hash function,
2359 * - 4-bit RSS type field.
2363 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2364 * Used as the default key.
2366 static uint8_t rss_intel_key[40] = {
2367 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2368 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2369 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2370 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2371 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2375 ixgbe_rss_disable(struct rte_eth_dev *dev)
2377 struct ixgbe_hw *hw;
2380 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2381 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2382 mrqc &= ~IXGBE_MRQC_RSSEN;
2383 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2387 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2395 hash_key = rss_conf->rss_key;
2396 if (hash_key != NULL) {
2397 /* Fill in RSS hash key */
2398 for (i = 0; i < 10; i++) {
2399 rss_key = hash_key[(i * 4)];
2400 rss_key |= hash_key[(i * 4) + 1] << 8;
2401 rss_key |= hash_key[(i * 4) + 2] << 16;
2402 rss_key |= hash_key[(i * 4) + 3] << 24;
2403 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2407 /* Set configured hashing protocols in MRQC register */
2408 rss_hf = rss_conf->rss_hf;
2409 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2410 if (rss_hf & ETH_RSS_IPV4)
2411 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2412 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2413 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2414 if (rss_hf & ETH_RSS_IPV6)
2415 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2416 if (rss_hf & ETH_RSS_IPV6_EX)
2417 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2418 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2419 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2420 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2421 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2422 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2423 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2424 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2425 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2426 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2427 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2428 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2432 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2433 struct rte_eth_rss_conf *rss_conf)
2435 struct ixgbe_hw *hw;
2439 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2442 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2443 * "RSS enabling cannot be done dynamically while it must be
2444 * preceded by a software reset"
2445 * Before changing anything, first check that the update RSS operation
2446 * does not attempt to disable RSS, if RSS was enabled at
2447 * initialization time, or does not attempt to enable RSS, if RSS was
2448 * disabled at initialization time.
2450 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2451 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2452 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2453 if (rss_hf != 0) /* Enable RSS */
2455 return 0; /* Nothing to do */
2458 if (rss_hf == 0) /* Disable RSS */
2460 ixgbe_hw_rss_hash_set(hw, rss_conf);
2465 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2466 struct rte_eth_rss_conf *rss_conf)
2468 struct ixgbe_hw *hw;
2475 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2476 hash_key = rss_conf->rss_key;
2477 if (hash_key != NULL) {
2478 /* Return RSS hash key */
2479 for (i = 0; i < 10; i++) {
2480 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2481 hash_key[(i * 4)] = rss_key & 0x000000FF;
2482 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2483 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2484 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2488 /* Get RSS functions configured in MRQC register */
2489 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2490 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2491 rss_conf->rss_hf = 0;
2495 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2496 rss_hf |= ETH_RSS_IPV4;
2497 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2498 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2499 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2500 rss_hf |= ETH_RSS_IPV6;
2501 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2502 rss_hf |= ETH_RSS_IPV6_EX;
2503 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2504 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2505 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2506 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2507 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2508 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2509 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2510 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2511 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2512 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2513 rss_conf->rss_hf = rss_hf;
2518 ixgbe_rss_configure(struct rte_eth_dev *dev)
2520 struct rte_eth_rss_conf rss_conf;
2521 struct ixgbe_hw *hw;
2526 PMD_INIT_FUNC_TRACE();
2527 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2530 * Fill in redirection table
2531 * The byte-swap is needed because NIC registers are in
2532 * little-endian order.
2535 for (i = 0, j = 0; i < 128; i++, j++) {
2536 if (j == dev->data->nb_rx_queues)
2538 reta = (reta << 8) | j;
2540 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2545 * Configure the RSS key and the RSS protocols used to compute
2546 * the RSS hash of input packets.
2548 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2549 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2550 ixgbe_rss_disable(dev);
2553 if (rss_conf.rss_key == NULL)
2554 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2555 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2558 #define NUM_VFTA_REGISTERS 128
2559 #define NIC_RX_BUFFER_SIZE 0x200
2562 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2564 struct rte_eth_vmdq_dcb_conf *cfg;
2565 struct ixgbe_hw *hw;
2566 enum rte_eth_nb_pools num_pools;
2567 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2569 uint8_t nb_tcs; /* number of traffic classes */
2572 PMD_INIT_FUNC_TRACE();
2573 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2574 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2575 num_pools = cfg->nb_queue_pools;
2576 /* Check we have a valid number of pools */
2577 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2578 ixgbe_rss_disable(dev);
2581 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2582 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2586 * split rx buffer up into sections, each for 1 traffic class
2588 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2589 for (i = 0 ; i < nb_tcs; i++) {
2590 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2591 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2592 /* clear 10 bits. */
2593 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2594 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2596 /* zero alloc all unused TCs */
2597 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2598 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2599 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2600 /* clear 10 bits. */
2601 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2604 /* MRQC: enable vmdq and dcb */
2605 mrqc = ((num_pools == ETH_16_POOLS) ? \
2606 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2607 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2609 /* PFVTCTL: turn on virtualisation and set the default pool */
2610 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2611 if (cfg->enable_default_pool) {
2612 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2614 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2617 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2619 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2621 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2623 * mapping is done with 3 bits per priority,
2624 * so shift by i*3 each time
2626 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2628 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2630 /* RTRPCS: DCB related */
2631 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2633 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2634 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2635 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2636 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2638 /* VFTA - enable all vlan filters */
2639 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2640 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2643 /* VFRE: pool enabling for receive - 16 or 32 */
2644 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2645 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2648 * MPSAR - allow pools to read specific mac addresses
2649 * In this case, all pools should be able to read from mac addr 0
2651 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2652 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2654 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2655 for (i = 0; i < cfg->nb_pool_maps; i++) {
2656 /* set vlan id in VF register and set the valid bit */
2657 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2658 (cfg->pool_map[i].vlan_id & 0xFFF)));
2660 * Put the allowed pools in VFB reg. As we only have 16 or 32
2661 * pools, we only need to use the first half of the register
2664 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2669 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2670 * @hw: pointer to hardware structure
2671 * @dcb_config: pointer to ixgbe_dcb_config structure
2674 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2675 struct ixgbe_dcb_config *dcb_config)
2680 PMD_INIT_FUNC_TRACE();
2681 if (hw->mac.type != ixgbe_mac_82598EB) {
2682 /* Disable the Tx desc arbiter so that MTQC can be changed */
2683 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2684 reg |= IXGBE_RTTDCS_ARBDIS;
2685 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2687 /* Enable DCB for Tx with 8 TCs */
2688 if (dcb_config->num_tcs.pg_tcs == 8) {
2689 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2692 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2694 if (dcb_config->vt_mode)
2695 reg |= IXGBE_MTQC_VT_ENA;
2696 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2698 /* Disable drop for all queues */
2699 for (q = 0; q < 128; q++)
2700 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2701 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2703 /* Enable the Tx desc arbiter */
2704 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2705 reg &= ~IXGBE_RTTDCS_ARBDIS;
2706 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2708 /* Enable Security TX Buffer IFG for DCB */
2709 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2710 reg |= IXGBE_SECTX_DCB;
2711 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2717 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2718 * @dev: pointer to rte_eth_dev structure
2719 * @dcb_config: pointer to ixgbe_dcb_config structure
2722 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2723 struct ixgbe_dcb_config *dcb_config)
2725 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2726 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2727 struct ixgbe_hw *hw =
2728 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2730 PMD_INIT_FUNC_TRACE();
2731 if (hw->mac.type != ixgbe_mac_82598EB)
2732 /*PF VF Transmit Enable*/
2733 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2734 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2736 /*Configure general DCB TX parameters*/
2737 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2742 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2743 struct ixgbe_dcb_config *dcb_config)
2745 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2746 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2747 struct ixgbe_dcb_tc_config *tc;
2750 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2751 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2752 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2753 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2756 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2757 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2759 /* User Priority to Traffic Class mapping */
2760 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2761 j = vmdq_rx_conf->dcb_queue[i];
2762 tc = &dcb_config->tc_config[j];
2763 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2769 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2770 struct ixgbe_dcb_config *dcb_config)
2772 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2773 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2774 struct ixgbe_dcb_tc_config *tc;
2777 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2778 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2779 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2780 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2783 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2784 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2787 /* User Priority to Traffic Class mapping */
2788 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2789 j = vmdq_tx_conf->dcb_queue[i];
2790 tc = &dcb_config->tc_config[j];
2791 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2798 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2799 struct ixgbe_dcb_config *dcb_config)
2801 struct rte_eth_dcb_rx_conf *rx_conf =
2802 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2803 struct ixgbe_dcb_tc_config *tc;
2806 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2807 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2809 /* User Priority to Traffic Class mapping */
2810 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2811 j = rx_conf->dcb_queue[i];
2812 tc = &dcb_config->tc_config[j];
2813 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2819 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2820 struct ixgbe_dcb_config *dcb_config)
2822 struct rte_eth_dcb_tx_conf *tx_conf =
2823 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2824 struct ixgbe_dcb_tc_config *tc;
2827 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2828 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2830 /* User Priority to Traffic Class mapping */
2831 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2832 j = tx_conf->dcb_queue[i];
2833 tc = &dcb_config->tc_config[j];
2834 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2840 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2841 * @hw: pointer to hardware structure
2842 * @dcb_config: pointer to ixgbe_dcb_config structure
2845 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2846 struct ixgbe_dcb_config *dcb_config)
2852 PMD_INIT_FUNC_TRACE();
2854 * Disable the arbiter before changing parameters
2855 * (always enable recycle mode; WSP)
2857 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2858 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2860 if (hw->mac.type != ixgbe_mac_82598EB) {
2861 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2862 if (dcb_config->num_tcs.pg_tcs == 4) {
2863 if (dcb_config->vt_mode)
2864 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2865 IXGBE_MRQC_VMDQRT4TCEN;
2867 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2868 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2872 if (dcb_config->num_tcs.pg_tcs == 8) {
2873 if (dcb_config->vt_mode)
2874 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2875 IXGBE_MRQC_VMDQRT8TCEN;
2877 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2878 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2883 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2886 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2887 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2888 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2889 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2891 /* VFTA - enable all vlan filters */
2892 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2893 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2897 * Configure Rx packet plane (recycle mode; WSP) and
2900 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2901 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2907 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2908 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2910 switch (hw->mac.type) {
2911 case ixgbe_mac_82598EB:
2912 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2914 case ixgbe_mac_82599EB:
2915 case ixgbe_mac_X540:
2916 case ixgbe_mac_X550:
2917 case ixgbe_mac_X550EM_x:
2918 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2927 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2928 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2930 switch (hw->mac.type) {
2931 case ixgbe_mac_82598EB:
2932 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2933 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2935 case ixgbe_mac_82599EB:
2936 case ixgbe_mac_X540:
2937 case ixgbe_mac_X550:
2938 case ixgbe_mac_X550EM_x:
2939 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2940 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2947 #define DCB_RX_CONFIG 1
2948 #define DCB_TX_CONFIG 1
2949 #define DCB_TX_PB 1024
2951 * ixgbe_dcb_hw_configure - Enable DCB and configure
2952 * general DCB in VT mode and non-VT mode parameters
2953 * @dev: pointer to rte_eth_dev structure
2954 * @dcb_config: pointer to ixgbe_dcb_config structure
2957 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2958 struct ixgbe_dcb_config *dcb_config)
2961 uint8_t i,pfc_en,nb_tcs;
2963 uint8_t config_dcb_rx = 0;
2964 uint8_t config_dcb_tx = 0;
2965 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2966 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2967 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2968 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2969 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2970 struct ixgbe_dcb_tc_config *tc;
2971 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2972 struct ixgbe_hw *hw =
2973 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2975 switch(dev->data->dev_conf.rxmode.mq_mode){
2976 case ETH_MQ_RX_VMDQ_DCB:
2977 dcb_config->vt_mode = true;
2978 if (hw->mac.type != ixgbe_mac_82598EB) {
2979 config_dcb_rx = DCB_RX_CONFIG;
2981 *get dcb and VT rx configuration parameters
2984 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2985 /*Configure general VMDQ and DCB RX parameters*/
2986 ixgbe_vmdq_dcb_configure(dev);
2990 dcb_config->vt_mode = false;
2991 config_dcb_rx = DCB_RX_CONFIG;
2992 /* Get dcb TX configuration parameters from rte_eth_conf */
2993 ixgbe_dcb_rx_config(dev,dcb_config);
2994 /*Configure general DCB RX parameters*/
2995 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2998 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3001 switch (dev->data->dev_conf.txmode.mq_mode) {
3002 case ETH_MQ_TX_VMDQ_DCB:
3003 dcb_config->vt_mode = true;
3004 config_dcb_tx = DCB_TX_CONFIG;
3005 /* get DCB and VT TX configuration parameters from rte_eth_conf */
3006 ixgbe_dcb_vt_tx_config(dev,dcb_config);
3007 /*Configure general VMDQ and DCB TX parameters*/
3008 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
3012 dcb_config->vt_mode = false;
3013 config_dcb_tx = DCB_TX_CONFIG;
3014 /*get DCB TX configuration parameters from rte_eth_conf*/
3015 ixgbe_dcb_tx_config(dev,dcb_config);
3016 /*Configure general DCB TX parameters*/
3017 ixgbe_dcb_tx_hw_config(hw, dcb_config);
3020 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3024 nb_tcs = dcb_config->num_tcs.pfc_tcs;
3026 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3027 if(nb_tcs == ETH_4_TCS) {
3028 /* Avoid un-configured priority mapping to TC0 */
3030 uint8_t mask = 0xFF;
3031 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3032 mask = (uint8_t)(mask & (~ (1 << map[i])));
3033 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3034 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3038 /* Re-configure 4 TCs BW */
3039 for (i = 0; i < nb_tcs; i++) {
3040 tc = &dcb_config->tc_config[i];
3041 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3042 (uint8_t)(100 / nb_tcs);
3043 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3044 (uint8_t)(100 / nb_tcs);
3046 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3047 tc = &dcb_config->tc_config[i];
3048 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3049 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3054 /* Set RX buffer size */
3055 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3056 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3057 for (i = 0 ; i < nb_tcs; i++) {
3058 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3060 /* zero alloc all unused TCs */
3061 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3062 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3066 /* Only support an equally distributed Tx packet buffer strategy. */
3067 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3068 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3069 for (i = 0; i < nb_tcs; i++) {
3070 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3071 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3073 /* Clear unused TCs, if any, to zero buffer size*/
3074 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3075 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3076 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3080 /*Calculates traffic class credits*/
3081 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3082 IXGBE_DCB_TX_CONFIG);
3083 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3084 IXGBE_DCB_RX_CONFIG);
3087 /* Unpack CEE standard containers */
3088 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3089 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3090 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3091 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3092 /* Configure PG(ETS) RX */
3093 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3097 /* Unpack CEE standard containers */
3098 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3099 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3100 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3101 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3102 /* Configure PG(ETS) TX */
3103 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3106 /*Configure queue statistics registers*/
3107 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3109 /* Check if the PFC is supported */
3110 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3111 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3112 for (i = 0; i < nb_tcs; i++) {
3114 * If the TC count is 8,and the default high_water is 48,
3115 * the low_water is 16 as default.
3117 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3118 hw->fc.low_water[i] = pbsize / 4;
3119 /* Enable pfc for this TC */
3120 tc = &dcb_config->tc_config[i];
3121 tc->pfc = ixgbe_dcb_pfc_enabled;
3123 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3124 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3126 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3133 * ixgbe_configure_dcb - Configure DCB Hardware
3134 * @dev: pointer to rte_eth_dev
3136 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3138 struct ixgbe_dcb_config *dcb_cfg =
3139 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3140 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3142 PMD_INIT_FUNC_TRACE();
3144 /* check support mq_mode for DCB */
3145 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3146 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3149 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3152 /** Configure DCB hardware **/
3153 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3159 * VMDq only support for 10 GbE NIC.
3162 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3164 struct rte_eth_vmdq_rx_conf *cfg;
3165 struct ixgbe_hw *hw;
3166 enum rte_eth_nb_pools num_pools;
3167 uint32_t mrqc, vt_ctl, vlanctrl;
3171 PMD_INIT_FUNC_TRACE();
3172 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3173 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3174 num_pools = cfg->nb_queue_pools;
3176 ixgbe_rss_disable(dev);
3178 /* MRQC: enable vmdq */
3179 mrqc = IXGBE_MRQC_VMDQEN;
3180 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3182 /* PFVTCTL: turn on virtualisation and set the default pool */
3183 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3184 if (cfg->enable_default_pool)
3185 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3187 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3189 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3191 for (i = 0; i < (int)num_pools; i++) {
3192 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
3193 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
3196 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3197 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3198 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3199 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3201 /* VFTA - enable all vlan filters */
3202 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3203 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3205 /* VFRE: pool enabling for receive - 64 */
3206 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3207 if (num_pools == ETH_64_POOLS)
3208 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3211 * MPSAR - allow pools to read specific mac addresses
3212 * In this case, all pools should be able to read from mac addr 0
3214 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3215 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3217 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3218 for (i = 0; i < cfg->nb_pool_maps; i++) {
3219 /* set vlan id in VF register and set the valid bit */
3220 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3221 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3223 * Put the allowed pools in VFB reg. As we only have 16 or 64
3224 * pools, we only need to use the first half of the register
3227 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3228 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3229 (cfg->pool_map[i].pools & UINT32_MAX));
3231 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3232 ((cfg->pool_map[i].pools >> 32) \
3237 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3238 if (cfg->enable_loop_back) {
3239 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3240 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3241 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3244 IXGBE_WRITE_FLUSH(hw);
3248 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3249 * @hw: pointer to hardware structure
3252 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3257 PMD_INIT_FUNC_TRACE();
3258 /*PF VF Transmit Enable*/
3259 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3260 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3262 /* Disable the Tx desc arbiter so that MTQC can be changed */
3263 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3264 reg |= IXGBE_RTTDCS_ARBDIS;
3265 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3267 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3268 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3270 /* Disable drop for all queues */
3271 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3272 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3273 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3275 /* Enable the Tx desc arbiter */
3276 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3277 reg &= ~IXGBE_RTTDCS_ARBDIS;
3278 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3280 IXGBE_WRITE_FLUSH(hw);
3286 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
3288 struct ixgbe_rx_entry *rxe = rxq->sw_ring;
3292 /* Initialize software ring entries */
3293 for (i = 0; i < rxq->nb_rx_desc; i++) {
3294 volatile union ixgbe_adv_rx_desc *rxd;
3295 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3297 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3298 (unsigned) rxq->queue_id);
3302 rte_mbuf_refcnt_set(mbuf, 1);
3304 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3306 mbuf->port = rxq->port_id;
3309 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3310 rxd = &rxq->rx_ring[i];
3311 rxd->read.hdr_addr = dma_addr;
3312 rxd->read.pkt_addr = dma_addr;
3320 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
3322 struct ixgbe_hw *hw;
3325 ixgbe_rss_configure(dev);
3327 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3329 /* MRQC: enable VF RSS */
3330 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
3331 mrqc &= ~IXGBE_MRQC_MRQE_MASK;
3332 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3334 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
3338 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
3342 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
3346 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3352 ixgbe_config_vf_default(struct rte_eth_dev *dev)
3354 struct ixgbe_hw *hw =
3355 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3357 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3359 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3364 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3365 IXGBE_MRQC_VMDQRT4TCEN);
3369 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3370 IXGBE_MRQC_VMDQRT8TCEN);
3374 "invalid pool number in IOV mode");
3381 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3383 struct ixgbe_hw *hw =
3384 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3386 if (hw->mac.type == ixgbe_mac_82598EB)
3389 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3391 * SRIOV inactive scheme
3392 * any DCB/RSS w/o VMDq multi-queue setting
3394 switch (dev->data->dev_conf.rxmode.mq_mode) {
3396 ixgbe_rss_configure(dev);
3399 case ETH_MQ_RX_VMDQ_DCB:
3400 ixgbe_vmdq_dcb_configure(dev);
3403 case ETH_MQ_RX_VMDQ_ONLY:
3404 ixgbe_vmdq_rx_hw_configure(dev);
3407 case ETH_MQ_RX_NONE:
3408 /* if mq_mode is none, disable rss mode.*/
3409 default: ixgbe_rss_disable(dev);
3413 * SRIOV active scheme
3414 * Support RSS together with VMDq & SRIOV
3416 switch (dev->data->dev_conf.rxmode.mq_mode) {
3418 case ETH_MQ_RX_VMDQ_RSS:
3419 ixgbe_config_vf_rss(dev);
3422 /* FIXME if support DCB/RSS together with VMDq & SRIOV */
3423 case ETH_MQ_RX_VMDQ_DCB:
3424 case ETH_MQ_RX_VMDQ_DCB_RSS:
3426 "Could not support DCB with VMDq & SRIOV");
3429 ixgbe_config_vf_default(dev);
3438 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3440 struct ixgbe_hw *hw =
3441 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3445 if (hw->mac.type == ixgbe_mac_82598EB)
3448 /* disable arbiter before setting MTQC */
3449 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3450 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3451 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3453 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3455 * SRIOV inactive scheme
3456 * any DCB w/o VMDq multi-queue setting
3458 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3459 ixgbe_vmdq_tx_hw_configure(hw);
3461 mtqc = IXGBE_MTQC_64Q_1PB;
3462 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3465 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3468 * SRIOV active scheme
3469 * FIXME if support DCB together with VMDq & SRIOV
3472 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3475 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3478 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3482 mtqc = IXGBE_MTQC_64Q_1PB;
3483 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3485 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3488 /* re-enable arbiter */
3489 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3490 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3495 void ixgbe_set_rx_function(struct rte_eth_dev *dev)
3497 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3500 * In order to allow Vector Rx there are a few configuration
3501 * conditions to be met and Rx Bulk Allocation should be allowed.
3503 if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
3504 !hw->rx_bulk_alloc_allowed) {
3505 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
3506 "preconditions or RTE_IXGBE_INC_VECTOR is "
3508 dev->data->port_id);
3510 hw->rx_vec_allowed = false;
3513 if (dev->data->scattered_rx) {
3515 * Set the non-LRO scattered callback: there are Vector and
3516 * single allocation versions.
3518 if (hw->rx_vec_allowed) {
3519 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3520 "callback (port=%d).",
3521 dev->data->port_id);
3523 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3525 PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector) "
3526 "Scattered Rx callback "
3528 dev->data->port_id);
3530 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3533 * Below we set "simple" callbacks according to port/queues parameters.
3534 * If parameters allow we are going to choose between the following
3538 * - Single buffer allocation (the simplest one)
3540 } else if (hw->rx_vec_allowed) {
3541 PMD_INIT_LOG(INFO, "Vector rx enabled, please make sure RX "
3542 "burst size no less than 32.");
3544 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
3545 } else if (hw->rx_bulk_alloc_allowed) {
3546 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3547 "satisfied. Rx Burst Bulk Alloc function "
3548 "will be used on port=%d.",
3549 dev->data->port_id);
3551 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
3553 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3554 "satisfied, or Scattered Rx is requested, "
3555 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC "
3556 "is not enabled (port=%d).",
3557 dev->data->port_id);
3559 dev->rx_pkt_burst = ixgbe_recv_pkts;
3564 * Initializes Receive Unit.
3567 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3569 struct ixgbe_hw *hw;
3570 struct ixgbe_rx_queue *rxq;
3571 struct rte_pktmbuf_pool_private *mbp_priv;
3583 PMD_INIT_FUNC_TRACE();
3584 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3587 * Make sure receives are disabled while setting
3588 * up the RX context (registers, descriptor rings, etc.).
3590 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3591 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3593 /* Enable receipt of broadcasted frames */
3594 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3595 fctrl |= IXGBE_FCTRL_BAM;
3596 fctrl |= IXGBE_FCTRL_DPF;
3597 fctrl |= IXGBE_FCTRL_PMCF;
3598 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3601 * Configure CRC stripping, if any.
3603 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3604 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3605 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3607 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3610 * Configure jumbo frame support, if any.
3612 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3613 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3614 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3615 maxfrs &= 0x0000FFFF;
3616 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3617 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3619 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3622 * If loopback mode is configured for 82599, set LPBK bit.
3624 if (hw->mac.type == ixgbe_mac_82599EB &&
3625 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3626 hlreg0 |= IXGBE_HLREG0_LPBK;
3628 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3630 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3632 /* Setup RX queues */
3633 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3634 rxq = dev->data->rx_queues[i];
3637 * Reset crc_len in case it was changed after queue setup by a
3638 * call to configure.
3640 rxq->crc_len = (uint8_t)
3641 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3644 /* Setup the Base and Length of the Rx Descriptor Rings */
3645 bus_addr = rxq->rx_ring_phys_addr;
3646 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3647 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3648 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3649 (uint32_t)(bus_addr >> 32));
3650 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3651 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3652 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3653 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3655 /* Configure the SRRCTL register */
3656 #ifdef RTE_HEADER_SPLIT_ENABLE
3658 * Configure Header Split
3660 if (dev->data->dev_conf.rxmode.header_split) {
3661 if (hw->mac.type == ixgbe_mac_82599EB) {
3662 /* Must setup the PSRTYPE register */
3664 psrtype = IXGBE_PSRTYPE_TCPHDR |
3665 IXGBE_PSRTYPE_UDPHDR |
3666 IXGBE_PSRTYPE_IPV4HDR |
3667 IXGBE_PSRTYPE_IPV6HDR;
3668 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3670 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3671 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3672 IXGBE_SRRCTL_BSIZEHDR_MASK);
3673 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3676 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3678 /* Set if packets are dropped when no descriptors available */
3680 srrctl |= IXGBE_SRRCTL_DROP_EN;
3683 * Configure the RX buffer size in the BSIZEPACKET field of
3684 * the SRRCTL register of the queue.
3685 * The value is in 1 KB resolution. Valid values can be from
3688 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3689 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3690 RTE_PKTMBUF_HEADROOM);
3691 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3692 IXGBE_SRRCTL_BSIZEPKT_MASK);
3693 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3695 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3696 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3698 /* It adds dual VLAN length for supporting dual VLAN */
3699 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
3700 2 * IXGBE_VLAN_TAG_SIZE > buf_size)
3701 dev->data->scattered_rx = 1;
3704 if (dev->data->dev_conf.rxmode.enable_scatter)
3705 dev->data->scattered_rx = 1;
3707 ixgbe_set_rx_function(dev);
3710 * Device configured with multiple RX queues.
3712 ixgbe_dev_mq_rx_configure(dev);
3715 * Setup the Checksum Register.
3716 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3717 * Enable IP/L4 checkum computation by hardware if requested to do so.
3719 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3720 rxcsum |= IXGBE_RXCSUM_PCSD;
3721 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3722 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3724 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3726 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3728 if (hw->mac.type == ixgbe_mac_82599EB ||
3729 hw->mac.type == ixgbe_mac_X540) {
3730 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3731 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3732 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3734 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3735 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3736 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3743 * Initializes Transmit Unit.
3746 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3748 struct ixgbe_hw *hw;
3749 struct ixgbe_tx_queue *txq;
3755 PMD_INIT_FUNC_TRACE();
3756 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3758 /* Enable TX CRC (checksum offload requirement) and hw padding
3759 * (TSO requirement) */
3760 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3761 hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
3762 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3764 /* Setup the Base and Length of the Tx Descriptor Rings */
3765 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3766 txq = dev->data->tx_queues[i];
3768 bus_addr = txq->tx_ring_phys_addr;
3769 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3770 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3771 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3772 (uint32_t)(bus_addr >> 32));
3773 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3774 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3775 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3776 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3777 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3780 * Disable Tx Head Writeback RO bit, since this hoses
3781 * bookkeeping if things aren't delivered in order.
3783 switch (hw->mac.type) {
3784 case ixgbe_mac_82598EB:
3785 txctrl = IXGBE_READ_REG(hw,
3786 IXGBE_DCA_TXCTRL(txq->reg_idx));
3787 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3788 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3792 case ixgbe_mac_82599EB:
3793 case ixgbe_mac_X540:
3794 case ixgbe_mac_X550:
3795 case ixgbe_mac_X550EM_x:
3797 txctrl = IXGBE_READ_REG(hw,
3798 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3799 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3800 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3806 /* Device configured with multiple TX queues. */
3807 ixgbe_dev_mq_tx_configure(dev);
3811 * Set up link for 82599 loopback mode Tx->Rx.
3814 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3816 PMD_INIT_FUNC_TRACE();
3818 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3819 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3821 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
3830 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3831 ixgbe_reset_pipeline_82599(hw);
3833 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3839 * Start Transmit and Receive Units.
3842 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3844 struct ixgbe_hw *hw;
3845 struct ixgbe_tx_queue *txq;
3846 struct ixgbe_rx_queue *rxq;
3853 PMD_INIT_FUNC_TRACE();
3854 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3856 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3857 txq = dev->data->tx_queues[i];
3858 /* Setup Transmit Threshold Registers */
3859 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3860 txdctl |= txq->pthresh & 0x7F;
3861 txdctl |= ((txq->hthresh & 0x7F) << 8);
3862 txdctl |= ((txq->wthresh & 0x7F) << 16);
3863 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3866 if (hw->mac.type != ixgbe_mac_82598EB) {
3867 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3868 dmatxctl |= IXGBE_DMATXCTL_TE;
3869 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3872 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3873 txq = dev->data->tx_queues[i];
3874 if (!txq->tx_deferred_start) {
3875 ret = ixgbe_dev_tx_queue_start(dev, i);
3881 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3882 rxq = dev->data->rx_queues[i];
3883 if (!rxq->rx_deferred_start) {
3884 ret = ixgbe_dev_rx_queue_start(dev, i);
3890 /* Enable Receive engine */
3891 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3892 if (hw->mac.type == ixgbe_mac_82598EB)
3893 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3894 rxctrl |= IXGBE_RXCTRL_RXEN;
3895 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3897 /* If loopback mode is enabled for 82599, set up the link accordingly */
3898 if (hw->mac.type == ixgbe_mac_82599EB &&
3899 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3900 ixgbe_setup_loopback_link_82599(hw);
3906 * Start Receive Units for specified queue.
3909 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3911 struct ixgbe_hw *hw;
3912 struct ixgbe_rx_queue *rxq;
3916 PMD_INIT_FUNC_TRACE();
3917 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3919 if (rx_queue_id < dev->data->nb_rx_queues) {
3920 rxq = dev->data->rx_queues[rx_queue_id];
3922 /* Allocate buffers for descriptor rings */
3923 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
3924 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
3928 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3929 rxdctl |= IXGBE_RXDCTL_ENABLE;
3930 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3932 /* Wait until RX Enable ready */
3933 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3936 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3937 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3939 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
3942 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3943 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3951 * Stop Receive Units for specified queue.
3954 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3956 struct ixgbe_hw *hw;
3957 struct ixgbe_rx_queue *rxq;
3961 PMD_INIT_FUNC_TRACE();
3962 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3964 if (rx_queue_id < dev->data->nb_rx_queues) {
3965 rxq = dev->data->rx_queues[rx_queue_id];
3967 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3968 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3969 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3971 /* Wait until RX Enable ready */
3972 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3975 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3976 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
3978 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
3981 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3983 ixgbe_rx_queue_release_mbufs(rxq);
3984 ixgbe_reset_rx_queue(hw, rxq);
3993 * Start Transmit Units for specified queue.
3996 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3998 struct ixgbe_hw *hw;
3999 struct ixgbe_tx_queue *txq;
4003 PMD_INIT_FUNC_TRACE();
4004 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4006 if (tx_queue_id < dev->data->nb_tx_queues) {
4007 txq = dev->data->tx_queues[tx_queue_id];
4008 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4009 txdctl |= IXGBE_TXDCTL_ENABLE;
4010 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4012 /* Wait until TX Enable ready */
4013 if (hw->mac.type == ixgbe_mac_82599EB) {
4014 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4017 txdctl = IXGBE_READ_REG(hw,
4018 IXGBE_TXDCTL(txq->reg_idx));
4019 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4021 PMD_INIT_LOG(ERR, "Could not enable "
4022 "Tx Queue %d", tx_queue_id);
4025 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4026 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4034 * Stop Transmit Units for specified queue.
4037 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4039 struct ixgbe_hw *hw;
4040 struct ixgbe_tx_queue *txq;
4042 uint32_t txtdh, txtdt;
4045 PMD_INIT_FUNC_TRACE();
4046 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4048 if (tx_queue_id < dev->data->nb_tx_queues) {
4049 txq = dev->data->tx_queues[tx_queue_id];
4051 /* Wait until TX queue is empty */
4052 if (hw->mac.type == ixgbe_mac_82599EB) {
4053 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4055 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4056 txtdh = IXGBE_READ_REG(hw,
4057 IXGBE_TDH(txq->reg_idx));
4058 txtdt = IXGBE_READ_REG(hw,
4059 IXGBE_TDT(txq->reg_idx));
4060 } while (--poll_ms && (txtdh != txtdt));
4062 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
4063 "when stopping.", tx_queue_id);
4066 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4067 txdctl &= ~IXGBE_TXDCTL_ENABLE;
4068 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4070 /* Wait until TX Enable ready */
4071 if (hw->mac.type == ixgbe_mac_82599EB) {
4072 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4075 txdctl = IXGBE_READ_REG(hw,
4076 IXGBE_TXDCTL(txq->reg_idx));
4077 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
4079 PMD_INIT_LOG(ERR, "Could not disable "
4080 "Tx Queue %d", tx_queue_id);
4083 if (txq->ops != NULL) {
4084 txq->ops->release_mbufs(txq);
4085 txq->ops->reset(txq);
4094 * [VF] Initializes Receive Unit.
4097 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
4099 struct ixgbe_hw *hw;
4100 struct ixgbe_rx_queue *rxq;
4101 struct rte_pktmbuf_pool_private *mbp_priv;
4103 uint32_t srrctl, psrtype = 0;
4108 PMD_INIT_FUNC_TRACE();
4109 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4111 if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
4112 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4113 "it should be power of 2");
4117 if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
4118 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4119 "it should be equal to or less than %d",
4120 hw->mac.max_rx_queues);
4125 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
4126 * disables the VF receipt of packets if the PF MTU is > 1500.
4127 * This is done to deal with 82599 limitations that imposes
4128 * the PF and all VFs to share the same MTU.
4129 * Then, the PF driver enables again the VF receipt of packet when
4130 * the VF driver issues a IXGBE_VF_SET_LPE request.
4131 * In the meantime, the VF device cannot be used, even if the VF driver
4132 * and the Guest VM network stack are ready to accept packets with a
4133 * size up to the PF MTU.
4134 * As a work-around to this PF behaviour, force the call to
4135 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
4136 * VF packets received can work in all cases.
4138 ixgbevf_rlpml_set_vf(hw,
4139 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
4141 /* Setup RX queues */
4142 dev->rx_pkt_burst = ixgbe_recv_pkts;
4143 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4144 rxq = dev->data->rx_queues[i];
4146 /* Allocate buffers for descriptor rings */
4147 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
4151 /* Setup the Base and Length of the Rx Descriptor Rings */
4152 bus_addr = rxq->rx_ring_phys_addr;
4154 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
4155 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4156 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
4157 (uint32_t)(bus_addr >> 32));
4158 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
4159 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4160 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
4161 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
4164 /* Configure the SRRCTL register */
4165 #ifdef RTE_HEADER_SPLIT_ENABLE
4167 * Configure Header Split
4169 if (dev->data->dev_conf.rxmode.header_split) {
4170 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
4171 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4172 IXGBE_SRRCTL_BSIZEHDR_MASK);
4173 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4176 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4178 /* Set if packets are dropped when no descriptors available */
4180 srrctl |= IXGBE_SRRCTL_DROP_EN;
4183 * Configure the RX buffer size in the BSIZEPACKET field of
4184 * the SRRCTL register of the queue.
4185 * The value is in 1 KB resolution. Valid values can be from
4188 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
4189 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
4190 RTE_PKTMBUF_HEADROOM);
4191 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4192 IXGBE_SRRCTL_BSIZEPKT_MASK);
4195 * VF modification to write virtual function SRRCTL register
4197 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
4199 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4200 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4202 if (dev->data->dev_conf.rxmode.enable_scatter ||
4203 /* It adds dual VLAN length for supporting dual VLAN */
4204 (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4205 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
4206 if (!dev->data->scattered_rx)
4207 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4208 dev->data->scattered_rx = 1;
4209 #ifdef RTE_IXGBE_INC_VECTOR
4210 if (rte_is_power_of_2(rxq->nb_rx_desc))
4212 ixgbe_recv_scattered_pkts_vec;
4215 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
4219 #ifdef RTE_HEADER_SPLIT_ENABLE
4220 if (dev->data->dev_conf.rxmode.header_split)
4221 /* Must setup the PSRTYPE register */
4222 psrtype = IXGBE_PSRTYPE_TCPHDR |
4223 IXGBE_PSRTYPE_UDPHDR |
4224 IXGBE_PSRTYPE_IPV4HDR |
4225 IXGBE_PSRTYPE_IPV6HDR;
4228 /* Set RQPL for VF RSS according to max Rx queue */
4229 psrtype |= (dev->data->nb_rx_queues >> 1) <<
4230 IXGBE_PSRTYPE_RQPL_SHIFT;
4231 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
4237 * [VF] Initializes Transmit Unit.
4240 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4242 struct ixgbe_hw *hw;
4243 struct ixgbe_tx_queue *txq;
4248 PMD_INIT_FUNC_TRACE();
4249 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4251 /* Setup the Base and Length of the Tx Descriptor Rings */
4252 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4253 txq = dev->data->tx_queues[i];
4254 bus_addr = txq->tx_ring_phys_addr;
4255 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4256 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4257 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4258 (uint32_t)(bus_addr >> 32));
4259 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4260 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4261 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4262 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4263 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4266 * Disable Tx Head Writeback RO bit, since this hoses
4267 * bookkeeping if things aren't delivered in order.
4269 txctrl = IXGBE_READ_REG(hw,
4270 IXGBE_VFDCA_TXCTRL(i));
4271 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4272 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4278 * [VF] Start Transmit and Receive Units.
4281 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4283 struct ixgbe_hw *hw;
4284 struct ixgbe_tx_queue *txq;
4285 struct ixgbe_rx_queue *rxq;
4291 PMD_INIT_FUNC_TRACE();
4292 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4294 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4295 txq = dev->data->tx_queues[i];
4296 /* Setup Transmit Threshold Registers */
4297 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4298 txdctl |= txq->pthresh & 0x7F;
4299 txdctl |= ((txq->hthresh & 0x7F) << 8);
4300 txdctl |= ((txq->wthresh & 0x7F) << 16);
4301 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4304 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4306 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4307 txdctl |= IXGBE_TXDCTL_ENABLE;
4308 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4311 /* Wait until TX Enable ready */
4314 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4315 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4317 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
4319 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4321 rxq = dev->data->rx_queues[i];
4323 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4324 rxdctl |= IXGBE_RXDCTL_ENABLE;
4325 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4327 /* Wait until RX Enable ready */
4331 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4332 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4334 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
4336 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
4341 /* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */
4342 int __attribute__((weak))
4343 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
4348 uint16_t __attribute__((weak))
4349 ixgbe_recv_pkts_vec(
4350 void __rte_unused *rx_queue,
4351 struct rte_mbuf __rte_unused **rx_pkts,
4352 uint16_t __rte_unused nb_pkts)
4357 uint16_t __attribute__((weak))
4358 ixgbe_recv_scattered_pkts_vec(
4359 void __rte_unused *rx_queue,
4360 struct rte_mbuf __rte_unused **rx_pkts,
4361 uint16_t __rte_unused nb_pkts)
4366 int __attribute__((weak))
4367 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)