4 * Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
46 #include <rte_byteorder.h>
47 #include <rte_common.h>
48 #include <rte_cycles.h>
50 #include <rte_debug.h>
51 #include <rte_interrupts.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_launch.h>
56 #include <rte_tailq.h>
58 #include <rte_per_lcore.h>
59 #include <rte_lcore.h>
60 #include <rte_atomic.h>
61 #include <rte_branch_prediction.h>
63 #include <rte_mempool.h>
64 #include <rte_malloc.h>
66 #include <rte_ether.h>
67 #include <rte_ethdev.h>
68 #include <rte_prefetch.h>
72 #include <rte_string_fns.h>
73 #include <rte_errno.h>
75 #include "ixgbe_logs.h"
76 #include "ixgbe/ixgbe_api.h"
77 #include "ixgbe/ixgbe_vf.h"
78 #include "ixgbe_ethdev.h"
79 #include "ixgbe/ixgbe_dcb.h"
82 #define RTE_PMD_IXGBE_TX_MAX_BURST 32
84 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
85 #define RTE_PMD_IXGBE_RX_MAX_BURST 32
88 static inline struct rte_mbuf *
89 rte_rxmbuf_alloc(struct rte_mempool *mp)
93 m = __rte_mbuf_raw_alloc(mp);
94 __rte_mbuf_sanity_check_raw(m, RTE_MBUF_PKT, 0);
98 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
99 (uint64_t) ((mb)->buf_physaddr + (uint64_t)((char *)((mb)->pkt.data) - \
100 (char *)(mb)->buf_addr))
102 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
103 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
106 * Structure associated with each descriptor of the RX ring of a RX queue.
108 struct igb_rx_entry {
109 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
113 * Structure associated with each descriptor of the TX ring of a TX queue.
115 struct igb_tx_entry {
116 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
117 uint16_t next_id; /**< Index of next descriptor in ring. */
118 uint16_t last_id; /**< Index of last scattered descriptor. */
122 * Structure associated with each RX queue.
124 struct igb_rx_queue {
125 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
126 volatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
127 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
128 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
129 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
130 struct igb_rx_entry *sw_ring; /**< address of RX software ring. */
131 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
132 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
133 uint16_t nb_rx_desc; /**< number of RX descriptors. */
134 uint16_t rx_tail; /**< current value of RDT register. */
135 uint16_t nb_rx_hold; /**< number of held free RX desc. */
136 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
137 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
138 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
139 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
141 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
142 uint16_t queue_id; /**< RX queue index. */
143 uint16_t reg_idx; /**< RX queue register index. */
144 uint8_t port_id; /**< Device port identifier. */
145 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
146 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
147 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
148 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */
149 struct rte_mbuf fake_mbuf;
150 /** hold packets to return to application */
151 struct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2];
156 * IXGBE CTX Constants
158 enum ixgbe_advctx_num {
159 IXGBE_CTX_0 = 0, /**< CTX0 */
160 IXGBE_CTX_1 = 1, /**< CTX1 */
161 IXGBE_CTX_NUM = 2, /**< CTX NUMBER */
165 * Structure to check if new context need be built
168 struct ixgbe_advctx_info {
169 uint16_t flags; /**< ol_flags for context build. */
170 uint32_t cmp_mask; /**< compare mask for vlan_macip_lens */
171 union rte_vlan_macip vlan_macip_lens; /**< vlan, mac ip length. */
175 * Structure associated with each TX queue.
177 struct igb_tx_queue {
178 /** TX ring virtual address. */
179 volatile union ixgbe_adv_tx_desc *tx_ring;
180 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
181 struct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */
182 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
183 uint16_t nb_tx_desc; /**< number of TX descriptors. */
184 uint16_t tx_tail; /**< current value of TDT reg. */
185 uint16_t tx_free_thresh;/**< minimum TX before freeing. */
186 /** Number of TX descriptors to use before RS bit is set. */
187 uint16_t tx_rs_thresh;
188 /** Number of TX descriptors used since RS bit was set. */
190 /** Index to last TX descriptor to have been cleaned. */
191 uint16_t last_desc_cleaned;
192 /** Total number of TX descriptors ready to be allocated. */
194 uint16_t tx_next_dd; /**< next desc to scan for DD bit */
195 uint16_t tx_next_rs; /**< next desc to set RS bit */
196 uint16_t queue_id; /**< TX queue index. */
197 uint16_t reg_idx; /**< TX queue register index. */
198 uint8_t port_id; /**< Device port identifier. */
199 uint8_t pthresh; /**< Prefetch threshold register. */
200 uint8_t hthresh; /**< Host threshold register. */
201 uint8_t wthresh; /**< Write-back threshold reg. */
202 uint32_t txq_flags; /**< Holds flags for this TXq */
203 uint32_t ctx_curr; /**< Hardware context states. */
204 /** Hardware context0 history. */
205 struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM];
210 #define RTE_PMD_USE_PREFETCH
213 #ifdef RTE_PMD_USE_PREFETCH
215 * Prefetch a cache line into all cache levels.
217 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
219 #define rte_ixgbe_prefetch(p) do {} while(0)
222 #ifdef RTE_PMD_PACKET_PREFETCH
223 #define rte_packet_prefetch(p) rte_prefetch1(p)
225 #define rte_packet_prefetch(p) do {} while(0)
228 /*********************************************************************
232 **********************************************************************/
235 * The "simple" TX queue functions require that the following
236 * flags are set when the TX queue is configured:
237 * - ETH_TXQ_FLAGS_NOMULTSEGS
238 * - ETH_TXQ_FLAGS_NOVLANOFFL
239 * - ETH_TXQ_FLAGS_NOXSUMSCTP
240 * - ETH_TXQ_FLAGS_NOXSUMUDP
241 * - ETH_TXQ_FLAGS_NOXSUMTCP
242 * and that the RS bit threshold (tx_rs_thresh) is at least equal to
243 * RTE_PMD_IXGBE_TX_MAX_BURST.
245 #define IXGBE_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
246 ETH_TXQ_FLAGS_NOOFFLOADS)
249 * Check for descriptors with their DD bit set and free mbufs.
250 * Return the total number of buffers freed.
252 static inline int __attribute__((always_inline))
253 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
255 struct igb_tx_entry *txep;
259 /* check DD bit on threshold descriptor */
260 status = txq->tx_ring[txq->tx_next_dd].wb.status;
261 if (! (status & IXGBE_ADVTXD_STAT_DD))
265 * first buffer to free from S/W ring is at index
266 * tx_next_dd - (tx_rs_thresh-1)
268 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
270 /* prefetch the mbufs that are about to be freed */
271 for (i = 0; i < txq->tx_rs_thresh; ++i)
272 rte_prefetch0((txep + i)->mbuf);
274 /* free buffers one at a time */
275 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
276 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
277 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
281 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
282 rte_pktmbuf_free_seg(txep->mbuf);
287 /* buffers were freed, update counters */
288 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
289 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
290 if (txq->tx_next_dd >= txq->nb_tx_desc)
291 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
293 return txq->tx_rs_thresh;
297 * Populate descriptors with the following info:
298 * 1.) buffer_addr = phys_addr + headroom
299 * 2.) cmd_type_len = DCMD_DTYP_FLAGS | pkt_len
300 * 3.) olinfo_status = pkt_len << PAYLEN_SHIFT
303 /* Defines for Tx descriptor */
304 #define DCMD_DTYP_FLAGS (IXGBE_ADVTXD_DTYP_DATA |\
305 IXGBE_ADVTXD_DCMD_IFCS |\
306 IXGBE_ADVTXD_DCMD_DEXT |\
307 IXGBE_ADVTXD_DCMD_EOP)
309 /* Populate 4 descriptors with data from 4 mbufs */
311 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
313 uint64_t buf_dma_addr;
317 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
318 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
319 pkt_len = (*pkts)->pkt.data_len;
321 /* write data to descriptor */
322 txdp->read.buffer_addr = buf_dma_addr;
323 txdp->read.cmd_type_len =
324 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
325 txdp->read.olinfo_status =
326 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
330 /* Populate 1 descriptor with data from 1 mbuf */
332 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
334 uint64_t buf_dma_addr;
337 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
338 pkt_len = (*pkts)->pkt.data_len;
340 /* write data to descriptor */
341 txdp->read.buffer_addr = buf_dma_addr;
342 txdp->read.cmd_type_len =
343 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
344 txdp->read.olinfo_status =
345 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
349 * Fill H/W descriptor ring with mbuf data.
350 * Copy mbuf pointers to the S/W ring.
353 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
356 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
357 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
358 const int N_PER_LOOP = 4;
359 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
360 int mainpart, leftover;
364 * Process most of the packets in chunks of N pkts. Any
365 * leftover packets will get processed one at a time.
367 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
368 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
369 for (i = 0; i < mainpart; i += N_PER_LOOP) {
370 /* Copy N mbuf pointers to the S/W ring */
371 for (j = 0; j < N_PER_LOOP; ++j) {
372 (txep + i + j)->mbuf = *(pkts + i + j);
374 tx4(txdp + i, pkts + i);
377 if (unlikely(leftover > 0)) {
378 for (i = 0; i < leftover; ++i) {
379 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
380 tx1(txdp + mainpart + i, pkts + mainpart + i);
385 static inline uint16_t
386 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
389 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
390 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
394 * Begin scanning the H/W ring for done descriptors when the
395 * number of available descriptors drops below tx_free_thresh. For
396 * each done descriptor, free the associated buffer.
398 if (txq->nb_tx_free < txq->tx_free_thresh)
399 ixgbe_tx_free_bufs(txq);
401 /* Only use descriptors that are available */
402 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
403 if (unlikely(nb_pkts == 0))
406 /* Use exactly nb_pkts descriptors */
407 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
410 * At this point, we know there are enough descriptors in the
411 * ring to transmit all the packets. This assumes that each
412 * mbuf contains a single segment, and that no new offloads
413 * are expected, which would require a new context descriptor.
417 * See if we're going to wrap-around. If so, handle the top
418 * of the descriptor ring first, then do the bottom. If not,
419 * the processing looks just like the "bottom" part anyway...
421 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
422 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
423 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
426 * We know that the last descriptor in the ring will need to
427 * have its RS bit set because tx_rs_thresh has to be
428 * a divisor of the ring size
430 tx_r[txq->tx_next_rs].read.cmd_type_len |=
431 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
432 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
437 /* Fill H/W descriptor ring with mbuf data */
438 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
439 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
442 * Determine if RS bit should be set
443 * This is what we actually want:
444 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
445 * but instead of subtracting 1 and doing >=, we can just do
446 * greater than without subtracting.
448 if (txq->tx_tail > txq->tx_next_rs) {
449 tx_r[txq->tx_next_rs].read.cmd_type_len |=
450 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
451 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
453 if (txq->tx_next_rs >= txq->nb_tx_desc)
454 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
458 * Check for wrap-around. This would only happen if we used
459 * up to the last descriptor in the ring, no more, no less.
461 if (txq->tx_tail >= txq->nb_tx_desc)
464 /* update tail pointer */
466 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
472 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
477 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
478 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
479 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
481 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
485 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
486 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
487 nb_tx = (uint16_t)(nb_tx + ret);
488 nb_pkts = (uint16_t)(nb_pkts - ret);
497 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
498 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
499 uint16_t ol_flags, uint32_t vlan_macip_lens)
501 uint32_t type_tucmd_mlhl;
502 uint32_t mss_l4len_idx;
506 ctx_idx = txq->ctx_curr;
510 if (ol_flags & PKT_TX_VLAN_PKT) {
511 cmp_mask |= TX_VLAN_CMP_MASK;
514 if (ol_flags & PKT_TX_IP_CKSUM) {
515 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
516 cmp_mask |= TX_MAC_LEN_CMP_MASK;
519 /* Specify which HW CTX to upload. */
520 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
521 switch (ol_flags & PKT_TX_L4_MASK) {
522 case PKT_TX_UDP_CKSUM:
523 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
524 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
525 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
526 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
528 case PKT_TX_TCP_CKSUM:
529 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
530 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
531 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
532 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
534 case PKT_TX_SCTP_CKSUM:
535 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
536 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
537 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
538 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
541 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
542 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
546 txq->ctx_cache[ctx_idx].flags = ol_flags;
547 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
548 txq->ctx_cache[ctx_idx].vlan_macip_lens.data =
549 vlan_macip_lens & cmp_mask;
551 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
552 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
553 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
554 ctx_txd->seqnum_seed = 0;
558 * Check which hardware context can be used. Use the existing match
559 * or create a new context descriptor.
561 static inline uint32_t
562 what_advctx_update(struct igb_tx_queue *txq, uint16_t flags,
563 uint32_t vlan_macip_lens)
565 /* If match with the current used context */
566 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
567 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
568 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
569 return txq->ctx_curr;
572 /* What if match with the next context */
574 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
575 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
576 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
577 return txq->ctx_curr;
580 /* Mismatch, use the previous context */
581 return (IXGBE_CTX_NUM);
584 static inline uint32_t
585 tx_desc_cksum_flags_to_olinfo(uint16_t ol_flags)
587 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
588 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
591 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
592 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
596 static inline uint32_t
597 tx_desc_vlan_flags_to_cmdtype(uint16_t ol_flags)
599 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
600 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
603 /* Default RS bit threshold values */
604 #ifndef DEFAULT_TX_RS_THRESH
605 #define DEFAULT_TX_RS_THRESH 32
607 #ifndef DEFAULT_TX_FREE_THRESH
608 #define DEFAULT_TX_FREE_THRESH 32
611 /* Reset transmit descriptors after they have been used */
613 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
615 struct igb_tx_entry *sw_ring = txq->sw_ring;
616 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
617 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
618 uint16_t nb_tx_desc = txq->nb_tx_desc;
619 uint16_t desc_to_clean_to;
620 uint16_t nb_tx_to_clean;
622 /* Determine the last descriptor needing to be cleaned */
623 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
624 if (desc_to_clean_to >= nb_tx_desc)
625 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
627 /* Check to make sure the last descriptor to clean is done */
628 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
629 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
631 PMD_TX_FREE_LOG(DEBUG,
632 "TX descriptor %4u is not done"
633 "(port=%d queue=%d)",
635 txq->port_id, txq->queue_id);
636 /* Failed to clean any descriptors, better luck next time */
640 /* Figure out how many descriptors will be cleaned */
641 if (last_desc_cleaned > desc_to_clean_to)
642 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
645 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
648 PMD_TX_FREE_LOG(DEBUG,
649 "Cleaning %4u TX descriptors: %4u to %4u "
650 "(port=%d queue=%d)",
651 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
652 txq->port_id, txq->queue_id);
655 * The last descriptor to clean is done, so that means all the
656 * descriptors from the last descriptor that was cleaned
657 * up to the last descriptor with the RS bit set
658 * are done. Only reset the threshold descriptor.
660 txr[desc_to_clean_to].wb.status = 0;
662 /* Update the txq to reflect the last descriptor that was cleaned */
663 txq->last_desc_cleaned = desc_to_clean_to;
664 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
671 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
674 struct igb_tx_queue *txq;
675 struct igb_tx_entry *sw_ring;
676 struct igb_tx_entry *txe, *txn;
677 volatile union ixgbe_adv_tx_desc *txr;
678 volatile union ixgbe_adv_tx_desc *txd;
679 struct rte_mbuf *tx_pkt;
680 struct rte_mbuf *m_seg;
681 uint64_t buf_dma_addr;
682 uint32_t olinfo_status;
683 uint32_t cmd_type_len;
692 uint32_t vlan_macip_lens;
697 sw_ring = txq->sw_ring;
699 tx_id = txq->tx_tail;
700 txe = &sw_ring[tx_id];
702 /* Determine if the descriptor ring needs to be cleaned. */
703 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
704 ixgbe_xmit_cleanup(txq);
708 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
711 pkt_len = tx_pkt->pkt.pkt_len;
713 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
716 * Determine how many (if any) context descriptors
717 * are needed for offload functionality.
719 ol_flags = tx_pkt->ol_flags;
720 vlan_macip_lens = tx_pkt->pkt.vlan_macip.data;
722 /* If hardware offload required */
723 tx_ol_req = (uint16_t)(ol_flags & PKT_TX_OFFLOAD_MASK);
725 /* If new context need be built or reuse the exist ctx. */
726 ctx = what_advctx_update(txq, tx_ol_req,
728 /* Only allocate context descriptor if required*/
729 new_ctx = (ctx == IXGBE_CTX_NUM);
734 * Keep track of how many descriptors are used this loop
735 * This will always be the number of segments + the number of
736 * Context descriptors required to transmit the packet
738 nb_used = (uint16_t)(tx_pkt->pkt.nb_segs + new_ctx);
741 * The number of descriptors that must be allocated for a
742 * packet is the number of segments of that packet, plus 1
743 * Context Descriptor for the hardware offload, if any.
744 * Determine the last TX descriptor to allocate in the TX ring
745 * for the packet, starting from the current position (tx_id)
748 tx_last = (uint16_t) (tx_id + nb_used - 1);
751 if (tx_last >= txq->nb_tx_desc)
752 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
754 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
755 " tx_first=%u tx_last=%u\n",
756 (unsigned) txq->port_id,
757 (unsigned) txq->queue_id,
763 * Make sure there are enough TX descriptors available to
764 * transmit the entire packet.
765 * nb_used better be less than or equal to txq->tx_rs_thresh
767 if (nb_used > txq->nb_tx_free) {
768 PMD_TX_FREE_LOG(DEBUG,
769 "Not enough free TX descriptors "
770 "nb_used=%4u nb_free=%4u "
771 "(port=%d queue=%d)",
772 nb_used, txq->nb_tx_free,
773 txq->port_id, txq->queue_id);
775 if (ixgbe_xmit_cleanup(txq) != 0) {
776 /* Could not clean any descriptors */
782 /* nb_used better be <= txq->tx_rs_thresh */
783 if (unlikely(nb_used > txq->tx_rs_thresh)) {
784 PMD_TX_FREE_LOG(DEBUG,
785 "The number of descriptors needed to "
786 "transmit the packet exceeds the "
787 "RS bit threshold. This will impact "
789 "nb_used=%4u nb_free=%4u "
791 "(port=%d queue=%d)",
792 nb_used, txq->nb_tx_free,
794 txq->port_id, txq->queue_id);
796 * Loop here until there are enough TX
797 * descriptors or until the ring cannot be
800 while (nb_used > txq->nb_tx_free) {
801 if (ixgbe_xmit_cleanup(txq) != 0) {
803 * Could not clean any
815 * By now there are enough free TX descriptors to transmit
820 * Set common flags of all TX Data Descriptors.
822 * The following bits must be set in all Data Descriptors:
823 * - IXGBE_ADVTXD_DTYP_DATA
824 * - IXGBE_ADVTXD_DCMD_DEXT
826 * The following bits must be set in the first Data Descriptor
827 * and are ignored in the other ones:
828 * - IXGBE_ADVTXD_DCMD_IFCS
829 * - IXGBE_ADVTXD_MAC_1588
830 * - IXGBE_ADVTXD_DCMD_VLE
832 * The following bits must only be set in the last Data
834 * - IXGBE_TXD_CMD_EOP
836 * The following bits can be set in any Data Descriptor, but
837 * are only set in the last Data Descriptor:
840 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
841 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
842 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
843 #ifdef RTE_LIBRTE_IEEE1588
844 if (ol_flags & PKT_TX_IEEE1588_TMST)
845 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
850 * Setup the TX Advanced Context Descriptor if required
853 volatile struct ixgbe_adv_tx_context_desc *
856 ctx_txd = (volatile struct
857 ixgbe_adv_tx_context_desc *)
860 txn = &sw_ring[txe->next_id];
861 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
863 if (txe->mbuf != NULL) {
864 rte_pktmbuf_free_seg(txe->mbuf);
868 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
871 txe->last_id = tx_last;
872 tx_id = txe->next_id;
877 * Setup the TX Advanced Data Descriptor,
878 * This path will go through
879 * whatever new/reuse the context descriptor
881 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
882 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
883 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
889 txn = &sw_ring[txe->next_id];
891 if (txe->mbuf != NULL)
892 rte_pktmbuf_free_seg(txe->mbuf);
896 * Set up Transmit Data Descriptor.
898 slen = m_seg->pkt.data_len;
899 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
900 txd->read.buffer_addr =
901 rte_cpu_to_le_64(buf_dma_addr);
902 txd->read.cmd_type_len =
903 rte_cpu_to_le_32(cmd_type_len | slen);
904 txd->read.olinfo_status =
905 rte_cpu_to_le_32(olinfo_status);
906 txe->last_id = tx_last;
907 tx_id = txe->next_id;
909 m_seg = m_seg->pkt.next;
910 } while (m_seg != NULL);
913 * The last packet data descriptor needs End Of Packet (EOP)
915 cmd_type_len |= IXGBE_TXD_CMD_EOP;
916 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
917 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
919 /* Set RS bit only on threshold packets' last descriptor */
920 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
921 PMD_TX_FREE_LOG(DEBUG,
922 "Setting RS bit on TXD id="
923 "%4u (port=%d queue=%d)",
924 tx_last, txq->port_id, txq->queue_id);
926 cmd_type_len |= IXGBE_TXD_CMD_RS;
928 /* Update txq RS bit counters */
931 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
937 * Set the Transmit Descriptor Tail (TDT)
939 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
940 (unsigned) txq->port_id, (unsigned) txq->queue_id,
941 (unsigned) tx_id, (unsigned) nb_tx);
942 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
943 txq->tx_tail = tx_id;
948 /*********************************************************************
952 **********************************************************************/
953 static inline uint16_t
954 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
958 static uint16_t ip_pkt_types_map[16] = {
959 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
960 PKT_RX_IPV6_HDR, 0, 0, 0,
961 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
962 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
965 static uint16_t ip_rss_types_map[16] = {
966 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
967 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
968 PKT_RX_RSS_HASH, 0, 0, 0,
969 0, 0, 0, PKT_RX_FDIR,
972 #ifdef RTE_LIBRTE_IEEE1588
973 static uint32_t ip_pkt_etqf_map[8] = {
974 0, 0, 0, PKT_RX_IEEE1588_PTP,
978 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
979 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
980 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
982 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
983 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
986 return (uint16_t)(pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF]);
989 static inline uint16_t
990 rx_desc_status_to_pkt_flags(uint32_t rx_status)
995 * Check if VLAN present only.
996 * Do not check whether L3/L4 rx checksum done by NIC or not,
997 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
999 pkt_flags = (uint16_t)((rx_status & IXGBE_RXD_STAT_VP) ?
1000 PKT_RX_VLAN_PKT : 0);
1002 #ifdef RTE_LIBRTE_IEEE1588
1003 if (rx_status & IXGBE_RXD_STAT_TMST)
1004 pkt_flags = (uint16_t)(pkt_flags | PKT_RX_IEEE1588_TMST);
1009 static inline uint16_t
1010 rx_desc_error_to_pkt_flags(uint32_t rx_status)
1013 * Bit 31: IPE, IPv4 checksum error
1014 * Bit 30: L4I, L4I integrity error
1016 static uint16_t error_to_pkt_flags_map[4] = {
1017 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
1018 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1020 return error_to_pkt_flags_map[(rx_status >>
1021 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1024 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1026 * LOOK_AHEAD defines how many desc statuses to check beyond the
1027 * current descriptor.
1028 * It must be a pound define for optimal performance.
1029 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1030 * function only works with LOOK_AHEAD=8.
1032 #define LOOK_AHEAD 8
1033 #if (LOOK_AHEAD != 8)
1034 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1037 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
1039 volatile union ixgbe_adv_rx_desc *rxdp;
1040 struct igb_rx_entry *rxep;
1041 struct rte_mbuf *mb;
1043 int s[LOOK_AHEAD], nb_dd;
1044 int i, j, nb_rx = 0;
1047 /* get references to current descriptor and S/W ring entry */
1048 rxdp = &rxq->rx_ring[rxq->rx_tail];
1049 rxep = &rxq->sw_ring[rxq->rx_tail];
1051 /* check to make sure there is at least 1 packet to receive */
1052 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
1056 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1057 * reference packets that are ready to be received.
1059 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1060 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
1062 /* Read desc statuses backwards to avoid race condition */
1063 for (j = LOOK_AHEAD-1; j >= 0; --j)
1064 s[j] = rxdp[j].wb.upper.status_error;
1066 /* Clear everything but the status bits (LSB) */
1067 for (j = 0; j < LOOK_AHEAD; ++j)
1068 s[j] &= IXGBE_RXDADV_STAT_DD;
1070 /* Compute how many status bits were set */
1071 nb_dd = s[0]+s[1]+s[2]+s[3]+s[4]+s[5]+s[6]+s[7];
1074 /* Translate descriptor info to mbuf format */
1075 for (j = 0; j < nb_dd; ++j) {
1077 pkt_len = (uint16_t)(rxdp[j].wb.upper.length -
1079 mb->pkt.data_len = pkt_len;
1080 mb->pkt.pkt_len = pkt_len;
1081 mb->pkt.vlan_macip.f.vlan_tci = rxdp[j].wb.upper.vlan;
1082 mb->pkt.hash.rss = rxdp[j].wb.lower.hi_dword.rss;
1084 /* convert descriptor fields to rte mbuf flags */
1085 mb->ol_flags = rx_desc_hlen_type_rss_to_pkt_flags(
1086 rxdp[j].wb.lower.lo_dword.data);
1087 /* reuse status field from scan list */
1088 mb->ol_flags = (uint16_t)(mb->ol_flags |
1089 rx_desc_status_to_pkt_flags(s[j]));
1090 mb->ol_flags = (uint16_t)(mb->ol_flags |
1091 rx_desc_error_to_pkt_flags(s[j]));
1094 /* Move mbuf pointers from the S/W ring to the stage */
1095 for (j = 0; j < LOOK_AHEAD; ++j) {
1096 rxq->rx_stage[i + j] = rxep[j].mbuf;
1099 /* stop if all requested packets could not be received */
1100 if (nb_dd != LOOK_AHEAD)
1104 /* clear software ring entries so we can cleanup correctly */
1105 for (i = 0; i < nb_rx; ++i) {
1106 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1114 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
1116 volatile union ixgbe_adv_rx_desc *rxdp;
1117 struct igb_rx_entry *rxep;
1118 struct rte_mbuf *mb;
1123 /* allocate buffers in bulk directly into the S/W ring */
1124 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1125 (rxq->rx_free_thresh - 1));
1126 rxep = &rxq->sw_ring[alloc_idx];
1127 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1128 rxq->rx_free_thresh);
1129 if (unlikely(diag != 0))
1132 rxdp = &rxq->rx_ring[alloc_idx];
1133 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1134 /* populate the static rte mbuf fields */
1136 rte_mbuf_refcnt_set(mb, 1);
1137 mb->type = RTE_MBUF_PKT;
1138 mb->pkt.next = NULL;
1139 mb->pkt.data = (char *)mb->buf_addr + RTE_PKTMBUF_HEADROOM;
1140 mb->pkt.nb_segs = 1;
1141 mb->pkt.in_port = rxq->port_id;
1143 /* populate the descriptors */
1144 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1145 rxdp[i].read.hdr_addr = dma_addr;
1146 rxdp[i].read.pkt_addr = dma_addr;
1149 /* update tail pointer */
1151 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1153 /* update state of internal queue structure */
1154 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1155 rxq->rx_free_thresh);
1156 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1157 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1163 static inline uint16_t
1164 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1167 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1170 /* how many packets are ready to return? */
1171 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1173 /* copy mbuf pointers to the application's packet list */
1174 for (i = 0; i < nb_pkts; ++i)
1175 rx_pkts[i] = stage[i];
1177 /* update internal queue state */
1178 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1179 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1184 static inline uint16_t
1185 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1188 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1191 /* Any previously recv'd pkts will be returned from the Rx stage */
1192 if (rxq->rx_nb_avail)
1193 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1195 /* Scan the H/W ring for packets to receive */
1196 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1198 /* update internal queue state */
1199 rxq->rx_next_avail = 0;
1200 rxq->rx_nb_avail = nb_rx;
1201 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1203 /* if required, allocate new buffers to replenish descriptors */
1204 if (rxq->rx_tail > rxq->rx_free_trigger) {
1205 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1207 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1208 "queue_id=%u\n", (unsigned) rxq->port_id,
1209 (unsigned) rxq->queue_id);
1211 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1212 rxq->rx_free_thresh;
1215 * Need to rewind any previous receives if we cannot
1216 * allocate new buffers to replenish the old ones.
1218 rxq->rx_nb_avail = 0;
1219 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1220 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1221 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1227 if (rxq->rx_tail >= rxq->nb_rx_desc)
1230 /* received any packets this loop? */
1231 if (rxq->rx_nb_avail)
1232 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1237 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1239 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1244 if (unlikely(nb_pkts == 0))
1247 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1248 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1250 /* request is relatively large, chunk it up */
1254 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1255 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1256 nb_rx = (uint16_t)(nb_rx + ret);
1257 nb_pkts = (uint16_t)(nb_pkts - ret);
1264 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1267 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1270 struct igb_rx_queue *rxq;
1271 volatile union ixgbe_adv_rx_desc *rx_ring;
1272 volatile union ixgbe_adv_rx_desc *rxdp;
1273 struct igb_rx_entry *sw_ring;
1274 struct igb_rx_entry *rxe;
1275 struct rte_mbuf *rxm;
1276 struct rte_mbuf *nmb;
1277 union ixgbe_adv_rx_desc rxd;
1280 uint32_t hlen_type_rss;
1290 rx_id = rxq->rx_tail;
1291 rx_ring = rxq->rx_ring;
1292 sw_ring = rxq->sw_ring;
1293 while (nb_rx < nb_pkts) {
1295 * The order of operations here is important as the DD status
1296 * bit must not be read after any other descriptor fields.
1297 * rx_ring and rxdp are pointing to volatile data so the order
1298 * of accesses cannot be reordered by the compiler. If they were
1299 * not volatile, they could be reordered which could lead to
1300 * using invalid descriptor fields when read from rxd.
1302 rxdp = &rx_ring[rx_id];
1303 staterr = rxdp->wb.upper.status_error;
1304 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1311 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1312 * is likely to be invalid and to be dropped by the various
1313 * validation checks performed by the network stack.
1315 * Allocate a new mbuf to replenish the RX ring descriptor.
1316 * If the allocation fails:
1317 * - arrange for that RX descriptor to be the first one
1318 * being parsed the next time the receive function is
1319 * invoked [on the same queue].
1321 * - Stop parsing the RX ring and return immediately.
1323 * This policy do not drop the packet received in the RX
1324 * descriptor for which the allocation of a new mbuf failed.
1325 * Thus, it allows that packet to be later retrieved if
1326 * mbuf have been freed in the mean time.
1327 * As a side effect, holding RX descriptors instead of
1328 * systematically giving them back to the NIC may lead to
1329 * RX ring exhaustion situations.
1330 * However, the NIC can gracefully prevent such situations
1331 * to happen by sending specific "back-pressure" flow control
1332 * frames to its peer(s).
1334 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1335 "ext_err_stat=0x%08x pkt_len=%u\n",
1336 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1337 (unsigned) rx_id, (unsigned) staterr,
1338 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1340 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1342 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1343 "queue_id=%u\n", (unsigned) rxq->port_id,
1344 (unsigned) rxq->queue_id);
1345 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1350 rxe = &sw_ring[rx_id];
1352 if (rx_id == rxq->nb_rx_desc)
1355 /* Prefetch next mbuf while processing current one. */
1356 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1359 * When next RX descriptor is on a cache-line boundary,
1360 * prefetch the next 4 RX descriptors and the next 8 pointers
1363 if ((rx_id & 0x3) == 0) {
1364 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1365 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1371 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1372 rxdp->read.hdr_addr = dma_addr;
1373 rxdp->read.pkt_addr = dma_addr;
1376 * Initialize the returned mbuf.
1377 * 1) setup generic mbuf fields:
1378 * - number of segments,
1381 * - RX port identifier.
1382 * 2) integrate hardware offload data, if any:
1383 * - RSS flag & hash,
1384 * - IP checksum flag,
1385 * - VLAN TCI, if any,
1388 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1390 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1391 rte_packet_prefetch(rxm->pkt.data);
1392 rxm->pkt.nb_segs = 1;
1393 rxm->pkt.next = NULL;
1394 rxm->pkt.pkt_len = pkt_len;
1395 rxm->pkt.data_len = pkt_len;
1396 rxm->pkt.in_port = rxq->port_id;
1398 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1399 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1400 rxm->pkt.vlan_macip.f.vlan_tci =
1401 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1403 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1404 pkt_flags = (uint16_t)(pkt_flags |
1405 rx_desc_status_to_pkt_flags(staterr));
1406 pkt_flags = (uint16_t)(pkt_flags |
1407 rx_desc_error_to_pkt_flags(staterr));
1408 rxm->ol_flags = pkt_flags;
1410 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1411 rxm->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1412 else if (pkt_flags & PKT_RX_FDIR) {
1413 rxm->pkt.hash.fdir.hash =
1414 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1415 & IXGBE_ATR_HASH_MASK);
1416 rxm->pkt.hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1419 * Store the mbuf address into the next entry of the array
1420 * of returned packets.
1422 rx_pkts[nb_rx++] = rxm;
1424 rxq->rx_tail = rx_id;
1427 * If the number of free RX descriptors is greater than the RX free
1428 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1430 * Update the RDT with the value of the last processed RX descriptor
1431 * minus 1, to guarantee that the RDT register is never equal to the
1432 * RDH register, which creates a "full" ring situtation from the
1433 * hardware point of view...
1435 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1436 if (nb_hold > rxq->rx_free_thresh) {
1437 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1438 "nb_hold=%u nb_rx=%u\n",
1439 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1440 (unsigned) rx_id, (unsigned) nb_hold,
1442 rx_id = (uint16_t) ((rx_id == 0) ?
1443 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1444 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1447 rxq->nb_rx_hold = nb_hold;
1452 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1455 struct igb_rx_queue *rxq;
1456 volatile union ixgbe_adv_rx_desc *rx_ring;
1457 volatile union ixgbe_adv_rx_desc *rxdp;
1458 struct igb_rx_entry *sw_ring;
1459 struct igb_rx_entry *rxe;
1460 struct rte_mbuf *first_seg;
1461 struct rte_mbuf *last_seg;
1462 struct rte_mbuf *rxm;
1463 struct rte_mbuf *nmb;
1464 union ixgbe_adv_rx_desc rxd;
1465 uint64_t dma; /* Physical address of mbuf data buffer */
1467 uint32_t hlen_type_rss;
1477 rx_id = rxq->rx_tail;
1478 rx_ring = rxq->rx_ring;
1479 sw_ring = rxq->sw_ring;
1482 * Retrieve RX context of current packet, if any.
1484 first_seg = rxq->pkt_first_seg;
1485 last_seg = rxq->pkt_last_seg;
1487 while (nb_rx < nb_pkts) {
1490 * The order of operations here is important as the DD status
1491 * bit must not be read after any other descriptor fields.
1492 * rx_ring and rxdp are pointing to volatile data so the order
1493 * of accesses cannot be reordered by the compiler. If they were
1494 * not volatile, they could be reordered which could lead to
1495 * using invalid descriptor fields when read from rxd.
1497 rxdp = &rx_ring[rx_id];
1498 staterr = rxdp->wb.upper.status_error;
1499 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1506 * Allocate a new mbuf to replenish the RX ring descriptor.
1507 * If the allocation fails:
1508 * - arrange for that RX descriptor to be the first one
1509 * being parsed the next time the receive function is
1510 * invoked [on the same queue].
1512 * - Stop parsing the RX ring and return immediately.
1514 * This policy does not drop the packet received in the RX
1515 * descriptor for which the allocation of a new mbuf failed.
1516 * Thus, it allows that packet to be later retrieved if
1517 * mbuf have been freed in the mean time.
1518 * As a side effect, holding RX descriptors instead of
1519 * systematically giving them back to the NIC may lead to
1520 * RX ring exhaustion situations.
1521 * However, the NIC can gracefully prevent such situations
1522 * to happen by sending specific "back-pressure" flow control
1523 * frames to its peer(s).
1525 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
1526 "staterr=0x%x data_len=%u\n",
1527 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1528 (unsigned) rx_id, (unsigned) staterr,
1529 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1531 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1533 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1534 "queue_id=%u\n", (unsigned) rxq->port_id,
1535 (unsigned) rxq->queue_id);
1536 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1541 rxe = &sw_ring[rx_id];
1543 if (rx_id == rxq->nb_rx_desc)
1546 /* Prefetch next mbuf while processing current one. */
1547 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1550 * When next RX descriptor is on a cache-line boundary,
1551 * prefetch the next 4 RX descriptors and the next 8 pointers
1554 if ((rx_id & 0x3) == 0) {
1555 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1556 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1560 * Update RX descriptor with the physical address of the new
1561 * data buffer of the new allocated mbuf.
1565 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1566 rxdp->read.hdr_addr = dma;
1567 rxdp->read.pkt_addr = dma;
1570 * Set data length & data buffer address of mbuf.
1572 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1573 rxm->pkt.data_len = data_len;
1574 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1577 * If this is the first buffer of the received packet,
1578 * set the pointer to the first mbuf of the packet and
1579 * initialize its context.
1580 * Otherwise, update the total length and the number of segments
1581 * of the current scattered packet, and update the pointer to
1582 * the last mbuf of the current packet.
1584 if (first_seg == NULL) {
1586 first_seg->pkt.pkt_len = data_len;
1587 first_seg->pkt.nb_segs = 1;
1589 first_seg->pkt.pkt_len = (uint16_t)(first_seg->pkt.pkt_len
1591 first_seg->pkt.nb_segs++;
1592 last_seg->pkt.next = rxm;
1596 * If this is not the last buffer of the received packet,
1597 * update the pointer to the last mbuf of the current scattered
1598 * packet and continue to parse the RX ring.
1600 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1606 * This is the last buffer of the received packet.
1607 * If the CRC is not stripped by the hardware:
1608 * - Subtract the CRC length from the total packet length.
1609 * - If the last buffer only contains the whole CRC or a part
1610 * of it, free the mbuf associated to the last buffer.
1611 * If part of the CRC is also contained in the previous
1612 * mbuf, subtract the length of that CRC part from the
1613 * data length of the previous mbuf.
1615 rxm->pkt.next = NULL;
1616 if (unlikely(rxq->crc_len > 0)) {
1617 first_seg->pkt.pkt_len -= ETHER_CRC_LEN;
1618 if (data_len <= ETHER_CRC_LEN) {
1619 rte_pktmbuf_free_seg(rxm);
1620 first_seg->pkt.nb_segs--;
1621 last_seg->pkt.data_len = (uint16_t)
1622 (last_seg->pkt.data_len -
1623 (ETHER_CRC_LEN - data_len));
1624 last_seg->pkt.next = NULL;
1627 (uint16_t) (data_len - ETHER_CRC_LEN);
1631 * Initialize the first mbuf of the returned packet:
1632 * - RX port identifier,
1633 * - hardware offload data, if any:
1634 * - RSS flag & hash,
1635 * - IP checksum flag,
1636 * - VLAN TCI, if any,
1639 first_seg->pkt.in_port = rxq->port_id;
1642 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1643 * set in the pkt_flags field.
1645 first_seg->pkt.vlan_macip.f.vlan_tci =
1646 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1647 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1648 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1649 pkt_flags = (uint16_t)(pkt_flags |
1650 rx_desc_status_to_pkt_flags(staterr));
1651 pkt_flags = (uint16_t)(pkt_flags |
1652 rx_desc_error_to_pkt_flags(staterr));
1653 first_seg->ol_flags = pkt_flags;
1655 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1656 first_seg->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1657 else if (pkt_flags & PKT_RX_FDIR) {
1658 first_seg->pkt.hash.fdir.hash =
1659 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1660 & IXGBE_ATR_HASH_MASK);
1661 first_seg->pkt.hash.fdir.id =
1662 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1665 /* Prefetch data of first segment, if configured to do so. */
1666 rte_packet_prefetch(first_seg->pkt.data);
1669 * Store the mbuf address into the next entry of the array
1670 * of returned packets.
1672 rx_pkts[nb_rx++] = first_seg;
1675 * Setup receipt context for a new packet.
1681 * Record index of the next RX descriptor to probe.
1683 rxq->rx_tail = rx_id;
1686 * Save receive context.
1688 rxq->pkt_first_seg = first_seg;
1689 rxq->pkt_last_seg = last_seg;
1692 * If the number of free RX descriptors is greater than the RX free
1693 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1695 * Update the RDT with the value of the last processed RX descriptor
1696 * minus 1, to guarantee that the RDT register is never equal to the
1697 * RDH register, which creates a "full" ring situtation from the
1698 * hardware point of view...
1700 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1701 if (nb_hold > rxq->rx_free_thresh) {
1702 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1703 "nb_hold=%u nb_rx=%u\n",
1704 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1705 (unsigned) rx_id, (unsigned) nb_hold,
1707 rx_id = (uint16_t) ((rx_id == 0) ?
1708 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1709 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1712 rxq->nb_rx_hold = nb_hold;
1716 /*********************************************************************
1718 * Queue management functions
1720 **********************************************************************/
1723 * Rings setup and release.
1725 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1726 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1727 * also optimize cache line size effect. H/W supports up to cache line size 128.
1729 #define IXGBE_ALIGN 128
1732 * Maximum number of Ring Descriptors.
1734 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1735 * descriptors should meet the following condition:
1736 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1738 #define IXGBE_MIN_RING_DESC 64
1739 #define IXGBE_MAX_RING_DESC 4096
1742 * Create memzone for HW rings. malloc can't be used as the physical address is
1743 * needed. If the memzone is already created, then this function returns a ptr
1746 static const struct rte_memzone *
1747 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1748 uint16_t queue_id, uint32_t ring_size, int socket_id)
1750 char z_name[RTE_MEMZONE_NAMESIZE];
1751 const struct rte_memzone *mz;
1753 rte_snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1754 dev->driver->pci_drv.name, ring_name,
1755 dev->data->port_id, queue_id);
1757 mz = rte_memzone_lookup(z_name);
1761 return rte_memzone_reserve_aligned(z_name, ring_size,
1762 socket_id, 0, IXGBE_ALIGN);
1766 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1770 if (txq->sw_ring != NULL) {
1771 for (i = 0; i < txq->nb_tx_desc; i++) {
1772 if (txq->sw_ring[i].mbuf != NULL) {
1773 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1774 txq->sw_ring[i].mbuf = NULL;
1781 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1784 ixgbe_tx_queue_release_mbufs(txq);
1785 rte_free(txq->sw_ring);
1791 ixgbe_dev_tx_queue_release(void *txq)
1793 ixgbe_tx_queue_release(txq);
1796 /* (Re)set dynamic igb_tx_queue fields to defaults */
1798 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1800 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1802 struct igb_tx_entry *txe = txq->sw_ring;
1805 /* Zero out HW ring memory */
1806 for (i = 0; i < txq->nb_tx_desc; i++) {
1807 txq->tx_ring[i] = zeroed_desc;
1810 /* Initialize SW ring entries */
1811 prev = (uint16_t) (txq->nb_tx_desc - 1);
1812 for (i = 0; i < txq->nb_tx_desc; i++) {
1813 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1814 txd->wb.status = IXGBE_TXD_STAT_DD;
1817 txe[prev].next_id = i;
1821 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1822 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1825 txq->nb_tx_used = 0;
1827 * Always allow 1 descriptor to be un-allocated to avoid
1828 * a H/W race condition
1830 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1831 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1833 memset((void*)&txq->ctx_cache, 0,
1834 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1838 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1841 unsigned int socket_id,
1842 const struct rte_eth_txconf *tx_conf)
1844 const struct rte_memzone *tz;
1845 struct igb_tx_queue *txq;
1846 struct ixgbe_hw *hw;
1847 uint16_t tx_rs_thresh, tx_free_thresh;
1849 PMD_INIT_FUNC_TRACE();
1850 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853 * Validate number of transmit descriptors.
1854 * It must not exceed hardware maximum, and must be multiple
1857 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1858 (nb_desc > IXGBE_MAX_RING_DESC) ||
1859 (nb_desc < IXGBE_MIN_RING_DESC)) {
1864 * The following two parameters control the setting of the RS bit on
1865 * transmit descriptors.
1866 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1867 * descriptors have been used.
1868 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1869 * descriptors are used or if the number of descriptors required
1870 * to transmit a packet is greater than the number of free TX
1872 * The following constraints must be satisfied:
1873 * tx_rs_thresh must be greater than 0.
1874 * tx_rs_thresh must be less than the size of the ring minus 2.
1875 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1876 * tx_rs_thresh must be a divisor of the ring size.
1877 * tx_free_thresh must be greater than 0.
1878 * tx_free_thresh must be less than the size of the ring minus 3.
1879 * One descriptor in the TX ring is used as a sentinel to avoid a
1880 * H/W race condition, hence the maximum threshold constraints.
1881 * When set to zero use default values.
1883 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1884 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1885 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1886 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1887 if (tx_rs_thresh >= (nb_desc - 2)) {
1888 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the number "
1889 "of TX descriptors minus 2. (tx_rs_thresh=%u port=%d "
1890 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1891 (int)dev->data->port_id, (int)queue_idx);
1894 if (tx_free_thresh >= (nb_desc - 3)) {
1895 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the "
1896 "tx_free_thresh must be less than the number of TX "
1897 "descriptors minus 3. (tx_free_thresh=%u port=%d "
1898 "queue=%d)\n", (unsigned int)tx_free_thresh,
1899 (int)dev->data->port_id, (int)queue_idx);
1902 if (tx_rs_thresh > tx_free_thresh) {
1903 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than or equal to "
1904 "tx_free_thresh. (tx_free_thresh=%u tx_rs_thresh=%u "
1905 "port=%d queue=%d)\n", (unsigned int)tx_free_thresh,
1906 (unsigned int)tx_rs_thresh, (int)dev->data->port_id,
1910 if ((nb_desc % tx_rs_thresh) != 0) {
1911 RTE_LOG(ERR, PMD, "tx_rs_thresh must be a divisor of the "
1912 "number of TX descriptors. (tx_rs_thresh=%u port=%d "
1913 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1914 (int)dev->data->port_id, (int)queue_idx);
1919 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1920 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1921 * by the NIC and all descriptors are written back after the NIC
1922 * accumulates WTHRESH descriptors.
1924 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1925 RTE_LOG(ERR, PMD, "TX WTHRESH must be set to 0 if "
1926 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1927 "port=%d queue=%d)\n", (unsigned int)tx_rs_thresh,
1928 (int)dev->data->port_id, (int)queue_idx);
1932 /* Free memory prior to re-allocation if needed... */
1933 if (dev->data->tx_queues[queue_idx] != NULL)
1934 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1936 /* First allocate the tx queue data structure */
1937 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct igb_tx_queue),
1938 CACHE_LINE_SIZE, socket_id);
1943 * Allocate TX ring hardware descriptors. A memzone large enough to
1944 * handle the maximum ring size is allocated in order to allow for
1945 * resizing in later calls to the queue setup function.
1947 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1948 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1951 ixgbe_tx_queue_release(txq);
1955 txq->nb_tx_desc = nb_desc;
1956 txq->tx_rs_thresh = tx_rs_thresh;
1957 txq->tx_free_thresh = tx_free_thresh;
1958 txq->pthresh = tx_conf->tx_thresh.pthresh;
1959 txq->hthresh = tx_conf->tx_thresh.hthresh;
1960 txq->wthresh = tx_conf->tx_thresh.wthresh;
1961 txq->queue_id = queue_idx;
1962 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1963 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1964 txq->port_id = dev->data->port_id;
1965 txq->txq_flags = tx_conf->txq_flags;
1968 * Modification to set VFTDT for virtual function if vf is detected
1970 if (hw->mac.type == ixgbe_mac_82599_vf)
1971 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1973 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1975 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1976 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1978 /* Allocate software ring */
1979 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1980 sizeof(struct igb_tx_entry) * nb_desc,
1981 CACHE_LINE_SIZE, socket_id);
1982 if (txq->sw_ring == NULL) {
1983 ixgbe_tx_queue_release(txq);
1986 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1987 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1989 ixgbe_reset_tx_queue(txq);
1991 dev->data->tx_queues[queue_idx] = txq;
1993 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1994 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
1995 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1996 PMD_INIT_LOG(INFO, "Using simple tx code path\n");
1997 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1999 PMD_INIT_LOG(INFO, "Using full-featured tx code path\n");
2000 PMD_INIT_LOG(INFO, " - txq_flags = %lx [IXGBE_SIMPLE_FLAGS=%lx]\n", (long unsigned)txq->txq_flags, (long unsigned)IXGBE_SIMPLE_FLAGS);
2001 PMD_INIT_LOG(INFO, " - tx_rs_thresh = %lu [RTE_PMD_IXGBE_TX_MAX_BURST=%lu]\n", (long unsigned)txq->tx_rs_thresh, (long unsigned)RTE_PMD_IXGBE_TX_MAX_BURST);
2002 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2009 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
2013 if (rxq->sw_ring != NULL) {
2014 for (i = 0; i < rxq->nb_rx_desc; i++) {
2015 if (rxq->sw_ring[i].mbuf != NULL) {
2016 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2017 rxq->sw_ring[i].mbuf = NULL;
2020 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2021 if (rxq->rx_nb_avail) {
2022 for (i = 0; i < rxq->rx_nb_avail; ++i) {
2023 struct rte_mbuf *mb;
2024 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2025 rte_pktmbuf_free_seg(mb);
2027 rxq->rx_nb_avail = 0;
2034 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
2037 ixgbe_rx_queue_release_mbufs(rxq);
2038 rte_free(rxq->sw_ring);
2044 ixgbe_dev_rx_queue_release(void *rxq)
2046 ixgbe_rx_queue_release(rxq);
2050 * Check if Rx Burst Bulk Alloc function can be used.
2052 * 0: the preconditions are satisfied and the bulk allocation function
2054 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2055 * function must be used.
2058 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2059 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
2061 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct igb_rx_queue *rxq)
2067 * Make sure the following pre-conditions are satisfied:
2068 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2069 * rxq->rx_free_thresh < rxq->nb_rx_desc
2070 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2071 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2072 * Scattered packets are not supported. This should be checked
2073 * outside of this function.
2075 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2076 if (! (rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST))
2078 else if (! (rxq->rx_free_thresh < rxq->nb_rx_desc))
2080 else if (! ((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0))
2082 else if (! (rxq->nb_rx_desc <
2083 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST)))
2092 /* Reset dynamic igb_rx_queue fields back to defaults */
2094 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
2096 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
2102 * By default, the Rx queue setup function allocates enough memory for
2103 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2104 * extra memory at the end of the descriptor ring to be zero'd out. A
2105 * pre-condition for using the Rx burst bulk alloc function is that the
2106 * number of descriptors is less than or equal to
2107 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2108 * constraints here to see if we need to zero out memory after the end
2109 * of the H/W descriptor ring.
2111 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2112 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2113 /* zero out extra memory */
2114 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2117 /* do not zero out extra memory */
2118 len = rxq->nb_rx_desc;
2121 * Zero out HW ring memory. Zero out extra memory at the end of
2122 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2123 * reads extra memory as zeros.
2125 for (i = 0; i < len; i++) {
2126 rxq->rx_ring[i] = zeroed_desc;
2129 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2131 * initialize extra software ring entries. Space for these extra
2132 * entries is always allocated
2134 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2135 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2136 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2139 rxq->rx_nb_avail = 0;
2140 rxq->rx_next_avail = 0;
2141 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2142 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2144 rxq->nb_rx_hold = 0;
2145 rxq->pkt_first_seg = NULL;
2146 rxq->pkt_last_seg = NULL;
2150 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2153 unsigned int socket_id,
2154 const struct rte_eth_rxconf *rx_conf,
2155 struct rte_mempool *mp)
2157 const struct rte_memzone *rz;
2158 struct igb_rx_queue *rxq;
2159 struct ixgbe_hw *hw;
2160 int use_def_burst_func = 1;
2163 PMD_INIT_FUNC_TRACE();
2164 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2167 * Validate number of receive descriptors.
2168 * It must not exceed hardware maximum, and must be multiple
2171 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2172 (nb_desc > IXGBE_MAX_RING_DESC) ||
2173 (nb_desc < IXGBE_MIN_RING_DESC)) {
2177 /* Free memory prior to re-allocation if needed... */
2178 if (dev->data->rx_queues[queue_idx] != NULL)
2179 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2181 /* First allocate the rx queue data structure */
2182 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct igb_rx_queue),
2183 CACHE_LINE_SIZE, socket_id);
2187 rxq->nb_rx_desc = nb_desc;
2188 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2189 rxq->queue_id = queue_idx;
2190 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2191 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2192 rxq->port_id = dev->data->port_id;
2193 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2195 rxq->drop_en = rx_conf->rx_drop_en;
2198 * Allocate RX ring hardware descriptors. A memzone large enough to
2199 * handle the maximum ring size is allocated in order to allow for
2200 * resizing in later calls to the queue setup function.
2202 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2203 IXGBE_MAX_RING_DESC * sizeof(union ixgbe_adv_rx_desc),
2206 ixgbe_rx_queue_release(rxq);
2210 * Modified to setup VFRDT for Virtual Function
2212 if (hw->mac.type == ixgbe_mac_82599_vf) {
2214 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2216 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2220 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2222 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2225 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2226 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2229 * Allocate software ring. Allow for space at the end of the
2230 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2231 * function does not access an invalid memory region.
2233 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2234 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2238 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2239 sizeof(struct igb_rx_entry) * len,
2240 CACHE_LINE_SIZE, socket_id);
2241 if (rxq->sw_ring == NULL) {
2242 ixgbe_rx_queue_release(rxq);
2245 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
2246 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2249 * Certain constaints must be met in order to use the bulk buffer
2250 * allocation Rx burst function.
2252 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2254 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2255 if (!use_def_burst_func && !dev->data->scattered_rx) {
2256 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2257 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2258 "satisfied. Rx Burst Bulk Alloc function will be "
2259 "used on port=%d, queue=%d.\n",
2260 rxq->port_id, rxq->queue_id);
2261 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2264 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2265 "are not satisfied, Scattered Rx is requested, "
2266 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2267 "enabled (port=%d, queue=%d).\n",
2268 rxq->port_id, rxq->queue_id);
2270 dev->data->rx_queues[queue_idx] = rxq;
2272 ixgbe_reset_rx_queue(rxq);
2278 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2280 #define IXGBE_RXQ_SCAN_INTERVAL 4
2281 volatile union ixgbe_adv_rx_desc *rxdp;
2282 struct igb_rx_queue *rxq;
2285 if (rx_queue_id >= dev->data->nb_rx_queues) {
2286 PMD_RX_LOG(ERR, "Invalid RX queue id=%d\n", rx_queue_id);
2290 rxq = dev->data->rx_queues[rx_queue_id];
2291 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2293 while ((desc < rxq->nb_rx_desc) &&
2294 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2295 desc += IXGBE_RXQ_SCAN_INTERVAL;
2296 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2297 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2298 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2299 desc - rxq->nb_rx_desc]);
2306 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2308 volatile union ixgbe_adv_rx_desc *rxdp;
2309 struct igb_rx_queue *rxq = rx_queue;
2312 if (unlikely(offset >= rxq->nb_rx_desc))
2314 desc = rxq->rx_tail + offset;
2315 if (desc >= rxq->nb_rx_desc)
2316 desc -= rxq->nb_rx_desc;
2318 rxdp = &rxq->rx_ring[desc];
2319 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2323 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2327 PMD_INIT_FUNC_TRACE();
2329 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2330 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2332 ixgbe_tx_queue_release_mbufs(txq);
2333 ixgbe_reset_tx_queue(txq);
2337 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2338 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2340 ixgbe_rx_queue_release_mbufs(rxq);
2341 ixgbe_reset_rx_queue(rxq);
2346 /*********************************************************************
2348 * Device RX/TX init functions
2350 **********************************************************************/
2353 * Receive Side Scaling (RSS)
2354 * See section 7.1.2.8 in the following document:
2355 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2358 * The source and destination IP addresses of the IP header and the source
2359 * and destination ports of TCP/UDP headers, if any, of received packets are
2360 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2361 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2362 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2363 * RSS output index which is used as the RX queue index where to store the
2365 * The following output is supplied in the RX write-back descriptor:
2366 * - 32-bit result of the Microsoft RSS hash function,
2367 * - 4-bit RSS type field.
2371 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2372 * Used as the default key.
2374 static uint8_t rss_intel_key[40] = {
2375 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2376 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2377 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2378 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2379 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2383 ixgbe_rss_disable(struct rte_eth_dev *dev)
2385 struct ixgbe_hw *hw;
2388 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2390 mrqc &= ~IXGBE_MRQC_RSSEN;
2391 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2395 ixgbe_rss_configure(struct rte_eth_dev *dev)
2397 struct ixgbe_hw *hw;
2406 PMD_INIT_FUNC_TRACE();
2407 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2409 rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
2410 if (rss_hf == 0) { /* Disable RSS */
2411 ixgbe_rss_disable(dev);
2414 hash_key = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key;
2415 if (hash_key == NULL)
2416 hash_key = rss_intel_key; /* Default hash key */
2418 /* Fill in RSS hash key */
2419 for (i = 0; i < 10; i++) {
2420 rss_key = hash_key[(i * 4)];
2421 rss_key |= hash_key[(i * 4) + 1] << 8;
2422 rss_key |= hash_key[(i * 4) + 2] << 16;
2423 rss_key |= hash_key[(i * 4) + 3] << 24;
2424 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2427 /* Fill in redirection table */
2429 for (i = 0, j = 0; i < 128; i++, j++) {
2430 if (j == dev->data->nb_rx_queues) j = 0;
2431 reta = (reta << 8) | j;
2433 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), rte_bswap32(reta));
2436 /* Set configured hashing functions in MRQC register */
2437 mrqc = IXGBE_MRQC_RSSEN; /* RSS enable */
2438 if (rss_hf & ETH_RSS_IPV4)
2439 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2440 if (rss_hf & ETH_RSS_IPV4_TCP)
2441 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2442 if (rss_hf & ETH_RSS_IPV6)
2443 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2444 if (rss_hf & ETH_RSS_IPV6_EX)
2445 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2446 if (rss_hf & ETH_RSS_IPV6_TCP)
2447 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2448 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2449 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2450 if (rss_hf & ETH_RSS_IPV4_UDP)
2451 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2452 if (rss_hf & ETH_RSS_IPV6_UDP)
2453 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2454 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2455 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2456 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2459 #define NUM_VFTA_REGISTERS 128
2460 #define NIC_RX_BUFFER_SIZE 0x200
2463 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2465 struct rte_eth_vmdq_dcb_conf *cfg;
2466 struct ixgbe_hw *hw;
2467 enum rte_eth_nb_pools num_pools;
2468 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2470 uint8_t nb_tcs; /* number of traffic classes */
2473 PMD_INIT_FUNC_TRACE();
2474 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2475 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2476 num_pools = cfg->nb_queue_pools;
2477 /* Check we have a valid number of pools */
2478 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2479 ixgbe_rss_disable(dev);
2482 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2483 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2487 * split rx buffer up into sections, each for 1 traffic class
2489 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2490 for (i = 0 ; i < nb_tcs; i++) {
2491 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2492 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2493 /* clear 10 bits. */
2494 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2495 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2497 /* zero alloc all unused TCs */
2498 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2499 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2500 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2501 /* clear 10 bits. */
2502 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2505 /* MRQC: enable vmdq and dcb */
2506 mrqc = ((num_pools == ETH_16_POOLS) ? \
2507 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2508 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2510 /* PFVTCTL: turn on virtualisation and set the default pool */
2511 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2512 if (cfg->enable_default_pool) {
2513 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2515 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2518 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2520 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2522 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2524 * mapping is done with 3 bits per priority,
2525 * so shift by i*3 each time
2527 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2529 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2531 /* RTRPCS: DCB related */
2532 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2534 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2535 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2536 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2537 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2539 /* VFTA - enable all vlan filters */
2540 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2541 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2544 /* VFRE: pool enabling for receive - 16 or 32 */
2545 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2546 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2549 * MPSAR - allow pools to read specific mac addresses
2550 * In this case, all pools should be able to read from mac addr 0
2552 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2553 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2555 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2556 for (i = 0; i < cfg->nb_pool_maps; i++) {
2557 /* set vlan id in VF register and set the valid bit */
2558 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2559 (cfg->pool_map[i].vlan_id & 0xFFF)));
2561 * Put the allowed pools in VFB reg. As we only have 16 or 32
2562 * pools, we only need to use the first half of the register
2565 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2570 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2571 * @hw: pointer to hardware structure
2572 * @dcb_config: pointer to ixgbe_dcb_config structure
2575 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2576 struct ixgbe_dcb_config *dcb_config)
2581 PMD_INIT_FUNC_TRACE();
2582 if (hw->mac.type != ixgbe_mac_82598EB) {
2583 /* Disable the Tx desc arbiter so that MTQC can be changed */
2584 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2585 reg |= IXGBE_RTTDCS_ARBDIS;
2586 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2588 /* Enable DCB for Tx with 8 TCs */
2589 if (dcb_config->num_tcs.pg_tcs == 8) {
2590 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2593 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2595 if (dcb_config->vt_mode)
2596 reg |= IXGBE_MTQC_VT_ENA;
2597 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2599 /* Disable drop for all queues */
2600 for (q = 0; q < 128; q++)
2601 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2602 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2604 /* Enable the Tx desc arbiter */
2605 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2606 reg &= ~IXGBE_RTTDCS_ARBDIS;
2607 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2609 /* Enable Security TX Buffer IFG for DCB */
2610 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2611 reg |= IXGBE_SECTX_DCB;
2612 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2618 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2619 * @dev: pointer to rte_eth_dev structure
2620 * @dcb_config: pointer to ixgbe_dcb_config structure
2623 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2624 struct ixgbe_dcb_config *dcb_config)
2626 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2627 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2628 struct ixgbe_hw *hw =
2629 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2631 PMD_INIT_FUNC_TRACE();
2632 if (hw->mac.type != ixgbe_mac_82598EB)
2633 /*PF VF Transmit Enable*/
2634 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2635 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2637 /*Configure general DCB TX parameters*/
2638 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2643 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2644 struct ixgbe_dcb_config *dcb_config)
2646 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2647 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2648 struct ixgbe_dcb_tc_config *tc;
2651 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2652 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2653 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2654 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2657 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2658 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2660 /* User Priority to Traffic Class mapping */
2661 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2662 j = vmdq_rx_conf->dcb_queue[i];
2663 tc = &dcb_config->tc_config[j];
2664 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2670 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2671 struct ixgbe_dcb_config *dcb_config)
2673 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2674 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2675 struct ixgbe_dcb_tc_config *tc;
2678 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2679 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2680 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2681 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2684 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2685 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2688 /* User Priority to Traffic Class mapping */
2689 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2690 j = vmdq_tx_conf->dcb_queue[i];
2691 tc = &dcb_config->tc_config[j];
2692 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2699 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2700 struct ixgbe_dcb_config *dcb_config)
2702 struct rte_eth_dcb_rx_conf *rx_conf =
2703 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2704 struct ixgbe_dcb_tc_config *tc;
2707 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2708 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2710 /* User Priority to Traffic Class mapping */
2711 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2712 j = rx_conf->dcb_queue[i];
2713 tc = &dcb_config->tc_config[j];
2714 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2720 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2721 struct ixgbe_dcb_config *dcb_config)
2723 struct rte_eth_dcb_tx_conf *tx_conf =
2724 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2725 struct ixgbe_dcb_tc_config *tc;
2728 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2729 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2731 /* User Priority to Traffic Class mapping */
2732 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2733 j = tx_conf->dcb_queue[i];
2734 tc = &dcb_config->tc_config[j];
2735 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2741 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2742 * @hw: pointer to hardware structure
2743 * @dcb_config: pointer to ixgbe_dcb_config structure
2746 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2747 struct ixgbe_dcb_config *dcb_config)
2753 PMD_INIT_FUNC_TRACE();
2755 * Disable the arbiter before changing parameters
2756 * (always enable recycle mode; WSP)
2758 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2759 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2761 if (hw->mac.type != ixgbe_mac_82598EB) {
2762 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2763 if (dcb_config->num_tcs.pg_tcs == 4) {
2764 if (dcb_config->vt_mode)
2765 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2766 IXGBE_MRQC_VMDQRT4TCEN;
2768 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2769 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2773 if (dcb_config->num_tcs.pg_tcs == 8) {
2774 if (dcb_config->vt_mode)
2775 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2776 IXGBE_MRQC_VMDQRT8TCEN;
2778 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2779 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2784 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2787 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2788 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2789 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2790 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2792 /* VFTA - enable all vlan filters */
2793 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2794 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2798 * Configure Rx packet plane (recycle mode; WSP) and
2801 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2802 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2808 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2809 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2811 switch (hw->mac.type) {
2812 case ixgbe_mac_82598EB:
2813 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2815 case ixgbe_mac_82599EB:
2816 case ixgbe_mac_X540:
2817 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2826 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2827 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2829 switch (hw->mac.type) {
2830 case ixgbe_mac_82598EB:
2831 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2832 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2834 case ixgbe_mac_82599EB:
2835 case ixgbe_mac_X540:
2836 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2837 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2844 #define DCB_RX_CONFIG 1
2845 #define DCB_TX_CONFIG 1
2846 #define DCB_TX_PB 1024
2848 * ixgbe_dcb_hw_configure - Enable DCB and configure
2849 * general DCB in VT mode and non-VT mode parameters
2850 * @dev: pointer to rte_eth_dev structure
2851 * @dcb_config: pointer to ixgbe_dcb_config structure
2854 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2855 struct ixgbe_dcb_config *dcb_config)
2858 uint8_t i,pfc_en,nb_tcs;
2860 uint8_t config_dcb_rx = 0;
2861 uint8_t config_dcb_tx = 0;
2862 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2863 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2864 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2865 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2866 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2867 struct ixgbe_dcb_tc_config *tc;
2868 uint32_t max_frame = dev->data->max_frame_size;
2869 struct ixgbe_hw *hw =
2870 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2872 switch(dev->data->dev_conf.rxmode.mq_mode){
2873 case ETH_MQ_RX_VMDQ_DCB:
2874 dcb_config->vt_mode = true;
2875 if (hw->mac.type != ixgbe_mac_82598EB) {
2876 config_dcb_rx = DCB_RX_CONFIG;
2878 *get dcb and VT rx configuration parameters
2881 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2882 /*Configure general VMDQ and DCB RX parameters*/
2883 ixgbe_vmdq_dcb_configure(dev);
2887 dcb_config->vt_mode = false;
2888 config_dcb_rx = DCB_RX_CONFIG;
2889 /* Get dcb TX configuration parameters from rte_eth_conf */
2890 ixgbe_dcb_rx_config(dev,dcb_config);
2891 /*Configure general DCB RX parameters*/
2892 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2895 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration\n");
2898 switch (dev->data->dev_conf.txmode.mq_mode) {
2899 case ETH_MQ_TX_VMDQ_DCB:
2900 dcb_config->vt_mode = true;
2901 config_dcb_tx = DCB_TX_CONFIG;
2902 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2903 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2904 /*Configure general VMDQ and DCB TX parameters*/
2905 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2909 dcb_config->vt_mode = false;
2910 config_dcb_tx = DCB_TX_CONFIG;
2911 /*get DCB TX configuration parameters from rte_eth_conf*/
2912 ixgbe_dcb_tx_config(dev,dcb_config);
2913 /*Configure general DCB TX parameters*/
2914 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2917 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration\n");
2921 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2923 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2924 if(nb_tcs == ETH_4_TCS) {
2925 /* Avoid un-configured priority mapping to TC0 */
2927 uint8_t mask = 0xFF;
2928 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
2929 mask = (uint8_t)(mask & (~ (1 << map[i])));
2930 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
2931 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
2935 /* Re-configure 4 TCs BW */
2936 for (i = 0; i < nb_tcs; i++) {
2937 tc = &dcb_config->tc_config[i];
2938 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
2939 (uint8_t)(100 / nb_tcs);
2940 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
2941 (uint8_t)(100 / nb_tcs);
2943 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2944 tc = &dcb_config->tc_config[i];
2945 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
2946 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
2951 /* Set RX buffer size */
2952 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2953 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
2954 for (i = 0 ; i < nb_tcs; i++) {
2955 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2957 /* zero alloc all unused TCs */
2958 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2959 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
2963 /* Only support an equally distributed Tx packet buffer strategy. */
2964 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
2965 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
2966 for (i = 0; i < nb_tcs; i++) {
2967 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
2968 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
2970 /* Clear unused TCs, if any, to zero buffer size*/
2971 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2972 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
2973 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
2977 /*Calculates traffic class credits*/
2978 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2979 IXGBE_DCB_TX_CONFIG);
2980 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2981 IXGBE_DCB_RX_CONFIG);
2984 /* Unpack CEE standard containers */
2985 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
2986 ixgbe_dcb_unpack_max_cee(dcb_config, max);
2987 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
2988 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
2989 /* Configure PG(ETS) RX */
2990 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
2994 /* Unpack CEE standard containers */
2995 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
2996 ixgbe_dcb_unpack_max_cee(dcb_config, max);
2997 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
2998 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
2999 /* Configure PG(ETS) TX */
3000 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3003 /*Configure queue statistics registers*/
3004 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3006 /* Check if the PFC is supported */
3007 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3008 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3009 for (i = 0; i < nb_tcs; i++) {
3011 * If the TC count is 8,and the default high_water is 48,
3012 * the low_water is 16 as default.
3014 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3015 hw->fc.low_water[i] = pbsize / 4;
3016 /* Enable pfc for this TC */
3017 tc = &dcb_config->tc_config[i];
3018 tc->pfc = ixgbe_dcb_pfc_enabled;
3020 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3021 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3023 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3030 * ixgbe_configure_dcb - Configure DCB Hardware
3031 * @dev: pointer to rte_eth_dev
3033 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3035 struct ixgbe_dcb_config *dcb_cfg =
3036 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3037 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3039 PMD_INIT_FUNC_TRACE();
3041 /* check support mq_mode for DCB */
3042 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3043 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3046 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3049 /** Configure DCB hardware **/
3050 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3056 * VMDq only support for 10 GbE NIC.
3059 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3061 struct rte_eth_vmdq_rx_conf *cfg;
3062 struct ixgbe_hw *hw;
3063 enum rte_eth_nb_pools num_pools;
3064 uint32_t mrqc, vt_ctl, vlanctrl;
3067 PMD_INIT_FUNC_TRACE();
3068 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3069 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3070 num_pools = cfg->nb_queue_pools;
3072 ixgbe_rss_disable(dev);
3074 /* MRQC: enable vmdq */
3075 mrqc = IXGBE_MRQC_VMDQEN;
3076 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3078 /* PFVTCTL: turn on virtualisation and set the default pool */
3079 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3080 if (cfg->enable_default_pool)
3081 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3083 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3085 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3087 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3088 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3089 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3090 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3092 /* VFTA - enable all vlan filters */
3093 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3094 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3096 /* VFRE: pool enabling for receive - 64 */
3097 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3098 if (num_pools == ETH_64_POOLS)
3099 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3102 * MPSAR - allow pools to read specific mac addresses
3103 * In this case, all pools should be able to read from mac addr 0
3105 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3106 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3108 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3109 for (i = 0; i < cfg->nb_pool_maps; i++) {
3110 /* set vlan id in VF register and set the valid bit */
3111 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3112 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3114 * Put the allowed pools in VFB reg. As we only have 16 or 64
3115 * pools, we only need to use the first half of the register
3118 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3119 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3120 (cfg->pool_map[i].pools & UINT32_MAX));
3122 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3123 ((cfg->pool_map[i].pools >> 32) \
3128 IXGBE_WRITE_FLUSH(hw);
3132 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3133 * @hw: pointer to hardware structure
3136 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3141 PMD_INIT_FUNC_TRACE();
3142 /*PF VF Transmit Enable*/
3143 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3144 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3146 /* Disable the Tx desc arbiter so that MTQC can be changed */
3147 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3148 reg |= IXGBE_RTTDCS_ARBDIS;
3149 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3151 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3152 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3154 /* Disable drop for all queues */
3155 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3156 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3157 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3159 /* Enable the Tx desc arbiter */
3160 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3161 reg &= ~IXGBE_RTTDCS_ARBDIS;
3162 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3164 IXGBE_WRITE_FLUSH(hw);
3170 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
3172 struct igb_rx_entry *rxe = rxq->sw_ring;
3176 /* Initialize software ring entries */
3177 for (i = 0; i < rxq->nb_rx_desc; i++) {
3178 volatile union ixgbe_adv_rx_desc *rxd;
3179 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3181 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u\n",
3182 (unsigned) rxq->queue_id);
3186 rte_mbuf_refcnt_set(mbuf, 1);
3187 mbuf->type = RTE_MBUF_PKT;
3188 mbuf->pkt.next = NULL;
3189 mbuf->pkt.data = (char *)mbuf->buf_addr + RTE_PKTMBUF_HEADROOM;
3190 mbuf->pkt.nb_segs = 1;
3191 mbuf->pkt.in_port = rxq->port_id;
3194 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3195 rxd = &rxq->rx_ring[i];
3196 rxd->read.hdr_addr = dma_addr;
3197 rxd->read.pkt_addr = dma_addr;
3205 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3207 struct ixgbe_hw *hw =
3208 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3210 if (hw->mac.type == ixgbe_mac_82598EB)
3213 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3215 * SRIOV inactive scheme
3216 * any DCB/RSS w/o VMDq multi-queue setting
3218 if (dev->data->nb_rx_queues > 1)
3219 switch (dev->data->dev_conf.rxmode.mq_mode) {
3220 case ETH_MQ_RX_NONE:
3221 /* if mq_mode not assign, we use rss mode.*/
3223 ixgbe_rss_configure(dev);
3226 case ETH_MQ_RX_VMDQ_DCB:
3227 ixgbe_vmdq_dcb_configure(dev);
3230 case ETH_MQ_RX_VMDQ_ONLY:
3231 ixgbe_vmdq_rx_hw_configure(dev);
3234 default: ixgbe_rss_disable(dev);
3237 ixgbe_rss_disable(dev);
3239 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3241 * SRIOV active scheme
3242 * FIXME if support DCB/RSS together with VMDq & SRIOV
3245 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQEN);
3249 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT4TCEN);
3253 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT8TCEN);
3256 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3264 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3266 struct ixgbe_hw *hw =
3267 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3271 if (hw->mac.type == ixgbe_mac_82598EB)
3274 /* disable arbiter before setting MTQC */
3275 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3276 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3277 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3279 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3281 * SRIOV inactive scheme
3282 * any DCB w/o VMDq multi-queue setting
3284 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3285 ixgbe_vmdq_tx_hw_configure(hw);
3287 mtqc = IXGBE_MTQC_64Q_1PB;
3288 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3291 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3294 * SRIOV active scheme
3295 * FIXME if support DCB together with VMDq & SRIOV
3298 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3301 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3304 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3308 mtqc = IXGBE_MTQC_64Q_1PB;
3309 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3311 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3314 /* re-enable arbiter */
3315 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3316 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3322 * Initializes Receive Unit.
3325 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3327 struct ixgbe_hw *hw;
3328 struct igb_rx_queue *rxq;
3329 struct rte_pktmbuf_pool_private *mbp_priv;
3342 PMD_INIT_FUNC_TRACE();
3343 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3346 * Make sure receives are disabled while setting
3347 * up the RX context (registers, descriptor rings, etc.).
3349 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3350 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3352 /* Enable receipt of broadcasted frames */
3353 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3354 fctrl |= IXGBE_FCTRL_BAM;
3355 fctrl |= IXGBE_FCTRL_DPF;
3356 fctrl |= IXGBE_FCTRL_PMCF;
3357 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3360 * Configure CRC stripping, if any.
3362 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3363 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3364 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3366 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3369 * Configure jumbo frame support, if any.
3371 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3372 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3373 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3374 maxfrs &= 0x0000FFFF;
3375 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3376 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3378 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3380 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3382 /* Setup RX queues */
3383 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3384 rxq = dev->data->rx_queues[i];
3386 /* Allocate buffers for descriptor rings */
3387 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3392 * Reset crc_len in case it was changed after queue setup by a
3393 * call to configure.
3395 rxq->crc_len = (uint8_t)
3396 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3399 /* Setup the Base and Length of the Rx Descriptor Rings */
3400 bus_addr = rxq->rx_ring_phys_addr;
3401 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3402 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3403 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3404 (uint32_t)(bus_addr >> 32));
3405 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3406 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3407 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3408 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3410 /* Configure the SRRCTL register */
3411 #ifdef RTE_HEADER_SPLIT_ENABLE
3413 * Configure Header Split
3415 if (dev->data->dev_conf.rxmode.header_split) {
3416 if (hw->mac.type == ixgbe_mac_82599EB) {
3417 /* Must setup the PSRTYPE register */
3419 psrtype = IXGBE_PSRTYPE_TCPHDR |
3420 IXGBE_PSRTYPE_UDPHDR |
3421 IXGBE_PSRTYPE_IPV4HDR |
3422 IXGBE_PSRTYPE_IPV6HDR;
3423 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3425 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3426 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3427 IXGBE_SRRCTL_BSIZEHDR_MASK);
3428 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3431 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3433 /* Set if packets are dropped when no descriptors available */
3435 srrctl |= IXGBE_SRRCTL_DROP_EN;
3438 * Configure the RX buffer size in the BSIZEPACKET field of
3439 * the SRRCTL register of the queue.
3440 * The value is in 1 KB resolution. Valid values can be from
3443 mbp_priv = (struct rte_pktmbuf_pool_private *)
3444 ((char *)rxq->mb_pool + sizeof(struct rte_mempool));
3445 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3446 RTE_PKTMBUF_HEADROOM);
3447 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3448 IXGBE_SRRCTL_BSIZEPKT_MASK);
3449 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3451 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3452 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3454 /* It adds dual VLAN length for supporting dual VLAN */
3455 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3456 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3457 dev->data->scattered_rx = 1;
3458 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3463 * Device configured with multiple RX queues.
3465 ixgbe_dev_mq_rx_configure(dev);
3468 * Setup the Checksum Register.
3469 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3470 * Enable IP/L4 checkum computation by hardware if requested to do so.
3472 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3473 rxcsum |= IXGBE_RXCSUM_PCSD;
3474 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3475 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3477 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3479 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3481 if (hw->mac.type == ixgbe_mac_82599EB) {
3482 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3483 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3484 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3486 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3487 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3488 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3495 * Initializes Transmit Unit.
3498 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3500 struct ixgbe_hw *hw;
3501 struct igb_tx_queue *txq;
3507 PMD_INIT_FUNC_TRACE();
3508 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3510 /* Enable TX CRC (checksum offload requirement) */
3511 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3512 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
3513 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3515 /* Setup the Base and Length of the Tx Descriptor Rings */
3516 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3517 txq = dev->data->tx_queues[i];
3519 bus_addr = txq->tx_ring_phys_addr;
3520 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3521 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3522 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3523 (uint32_t)(bus_addr >> 32));
3524 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3525 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3526 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3527 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3528 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3531 * Disable Tx Head Writeback RO bit, since this hoses
3532 * bookkeeping if things aren't delivered in order.
3534 switch (hw->mac.type) {
3535 case ixgbe_mac_82598EB:
3536 txctrl = IXGBE_READ_REG(hw,
3537 IXGBE_DCA_TXCTRL(txq->reg_idx));
3538 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3539 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3543 case ixgbe_mac_82599EB:
3544 case ixgbe_mac_X540:
3546 txctrl = IXGBE_READ_REG(hw,
3547 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3548 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3549 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3555 /* Device configured with multiple TX queues. */
3556 ixgbe_dev_mq_tx_configure(dev);
3560 * Start Transmit and Receive Units.
3563 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3565 struct ixgbe_hw *hw;
3566 struct igb_tx_queue *txq;
3567 struct igb_rx_queue *rxq;
3575 PMD_INIT_FUNC_TRACE();
3576 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3578 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3579 txq = dev->data->tx_queues[i];
3580 /* Setup Transmit Threshold Registers */
3581 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3582 txdctl |= txq->pthresh & 0x7F;
3583 txdctl |= ((txq->hthresh & 0x7F) << 8);
3584 txdctl |= ((txq->wthresh & 0x7F) << 16);
3585 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3588 if (hw->mac.type != ixgbe_mac_82598EB) {
3589 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3590 dmatxctl |= IXGBE_DMATXCTL_TE;
3591 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3594 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3595 txq = dev->data->tx_queues[i];
3596 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3597 txdctl |= IXGBE_TXDCTL_ENABLE;
3598 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3600 /* Wait until TX Enable ready */
3601 if (hw->mac.type == ixgbe_mac_82599EB) {
3605 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3606 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3608 PMD_INIT_LOG(ERR, "Could not enable "
3609 "Tx Queue %d\n", i);
3612 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3613 rxq = dev->data->rx_queues[i];
3614 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3615 rxdctl |= IXGBE_RXDCTL_ENABLE;
3616 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3618 /* Wait until RX Enable ready */
3622 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3623 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3625 PMD_INIT_LOG(ERR, "Could not enable "
3626 "Rx Queue %d\n", i);
3628 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3631 /* Enable Receive engine */
3632 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3633 if (hw->mac.type == ixgbe_mac_82598EB)
3634 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3635 rxctrl |= IXGBE_RXCTRL_RXEN;
3636 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3641 * [VF] Initializes Receive Unit.
3644 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3646 struct ixgbe_hw *hw;
3647 struct igb_rx_queue *rxq;
3648 struct rte_pktmbuf_pool_private *mbp_priv;
3655 PMD_INIT_FUNC_TRACE();
3656 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3658 /* Setup RX queues */
3659 dev->rx_pkt_burst = ixgbe_recv_pkts;
3660 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3661 rxq = dev->data->rx_queues[i];
3663 /* Allocate buffers for descriptor rings */
3664 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3668 /* Setup the Base and Length of the Rx Descriptor Rings */
3669 bus_addr = rxq->rx_ring_phys_addr;
3671 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3672 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3673 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3674 (uint32_t)(bus_addr >> 32));
3675 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3676 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3677 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3678 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3681 /* Configure the SRRCTL register */
3682 #ifdef RTE_HEADER_SPLIT_ENABLE
3684 * Configure Header Split
3686 if (dev->data->dev_conf.rxmode.header_split) {
3688 /* Must setup the PSRTYPE register */
3690 psrtype = IXGBE_PSRTYPE_TCPHDR |
3691 IXGBE_PSRTYPE_UDPHDR |
3692 IXGBE_PSRTYPE_IPV4HDR |
3693 IXGBE_PSRTYPE_IPV6HDR;
3695 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
3697 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3698 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3699 IXGBE_SRRCTL_BSIZEHDR_MASK);
3700 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3703 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3705 /* Set if packets are dropped when no descriptors available */
3707 srrctl |= IXGBE_SRRCTL_DROP_EN;
3710 * Configure the RX buffer size in the BSIZEPACKET field of
3711 * the SRRCTL register of the queue.
3712 * The value is in 1 KB resolution. Valid values can be from
3715 mbp_priv = (struct rte_pktmbuf_pool_private *)
3716 ((char *)rxq->mb_pool + sizeof(struct rte_mempool));
3717 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3718 RTE_PKTMBUF_HEADROOM);
3719 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3720 IXGBE_SRRCTL_BSIZEPKT_MASK);
3723 * VF modification to write virtual function SRRCTL register
3725 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
3727 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3728 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3730 /* It adds dual VLAN length for supporting dual VLAN */
3731 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3732 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
3733 dev->data->scattered_rx = 1;
3734 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3742 * [VF] Initializes Transmit Unit.
3745 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
3747 struct ixgbe_hw *hw;
3748 struct igb_tx_queue *txq;
3753 PMD_INIT_FUNC_TRACE();
3754 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3756 /* Setup the Base and Length of the Tx Descriptor Rings */
3757 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3758 txq = dev->data->tx_queues[i];
3759 bus_addr = txq->tx_ring_phys_addr;
3760 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
3761 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3762 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
3763 (uint32_t)(bus_addr >> 32));
3764 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
3765 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3766 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3767 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
3768 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
3771 * Disable Tx Head Writeback RO bit, since this hoses
3772 * bookkeeping if things aren't delivered in order.
3774 txctrl = IXGBE_READ_REG(hw,
3775 IXGBE_VFDCA_TXCTRL(i));
3776 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3777 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
3783 * [VF] Start Transmit and Receive Units.
3786 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
3788 struct ixgbe_hw *hw;
3789 struct igb_tx_queue *txq;
3790 struct igb_rx_queue *rxq;
3796 PMD_INIT_FUNC_TRACE();
3797 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3799 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3800 txq = dev->data->tx_queues[i];
3801 /* Setup Transmit Threshold Registers */
3802 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3803 txdctl |= txq->pthresh & 0x7F;
3804 txdctl |= ((txq->hthresh & 0x7F) << 8);
3805 txdctl |= ((txq->wthresh & 0x7F) << 16);
3806 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
3809 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3811 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3812 txdctl |= IXGBE_TXDCTL_ENABLE;
3813 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
3816 /* Wait until TX Enable ready */
3819 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3820 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3822 PMD_INIT_LOG(ERR, "Could not enable "
3823 "Tx Queue %d\n", i);
3825 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3827 rxq = dev->data->rx_queues[i];
3829 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
3830 rxdctl |= IXGBE_RXDCTL_ENABLE;
3831 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
3833 /* Wait until RX Enable ready */
3837 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
3838 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3840 PMD_INIT_LOG(ERR, "Could not enable "
3841 "Rx Queue %d\n", i);
3843 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);