4 * Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
47 #include <rte_byteorder.h>
48 #include <rte_common.h>
49 #include <rte_cycles.h>
51 #include <rte_debug.h>
52 #include <rte_interrupts.h>
54 #include <rte_memory.h>
55 #include <rte_memzone.h>
56 #include <rte_launch.h>
57 #include <rte_tailq.h>
59 #include <rte_per_lcore.h>
60 #include <rte_lcore.h>
61 #include <rte_atomic.h>
62 #include <rte_branch_prediction.h>
64 #include <rte_mempool.h>
65 #include <rte_malloc.h>
67 #include <rte_ether.h>
68 #include <rte_ethdev.h>
69 #include <rte_prefetch.h>
73 #include <rte_string_fns.h>
74 #include <rte_errno.h>
76 #include "ixgbe_logs.h"
77 #include "ixgbe/ixgbe_api.h"
78 #include "ixgbe/ixgbe_vf.h"
79 #include "ixgbe_ethdev.h"
80 #include "ixgbe/ixgbe_dcb.h"
83 #define RTE_PMD_IXGBE_TX_MAX_BURST 32
85 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
86 #define RTE_PMD_IXGBE_RX_MAX_BURST 32
89 static inline struct rte_mbuf *
90 rte_rxmbuf_alloc(struct rte_mempool *mp)
94 m = __rte_mbuf_raw_alloc(mp);
95 __rte_mbuf_sanity_check_raw(m, RTE_MBUF_PKT, 0);
99 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
100 (uint64_t) ((mb)->buf_physaddr + (uint64_t)((char *)((mb)->pkt.data) - \
101 (char *)(mb)->buf_addr))
103 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
104 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
107 * Structure associated with each descriptor of the RX ring of a RX queue.
109 struct igb_rx_entry {
110 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
114 * Structure associated with each descriptor of the TX ring of a TX queue.
116 struct igb_tx_entry {
117 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
118 uint16_t next_id; /**< Index of next descriptor in ring. */
119 uint16_t last_id; /**< Index of last scattered descriptor. */
123 * Structure associated with each RX queue.
125 struct igb_rx_queue {
126 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
127 volatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
128 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
129 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
130 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
131 struct igb_rx_entry *sw_ring; /**< address of RX software ring. */
132 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
133 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
134 uint16_t nb_rx_desc; /**< number of RX descriptors. */
135 uint16_t rx_tail; /**< current value of RDT register. */
136 uint16_t nb_rx_hold; /**< number of held free RX desc. */
137 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
138 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
139 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
140 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
142 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
143 uint16_t queue_id; /**< RX queue index. */
144 uint16_t reg_idx; /**< RX queue register index. */
145 uint8_t port_id; /**< Device port identifier. */
146 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
147 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
148 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
149 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */
150 struct rte_mbuf fake_mbuf;
151 /** hold packets to return to application */
152 struct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2];
157 * IXGBE CTX Constants
159 enum ixgbe_advctx_num {
160 IXGBE_CTX_0 = 0, /**< CTX0 */
161 IXGBE_CTX_1 = 1, /**< CTX1 */
162 IXGBE_CTX_NUM = 2, /**< CTX NUMBER */
166 * Structure to check if new context need be built
169 struct ixgbe_advctx_info {
170 uint16_t flags; /**< ol_flags for context build. */
171 uint32_t cmp_mask; /**< compare mask for vlan_macip_lens */
172 union rte_vlan_macip vlan_macip_lens; /**< vlan, mac ip length. */
176 * Structure associated with each TX queue.
178 struct igb_tx_queue {
179 /** TX ring virtual address. */
180 volatile union ixgbe_adv_tx_desc *tx_ring;
181 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
182 struct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */
183 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
184 uint16_t nb_tx_desc; /**< number of TX descriptors. */
185 uint16_t tx_tail; /**< current value of TDT reg. */
186 uint16_t tx_free_thresh;/**< minimum TX before freeing. */
187 /** Number of TX descriptors to use before RS bit is set. */
188 uint16_t tx_rs_thresh;
189 /** Number of TX descriptors used since RS bit was set. */
191 /** Index to last TX descriptor to have been cleaned. */
192 uint16_t last_desc_cleaned;
193 /** Total number of TX descriptors ready to be allocated. */
195 uint16_t tx_next_dd; /**< next desc to scan for DD bit */
196 uint16_t tx_next_rs; /**< next desc to set RS bit */
197 uint16_t queue_id; /**< TX queue index. */
198 uint16_t reg_idx; /**< TX queue register index. */
199 uint8_t port_id; /**< Device port identifier. */
200 uint8_t pthresh; /**< Prefetch threshold register. */
201 uint8_t hthresh; /**< Host threshold register. */
202 uint8_t wthresh; /**< Write-back threshold reg. */
203 uint32_t txq_flags; /**< Holds flags for this TXq */
204 uint32_t ctx_curr; /**< Hardware context states. */
205 /** Hardware context0 history. */
206 struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM];
211 #define RTE_PMD_USE_PREFETCH
214 #ifdef RTE_PMD_USE_PREFETCH
216 * Prefetch a cache line into all cache levels.
218 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
220 #define rte_ixgbe_prefetch(p) do {} while(0)
223 #ifdef RTE_PMD_PACKET_PREFETCH
224 #define rte_packet_prefetch(p) rte_prefetch1(p)
226 #define rte_packet_prefetch(p) do {} while(0)
229 /*********************************************************************
233 **********************************************************************/
236 * The "simple" TX queue functions require that the following
237 * flags are set when the TX queue is configured:
238 * - ETH_TXQ_FLAGS_NOMULTSEGS
239 * - ETH_TXQ_FLAGS_NOVLANOFFL
240 * - ETH_TXQ_FLAGS_NOXSUMSCTP
241 * - ETH_TXQ_FLAGS_NOXSUMUDP
242 * - ETH_TXQ_FLAGS_NOXSUMTCP
243 * and that the RS bit threshold (tx_rs_thresh) is at least equal to
244 * RTE_PMD_IXGBE_TX_MAX_BURST.
246 #define IXGBE_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
247 ETH_TXQ_FLAGS_NOOFFLOADS)
250 * Check for descriptors with their DD bit set and free mbufs.
251 * Return the total number of buffers freed.
253 static inline int __attribute__((always_inline))
254 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
256 struct igb_tx_entry *txep;
260 /* check DD bit on threshold descriptor */
261 status = txq->tx_ring[txq->tx_next_dd].wb.status;
262 if (! (status & IXGBE_ADVTXD_STAT_DD))
266 * first buffer to free from S/W ring is at index
267 * tx_next_dd - (tx_rs_thresh-1)
269 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
271 /* prefetch the mbufs that are about to be freed */
272 for (i = 0; i < txq->tx_rs_thresh; ++i)
273 rte_prefetch0((txep + i)->mbuf);
275 /* free buffers one at a time */
276 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
277 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
278 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
282 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
283 rte_pktmbuf_free_seg(txep->mbuf);
288 /* buffers were freed, update counters */
289 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
290 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
291 if (txq->tx_next_dd >= txq->nb_tx_desc)
292 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
294 return txq->tx_rs_thresh;
298 * Populate descriptors with the following info:
299 * 1.) buffer_addr = phys_addr + headroom
300 * 2.) cmd_type_len = DCMD_DTYP_FLAGS | pkt_len
301 * 3.) olinfo_status = pkt_len << PAYLEN_SHIFT
304 /* Defines for Tx descriptor */
305 #define DCMD_DTYP_FLAGS (IXGBE_ADVTXD_DTYP_DATA |\
306 IXGBE_ADVTXD_DCMD_IFCS |\
307 IXGBE_ADVTXD_DCMD_DEXT |\
308 IXGBE_ADVTXD_DCMD_EOP)
310 /* Populate 4 descriptors with data from 4 mbufs */
312 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
314 uint64_t buf_dma_addr;
318 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
319 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
320 pkt_len = (*pkts)->pkt.data_len;
322 /* write data to descriptor */
323 txdp->read.buffer_addr = buf_dma_addr;
324 txdp->read.cmd_type_len =
325 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
326 txdp->read.olinfo_status =
327 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
331 /* Populate 1 descriptor with data from 1 mbuf */
333 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
335 uint64_t buf_dma_addr;
338 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
339 pkt_len = (*pkts)->pkt.data_len;
341 /* write data to descriptor */
342 txdp->read.buffer_addr = buf_dma_addr;
343 txdp->read.cmd_type_len =
344 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
345 txdp->read.olinfo_status =
346 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
350 * Fill H/W descriptor ring with mbuf data.
351 * Copy mbuf pointers to the S/W ring.
354 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
357 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
358 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
359 const int N_PER_LOOP = 4;
360 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
361 int mainpart, leftover;
365 * Process most of the packets in chunks of N pkts. Any
366 * leftover packets will get processed one at a time.
368 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
369 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
370 for (i = 0; i < mainpart; i += N_PER_LOOP) {
371 /* Copy N mbuf pointers to the S/W ring */
372 for (j = 0; j < N_PER_LOOP; ++j) {
373 (txep + i + j)->mbuf = *(pkts + i + j);
375 tx4(txdp + i, pkts + i);
378 if (unlikely(leftover > 0)) {
379 for (i = 0; i < leftover; ++i) {
380 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
381 tx1(txdp + mainpart + i, pkts + mainpart + i);
386 static inline uint16_t
387 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
390 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
391 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
395 * Begin scanning the H/W ring for done descriptors when the
396 * number of available descriptors drops below tx_free_thresh. For
397 * each done descriptor, free the associated buffer.
399 if (txq->nb_tx_free < txq->tx_free_thresh)
400 ixgbe_tx_free_bufs(txq);
402 /* Only use descriptors that are available */
403 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
404 if (unlikely(nb_pkts == 0))
407 /* Use exactly nb_pkts descriptors */
408 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
411 * At this point, we know there are enough descriptors in the
412 * ring to transmit all the packets. This assumes that each
413 * mbuf contains a single segment, and that no new offloads
414 * are expected, which would require a new context descriptor.
418 * See if we're going to wrap-around. If so, handle the top
419 * of the descriptor ring first, then do the bottom. If not,
420 * the processing looks just like the "bottom" part anyway...
422 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
423 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
424 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
427 * We know that the last descriptor in the ring will need to
428 * have its RS bit set because tx_rs_thresh has to be
429 * a divisor of the ring size
431 tx_r[txq->tx_next_rs].read.cmd_type_len |=
432 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
433 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
438 /* Fill H/W descriptor ring with mbuf data */
439 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
440 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
443 * Determine if RS bit should be set
444 * This is what we actually want:
445 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
446 * but instead of subtracting 1 and doing >=, we can just do
447 * greater than without subtracting.
449 if (txq->tx_tail > txq->tx_next_rs) {
450 tx_r[txq->tx_next_rs].read.cmd_type_len |=
451 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
452 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
454 if (txq->tx_next_rs >= txq->nb_tx_desc)
455 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
459 * Check for wrap-around. This would only happen if we used
460 * up to the last descriptor in the ring, no more, no less.
462 if (txq->tx_tail >= txq->nb_tx_desc)
465 /* update tail pointer */
467 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
473 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
478 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
479 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
480 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
482 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
486 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
487 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
488 nb_tx = (uint16_t)(nb_tx + ret);
489 nb_pkts = (uint16_t)(nb_pkts - ret);
498 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
499 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
500 uint16_t ol_flags, uint32_t vlan_macip_lens)
502 uint32_t type_tucmd_mlhl;
503 uint32_t mss_l4len_idx;
507 ctx_idx = txq->ctx_curr;
511 if (ol_flags & PKT_TX_VLAN_PKT) {
512 cmp_mask |= TX_VLAN_CMP_MASK;
515 if (ol_flags & PKT_TX_IP_CKSUM) {
516 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
517 cmp_mask |= TX_MAC_LEN_CMP_MASK;
520 /* Specify which HW CTX to upload. */
521 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
522 switch (ol_flags & PKT_TX_L4_MASK) {
523 case PKT_TX_UDP_CKSUM:
524 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
525 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
526 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
527 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
529 case PKT_TX_TCP_CKSUM:
530 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
531 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
532 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
533 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
535 case PKT_TX_SCTP_CKSUM:
536 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
537 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
538 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
539 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
542 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
543 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
547 txq->ctx_cache[ctx_idx].flags = ol_flags;
548 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
549 txq->ctx_cache[ctx_idx].vlan_macip_lens.data =
550 vlan_macip_lens & cmp_mask;
552 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
553 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
554 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
555 ctx_txd->seqnum_seed = 0;
559 * Check which hardware context can be used. Use the existing match
560 * or create a new context descriptor.
562 static inline uint32_t
563 what_advctx_update(struct igb_tx_queue *txq, uint16_t flags,
564 uint32_t vlan_macip_lens)
566 /* If match with the current used context */
567 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
568 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
569 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
570 return txq->ctx_curr;
573 /* What if match with the next context */
575 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
576 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
577 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
578 return txq->ctx_curr;
581 /* Mismatch, use the previous context */
582 return (IXGBE_CTX_NUM);
585 static inline uint32_t
586 tx_desc_cksum_flags_to_olinfo(uint16_t ol_flags)
588 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
589 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
592 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
593 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
597 static inline uint32_t
598 tx_desc_vlan_flags_to_cmdtype(uint16_t ol_flags)
600 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
601 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
604 /* Default RS bit threshold values */
605 #ifndef DEFAULT_TX_RS_THRESH
606 #define DEFAULT_TX_RS_THRESH 32
608 #ifndef DEFAULT_TX_FREE_THRESH
609 #define DEFAULT_TX_FREE_THRESH 32
612 /* Reset transmit descriptors after they have been used */
614 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
616 struct igb_tx_entry *sw_ring = txq->sw_ring;
617 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
618 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
619 uint16_t nb_tx_desc = txq->nb_tx_desc;
620 uint16_t desc_to_clean_to;
621 uint16_t nb_tx_to_clean;
623 /* Determine the last descriptor needing to be cleaned */
624 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
625 if (desc_to_clean_to >= nb_tx_desc)
626 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
628 /* Check to make sure the last descriptor to clean is done */
629 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
630 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
632 PMD_TX_FREE_LOG(DEBUG,
633 "TX descriptor %4u is not done"
634 "(port=%d queue=%d)",
636 txq->port_id, txq->queue_id);
637 /* Failed to clean any descriptors, better luck next time */
641 /* Figure out how many descriptors will be cleaned */
642 if (last_desc_cleaned > desc_to_clean_to)
643 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
646 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
649 PMD_TX_FREE_LOG(DEBUG,
650 "Cleaning %4u TX descriptors: %4u to %4u "
651 "(port=%d queue=%d)",
652 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
653 txq->port_id, txq->queue_id);
656 * The last descriptor to clean is done, so that means all the
657 * descriptors from the last descriptor that was cleaned
658 * up to the last descriptor with the RS bit set
659 * are done. Only reset the threshold descriptor.
661 txr[desc_to_clean_to].wb.status = 0;
663 /* Update the txq to reflect the last descriptor that was cleaned */
664 txq->last_desc_cleaned = desc_to_clean_to;
665 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
672 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
675 struct igb_tx_queue *txq;
676 struct igb_tx_entry *sw_ring;
677 struct igb_tx_entry *txe, *txn;
678 volatile union ixgbe_adv_tx_desc *txr;
679 volatile union ixgbe_adv_tx_desc *txd;
680 struct rte_mbuf *tx_pkt;
681 struct rte_mbuf *m_seg;
682 uint64_t buf_dma_addr;
683 uint32_t olinfo_status;
684 uint32_t cmd_type_len;
693 uint32_t vlan_macip_lens;
698 sw_ring = txq->sw_ring;
700 tx_id = txq->tx_tail;
701 txe = &sw_ring[tx_id];
703 /* Determine if the descriptor ring needs to be cleaned. */
704 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
705 ixgbe_xmit_cleanup(txq);
709 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
712 pkt_len = tx_pkt->pkt.pkt_len;
714 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
717 * Determine how many (if any) context descriptors
718 * are needed for offload functionality.
720 ol_flags = tx_pkt->ol_flags;
721 vlan_macip_lens = tx_pkt->pkt.vlan_macip.data;
723 /* If hardware offload required */
724 tx_ol_req = (uint16_t)(ol_flags & PKT_TX_OFFLOAD_MASK);
726 /* If new context need be built or reuse the exist ctx. */
727 ctx = what_advctx_update(txq, tx_ol_req,
729 /* Only allocate context descriptor if required*/
730 new_ctx = (ctx == IXGBE_CTX_NUM);
735 * Keep track of how many descriptors are used this loop
736 * This will always be the number of segments + the number of
737 * Context descriptors required to transmit the packet
739 nb_used = (uint16_t)(tx_pkt->pkt.nb_segs + new_ctx);
742 * The number of descriptors that must be allocated for a
743 * packet is the number of segments of that packet, plus 1
744 * Context Descriptor for the hardware offload, if any.
745 * Determine the last TX descriptor to allocate in the TX ring
746 * for the packet, starting from the current position (tx_id)
749 tx_last = (uint16_t) (tx_id + nb_used - 1);
752 if (tx_last >= txq->nb_tx_desc)
753 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
755 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
756 " tx_first=%u tx_last=%u\n",
757 (unsigned) txq->port_id,
758 (unsigned) txq->queue_id,
764 * Make sure there are enough TX descriptors available to
765 * transmit the entire packet.
766 * nb_used better be less than or equal to txq->tx_rs_thresh
768 if (nb_used > txq->nb_tx_free) {
769 PMD_TX_FREE_LOG(DEBUG,
770 "Not enough free TX descriptors "
771 "nb_used=%4u nb_free=%4u "
772 "(port=%d queue=%d)",
773 nb_used, txq->nb_tx_free,
774 txq->port_id, txq->queue_id);
776 if (ixgbe_xmit_cleanup(txq) != 0) {
777 /* Could not clean any descriptors */
783 /* nb_used better be <= txq->tx_rs_thresh */
784 if (unlikely(nb_used > txq->tx_rs_thresh)) {
785 PMD_TX_FREE_LOG(DEBUG,
786 "The number of descriptors needed to "
787 "transmit the packet exceeds the "
788 "RS bit threshold. This will impact "
790 "nb_used=%4u nb_free=%4u "
792 "(port=%d queue=%d)",
793 nb_used, txq->nb_tx_free,
795 txq->port_id, txq->queue_id);
797 * Loop here until there are enough TX
798 * descriptors or until the ring cannot be
801 while (nb_used > txq->nb_tx_free) {
802 if (ixgbe_xmit_cleanup(txq) != 0) {
804 * Could not clean any
816 * By now there are enough free TX descriptors to transmit
821 * Set common flags of all TX Data Descriptors.
823 * The following bits must be set in all Data Descriptors:
824 * - IXGBE_ADVTXD_DTYP_DATA
825 * - IXGBE_ADVTXD_DCMD_DEXT
827 * The following bits must be set in the first Data Descriptor
828 * and are ignored in the other ones:
829 * - IXGBE_ADVTXD_DCMD_IFCS
830 * - IXGBE_ADVTXD_MAC_1588
831 * - IXGBE_ADVTXD_DCMD_VLE
833 * The following bits must only be set in the last Data
835 * - IXGBE_TXD_CMD_EOP
837 * The following bits can be set in any Data Descriptor, but
838 * are only set in the last Data Descriptor:
841 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
842 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
843 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
844 #ifdef RTE_LIBRTE_IEEE1588
845 if (ol_flags & PKT_TX_IEEE1588_TMST)
846 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
851 * Setup the TX Advanced Context Descriptor if required
854 volatile struct ixgbe_adv_tx_context_desc *
857 ctx_txd = (volatile struct
858 ixgbe_adv_tx_context_desc *)
861 txn = &sw_ring[txe->next_id];
862 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
864 if (txe->mbuf != NULL) {
865 rte_pktmbuf_free_seg(txe->mbuf);
869 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
872 txe->last_id = tx_last;
873 tx_id = txe->next_id;
878 * Setup the TX Advanced Data Descriptor,
879 * This path will go through
880 * whatever new/reuse the context descriptor
882 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
883 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
884 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
890 txn = &sw_ring[txe->next_id];
892 if (txe->mbuf != NULL)
893 rte_pktmbuf_free_seg(txe->mbuf);
897 * Set up Transmit Data Descriptor.
899 slen = m_seg->pkt.data_len;
900 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
901 txd->read.buffer_addr =
902 rte_cpu_to_le_64(buf_dma_addr);
903 txd->read.cmd_type_len =
904 rte_cpu_to_le_32(cmd_type_len | slen);
905 txd->read.olinfo_status =
906 rte_cpu_to_le_32(olinfo_status);
907 txe->last_id = tx_last;
908 tx_id = txe->next_id;
910 m_seg = m_seg->pkt.next;
911 } while (m_seg != NULL);
914 * The last packet data descriptor needs End Of Packet (EOP)
916 cmd_type_len |= IXGBE_TXD_CMD_EOP;
917 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
918 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
920 /* Set RS bit only on threshold packets' last descriptor */
921 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
922 PMD_TX_FREE_LOG(DEBUG,
923 "Setting RS bit on TXD id="
924 "%4u (port=%d queue=%d)",
925 tx_last, txq->port_id, txq->queue_id);
927 cmd_type_len |= IXGBE_TXD_CMD_RS;
929 /* Update txq RS bit counters */
932 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
938 * Set the Transmit Descriptor Tail (TDT)
940 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
941 (unsigned) txq->port_id, (unsigned) txq->queue_id,
942 (unsigned) tx_id, (unsigned) nb_tx);
943 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
944 txq->tx_tail = tx_id;
949 /*********************************************************************
953 **********************************************************************/
954 static inline uint16_t
955 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
959 static uint16_t ip_pkt_types_map[16] = {
960 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
961 PKT_RX_IPV6_HDR, 0, 0, 0,
962 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
963 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
966 static uint16_t ip_rss_types_map[16] = {
967 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
968 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
969 PKT_RX_RSS_HASH, 0, 0, 0,
970 0, 0, 0, PKT_RX_FDIR,
973 #ifdef RTE_LIBRTE_IEEE1588
974 static uint32_t ip_pkt_etqf_map[8] = {
975 0, 0, 0, PKT_RX_IEEE1588_PTP,
979 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
980 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
981 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
983 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
984 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
987 return (uint16_t)(pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF]);
990 static inline uint16_t
991 rx_desc_status_to_pkt_flags(uint32_t rx_status)
996 * Check if VLAN present only.
997 * Do not check whether L3/L4 rx checksum done by NIC or not,
998 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
1000 pkt_flags = (uint16_t)((rx_status & IXGBE_RXD_STAT_VP) ?
1001 PKT_RX_VLAN_PKT : 0);
1003 #ifdef RTE_LIBRTE_IEEE1588
1004 if (rx_status & IXGBE_RXD_STAT_TMST)
1005 pkt_flags = (uint16_t)(pkt_flags | PKT_RX_IEEE1588_TMST);
1010 static inline uint16_t
1011 rx_desc_error_to_pkt_flags(uint32_t rx_status)
1014 * Bit 31: IPE, IPv4 checksum error
1015 * Bit 30: L4I, L4I integrity error
1017 static uint16_t error_to_pkt_flags_map[4] = {
1018 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
1019 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1021 return error_to_pkt_flags_map[(rx_status >>
1022 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1025 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1027 * LOOK_AHEAD defines how many desc statuses to check beyond the
1028 * current descriptor.
1029 * It must be a pound define for optimal performance.
1030 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1031 * function only works with LOOK_AHEAD=8.
1033 #define LOOK_AHEAD 8
1034 #if (LOOK_AHEAD != 8)
1035 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1038 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
1040 volatile union ixgbe_adv_rx_desc *rxdp;
1041 struct igb_rx_entry *rxep;
1042 struct rte_mbuf *mb;
1044 int s[LOOK_AHEAD], nb_dd;
1045 int i, j, nb_rx = 0;
1048 /* get references to current descriptor and S/W ring entry */
1049 rxdp = &rxq->rx_ring[rxq->rx_tail];
1050 rxep = &rxq->sw_ring[rxq->rx_tail];
1052 /* check to make sure there is at least 1 packet to receive */
1053 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
1057 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1058 * reference packets that are ready to be received.
1060 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1061 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
1063 /* Read desc statuses backwards to avoid race condition */
1064 for (j = LOOK_AHEAD-1; j >= 0; --j)
1065 s[j] = rxdp[j].wb.upper.status_error;
1067 /* Clear everything but the status bits (LSB) */
1068 for (j = 0; j < LOOK_AHEAD; ++j)
1069 s[j] &= IXGBE_RXDADV_STAT_DD;
1071 /* Compute how many status bits were set */
1072 nb_dd = s[0]+s[1]+s[2]+s[3]+s[4]+s[5]+s[6]+s[7];
1075 /* Translate descriptor info to mbuf format */
1076 for (j = 0; j < nb_dd; ++j) {
1078 pkt_len = (uint16_t)(rxdp[j].wb.upper.length -
1080 mb->pkt.data_len = pkt_len;
1081 mb->pkt.pkt_len = pkt_len;
1082 mb->pkt.vlan_macip.f.vlan_tci = rxdp[j].wb.upper.vlan;
1083 mb->pkt.hash.rss = rxdp[j].wb.lower.hi_dword.rss;
1085 /* convert descriptor fields to rte mbuf flags */
1086 mb->ol_flags = rx_desc_hlen_type_rss_to_pkt_flags(
1087 rxdp[j].wb.lower.lo_dword.data);
1088 /* reuse status field from scan list */
1089 mb->ol_flags = (uint16_t)(mb->ol_flags |
1090 rx_desc_status_to_pkt_flags(s[j]));
1091 mb->ol_flags = (uint16_t)(mb->ol_flags |
1092 rx_desc_error_to_pkt_flags(s[j]));
1095 /* Move mbuf pointers from the S/W ring to the stage */
1096 for (j = 0; j < LOOK_AHEAD; ++j) {
1097 rxq->rx_stage[i + j] = rxep[j].mbuf;
1100 /* stop if all requested packets could not be received */
1101 if (nb_dd != LOOK_AHEAD)
1105 /* clear software ring entries so we can cleanup correctly */
1106 for (i = 0; i < nb_rx; ++i) {
1107 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1115 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
1117 volatile union ixgbe_adv_rx_desc *rxdp;
1118 struct igb_rx_entry *rxep;
1119 struct rte_mbuf *mb;
1124 /* allocate buffers in bulk directly into the S/W ring */
1125 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1126 (rxq->rx_free_thresh - 1));
1127 rxep = &rxq->sw_ring[alloc_idx];
1128 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1129 rxq->rx_free_thresh);
1130 if (unlikely(diag != 0))
1133 rxdp = &rxq->rx_ring[alloc_idx];
1134 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1135 /* populate the static rte mbuf fields */
1137 rte_mbuf_refcnt_set(mb, 1);
1138 mb->type = RTE_MBUF_PKT;
1139 mb->pkt.next = NULL;
1140 mb->pkt.data = (char *)mb->buf_addr + RTE_PKTMBUF_HEADROOM;
1141 mb->pkt.nb_segs = 1;
1142 mb->pkt.in_port = rxq->port_id;
1144 /* populate the descriptors */
1145 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1146 rxdp[i].read.hdr_addr = dma_addr;
1147 rxdp[i].read.pkt_addr = dma_addr;
1150 /* update tail pointer */
1152 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1154 /* update state of internal queue structure */
1155 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1156 rxq->rx_free_thresh);
1157 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1158 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1164 static inline uint16_t
1165 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1168 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1171 /* how many packets are ready to return? */
1172 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1174 /* copy mbuf pointers to the application's packet list */
1175 for (i = 0; i < nb_pkts; ++i)
1176 rx_pkts[i] = stage[i];
1178 /* update internal queue state */
1179 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1180 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1185 static inline uint16_t
1186 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1189 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1192 /* Any previously recv'd pkts will be returned from the Rx stage */
1193 if (rxq->rx_nb_avail)
1194 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1196 /* Scan the H/W ring for packets to receive */
1197 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1199 /* update internal queue state */
1200 rxq->rx_next_avail = 0;
1201 rxq->rx_nb_avail = nb_rx;
1202 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1204 /* if required, allocate new buffers to replenish descriptors */
1205 if (rxq->rx_tail > rxq->rx_free_trigger) {
1206 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1208 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1209 "queue_id=%u\n", (unsigned) rxq->port_id,
1210 (unsigned) rxq->queue_id);
1212 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1213 rxq->rx_free_thresh;
1216 * Need to rewind any previous receives if we cannot
1217 * allocate new buffers to replenish the old ones.
1219 rxq->rx_nb_avail = 0;
1220 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1221 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1222 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1228 if (rxq->rx_tail >= rxq->nb_rx_desc)
1231 /* received any packets this loop? */
1232 if (rxq->rx_nb_avail)
1233 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1238 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1240 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1245 if (unlikely(nb_pkts == 0))
1248 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1249 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1251 /* request is relatively large, chunk it up */
1255 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1256 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1257 nb_rx = (uint16_t)(nb_rx + ret);
1258 nb_pkts = (uint16_t)(nb_pkts - ret);
1265 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1268 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1271 struct igb_rx_queue *rxq;
1272 volatile union ixgbe_adv_rx_desc *rx_ring;
1273 volatile union ixgbe_adv_rx_desc *rxdp;
1274 struct igb_rx_entry *sw_ring;
1275 struct igb_rx_entry *rxe;
1276 struct rte_mbuf *rxm;
1277 struct rte_mbuf *nmb;
1278 union ixgbe_adv_rx_desc rxd;
1281 uint32_t hlen_type_rss;
1291 rx_id = rxq->rx_tail;
1292 rx_ring = rxq->rx_ring;
1293 sw_ring = rxq->sw_ring;
1294 while (nb_rx < nb_pkts) {
1296 * The order of operations here is important as the DD status
1297 * bit must not be read after any other descriptor fields.
1298 * rx_ring and rxdp are pointing to volatile data so the order
1299 * of accesses cannot be reordered by the compiler. If they were
1300 * not volatile, they could be reordered which could lead to
1301 * using invalid descriptor fields when read from rxd.
1303 rxdp = &rx_ring[rx_id];
1304 staterr = rxdp->wb.upper.status_error;
1305 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1312 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1313 * is likely to be invalid and to be dropped by the various
1314 * validation checks performed by the network stack.
1316 * Allocate a new mbuf to replenish the RX ring descriptor.
1317 * If the allocation fails:
1318 * - arrange for that RX descriptor to be the first one
1319 * being parsed the next time the receive function is
1320 * invoked [on the same queue].
1322 * - Stop parsing the RX ring and return immediately.
1324 * This policy do not drop the packet received in the RX
1325 * descriptor for which the allocation of a new mbuf failed.
1326 * Thus, it allows that packet to be later retrieved if
1327 * mbuf have been freed in the mean time.
1328 * As a side effect, holding RX descriptors instead of
1329 * systematically giving them back to the NIC may lead to
1330 * RX ring exhaustion situations.
1331 * However, the NIC can gracefully prevent such situations
1332 * to happen by sending specific "back-pressure" flow control
1333 * frames to its peer(s).
1335 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1336 "ext_err_stat=0x%08x pkt_len=%u\n",
1337 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1338 (unsigned) rx_id, (unsigned) staterr,
1339 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1341 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1343 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1344 "queue_id=%u\n", (unsigned) rxq->port_id,
1345 (unsigned) rxq->queue_id);
1346 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1351 rxe = &sw_ring[rx_id];
1353 if (rx_id == rxq->nb_rx_desc)
1356 /* Prefetch next mbuf while processing current one. */
1357 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1360 * When next RX descriptor is on a cache-line boundary,
1361 * prefetch the next 4 RX descriptors and the next 8 pointers
1364 if ((rx_id & 0x3) == 0) {
1365 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1366 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1372 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1373 rxdp->read.hdr_addr = dma_addr;
1374 rxdp->read.pkt_addr = dma_addr;
1377 * Initialize the returned mbuf.
1378 * 1) setup generic mbuf fields:
1379 * - number of segments,
1382 * - RX port identifier.
1383 * 2) integrate hardware offload data, if any:
1384 * - RSS flag & hash,
1385 * - IP checksum flag,
1386 * - VLAN TCI, if any,
1389 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1391 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1392 rte_packet_prefetch(rxm->pkt.data);
1393 rxm->pkt.nb_segs = 1;
1394 rxm->pkt.next = NULL;
1395 rxm->pkt.pkt_len = pkt_len;
1396 rxm->pkt.data_len = pkt_len;
1397 rxm->pkt.in_port = rxq->port_id;
1399 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1400 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1401 rxm->pkt.vlan_macip.f.vlan_tci =
1402 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1404 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1405 pkt_flags = (uint16_t)(pkt_flags |
1406 rx_desc_status_to_pkt_flags(staterr));
1407 pkt_flags = (uint16_t)(pkt_flags |
1408 rx_desc_error_to_pkt_flags(staterr));
1409 rxm->ol_flags = pkt_flags;
1411 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1412 rxm->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1413 else if (pkt_flags & PKT_RX_FDIR) {
1414 rxm->pkt.hash.fdir.hash =
1415 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1416 & IXGBE_ATR_HASH_MASK);
1417 rxm->pkt.hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1420 * Store the mbuf address into the next entry of the array
1421 * of returned packets.
1423 rx_pkts[nb_rx++] = rxm;
1425 rxq->rx_tail = rx_id;
1428 * If the number of free RX descriptors is greater than the RX free
1429 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1431 * Update the RDT with the value of the last processed RX descriptor
1432 * minus 1, to guarantee that the RDT register is never equal to the
1433 * RDH register, which creates a "full" ring situtation from the
1434 * hardware point of view...
1436 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1437 if (nb_hold > rxq->rx_free_thresh) {
1438 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1439 "nb_hold=%u nb_rx=%u\n",
1440 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1441 (unsigned) rx_id, (unsigned) nb_hold,
1443 rx_id = (uint16_t) ((rx_id == 0) ?
1444 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1445 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1448 rxq->nb_rx_hold = nb_hold;
1453 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1456 struct igb_rx_queue *rxq;
1457 volatile union ixgbe_adv_rx_desc *rx_ring;
1458 volatile union ixgbe_adv_rx_desc *rxdp;
1459 struct igb_rx_entry *sw_ring;
1460 struct igb_rx_entry *rxe;
1461 struct rte_mbuf *first_seg;
1462 struct rte_mbuf *last_seg;
1463 struct rte_mbuf *rxm;
1464 struct rte_mbuf *nmb;
1465 union ixgbe_adv_rx_desc rxd;
1466 uint64_t dma; /* Physical address of mbuf data buffer */
1468 uint32_t hlen_type_rss;
1478 rx_id = rxq->rx_tail;
1479 rx_ring = rxq->rx_ring;
1480 sw_ring = rxq->sw_ring;
1483 * Retrieve RX context of current packet, if any.
1485 first_seg = rxq->pkt_first_seg;
1486 last_seg = rxq->pkt_last_seg;
1488 while (nb_rx < nb_pkts) {
1491 * The order of operations here is important as the DD status
1492 * bit must not be read after any other descriptor fields.
1493 * rx_ring and rxdp are pointing to volatile data so the order
1494 * of accesses cannot be reordered by the compiler. If they were
1495 * not volatile, they could be reordered which could lead to
1496 * using invalid descriptor fields when read from rxd.
1498 rxdp = &rx_ring[rx_id];
1499 staterr = rxdp->wb.upper.status_error;
1500 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1507 * Allocate a new mbuf to replenish the RX ring descriptor.
1508 * If the allocation fails:
1509 * - arrange for that RX descriptor to be the first one
1510 * being parsed the next time the receive function is
1511 * invoked [on the same queue].
1513 * - Stop parsing the RX ring and return immediately.
1515 * This policy does not drop the packet received in the RX
1516 * descriptor for which the allocation of a new mbuf failed.
1517 * Thus, it allows that packet to be later retrieved if
1518 * mbuf have been freed in the mean time.
1519 * As a side effect, holding RX descriptors instead of
1520 * systematically giving them back to the NIC may lead to
1521 * RX ring exhaustion situations.
1522 * However, the NIC can gracefully prevent such situations
1523 * to happen by sending specific "back-pressure" flow control
1524 * frames to its peer(s).
1526 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
1527 "staterr=0x%x data_len=%u\n",
1528 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1529 (unsigned) rx_id, (unsigned) staterr,
1530 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1532 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1534 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1535 "queue_id=%u\n", (unsigned) rxq->port_id,
1536 (unsigned) rxq->queue_id);
1537 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1542 rxe = &sw_ring[rx_id];
1544 if (rx_id == rxq->nb_rx_desc)
1547 /* Prefetch next mbuf while processing current one. */
1548 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1551 * When next RX descriptor is on a cache-line boundary,
1552 * prefetch the next 4 RX descriptors and the next 8 pointers
1555 if ((rx_id & 0x3) == 0) {
1556 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1557 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1561 * Update RX descriptor with the physical address of the new
1562 * data buffer of the new allocated mbuf.
1566 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1567 rxdp->read.hdr_addr = dma;
1568 rxdp->read.pkt_addr = dma;
1571 * Set data length & data buffer address of mbuf.
1573 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1574 rxm->pkt.data_len = data_len;
1575 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1578 * If this is the first buffer of the received packet,
1579 * set the pointer to the first mbuf of the packet and
1580 * initialize its context.
1581 * Otherwise, update the total length and the number of segments
1582 * of the current scattered packet, and update the pointer to
1583 * the last mbuf of the current packet.
1585 if (first_seg == NULL) {
1587 first_seg->pkt.pkt_len = data_len;
1588 first_seg->pkt.nb_segs = 1;
1590 first_seg->pkt.pkt_len = (uint16_t)(first_seg->pkt.pkt_len
1592 first_seg->pkt.nb_segs++;
1593 last_seg->pkt.next = rxm;
1597 * If this is not the last buffer of the received packet,
1598 * update the pointer to the last mbuf of the current scattered
1599 * packet and continue to parse the RX ring.
1601 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1607 * This is the last buffer of the received packet.
1608 * If the CRC is not stripped by the hardware:
1609 * - Subtract the CRC length from the total packet length.
1610 * - If the last buffer only contains the whole CRC or a part
1611 * of it, free the mbuf associated to the last buffer.
1612 * If part of the CRC is also contained in the previous
1613 * mbuf, subtract the length of that CRC part from the
1614 * data length of the previous mbuf.
1616 rxm->pkt.next = NULL;
1617 if (unlikely(rxq->crc_len > 0)) {
1618 first_seg->pkt.pkt_len -= ETHER_CRC_LEN;
1619 if (data_len <= ETHER_CRC_LEN) {
1620 rte_pktmbuf_free_seg(rxm);
1621 first_seg->pkt.nb_segs--;
1622 last_seg->pkt.data_len = (uint16_t)
1623 (last_seg->pkt.data_len -
1624 (ETHER_CRC_LEN - data_len));
1625 last_seg->pkt.next = NULL;
1628 (uint16_t) (data_len - ETHER_CRC_LEN);
1632 * Initialize the first mbuf of the returned packet:
1633 * - RX port identifier,
1634 * - hardware offload data, if any:
1635 * - RSS flag & hash,
1636 * - IP checksum flag,
1637 * - VLAN TCI, if any,
1640 first_seg->pkt.in_port = rxq->port_id;
1643 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1644 * set in the pkt_flags field.
1646 first_seg->pkt.vlan_macip.f.vlan_tci =
1647 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1648 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1649 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1650 pkt_flags = (uint16_t)(pkt_flags |
1651 rx_desc_status_to_pkt_flags(staterr));
1652 pkt_flags = (uint16_t)(pkt_flags |
1653 rx_desc_error_to_pkt_flags(staterr));
1654 first_seg->ol_flags = pkt_flags;
1656 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1657 first_seg->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1658 else if (pkt_flags & PKT_RX_FDIR) {
1659 first_seg->pkt.hash.fdir.hash =
1660 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1661 & IXGBE_ATR_HASH_MASK);
1662 first_seg->pkt.hash.fdir.id =
1663 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1666 /* Prefetch data of first segment, if configured to do so. */
1667 rte_packet_prefetch(first_seg->pkt.data);
1670 * Store the mbuf address into the next entry of the array
1671 * of returned packets.
1673 rx_pkts[nb_rx++] = first_seg;
1676 * Setup receipt context for a new packet.
1682 * Record index of the next RX descriptor to probe.
1684 rxq->rx_tail = rx_id;
1687 * Save receive context.
1689 rxq->pkt_first_seg = first_seg;
1690 rxq->pkt_last_seg = last_seg;
1693 * If the number of free RX descriptors is greater than the RX free
1694 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1696 * Update the RDT with the value of the last processed RX descriptor
1697 * minus 1, to guarantee that the RDT register is never equal to the
1698 * RDH register, which creates a "full" ring situtation from the
1699 * hardware point of view...
1701 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1702 if (nb_hold > rxq->rx_free_thresh) {
1703 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1704 "nb_hold=%u nb_rx=%u\n",
1705 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1706 (unsigned) rx_id, (unsigned) nb_hold,
1708 rx_id = (uint16_t) ((rx_id == 0) ?
1709 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1710 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1713 rxq->nb_rx_hold = nb_hold;
1717 /*********************************************************************
1719 * Queue management functions
1721 **********************************************************************/
1724 * Rings setup and release.
1726 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1727 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1728 * also optimize cache line size effect. H/W supports up to cache line size 128.
1730 #define IXGBE_ALIGN 128
1733 * Maximum number of Ring Descriptors.
1735 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1736 * descriptors should meet the following condition:
1737 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1739 #define IXGBE_MIN_RING_DESC 64
1740 #define IXGBE_MAX_RING_DESC 4096
1743 * Create memzone for HW rings. malloc can't be used as the physical address is
1744 * needed. If the memzone is already created, then this function returns a ptr
1747 static const struct rte_memzone *
1748 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1749 uint16_t queue_id, uint32_t ring_size, int socket_id)
1751 char z_name[RTE_MEMZONE_NAMESIZE];
1752 const struct rte_memzone *mz;
1754 rte_snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1755 dev->driver->pci_drv.name, ring_name,
1756 dev->data->port_id, queue_id);
1758 mz = rte_memzone_lookup(z_name);
1762 return rte_memzone_reserve_aligned(z_name, ring_size,
1763 socket_id, 0, IXGBE_ALIGN);
1767 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1771 if (txq->sw_ring != NULL) {
1772 for (i = 0; i < txq->nb_tx_desc; i++) {
1773 if (txq->sw_ring[i].mbuf != NULL) {
1774 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1775 txq->sw_ring[i].mbuf = NULL;
1782 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1785 ixgbe_tx_queue_release_mbufs(txq);
1786 rte_free(txq->sw_ring);
1792 ixgbe_dev_tx_queue_release(void *txq)
1794 ixgbe_tx_queue_release(txq);
1797 /* (Re)set dynamic igb_tx_queue fields to defaults */
1799 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1801 struct igb_tx_entry *txe = txq->sw_ring;
1804 /* Zero out HW ring memory */
1805 for (i = 0; i < sizeof(union ixgbe_adv_tx_desc) * txq->nb_tx_desc; i++) {
1806 ((volatile char *)txq->tx_ring)[i] = 0;
1809 /* Initialize SW ring entries */
1810 prev = (uint16_t) (txq->nb_tx_desc - 1);
1811 for (i = 0; i < txq->nb_tx_desc; i++) {
1812 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1813 txd->wb.status = IXGBE_TXD_STAT_DD;
1816 txe[prev].next_id = i;
1820 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1821 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1824 txq->nb_tx_used = 0;
1826 * Always allow 1 descriptor to be un-allocated to avoid
1827 * a H/W race condition
1829 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1830 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1832 memset((void*)&txq->ctx_cache, 0,
1833 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1837 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1840 unsigned int socket_id,
1841 const struct rte_eth_txconf *tx_conf)
1843 const struct rte_memzone *tz;
1844 struct igb_tx_queue *txq;
1845 struct ixgbe_hw *hw;
1846 uint16_t tx_rs_thresh, tx_free_thresh;
1848 PMD_INIT_FUNC_TRACE();
1849 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1852 * Validate number of transmit descriptors.
1853 * It must not exceed hardware maximum, and must be multiple
1856 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1857 (nb_desc > IXGBE_MAX_RING_DESC) ||
1858 (nb_desc < IXGBE_MIN_RING_DESC)) {
1863 * The following two parameters control the setting of the RS bit on
1864 * transmit descriptors.
1865 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1866 * descriptors have been used.
1867 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1868 * descriptors are used or if the number of descriptors required
1869 * to transmit a packet is greater than the number of free TX
1871 * The following constraints must be satisfied:
1872 * tx_rs_thresh must be greater than 0.
1873 * tx_rs_thresh must be less than the size of the ring minus 2.
1874 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1875 * tx_rs_thresh must be a divisor of the ring size.
1876 * tx_free_thresh must be greater than 0.
1877 * tx_free_thresh must be less than the size of the ring minus 3.
1878 * One descriptor in the TX ring is used as a sentinel to avoid a
1879 * H/W race condition, hence the maximum threshold constraints.
1880 * When set to zero use default values.
1882 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1883 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1884 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1885 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1886 if (tx_rs_thresh >= (nb_desc - 2)) {
1887 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the number "
1888 "of TX descriptors minus 2. (tx_rs_thresh=%u port=%d "
1889 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1890 (int)dev->data->port_id, (int)queue_idx);
1893 if (tx_free_thresh >= (nb_desc - 3)) {
1894 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the "
1895 "tx_free_thresh must be less than the number of TX "
1896 "descriptors minus 3. (tx_free_thresh=%u port=%d "
1897 "queue=%d)\n", (unsigned int)tx_free_thresh,
1898 (int)dev->data->port_id, (int)queue_idx);
1901 if (tx_rs_thresh > tx_free_thresh) {
1902 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than or equal to "
1903 "tx_free_thresh. (tx_free_thresh=%u tx_rs_thresh=%u "
1904 "port=%d queue=%d)\n", (unsigned int)tx_free_thresh,
1905 (unsigned int)tx_rs_thresh, (int)dev->data->port_id,
1909 if ((nb_desc % tx_rs_thresh) != 0) {
1910 RTE_LOG(ERR, PMD, "tx_rs_thresh must be a divisor of the "
1911 "number of TX descriptors. (tx_rs_thresh=%u port=%d "
1912 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1913 (int)dev->data->port_id, (int)queue_idx);
1918 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1919 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1920 * by the NIC and all descriptors are written back after the NIC
1921 * accumulates WTHRESH descriptors.
1923 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1924 RTE_LOG(ERR, PMD, "TX WTHRESH must be set to 0 if "
1925 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1926 "port=%d queue=%d)\n", (unsigned int)tx_rs_thresh,
1927 (int)dev->data->port_id, (int)queue_idx);
1931 /* Free memory prior to re-allocation if needed... */
1932 if (dev->data->tx_queues[queue_idx] != NULL)
1933 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1935 /* First allocate the tx queue data structure */
1936 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct igb_tx_queue),
1937 CACHE_LINE_SIZE, socket_id);
1942 * Allocate TX ring hardware descriptors. A memzone large enough to
1943 * handle the maximum ring size is allocated in order to allow for
1944 * resizing in later calls to the queue setup function.
1946 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1947 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1950 ixgbe_tx_queue_release(txq);
1954 txq->nb_tx_desc = nb_desc;
1955 txq->tx_rs_thresh = tx_rs_thresh;
1956 txq->tx_free_thresh = tx_free_thresh;
1957 txq->pthresh = tx_conf->tx_thresh.pthresh;
1958 txq->hthresh = tx_conf->tx_thresh.hthresh;
1959 txq->wthresh = tx_conf->tx_thresh.wthresh;
1960 txq->queue_id = queue_idx;
1961 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1962 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1963 txq->port_id = dev->data->port_id;
1964 txq->txq_flags = tx_conf->txq_flags;
1967 * Modification to set VFTDT for virtual function if vf is detected
1969 if (hw->mac.type == ixgbe_mac_82599_vf)
1970 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1972 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1974 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1975 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1977 /* Allocate software ring */
1978 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1979 sizeof(struct igb_tx_entry) * nb_desc,
1980 CACHE_LINE_SIZE, socket_id);
1981 if (txq->sw_ring == NULL) {
1982 ixgbe_tx_queue_release(txq);
1985 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1986 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1988 ixgbe_reset_tx_queue(txq);
1990 dev->data->tx_queues[queue_idx] = txq;
1992 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1993 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
1994 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1995 PMD_INIT_LOG(INFO, "Using simple tx code path\n");
1996 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1998 PMD_INIT_LOG(INFO, "Using full-featured tx code path\n");
1999 PMD_INIT_LOG(INFO, " - txq_flags = %lx [IXGBE_SIMPLE_FLAGS=%lx]\n", (long unsigned)txq->txq_flags, (long unsigned)IXGBE_SIMPLE_FLAGS);
2000 PMD_INIT_LOG(INFO, " - tx_rs_thresh = %lu [RTE_PMD_IXGBE_TX_MAX_BURST=%lu]\n", (long unsigned)txq->tx_rs_thresh, (long unsigned)RTE_PMD_IXGBE_TX_MAX_BURST);
2001 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2008 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
2012 if (rxq->sw_ring != NULL) {
2013 for (i = 0; i < rxq->nb_rx_desc; i++) {
2014 if (rxq->sw_ring[i].mbuf != NULL) {
2015 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2016 rxq->sw_ring[i].mbuf = NULL;
2019 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2020 if (rxq->rx_nb_avail) {
2021 for (i = 0; i < rxq->rx_nb_avail; ++i) {
2022 struct rte_mbuf *mb;
2023 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2024 rte_pktmbuf_free_seg(mb);
2026 rxq->rx_nb_avail = 0;
2033 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
2036 ixgbe_rx_queue_release_mbufs(rxq);
2037 rte_free(rxq->sw_ring);
2043 ixgbe_dev_rx_queue_release(void *rxq)
2045 ixgbe_rx_queue_release(rxq);
2049 * Check if Rx Burst Bulk Alloc function can be used.
2051 * 0: the preconditions are satisfied and the bulk allocation function
2053 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2054 * function must be used.
2057 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2058 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
2060 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct igb_rx_queue *rxq)
2066 * Make sure the following pre-conditions are satisfied:
2067 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2068 * rxq->rx_free_thresh < rxq->nb_rx_desc
2069 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2070 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2071 * Scattered packets are not supported. This should be checked
2072 * outside of this function.
2074 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2075 if (! (rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST))
2077 else if (! (rxq->rx_free_thresh < rxq->nb_rx_desc))
2079 else if (! ((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0))
2081 else if (! (rxq->nb_rx_desc <
2082 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST)))
2091 /* Reset dynamic igb_rx_queue fields back to defaults */
2093 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
2099 * By default, the Rx queue setup function allocates enough memory for
2100 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2101 * extra memory at the end of the descriptor ring to be zero'd out. A
2102 * pre-condition for using the Rx burst bulk alloc function is that the
2103 * number of descriptors is less than or equal to
2104 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2105 * constraints here to see if we need to zero out memory after the end
2106 * of the H/W descriptor ring.
2108 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2109 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2110 /* zero out extra memory */
2111 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2114 /* do not zero out extra memory */
2115 len = rxq->nb_rx_desc;
2118 * Zero out HW ring memory. Zero out extra memory at the end of
2119 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2120 * reads extra memory as zeros.
2122 for (i = 0; i < len * sizeof(union ixgbe_adv_rx_desc); i++) {
2123 ((volatile char *)rxq->rx_ring)[i] = 0;
2126 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2128 * initialize extra software ring entries. Space for these extra
2129 * entries is always allocated
2131 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2132 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2133 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2136 rxq->rx_nb_avail = 0;
2137 rxq->rx_next_avail = 0;
2138 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2139 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2141 rxq->nb_rx_hold = 0;
2142 rxq->pkt_first_seg = NULL;
2143 rxq->pkt_last_seg = NULL;
2147 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2150 unsigned int socket_id,
2151 const struct rte_eth_rxconf *rx_conf,
2152 struct rte_mempool *mp)
2154 const struct rte_memzone *rz;
2155 struct igb_rx_queue *rxq;
2156 struct ixgbe_hw *hw;
2157 int use_def_burst_func = 1;
2160 PMD_INIT_FUNC_TRACE();
2161 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164 * Validate number of receive descriptors.
2165 * It must not exceed hardware maximum, and must be multiple
2168 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2169 (nb_desc > IXGBE_MAX_RING_DESC) ||
2170 (nb_desc < IXGBE_MIN_RING_DESC)) {
2174 /* Free memory prior to re-allocation if needed... */
2175 if (dev->data->rx_queues[queue_idx] != NULL)
2176 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2178 /* First allocate the rx queue data structure */
2179 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct igb_rx_queue),
2180 CACHE_LINE_SIZE, socket_id);
2184 rxq->nb_rx_desc = nb_desc;
2185 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2186 rxq->queue_id = queue_idx;
2187 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2188 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2189 rxq->port_id = dev->data->port_id;
2190 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2192 rxq->drop_en = rx_conf->rx_drop_en;
2195 * Allocate RX ring hardware descriptors. A memzone large enough to
2196 * handle the maximum ring size is allocated in order to allow for
2197 * resizing in later calls to the queue setup function.
2199 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2200 IXGBE_MAX_RING_DESC * sizeof(union ixgbe_adv_rx_desc),
2203 ixgbe_rx_queue_release(rxq);
2207 * Modified to setup VFRDT for Virtual Function
2209 if (hw->mac.type == ixgbe_mac_82599_vf) {
2211 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2213 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2217 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2219 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2222 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2223 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2226 * Allocate software ring. Allow for space at the end of the
2227 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2228 * function does not access an invalid memory region.
2230 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2231 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2235 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2236 sizeof(struct igb_rx_entry) * len,
2237 CACHE_LINE_SIZE, socket_id);
2238 if (rxq->sw_ring == NULL) {
2239 ixgbe_rx_queue_release(rxq);
2242 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
2243 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2246 * Certain constaints must be met in order to use the bulk buffer
2247 * allocation Rx burst function.
2249 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2251 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2252 if (!use_def_burst_func && !dev->data->scattered_rx) {
2253 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2254 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2255 "satisfied. Rx Burst Bulk Alloc function will be "
2256 "used on port=%d, queue=%d.\n",
2257 rxq->port_id, rxq->queue_id);
2258 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2261 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2262 "are not satisfied, Scattered Rx is requested, "
2263 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2264 "enabled (port=%d, queue=%d).\n",
2265 rxq->port_id, rxq->queue_id);
2267 dev->data->rx_queues[queue_idx] = rxq;
2269 ixgbe_reset_rx_queue(rxq);
2275 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2277 #define IXGBE_RXQ_SCAN_INTERVAL 4
2278 volatile union ixgbe_adv_rx_desc *rxdp;
2279 struct igb_rx_queue *rxq;
2282 if (rx_queue_id >= dev->data->nb_rx_queues) {
2283 PMD_RX_LOG(ERR, "Invalid RX queue id=%d\n", rx_queue_id);
2287 rxq = dev->data->rx_queues[rx_queue_id];
2288 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2290 while ((desc < rxq->nb_rx_desc) &&
2291 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2292 desc += IXGBE_RXQ_SCAN_INTERVAL;
2293 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2294 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2295 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2296 desc - rxq->nb_rx_desc]);
2303 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2307 PMD_INIT_FUNC_TRACE();
2309 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2310 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2312 ixgbe_tx_queue_release_mbufs(txq);
2313 ixgbe_reset_tx_queue(txq);
2317 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2318 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2320 ixgbe_rx_queue_release_mbufs(rxq);
2321 ixgbe_reset_rx_queue(rxq);
2326 /*********************************************************************
2328 * Device RX/TX init functions
2330 **********************************************************************/
2333 * Receive Side Scaling (RSS)
2334 * See section 7.1.2.8 in the following document:
2335 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2338 * The source and destination IP addresses of the IP header and the source
2339 * and destination ports of TCP/UDP headers, if any, of received packets are
2340 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2341 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2342 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2343 * RSS output index which is used as the RX queue index where to store the
2345 * The following output is supplied in the RX write-back descriptor:
2346 * - 32-bit result of the Microsoft RSS hash function,
2347 * - 4-bit RSS type field.
2351 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2352 * Used as the default key.
2354 static uint8_t rss_intel_key[40] = {
2355 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2356 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2357 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2358 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2359 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2363 ixgbe_rss_disable(struct rte_eth_dev *dev)
2365 struct ixgbe_hw *hw;
2368 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2369 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2370 mrqc &= ~IXGBE_MRQC_RSSEN;
2371 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2375 ixgbe_rss_configure(struct rte_eth_dev *dev)
2377 struct ixgbe_hw *hw;
2386 PMD_INIT_FUNC_TRACE();
2387 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389 rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
2390 if (rss_hf == 0) { /* Disable RSS */
2391 ixgbe_rss_disable(dev);
2394 hash_key = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key;
2395 if (hash_key == NULL)
2396 hash_key = rss_intel_key; /* Default hash key */
2398 /* Fill in RSS hash key */
2399 for (i = 0; i < 10; i++) {
2400 rss_key = hash_key[(i * 4)];
2401 rss_key |= hash_key[(i * 4) + 1] << 8;
2402 rss_key |= hash_key[(i * 4) + 2] << 16;
2403 rss_key |= hash_key[(i * 4) + 3] << 24;
2404 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2407 /* Fill in redirection table */
2409 for (i = 0, j = 0; i < 128; i++, j++) {
2410 if (j == dev->data->nb_rx_queues) j = 0;
2411 reta = (reta << 8) | j;
2413 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), rte_bswap32(reta));
2416 /* Set configured hashing functions in MRQC register */
2417 mrqc = IXGBE_MRQC_RSSEN; /* RSS enable */
2418 if (rss_hf & ETH_RSS_IPV4)
2419 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2420 if (rss_hf & ETH_RSS_IPV4_TCP)
2421 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2422 if (rss_hf & ETH_RSS_IPV6)
2423 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2424 if (rss_hf & ETH_RSS_IPV6_EX)
2425 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2426 if (rss_hf & ETH_RSS_IPV6_TCP)
2427 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2428 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2429 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2430 if (rss_hf & ETH_RSS_IPV4_UDP)
2431 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2432 if (rss_hf & ETH_RSS_IPV6_UDP)
2433 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2434 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2435 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2436 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2439 #define NUM_VFTA_REGISTERS 128
2440 #define NIC_RX_BUFFER_SIZE 0x200
2443 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2445 struct rte_eth_vmdq_dcb_conf *cfg;
2446 struct ixgbe_hw *hw;
2447 enum rte_eth_nb_pools num_pools;
2448 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2450 uint8_t nb_tcs; /* number of traffic classes */
2453 PMD_INIT_FUNC_TRACE();
2454 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2455 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2456 num_pools = cfg->nb_queue_pools;
2457 /* Check we have a valid number of pools */
2458 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2459 ixgbe_rss_disable(dev);
2462 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2463 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2467 * split rx buffer up into sections, each for 1 traffic class
2469 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2470 for (i = 0 ; i < nb_tcs; i++) {
2471 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2472 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2473 /* clear 10 bits. */
2474 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2475 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2477 /* zero alloc all unused TCs */
2478 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2479 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2480 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2481 /* clear 10 bits. */
2482 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2485 /* MRQC: enable vmdq and dcb */
2486 mrqc = ((num_pools == ETH_16_POOLS) ? \
2487 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2488 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2490 /* PFVTCTL: turn on virtualisation and set the default pool */
2491 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2492 if (cfg->enable_default_pool) {
2493 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2495 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2498 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2500 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2502 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2504 * mapping is done with 3 bits per priority,
2505 * so shift by i*3 each time
2507 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2509 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2511 /* RTRPCS: DCB related */
2512 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2514 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2515 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2516 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2517 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2519 /* VFTA - enable all vlan filters */
2520 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2521 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2524 /* VFRE: pool enabling for receive - 16 or 32 */
2525 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2526 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2529 * MPSAR - allow pools to read specific mac addresses
2530 * In this case, all pools should be able to read from mac addr 0
2532 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2533 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2535 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2536 for (i = 0; i < cfg->nb_pool_maps; i++) {
2537 /* set vlan id in VF register and set the valid bit */
2538 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2539 (cfg->pool_map[i].vlan_id & 0xFFF)));
2541 * Put the allowed pools in VFB reg. As we only have 16 or 32
2542 * pools, we only need to use the first half of the register
2545 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2550 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2551 * @hw: pointer to hardware structure
2552 * @dcb_config: pointer to ixgbe_dcb_config structure
2555 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2556 struct ixgbe_dcb_config *dcb_config)
2561 PMD_INIT_FUNC_TRACE();
2562 if (hw->mac.type != ixgbe_mac_82598EB) {
2563 /* Disable the Tx desc arbiter so that MTQC can be changed */
2564 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2565 reg |= IXGBE_RTTDCS_ARBDIS;
2566 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2568 /* Enable DCB for Tx with 8 TCs */
2569 if (dcb_config->num_tcs.pg_tcs == 8) {
2570 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2573 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2575 if (dcb_config->vt_mode)
2576 reg |= IXGBE_MTQC_VT_ENA;
2577 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2579 /* Disable drop for all queues */
2580 for (q = 0; q < 128; q++)
2581 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2582 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2584 /* Enable the Tx desc arbiter */
2585 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2586 reg &= ~IXGBE_RTTDCS_ARBDIS;
2587 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2589 /* Enable Security TX Buffer IFG for DCB */
2590 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2591 reg |= IXGBE_SECTX_DCB;
2592 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2598 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2599 * @dev: pointer to rte_eth_dev structure
2600 * @dcb_config: pointer to ixgbe_dcb_config structure
2603 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2604 struct ixgbe_dcb_config *dcb_config)
2606 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2607 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2608 struct ixgbe_hw *hw =
2609 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2611 PMD_INIT_FUNC_TRACE();
2612 if (hw->mac.type != ixgbe_mac_82598EB)
2613 /*PF VF Transmit Enable*/
2614 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2615 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2617 /*Configure general DCB TX parameters*/
2618 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2623 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2624 struct ixgbe_dcb_config *dcb_config)
2626 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2627 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2628 struct ixgbe_dcb_tc_config *tc;
2631 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2632 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2633 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2634 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2637 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2638 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2640 /* User Priority to Traffic Class mapping */
2641 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2642 j = vmdq_rx_conf->dcb_queue[i];
2643 tc = &dcb_config->tc_config[j];
2644 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2650 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2651 struct ixgbe_dcb_config *dcb_config)
2653 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2654 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2655 struct ixgbe_dcb_tc_config *tc;
2658 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2659 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2660 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2661 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2664 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2665 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2668 /* User Priority to Traffic Class mapping */
2669 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2670 j = vmdq_tx_conf->dcb_queue[i];
2671 tc = &dcb_config->tc_config[j];
2672 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2679 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2680 struct ixgbe_dcb_config *dcb_config)
2682 struct rte_eth_dcb_rx_conf *rx_conf =
2683 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2684 struct ixgbe_dcb_tc_config *tc;
2687 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2688 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2690 /* User Priority to Traffic Class mapping */
2691 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2692 j = rx_conf->dcb_queue[i];
2693 tc = &dcb_config->tc_config[j];
2694 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2700 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2701 struct ixgbe_dcb_config *dcb_config)
2703 struct rte_eth_dcb_tx_conf *tx_conf =
2704 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2705 struct ixgbe_dcb_tc_config *tc;
2708 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2709 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2711 /* User Priority to Traffic Class mapping */
2712 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2713 j = tx_conf->dcb_queue[i];
2714 tc = &dcb_config->tc_config[j];
2715 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2721 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2722 * @hw: pointer to hardware structure
2723 * @dcb_config: pointer to ixgbe_dcb_config structure
2726 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2727 struct ixgbe_dcb_config *dcb_config)
2733 PMD_INIT_FUNC_TRACE();
2735 * Disable the arbiter before changing parameters
2736 * (always enable recycle mode; WSP)
2738 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2739 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2741 if (hw->mac.type != ixgbe_mac_82598EB) {
2742 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2743 if (dcb_config->num_tcs.pg_tcs == 4) {
2744 if (dcb_config->vt_mode)
2745 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2746 IXGBE_MRQC_VMDQRT4TCEN;
2748 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2749 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2753 if (dcb_config->num_tcs.pg_tcs == 8) {
2754 if (dcb_config->vt_mode)
2755 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2756 IXGBE_MRQC_VMDQRT8TCEN;
2758 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2759 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2764 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2767 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2768 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2769 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2770 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2772 /* VFTA - enable all vlan filters */
2773 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2774 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2778 * Configure Rx packet plane (recycle mode; WSP) and
2781 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2782 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2788 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2789 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2791 switch (hw->mac.type) {
2792 case ixgbe_mac_82598EB:
2793 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2795 case ixgbe_mac_82599EB:
2796 case ixgbe_mac_X540:
2797 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2806 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2807 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2809 switch (hw->mac.type) {
2810 case ixgbe_mac_82598EB:
2811 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2812 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2814 case ixgbe_mac_82599EB:
2815 case ixgbe_mac_X540:
2816 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2817 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2824 #define DCB_RX_CONFIG 1
2825 #define DCB_TX_CONFIG 1
2826 #define DCB_TX_PB 1024
2828 * ixgbe_dcb_hw_configure - Enable DCB and configure
2829 * general DCB in VT mode and non-VT mode parameters
2830 * @dev: pointer to rte_eth_dev structure
2831 * @dcb_config: pointer to ixgbe_dcb_config structure
2834 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2835 struct ixgbe_dcb_config *dcb_config)
2838 uint8_t i,pfc_en,nb_tcs;
2840 uint8_t config_dcb_rx = 0;
2841 uint8_t config_dcb_tx = 0;
2842 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2843 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2844 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2845 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2846 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2847 struct ixgbe_dcb_tc_config *tc;
2848 uint32_t max_frame = dev->data->max_frame_size;
2849 struct ixgbe_hw *hw =
2850 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2852 switch(dev->data->dev_conf.rxmode.mq_mode){
2853 case ETH_MQ_RX_VMDQ_DCB:
2854 dcb_config->vt_mode = true;
2855 if (hw->mac.type != ixgbe_mac_82598EB) {
2856 config_dcb_rx = DCB_RX_CONFIG;
2858 *get dcb and VT rx configuration parameters
2861 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2862 /*Configure general VMDQ and DCB RX parameters*/
2863 ixgbe_vmdq_dcb_configure(dev);
2867 dcb_config->vt_mode = false;
2868 config_dcb_rx = DCB_RX_CONFIG;
2869 /* Get dcb TX configuration parameters from rte_eth_conf */
2870 ixgbe_dcb_rx_config(dev,dcb_config);
2871 /*Configure general DCB RX parameters*/
2872 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2875 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration\n");
2878 switch (dev->data->dev_conf.txmode.mq_mode) {
2879 case ETH_MQ_TX_VMDQ_DCB:
2880 dcb_config->vt_mode = true;
2881 config_dcb_tx = DCB_TX_CONFIG;
2882 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2883 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2884 /*Configure general VMDQ and DCB TX parameters*/
2885 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2889 dcb_config->vt_mode = false;
2890 config_dcb_tx = DCB_TX_CONFIG;
2891 /*get DCB TX configuration parameters from rte_eth_conf*/
2892 ixgbe_dcb_tx_config(dev,dcb_config);
2893 /*Configure general DCB TX parameters*/
2894 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2897 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration\n");
2901 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2903 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2904 if(nb_tcs == ETH_4_TCS) {
2905 /* Avoid un-configured priority mapping to TC0 */
2907 uint8_t mask = 0xFF;
2908 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
2909 mask = (uint8_t)(mask & (~ (1 << map[i])));
2910 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
2911 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
2915 /* Re-configure 4 TCs BW */
2916 for (i = 0; i < nb_tcs; i++) {
2917 tc = &dcb_config->tc_config[i];
2918 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
2919 (uint8_t)(100 / nb_tcs);
2920 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
2921 (uint8_t)(100 / nb_tcs);
2923 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2924 tc = &dcb_config->tc_config[i];
2925 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
2926 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
2931 /* Set RX buffer size */
2932 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2933 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
2934 for (i = 0 ; i < nb_tcs; i++) {
2935 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2937 /* zero alloc all unused TCs */
2938 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2939 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
2943 /* Only support an equally distributed Tx packet buffer strategy. */
2944 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
2945 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
2946 for (i = 0; i < nb_tcs; i++) {
2947 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
2948 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
2950 /* Clear unused TCs, if any, to zero buffer size*/
2951 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2952 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
2953 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
2957 /*Calculates traffic class credits*/
2958 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2959 IXGBE_DCB_TX_CONFIG);
2960 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2961 IXGBE_DCB_RX_CONFIG);
2964 /* Unpack CEE standard containers */
2965 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
2966 ixgbe_dcb_unpack_max_cee(dcb_config, max);
2967 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
2968 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
2969 /* Configure PG(ETS) RX */
2970 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
2974 /* Unpack CEE standard containers */
2975 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
2976 ixgbe_dcb_unpack_max_cee(dcb_config, max);
2977 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
2978 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
2979 /* Configure PG(ETS) TX */
2980 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
2983 /*Configure queue statistics registers*/
2984 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
2986 /* Check if the PFC is supported */
2987 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
2988 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
2989 for (i = 0; i < nb_tcs; i++) {
2991 * If the TC count is 8,and the default high_water is 48,
2992 * the low_water is 16 as default.
2994 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
2995 hw->fc.low_water[i] = pbsize / 4;
2996 /* Enable pfc for this TC */
2997 tc = &dcb_config->tc_config[i];
2998 tc->pfc = ixgbe_dcb_pfc_enabled;
3000 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3001 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3003 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3010 * ixgbe_configure_dcb - Configure DCB Hardware
3011 * @dev: pointer to rte_eth_dev
3013 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3015 struct ixgbe_dcb_config *dcb_cfg =
3016 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3017 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3019 PMD_INIT_FUNC_TRACE();
3021 /* check support mq_mode for DCB */
3022 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) ||
3023 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3026 if ((dev_conf->txmode.mq_mode != ETH_MQ_TX_VMDQ_DCB) ||
3027 (dev_conf->txmode.mq_mode != ETH_MQ_TX_DCB))
3030 if ((dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES) ||
3031 (dev->data->nb_tx_queues != ETH_DCB_NUM_QUEUES))
3034 /** Configure DCB hardware **/
3035 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3041 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
3043 struct igb_rx_entry *rxe = rxq->sw_ring;
3047 /* Initialize software ring entries */
3048 for (i = 0; i < rxq->nb_rx_desc; i++) {
3049 volatile union ixgbe_adv_rx_desc *rxd;
3050 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3052 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u\n",
3053 (unsigned) rxq->queue_id);
3057 rte_mbuf_refcnt_set(mbuf, 1);
3058 mbuf->type = RTE_MBUF_PKT;
3059 mbuf->pkt.next = NULL;
3060 mbuf->pkt.data = (char *)mbuf->buf_addr + RTE_PKTMBUF_HEADROOM;
3061 mbuf->pkt.nb_segs = 1;
3062 mbuf->pkt.in_port = rxq->port_id;
3065 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3066 rxd = &rxq->rx_ring[i];
3067 rxd->read.hdr_addr = dma_addr;
3068 rxd->read.pkt_addr = dma_addr;
3076 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3078 struct ixgbe_hw *hw =
3079 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3081 if (hw->mac.type == ixgbe_mac_82598EB)
3084 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3086 * SRIOV inactive scheme
3087 * any DCB/RSS w/o VMDq multi-queue setting
3089 if (dev->data->nb_rx_queues > 1)
3090 switch (dev->data->dev_conf.rxmode.mq_mode) {
3091 case ETH_MQ_RX_NONE:
3092 /* if mq_mode not assign, we use rss mode.*/
3094 ixgbe_rss_configure(dev);
3097 case ETH_MQ_RX_VMDQ_DCB:
3098 ixgbe_vmdq_dcb_configure(dev);
3101 default: ixgbe_rss_disable(dev);
3104 ixgbe_rss_disable(dev);
3106 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3108 * SRIOV active scheme
3109 * FIXME if support DCB/RSS together with VMDq & SRIOV
3112 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQEN);
3116 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT4TCEN);
3120 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT8TCEN);
3123 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3131 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3133 struct ixgbe_hw *hw =
3134 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3138 if (hw->mac.type == ixgbe_mac_82598EB)
3141 /* disable arbiter before setting MTQC */
3142 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3143 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3144 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3146 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3148 * SRIOV inactive scheme
3149 * any DCB w/o VMDq multi-queue setting
3151 mtqc = IXGBE_MTQC_64Q_1PB;
3153 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3156 * SRIOV active scheme
3157 * FIXME if support DCB together with VMDq & SRIOV
3160 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3163 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3166 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3170 mtqc = IXGBE_MTQC_64Q_1PB;
3171 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3175 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3177 /* re-enable arbiter */
3178 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3179 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3185 * Initializes Receive Unit.
3188 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3190 struct ixgbe_hw *hw;
3191 struct igb_rx_queue *rxq;
3192 struct rte_pktmbuf_pool_private *mbp_priv;
3205 PMD_INIT_FUNC_TRACE();
3206 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3209 * Make sure receives are disabled while setting
3210 * up the RX context (registers, descriptor rings, etc.).
3212 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3213 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3215 /* Enable receipt of broadcasted frames */
3216 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3217 fctrl |= IXGBE_FCTRL_BAM;
3218 fctrl |= IXGBE_FCTRL_DPF;
3219 fctrl |= IXGBE_FCTRL_PMCF;
3220 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3223 * Configure CRC stripping, if any.
3225 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3226 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3227 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3229 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3232 * Configure jumbo frame support, if any.
3234 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3235 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3236 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3237 maxfrs &= 0x0000FFFF;
3238 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3239 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3241 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3243 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3245 /* Setup RX queues */
3246 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3247 rxq = dev->data->rx_queues[i];
3249 /* Allocate buffers for descriptor rings */
3250 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3255 * Reset crc_len in case it was changed after queue setup by a
3256 * call to configure.
3258 rxq->crc_len = (uint8_t)
3259 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3262 /* Setup the Base and Length of the Rx Descriptor Rings */
3263 bus_addr = rxq->rx_ring_phys_addr;
3264 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3265 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3266 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3267 (uint32_t)(bus_addr >> 32));
3268 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3269 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3270 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3271 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3273 /* Configure the SRRCTL register */
3274 #ifdef RTE_HEADER_SPLIT_ENABLE
3276 * Configure Header Split
3278 if (dev->data->dev_conf.rxmode.header_split) {
3279 if (hw->mac.type == ixgbe_mac_82599EB) {
3280 /* Must setup the PSRTYPE register */
3282 psrtype = IXGBE_PSRTYPE_TCPHDR |
3283 IXGBE_PSRTYPE_UDPHDR |
3284 IXGBE_PSRTYPE_IPV4HDR |
3285 IXGBE_PSRTYPE_IPV6HDR;
3286 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3288 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3289 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3290 IXGBE_SRRCTL_BSIZEHDR_MASK);
3291 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3294 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3296 /* Set if packets are dropped when no descriptors available */
3298 srrctl |= IXGBE_SRRCTL_DROP_EN;
3301 * Configure the RX buffer size in the BSIZEPACKET field of
3302 * the SRRCTL register of the queue.
3303 * The value is in 1 KB resolution. Valid values can be from
3306 mbp_priv = (struct rte_pktmbuf_pool_private *)
3307 ((char *)rxq->mb_pool + sizeof(struct rte_mempool));
3308 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3309 RTE_PKTMBUF_HEADROOM);
3310 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3311 IXGBE_SRRCTL_BSIZEPKT_MASK);
3312 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3314 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3315 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3317 /* It adds dual VLAN length for supporting dual VLAN */
3318 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3319 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3320 dev->data->scattered_rx = 1;
3321 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3326 * Device configured with multiple RX queues.
3328 ixgbe_dev_mq_rx_configure(dev);
3331 * Setup the Checksum Register.
3332 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3333 * Enable IP/L4 checkum computation by hardware if requested to do so.
3335 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3336 rxcsum |= IXGBE_RXCSUM_PCSD;
3337 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3338 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3340 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3342 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3344 if (hw->mac.type == ixgbe_mac_82599EB) {
3345 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3346 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3347 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3349 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3350 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3351 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3358 * Initializes Transmit Unit.
3361 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3363 struct ixgbe_hw *hw;
3364 struct igb_tx_queue *txq;
3370 PMD_INIT_FUNC_TRACE();
3371 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3373 /* Enable TX CRC (checksum offload requirement) */
3374 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3375 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
3376 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3378 /* Setup the Base and Length of the Tx Descriptor Rings */
3379 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3380 txq = dev->data->tx_queues[i];
3382 bus_addr = txq->tx_ring_phys_addr;
3383 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3384 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3385 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3386 (uint32_t)(bus_addr >> 32));
3387 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3388 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3389 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3390 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3391 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3394 * Disable Tx Head Writeback RO bit, since this hoses
3395 * bookkeeping if things aren't delivered in order.
3397 switch (hw->mac.type) {
3398 case ixgbe_mac_82598EB:
3399 txctrl = IXGBE_READ_REG(hw,
3400 IXGBE_DCA_TXCTRL(txq->reg_idx));
3401 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3402 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3406 case ixgbe_mac_82599EB:
3407 case ixgbe_mac_X540:
3409 txctrl = IXGBE_READ_REG(hw,
3410 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3411 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3412 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3418 /* Device configured with multiple TX queues. */
3419 ixgbe_dev_mq_tx_configure(dev);
3423 * Start Transmit and Receive Units.
3426 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3428 struct ixgbe_hw *hw;
3429 struct igb_tx_queue *txq;
3430 struct igb_rx_queue *rxq;
3438 PMD_INIT_FUNC_TRACE();
3439 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3441 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3442 txq = dev->data->tx_queues[i];
3443 /* Setup Transmit Threshold Registers */
3444 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3445 txdctl |= txq->pthresh & 0x7F;
3446 txdctl |= ((txq->hthresh & 0x7F) << 8);
3447 txdctl |= ((txq->wthresh & 0x7F) << 16);
3448 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3451 if (hw->mac.type != ixgbe_mac_82598EB) {
3452 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3453 dmatxctl |= IXGBE_DMATXCTL_TE;
3454 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3457 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3458 txq = dev->data->tx_queues[i];
3459 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3460 txdctl |= IXGBE_TXDCTL_ENABLE;
3461 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3463 /* Wait until TX Enable ready */
3464 if (hw->mac.type == ixgbe_mac_82599EB) {
3468 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3469 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3471 PMD_INIT_LOG(ERR, "Could not enable "
3472 "Tx Queue %d\n", i);
3475 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3476 rxq = dev->data->rx_queues[i];
3477 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3478 rxdctl |= IXGBE_RXDCTL_ENABLE;
3479 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3481 /* Wait until RX Enable ready */
3485 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3486 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3488 PMD_INIT_LOG(ERR, "Could not enable "
3489 "Rx Queue %d\n", i);
3491 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3494 /* Enable Receive engine */
3495 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3496 if (hw->mac.type == ixgbe_mac_82598EB)
3497 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3498 rxctrl |= IXGBE_RXCTRL_RXEN;
3499 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3504 * [VF] Initializes Receive Unit.
3507 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3509 struct ixgbe_hw *hw;
3510 struct igb_rx_queue *rxq;
3511 struct rte_pktmbuf_pool_private *mbp_priv;
3518 PMD_INIT_FUNC_TRACE();
3519 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3521 /* Setup RX queues */
3522 dev->rx_pkt_burst = ixgbe_recv_pkts;
3523 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3524 rxq = dev->data->rx_queues[i];
3526 /* Allocate buffers for descriptor rings */
3527 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3531 /* Setup the Base and Length of the Rx Descriptor Rings */
3532 bus_addr = rxq->rx_ring_phys_addr;
3534 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3535 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3536 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3537 (uint32_t)(bus_addr >> 32));
3538 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3539 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3540 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3541 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3544 /* Configure the SRRCTL register */
3545 #ifdef RTE_HEADER_SPLIT_ENABLE
3547 * Configure Header Split
3549 if (dev->data->dev_conf.rxmode.header_split) {
3551 /* Must setup the PSRTYPE register */
3553 psrtype = IXGBE_PSRTYPE_TCPHDR |
3554 IXGBE_PSRTYPE_UDPHDR |
3555 IXGBE_PSRTYPE_IPV4HDR |
3556 IXGBE_PSRTYPE_IPV6HDR;
3558 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
3560 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3561 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3562 IXGBE_SRRCTL_BSIZEHDR_MASK);
3563 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3566 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3568 /* Set if packets are dropped when no descriptors available */
3570 srrctl |= IXGBE_SRRCTL_DROP_EN;
3573 * Configure the RX buffer size in the BSIZEPACKET field of
3574 * the SRRCTL register of the queue.
3575 * The value is in 1 KB resolution. Valid values can be from
3578 mbp_priv = (struct rte_pktmbuf_pool_private *)
3579 ((char *)rxq->mb_pool + sizeof(struct rte_mempool));
3580 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3581 RTE_PKTMBUF_HEADROOM);
3582 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3583 IXGBE_SRRCTL_BSIZEPKT_MASK);
3586 * VF modification to write virtual function SRRCTL register
3588 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
3590 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3591 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3593 /* It adds dual VLAN length for supporting dual VLAN */
3594 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3595 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
3596 dev->data->scattered_rx = 1;
3597 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3605 * [VF] Initializes Transmit Unit.
3608 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
3610 struct ixgbe_hw *hw;
3611 struct igb_tx_queue *txq;
3616 PMD_INIT_FUNC_TRACE();
3617 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3619 /* Setup the Base and Length of the Tx Descriptor Rings */
3620 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3621 txq = dev->data->tx_queues[i];
3622 bus_addr = txq->tx_ring_phys_addr;
3623 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
3624 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3625 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
3626 (uint32_t)(bus_addr >> 32));
3627 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
3628 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3629 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3630 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
3631 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
3634 * Disable Tx Head Writeback RO bit, since this hoses
3635 * bookkeeping if things aren't delivered in order.
3637 txctrl = IXGBE_READ_REG(hw,
3638 IXGBE_VFDCA_TXCTRL(i));
3639 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3640 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
3646 * [VF] Start Transmit and Receive Units.
3649 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
3651 struct ixgbe_hw *hw;
3652 struct igb_tx_queue *txq;
3653 struct igb_rx_queue *rxq;
3659 PMD_INIT_FUNC_TRACE();
3660 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3662 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3663 txq = dev->data->tx_queues[i];
3664 /* Setup Transmit Threshold Registers */
3665 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3666 txdctl |= txq->pthresh & 0x7F;
3667 txdctl |= ((txq->hthresh & 0x7F) << 8);
3668 txdctl |= ((txq->wthresh & 0x7F) << 16);
3669 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
3672 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3674 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3675 txdctl |= IXGBE_TXDCTL_ENABLE;
3676 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
3679 /* Wait until TX Enable ready */
3682 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3683 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3685 PMD_INIT_LOG(ERR, "Could not enable "
3686 "Tx Queue %d\n", i);
3688 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3690 rxq = dev->data->rx_queues[i];
3692 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
3693 rxdctl |= IXGBE_RXDCTL_ENABLE;
3694 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
3696 /* Wait until RX Enable ready */
3700 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
3701 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3703 PMD_INIT_LOG(ERR, "Could not enable "
3704 "Rx Queue %d\n", i);
3706 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);