4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
47 #include <rte_cycles.h>
49 #include <rte_debug.h>
50 #include <rte_interrupts.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_launch.h>
55 #include <rte_tailq.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
80 #include "ixgbe_rxtx.h"
82 #define IXGBE_RSS_OFFLOAD_ALL ( \
88 ETH_RSS_IPV6_TCP_EX | \
93 static inline struct rte_mbuf *
94 rte_rxmbuf_alloc(struct rte_mempool *mp)
98 m = __rte_mbuf_raw_alloc(mp);
99 __rte_mbuf_sanity_check_raw(m, 0);
105 #define RTE_PMD_USE_PREFETCH
108 #ifdef RTE_PMD_USE_PREFETCH
110 * Prefetch a cache line into all cache levels.
112 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
114 #define rte_ixgbe_prefetch(p) do {} while(0)
117 /*********************************************************************
121 **********************************************************************/
124 * Check for descriptors with their DD bit set and free mbufs.
125 * Return the total number of buffers freed.
127 static inline int __attribute__((always_inline))
128 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
130 struct igb_tx_entry *txep;
134 /* check DD bit on threshold descriptor */
135 status = txq->tx_ring[txq->tx_next_dd].wb.status;
136 if (! (status & IXGBE_ADVTXD_STAT_DD))
140 * first buffer to free from S/W ring is at index
141 * tx_next_dd - (tx_rs_thresh-1)
143 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
145 /* free buffers one at a time */
146 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
147 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
148 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
152 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
153 rte_pktmbuf_free_seg(txep->mbuf);
158 /* buffers were freed, update counters */
159 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
160 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
161 if (txq->tx_next_dd >= txq->nb_tx_desc)
162 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
164 return txq->tx_rs_thresh;
167 /* Populate 4 descriptors with data from 4 mbufs */
169 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
171 uint64_t buf_dma_addr;
175 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
176 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
177 pkt_len = (*pkts)->data_len;
179 /* write data to descriptor */
180 txdp->read.buffer_addr = buf_dma_addr;
181 txdp->read.cmd_type_len =
182 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
183 txdp->read.olinfo_status =
184 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
185 rte_prefetch0(&(*pkts)->pool);
189 /* Populate 1 descriptor with data from 1 mbuf */
191 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
193 uint64_t buf_dma_addr;
196 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
197 pkt_len = (*pkts)->data_len;
199 /* write data to descriptor */
200 txdp->read.buffer_addr = buf_dma_addr;
201 txdp->read.cmd_type_len =
202 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
203 txdp->read.olinfo_status =
204 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
205 rte_prefetch0(&(*pkts)->pool);
209 * Fill H/W descriptor ring with mbuf data.
210 * Copy mbuf pointers to the S/W ring.
213 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
216 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
217 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
218 const int N_PER_LOOP = 4;
219 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
220 int mainpart, leftover;
224 * Process most of the packets in chunks of N pkts. Any
225 * leftover packets will get processed one at a time.
227 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
228 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
229 for (i = 0; i < mainpart; i += N_PER_LOOP) {
230 /* Copy N mbuf pointers to the S/W ring */
231 for (j = 0; j < N_PER_LOOP; ++j) {
232 (txep + i + j)->mbuf = *(pkts + i + j);
234 tx4(txdp + i, pkts + i);
237 if (unlikely(leftover > 0)) {
238 for (i = 0; i < leftover; ++i) {
239 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
240 tx1(txdp + mainpart + i, pkts + mainpart + i);
245 static inline uint16_t
246 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
249 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
250 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
254 * Begin scanning the H/W ring for done descriptors when the
255 * number of available descriptors drops below tx_free_thresh. For
256 * each done descriptor, free the associated buffer.
258 if (txq->nb_tx_free < txq->tx_free_thresh)
259 ixgbe_tx_free_bufs(txq);
261 /* Only use descriptors that are available */
262 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
263 if (unlikely(nb_pkts == 0))
266 /* Use exactly nb_pkts descriptors */
267 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
270 * At this point, we know there are enough descriptors in the
271 * ring to transmit all the packets. This assumes that each
272 * mbuf contains a single segment, and that no new offloads
273 * are expected, which would require a new context descriptor.
277 * See if we're going to wrap-around. If so, handle the top
278 * of the descriptor ring first, then do the bottom. If not,
279 * the processing looks just like the "bottom" part anyway...
281 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
282 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
283 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
286 * We know that the last descriptor in the ring will need to
287 * have its RS bit set because tx_rs_thresh has to be
288 * a divisor of the ring size
290 tx_r[txq->tx_next_rs].read.cmd_type_len |=
291 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
292 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
297 /* Fill H/W descriptor ring with mbuf data */
298 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
299 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
302 * Determine if RS bit should be set
303 * This is what we actually want:
304 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
305 * but instead of subtracting 1 and doing >=, we can just do
306 * greater than without subtracting.
308 if (txq->tx_tail > txq->tx_next_rs) {
309 tx_r[txq->tx_next_rs].read.cmd_type_len |=
310 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
311 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
313 if (txq->tx_next_rs >= txq->nb_tx_desc)
314 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
318 * Check for wrap-around. This would only happen if we used
319 * up to the last descriptor in the ring, no more, no less.
321 if (txq->tx_tail >= txq->nb_tx_desc)
324 /* update tail pointer */
326 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
332 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
337 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
338 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
339 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
341 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
345 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
346 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
347 nb_tx = (uint16_t)(nb_tx + ret);
348 nb_pkts = (uint16_t)(nb_pkts - ret);
357 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
358 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
359 uint64_t ol_flags, uint32_t vlan_macip_lens)
361 uint32_t type_tucmd_mlhl;
362 uint32_t mss_l4len_idx;
366 ctx_idx = txq->ctx_curr;
370 if (ol_flags & PKT_TX_VLAN_PKT) {
371 cmp_mask |= TX_VLAN_CMP_MASK;
374 if (ol_flags & PKT_TX_IP_CKSUM) {
375 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
376 cmp_mask |= TX_MAC_LEN_CMP_MASK;
379 /* Specify which HW CTX to upload. */
380 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
381 switch (ol_flags & PKT_TX_L4_MASK) {
382 case PKT_TX_UDP_CKSUM:
383 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
384 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
385 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
386 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
388 case PKT_TX_TCP_CKSUM:
389 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
390 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
391 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
392 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
394 case PKT_TX_SCTP_CKSUM:
395 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
396 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
397 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
398 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
401 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
402 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
406 txq->ctx_cache[ctx_idx].flags = ol_flags;
407 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
408 txq->ctx_cache[ctx_idx].vlan_macip_lens.data =
409 vlan_macip_lens & cmp_mask;
411 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
412 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
413 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
414 ctx_txd->seqnum_seed = 0;
418 * Check which hardware context can be used. Use the existing match
419 * or create a new context descriptor.
421 static inline uint32_t
422 what_advctx_update(struct igb_tx_queue *txq, uint64_t flags,
423 uint32_t vlan_macip_lens)
425 /* If match with the current used context */
426 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
427 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
428 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
429 return txq->ctx_curr;
432 /* What if match with the next context */
434 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
435 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
436 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
437 return txq->ctx_curr;
440 /* Mismatch, use the previous context */
441 return (IXGBE_CTX_NUM);
444 static inline uint32_t
445 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
447 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
448 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
451 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
452 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
456 static inline uint32_t
457 tx_desc_vlan_flags_to_cmdtype(uint64_t ol_flags)
459 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
460 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
463 /* Default RS bit threshold values */
464 #ifndef DEFAULT_TX_RS_THRESH
465 #define DEFAULT_TX_RS_THRESH 32
467 #ifndef DEFAULT_TX_FREE_THRESH
468 #define DEFAULT_TX_FREE_THRESH 32
471 /* Reset transmit descriptors after they have been used */
473 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
475 struct igb_tx_entry *sw_ring = txq->sw_ring;
476 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
477 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
478 uint16_t nb_tx_desc = txq->nb_tx_desc;
479 uint16_t desc_to_clean_to;
480 uint16_t nb_tx_to_clean;
482 /* Determine the last descriptor needing to be cleaned */
483 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
484 if (desc_to_clean_to >= nb_tx_desc)
485 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
487 /* Check to make sure the last descriptor to clean is done */
488 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
489 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
491 PMD_TX_FREE_LOG(DEBUG,
492 "TX descriptor %4u is not done"
493 "(port=%d queue=%d)",
495 txq->port_id, txq->queue_id);
496 /* Failed to clean any descriptors, better luck next time */
500 /* Figure out how many descriptors will be cleaned */
501 if (last_desc_cleaned > desc_to_clean_to)
502 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
505 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
508 PMD_TX_FREE_LOG(DEBUG,
509 "Cleaning %4u TX descriptors: %4u to %4u "
510 "(port=%d queue=%d)",
511 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
512 txq->port_id, txq->queue_id);
515 * The last descriptor to clean is done, so that means all the
516 * descriptors from the last descriptor that was cleaned
517 * up to the last descriptor with the RS bit set
518 * are done. Only reset the threshold descriptor.
520 txr[desc_to_clean_to].wb.status = 0;
522 /* Update the txq to reflect the last descriptor that was cleaned */
523 txq->last_desc_cleaned = desc_to_clean_to;
524 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
531 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
534 struct igb_tx_queue *txq;
535 struct igb_tx_entry *sw_ring;
536 struct igb_tx_entry *txe, *txn;
537 volatile union ixgbe_adv_tx_desc *txr;
538 volatile union ixgbe_adv_tx_desc *txd;
539 struct rte_mbuf *tx_pkt;
540 struct rte_mbuf *m_seg;
541 union ixgbe_vlan_macip vlan_macip_lens;
542 uint64_t buf_dma_addr;
543 uint32_t olinfo_status;
544 uint32_t cmd_type_len;
557 sw_ring = txq->sw_ring;
559 tx_id = txq->tx_tail;
560 txe = &sw_ring[tx_id];
562 /* Determine if the descriptor ring needs to be cleaned. */
563 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
564 ixgbe_xmit_cleanup(txq);
568 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
571 pkt_len = tx_pkt->pkt_len;
573 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
576 * Determine how many (if any) context descriptors
577 * are needed for offload functionality.
579 ol_flags = tx_pkt->ol_flags;
580 vlan_macip_lens.f.vlan_tci = tx_pkt->vlan_tci;
581 vlan_macip_lens.f.l2_l3_len = tx_pkt->l2_l3_len;
583 /* If hardware offload required */
584 tx_ol_req = ol_flags & PKT_TX_OFFLOAD_MASK;
586 /* If new context need be built or reuse the exist ctx. */
587 ctx = what_advctx_update(txq, tx_ol_req,
588 vlan_macip_lens.data);
589 /* Only allocate context descriptor if required*/
590 new_ctx = (ctx == IXGBE_CTX_NUM);
595 * Keep track of how many descriptors are used this loop
596 * This will always be the number of segments + the number of
597 * Context descriptors required to transmit the packet
599 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
602 * The number of descriptors that must be allocated for a
603 * packet is the number of segments of that packet, plus 1
604 * Context Descriptor for the hardware offload, if any.
605 * Determine the last TX descriptor to allocate in the TX ring
606 * for the packet, starting from the current position (tx_id)
609 tx_last = (uint16_t) (tx_id + nb_used - 1);
612 if (tx_last >= txq->nb_tx_desc)
613 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
615 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
616 " tx_first=%u tx_last=%u",
617 (unsigned) txq->port_id,
618 (unsigned) txq->queue_id,
624 * Make sure there are enough TX descriptors available to
625 * transmit the entire packet.
626 * nb_used better be less than or equal to txq->tx_rs_thresh
628 if (nb_used > txq->nb_tx_free) {
629 PMD_TX_FREE_LOG(DEBUG,
630 "Not enough free TX descriptors "
631 "nb_used=%4u nb_free=%4u "
632 "(port=%d queue=%d)",
633 nb_used, txq->nb_tx_free,
634 txq->port_id, txq->queue_id);
636 if (ixgbe_xmit_cleanup(txq) != 0) {
637 /* Could not clean any descriptors */
643 /* nb_used better be <= txq->tx_rs_thresh */
644 if (unlikely(nb_used > txq->tx_rs_thresh)) {
645 PMD_TX_FREE_LOG(DEBUG,
646 "The number of descriptors needed to "
647 "transmit the packet exceeds the "
648 "RS bit threshold. This will impact "
650 "nb_used=%4u nb_free=%4u "
652 "(port=%d queue=%d)",
653 nb_used, txq->nb_tx_free,
655 txq->port_id, txq->queue_id);
657 * Loop here until there are enough TX
658 * descriptors or until the ring cannot be
661 while (nb_used > txq->nb_tx_free) {
662 if (ixgbe_xmit_cleanup(txq) != 0) {
664 * Could not clean any
676 * By now there are enough free TX descriptors to transmit
681 * Set common flags of all TX Data Descriptors.
683 * The following bits must be set in all Data Descriptors:
684 * - IXGBE_ADVTXD_DTYP_DATA
685 * - IXGBE_ADVTXD_DCMD_DEXT
687 * The following bits must be set in the first Data Descriptor
688 * and are ignored in the other ones:
689 * - IXGBE_ADVTXD_DCMD_IFCS
690 * - IXGBE_ADVTXD_MAC_1588
691 * - IXGBE_ADVTXD_DCMD_VLE
693 * The following bits must only be set in the last Data
695 * - IXGBE_TXD_CMD_EOP
697 * The following bits can be set in any Data Descriptor, but
698 * are only set in the last Data Descriptor:
701 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
702 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
703 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
704 #ifdef RTE_LIBRTE_IEEE1588
705 if (ol_flags & PKT_TX_IEEE1588_TMST)
706 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
711 * Setup the TX Advanced Context Descriptor if required
714 volatile struct ixgbe_adv_tx_context_desc *
717 ctx_txd = (volatile struct
718 ixgbe_adv_tx_context_desc *)
721 txn = &sw_ring[txe->next_id];
722 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
724 if (txe->mbuf != NULL) {
725 rte_pktmbuf_free_seg(txe->mbuf);
729 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
730 vlan_macip_lens.data);
732 txe->last_id = tx_last;
733 tx_id = txe->next_id;
738 * Setup the TX Advanced Data Descriptor,
739 * This path will go through
740 * whatever new/reuse the context descriptor
742 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
743 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
744 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
750 txn = &sw_ring[txe->next_id];
752 if (txe->mbuf != NULL)
753 rte_pktmbuf_free_seg(txe->mbuf);
757 * Set up Transmit Data Descriptor.
759 slen = m_seg->data_len;
760 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
761 txd->read.buffer_addr =
762 rte_cpu_to_le_64(buf_dma_addr);
763 txd->read.cmd_type_len =
764 rte_cpu_to_le_32(cmd_type_len | slen);
765 txd->read.olinfo_status =
766 rte_cpu_to_le_32(olinfo_status);
767 txe->last_id = tx_last;
768 tx_id = txe->next_id;
771 } while (m_seg != NULL);
774 * The last packet data descriptor needs End Of Packet (EOP)
776 cmd_type_len |= IXGBE_TXD_CMD_EOP;
777 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
778 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
780 /* Set RS bit only on threshold packets' last descriptor */
781 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
782 PMD_TX_FREE_LOG(DEBUG,
783 "Setting RS bit on TXD id="
784 "%4u (port=%d queue=%d)",
785 tx_last, txq->port_id, txq->queue_id);
787 cmd_type_len |= IXGBE_TXD_CMD_RS;
789 /* Update txq RS bit counters */
792 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
798 * Set the Transmit Descriptor Tail (TDT)
800 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
801 (unsigned) txq->port_id, (unsigned) txq->queue_id,
802 (unsigned) tx_id, (unsigned) nb_tx);
803 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
804 txq->tx_tail = tx_id;
809 /*********************************************************************
813 **********************************************************************/
814 static inline uint64_t
815 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
819 static uint64_t ip_pkt_types_map[16] = {
820 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
821 PKT_RX_IPV6_HDR, 0, 0, 0,
822 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
823 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
826 static uint64_t ip_rss_types_map[16] = {
827 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
828 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
829 PKT_RX_RSS_HASH, 0, 0, 0,
830 0, 0, 0, PKT_RX_FDIR,
833 #ifdef RTE_LIBRTE_IEEE1588
834 static uint32_t ip_pkt_etqf_map[8] = {
835 0, 0, 0, PKT_RX_IEEE1588_PTP,
839 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
840 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
841 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
843 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
844 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
847 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
850 static inline uint64_t
851 rx_desc_status_to_pkt_flags(uint32_t rx_status)
856 * Check if VLAN present only.
857 * Do not check whether L3/L4 rx checksum done by NIC or not,
858 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
860 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
862 #ifdef RTE_LIBRTE_IEEE1588
863 if (rx_status & IXGBE_RXD_STAT_TMST)
864 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
869 static inline uint64_t
870 rx_desc_error_to_pkt_flags(uint32_t rx_status)
873 * Bit 31: IPE, IPv4 checksum error
874 * Bit 30: L4I, L4I integrity error
876 static uint64_t error_to_pkt_flags_map[4] = {
877 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
878 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
880 return error_to_pkt_flags_map[(rx_status >>
881 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
884 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
886 * LOOK_AHEAD defines how many desc statuses to check beyond the
887 * current descriptor.
888 * It must be a pound define for optimal performance.
889 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
890 * function only works with LOOK_AHEAD=8.
893 #if (LOOK_AHEAD != 8)
894 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
897 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
899 volatile union ixgbe_adv_rx_desc *rxdp;
900 struct igb_rx_entry *rxep;
904 int s[LOOK_AHEAD], nb_dd;
908 /* get references to current descriptor and S/W ring entry */
909 rxdp = &rxq->rx_ring[rxq->rx_tail];
910 rxep = &rxq->sw_ring[rxq->rx_tail];
912 /* check to make sure there is at least 1 packet to receive */
913 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
917 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
918 * reference packets that are ready to be received.
920 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
921 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
923 /* Read desc statuses backwards to avoid race condition */
924 for (j = LOOK_AHEAD-1; j >= 0; --j)
925 s[j] = rxdp[j].wb.upper.status_error;
927 /* Compute how many status bits were set */
929 for (j = 0; j < LOOK_AHEAD; ++j)
930 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
934 /* Translate descriptor info to mbuf format */
935 for (j = 0; j < nb_dd; ++j) {
937 pkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len);
938 mb->data_len = pkt_len;
939 mb->pkt_len = pkt_len;
940 mb->vlan_tci = rxdp[j].wb.upper.vlan;
941 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
943 /* convert descriptor fields to rte mbuf flags */
944 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(
945 rxdp[j].wb.lower.lo_dword.data);
946 /* reuse status field from scan list */
947 pkt_flags |= rx_desc_status_to_pkt_flags(s[j]);
948 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
949 mb->ol_flags = pkt_flags;
951 if (likely(pkt_flags & PKT_RX_RSS_HASH))
952 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
953 else if (pkt_flags & PKT_RX_FDIR) {
955 (uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum)
956 & IXGBE_ATR_HASH_MASK);
957 mb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id;
961 /* Move mbuf pointers from the S/W ring to the stage */
962 for (j = 0; j < LOOK_AHEAD; ++j) {
963 rxq->rx_stage[i + j] = rxep[j].mbuf;
966 /* stop if all requested packets could not be received */
967 if (nb_dd != LOOK_AHEAD)
971 /* clear software ring entries so we can cleanup correctly */
972 for (i = 0; i < nb_rx; ++i) {
973 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
981 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
983 volatile union ixgbe_adv_rx_desc *rxdp;
984 struct igb_rx_entry *rxep;
990 /* allocate buffers in bulk directly into the S/W ring */
991 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
992 (rxq->rx_free_thresh - 1));
993 rxep = &rxq->sw_ring[alloc_idx];
994 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
995 rxq->rx_free_thresh);
996 if (unlikely(diag != 0))
999 rxdp = &rxq->rx_ring[alloc_idx];
1000 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1001 /* populate the static rte mbuf fields */
1003 rte_mbuf_refcnt_set(mb, 1);
1005 mb->data_off = RTE_PKTMBUF_HEADROOM;
1007 mb->port = rxq->port_id;
1009 /* populate the descriptors */
1010 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1011 rxdp[i].read.hdr_addr = dma_addr;
1012 rxdp[i].read.pkt_addr = dma_addr;
1015 /* update tail pointer */
1017 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1019 /* update state of internal queue structure */
1020 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1021 rxq->rx_free_thresh);
1022 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1023 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1029 static inline uint16_t
1030 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1033 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1036 /* how many packets are ready to return? */
1037 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1039 /* copy mbuf pointers to the application's packet list */
1040 for (i = 0; i < nb_pkts; ++i)
1041 rx_pkts[i] = stage[i];
1043 /* update internal queue state */
1044 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1045 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1050 static inline uint16_t
1051 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1054 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1057 /* Any previously recv'd pkts will be returned from the Rx stage */
1058 if (rxq->rx_nb_avail)
1059 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1061 /* Scan the H/W ring for packets to receive */
1062 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1064 /* update internal queue state */
1065 rxq->rx_next_avail = 0;
1066 rxq->rx_nb_avail = nb_rx;
1067 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1069 /* if required, allocate new buffers to replenish descriptors */
1070 if (rxq->rx_tail > rxq->rx_free_trigger) {
1071 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1073 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1074 "queue_id=%u", (unsigned) rxq->port_id,
1075 (unsigned) rxq->queue_id);
1077 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1078 rxq->rx_free_thresh;
1081 * Need to rewind any previous receives if we cannot
1082 * allocate new buffers to replenish the old ones.
1084 rxq->rx_nb_avail = 0;
1085 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1086 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1087 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1093 if (rxq->rx_tail >= rxq->nb_rx_desc)
1096 /* received any packets this loop? */
1097 if (rxq->rx_nb_avail)
1098 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1103 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1105 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1110 if (unlikely(nb_pkts == 0))
1113 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1114 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1116 /* request is relatively large, chunk it up */
1120 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1121 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1122 nb_rx = (uint16_t)(nb_rx + ret);
1123 nb_pkts = (uint16_t)(nb_pkts - ret);
1130 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1133 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1136 struct igb_rx_queue *rxq;
1137 volatile union ixgbe_adv_rx_desc *rx_ring;
1138 volatile union ixgbe_adv_rx_desc *rxdp;
1139 struct igb_rx_entry *sw_ring;
1140 struct igb_rx_entry *rxe;
1141 struct rte_mbuf *rxm;
1142 struct rte_mbuf *nmb;
1143 union ixgbe_adv_rx_desc rxd;
1146 uint32_t hlen_type_rss;
1156 rx_id = rxq->rx_tail;
1157 rx_ring = rxq->rx_ring;
1158 sw_ring = rxq->sw_ring;
1159 while (nb_rx < nb_pkts) {
1161 * The order of operations here is important as the DD status
1162 * bit must not be read after any other descriptor fields.
1163 * rx_ring and rxdp are pointing to volatile data so the order
1164 * of accesses cannot be reordered by the compiler. If they were
1165 * not volatile, they could be reordered which could lead to
1166 * using invalid descriptor fields when read from rxd.
1168 rxdp = &rx_ring[rx_id];
1169 staterr = rxdp->wb.upper.status_error;
1170 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1177 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1178 * is likely to be invalid and to be dropped by the various
1179 * validation checks performed by the network stack.
1181 * Allocate a new mbuf to replenish the RX ring descriptor.
1182 * If the allocation fails:
1183 * - arrange for that RX descriptor to be the first one
1184 * being parsed the next time the receive function is
1185 * invoked [on the same queue].
1187 * - Stop parsing the RX ring and return immediately.
1189 * This policy do not drop the packet received in the RX
1190 * descriptor for which the allocation of a new mbuf failed.
1191 * Thus, it allows that packet to be later retrieved if
1192 * mbuf have been freed in the mean time.
1193 * As a side effect, holding RX descriptors instead of
1194 * systematically giving them back to the NIC may lead to
1195 * RX ring exhaustion situations.
1196 * However, the NIC can gracefully prevent such situations
1197 * to happen by sending specific "back-pressure" flow control
1198 * frames to its peer(s).
1200 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1201 "ext_err_stat=0x%08x pkt_len=%u",
1202 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1203 (unsigned) rx_id, (unsigned) staterr,
1204 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1206 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1208 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1209 "queue_id=%u", (unsigned) rxq->port_id,
1210 (unsigned) rxq->queue_id);
1211 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1216 rxe = &sw_ring[rx_id];
1218 if (rx_id == rxq->nb_rx_desc)
1221 /* Prefetch next mbuf while processing current one. */
1222 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1225 * When next RX descriptor is on a cache-line boundary,
1226 * prefetch the next 4 RX descriptors and the next 8 pointers
1229 if ((rx_id & 0x3) == 0) {
1230 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1231 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1237 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1238 rxdp->read.hdr_addr = dma_addr;
1239 rxdp->read.pkt_addr = dma_addr;
1242 * Initialize the returned mbuf.
1243 * 1) setup generic mbuf fields:
1244 * - number of segments,
1247 * - RX port identifier.
1248 * 2) integrate hardware offload data, if any:
1249 * - RSS flag & hash,
1250 * - IP checksum flag,
1251 * - VLAN TCI, if any,
1254 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1256 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1257 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1260 rxm->pkt_len = pkt_len;
1261 rxm->data_len = pkt_len;
1262 rxm->port = rxq->port_id;
1264 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1265 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1266 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1268 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1269 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1270 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1271 rxm->ol_flags = pkt_flags;
1273 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1274 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1275 else if (pkt_flags & PKT_RX_FDIR) {
1276 rxm->hash.fdir.hash =
1277 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1278 & IXGBE_ATR_HASH_MASK);
1279 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1282 * Store the mbuf address into the next entry of the array
1283 * of returned packets.
1285 rx_pkts[nb_rx++] = rxm;
1287 rxq->rx_tail = rx_id;
1290 * If the number of free RX descriptors is greater than the RX free
1291 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1293 * Update the RDT with the value of the last processed RX descriptor
1294 * minus 1, to guarantee that the RDT register is never equal to the
1295 * RDH register, which creates a "full" ring situtation from the
1296 * hardware point of view...
1298 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1299 if (nb_hold > rxq->rx_free_thresh) {
1300 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1301 "nb_hold=%u nb_rx=%u",
1302 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1303 (unsigned) rx_id, (unsigned) nb_hold,
1305 rx_id = (uint16_t) ((rx_id == 0) ?
1306 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1307 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1310 rxq->nb_rx_hold = nb_hold;
1315 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1318 struct igb_rx_queue *rxq;
1319 volatile union ixgbe_adv_rx_desc *rx_ring;
1320 volatile union ixgbe_adv_rx_desc *rxdp;
1321 struct igb_rx_entry *sw_ring;
1322 struct igb_rx_entry *rxe;
1323 struct rte_mbuf *first_seg;
1324 struct rte_mbuf *last_seg;
1325 struct rte_mbuf *rxm;
1326 struct rte_mbuf *nmb;
1327 union ixgbe_adv_rx_desc rxd;
1328 uint64_t dma; /* Physical address of mbuf data buffer */
1330 uint32_t hlen_type_rss;
1340 rx_id = rxq->rx_tail;
1341 rx_ring = rxq->rx_ring;
1342 sw_ring = rxq->sw_ring;
1345 * Retrieve RX context of current packet, if any.
1347 first_seg = rxq->pkt_first_seg;
1348 last_seg = rxq->pkt_last_seg;
1350 while (nb_rx < nb_pkts) {
1353 * The order of operations here is important as the DD status
1354 * bit must not be read after any other descriptor fields.
1355 * rx_ring and rxdp are pointing to volatile data so the order
1356 * of accesses cannot be reordered by the compiler. If they were
1357 * not volatile, they could be reordered which could lead to
1358 * using invalid descriptor fields when read from rxd.
1360 rxdp = &rx_ring[rx_id];
1361 staterr = rxdp->wb.upper.status_error;
1362 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1369 * Allocate a new mbuf to replenish the RX ring descriptor.
1370 * If the allocation fails:
1371 * - arrange for that RX descriptor to be the first one
1372 * being parsed the next time the receive function is
1373 * invoked [on the same queue].
1375 * - Stop parsing the RX ring and return immediately.
1377 * This policy does not drop the packet received in the RX
1378 * descriptor for which the allocation of a new mbuf failed.
1379 * Thus, it allows that packet to be later retrieved if
1380 * mbuf have been freed in the mean time.
1381 * As a side effect, holding RX descriptors instead of
1382 * systematically giving them back to the NIC may lead to
1383 * RX ring exhaustion situations.
1384 * However, the NIC can gracefully prevent such situations
1385 * to happen by sending specific "back-pressure" flow control
1386 * frames to its peer(s).
1388 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1389 "staterr=0x%x data_len=%u",
1390 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1391 (unsigned) rx_id, (unsigned) staterr,
1392 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1394 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1396 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1397 "queue_id=%u", (unsigned) rxq->port_id,
1398 (unsigned) rxq->queue_id);
1399 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1404 rxe = &sw_ring[rx_id];
1406 if (rx_id == rxq->nb_rx_desc)
1409 /* Prefetch next mbuf while processing current one. */
1410 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1413 * When next RX descriptor is on a cache-line boundary,
1414 * prefetch the next 4 RX descriptors and the next 8 pointers
1417 if ((rx_id & 0x3) == 0) {
1418 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1419 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1423 * Update RX descriptor with the physical address of the new
1424 * data buffer of the new allocated mbuf.
1428 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1429 rxdp->read.hdr_addr = dma;
1430 rxdp->read.pkt_addr = dma;
1433 * Set data length & data buffer address of mbuf.
1435 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1436 rxm->data_len = data_len;
1437 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1440 * If this is the first buffer of the received packet,
1441 * set the pointer to the first mbuf of the packet and
1442 * initialize its context.
1443 * Otherwise, update the total length and the number of segments
1444 * of the current scattered packet, and update the pointer to
1445 * the last mbuf of the current packet.
1447 if (first_seg == NULL) {
1449 first_seg->pkt_len = data_len;
1450 first_seg->nb_segs = 1;
1452 first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
1454 first_seg->nb_segs++;
1455 last_seg->next = rxm;
1459 * If this is not the last buffer of the received packet,
1460 * update the pointer to the last mbuf of the current scattered
1461 * packet and continue to parse the RX ring.
1463 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1469 * This is the last buffer of the received packet.
1470 * If the CRC is not stripped by the hardware:
1471 * - Subtract the CRC length from the total packet length.
1472 * - If the last buffer only contains the whole CRC or a part
1473 * of it, free the mbuf associated to the last buffer.
1474 * If part of the CRC is also contained in the previous
1475 * mbuf, subtract the length of that CRC part from the
1476 * data length of the previous mbuf.
1479 if (unlikely(rxq->crc_len > 0)) {
1480 first_seg->pkt_len -= ETHER_CRC_LEN;
1481 if (data_len <= ETHER_CRC_LEN) {
1482 rte_pktmbuf_free_seg(rxm);
1483 first_seg->nb_segs--;
1484 last_seg->data_len = (uint16_t)
1485 (last_seg->data_len -
1486 (ETHER_CRC_LEN - data_len));
1487 last_seg->next = NULL;
1490 (uint16_t) (data_len - ETHER_CRC_LEN);
1494 * Initialize the first mbuf of the returned packet:
1495 * - RX port identifier,
1496 * - hardware offload data, if any:
1497 * - RSS flag & hash,
1498 * - IP checksum flag,
1499 * - VLAN TCI, if any,
1502 first_seg->port = rxq->port_id;
1505 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1506 * set in the pkt_flags field.
1508 first_seg->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1509 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1510 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1511 pkt_flags = (uint16_t)(pkt_flags |
1512 rx_desc_status_to_pkt_flags(staterr));
1513 pkt_flags = (uint16_t)(pkt_flags |
1514 rx_desc_error_to_pkt_flags(staterr));
1515 first_seg->ol_flags = pkt_flags;
1517 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1518 first_seg->hash.rss = rxd.wb.lower.hi_dword.rss;
1519 else if (pkt_flags & PKT_RX_FDIR) {
1520 first_seg->hash.fdir.hash =
1521 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1522 & IXGBE_ATR_HASH_MASK);
1523 first_seg->hash.fdir.id =
1524 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1527 /* Prefetch data of first segment, if configured to do so. */
1528 rte_packet_prefetch((char *)first_seg->buf_addr +
1529 first_seg->data_off);
1532 * Store the mbuf address into the next entry of the array
1533 * of returned packets.
1535 rx_pkts[nb_rx++] = first_seg;
1538 * Setup receipt context for a new packet.
1544 * Record index of the next RX descriptor to probe.
1546 rxq->rx_tail = rx_id;
1549 * Save receive context.
1551 rxq->pkt_first_seg = first_seg;
1552 rxq->pkt_last_seg = last_seg;
1555 * If the number of free RX descriptors is greater than the RX free
1556 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1558 * Update the RDT with the value of the last processed RX descriptor
1559 * minus 1, to guarantee that the RDT register is never equal to the
1560 * RDH register, which creates a "full" ring situtation from the
1561 * hardware point of view...
1563 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1564 if (nb_hold > rxq->rx_free_thresh) {
1565 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1566 "nb_hold=%u nb_rx=%u",
1567 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1568 (unsigned) rx_id, (unsigned) nb_hold,
1570 rx_id = (uint16_t) ((rx_id == 0) ?
1571 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1572 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1575 rxq->nb_rx_hold = nb_hold;
1579 /*********************************************************************
1581 * Queue management functions
1583 **********************************************************************/
1586 * Rings setup and release.
1588 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1589 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1590 * also optimize cache line size effect. H/W supports up to cache line size 128.
1592 #define IXGBE_ALIGN 128
1595 * Maximum number of Ring Descriptors.
1597 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1598 * descriptors should meet the following condition:
1599 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1601 #define IXGBE_MIN_RING_DESC 32
1602 #define IXGBE_MAX_RING_DESC 4096
1605 * Create memzone for HW rings. malloc can't be used as the physical address is
1606 * needed. If the memzone is already created, then this function returns a ptr
1609 static const struct rte_memzone *
1610 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1611 uint16_t queue_id, uint32_t ring_size, int socket_id)
1613 char z_name[RTE_MEMZONE_NAMESIZE];
1614 const struct rte_memzone *mz;
1616 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1617 dev->driver->pci_drv.name, ring_name,
1618 dev->data->port_id, queue_id);
1620 mz = rte_memzone_lookup(z_name);
1624 #ifdef RTE_LIBRTE_XEN_DOM0
1625 return rte_memzone_reserve_bounded(z_name, ring_size,
1626 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1628 return rte_memzone_reserve_aligned(z_name, ring_size,
1629 socket_id, 0, IXGBE_ALIGN);
1634 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1638 if (txq->sw_ring != NULL) {
1639 for (i = 0; i < txq->nb_tx_desc; i++) {
1640 if (txq->sw_ring[i].mbuf != NULL) {
1641 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1642 txq->sw_ring[i].mbuf = NULL;
1649 ixgbe_tx_free_swring(struct igb_tx_queue *txq)
1652 txq->sw_ring != NULL)
1653 rte_free(txq->sw_ring);
1657 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1659 if (txq != NULL && txq->ops != NULL) {
1660 txq->ops->release_mbufs(txq);
1661 txq->ops->free_swring(txq);
1667 ixgbe_dev_tx_queue_release(void *txq)
1669 ixgbe_tx_queue_release(txq);
1672 /* (Re)set dynamic igb_tx_queue fields to defaults */
1674 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1676 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1678 struct igb_tx_entry *txe = txq->sw_ring;
1681 /* Zero out HW ring memory */
1682 for (i = 0; i < txq->nb_tx_desc; i++) {
1683 txq->tx_ring[i] = zeroed_desc;
1686 /* Initialize SW ring entries */
1687 prev = (uint16_t) (txq->nb_tx_desc - 1);
1688 for (i = 0; i < txq->nb_tx_desc; i++) {
1689 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1690 txd->wb.status = IXGBE_TXD_STAT_DD;
1693 txe[prev].next_id = i;
1697 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1698 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1701 txq->nb_tx_used = 0;
1703 * Always allow 1 descriptor to be un-allocated to avoid
1704 * a H/W race condition
1706 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1707 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1709 memset((void*)&txq->ctx_cache, 0,
1710 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1713 static struct ixgbe_txq_ops def_txq_ops = {
1714 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1715 .free_swring = ixgbe_tx_free_swring,
1716 .reset = ixgbe_reset_tx_queue,
1720 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1723 unsigned int socket_id,
1724 const struct rte_eth_txconf *tx_conf)
1726 const struct rte_memzone *tz;
1727 struct igb_tx_queue *txq;
1728 struct ixgbe_hw *hw;
1729 uint16_t tx_rs_thresh, tx_free_thresh;
1731 PMD_INIT_FUNC_TRACE();
1732 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1735 * Validate number of transmit descriptors.
1736 * It must not exceed hardware maximum, and must be multiple
1739 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1740 (nb_desc > IXGBE_MAX_RING_DESC) ||
1741 (nb_desc < IXGBE_MIN_RING_DESC)) {
1746 * The following two parameters control the setting of the RS bit on
1747 * transmit descriptors.
1748 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1749 * descriptors have been used.
1750 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1751 * descriptors are used or if the number of descriptors required
1752 * to transmit a packet is greater than the number of free TX
1754 * The following constraints must be satisfied:
1755 * tx_rs_thresh must be greater than 0.
1756 * tx_rs_thresh must be less than the size of the ring minus 2.
1757 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1758 * tx_rs_thresh must be a divisor of the ring size.
1759 * tx_free_thresh must be greater than 0.
1760 * tx_free_thresh must be less than the size of the ring minus 3.
1761 * One descriptor in the TX ring is used as a sentinel to avoid a
1762 * H/W race condition, hence the maximum threshold constraints.
1763 * When set to zero use default values.
1765 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1766 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1767 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1768 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1769 if (tx_rs_thresh >= (nb_desc - 2)) {
1770 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
1771 "of TX descriptors minus 2. (tx_rs_thresh=%u "
1772 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1773 (int)dev->data->port_id, (int)queue_idx);
1776 if (tx_free_thresh >= (nb_desc - 3)) {
1777 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1778 "tx_free_thresh must be less than the number of "
1779 "TX descriptors minus 3. (tx_free_thresh=%u "
1780 "port=%d queue=%d)",
1781 (unsigned int)tx_free_thresh,
1782 (int)dev->data->port_id, (int)queue_idx);
1785 if (tx_rs_thresh > tx_free_thresh) {
1786 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
1787 "tx_free_thresh. (tx_free_thresh=%u "
1788 "tx_rs_thresh=%u port=%d queue=%d)",
1789 (unsigned int)tx_free_thresh,
1790 (unsigned int)tx_rs_thresh,
1791 (int)dev->data->port_id,
1795 if ((nb_desc % tx_rs_thresh) != 0) {
1796 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1797 "number of TX descriptors. (tx_rs_thresh=%u "
1798 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1799 (int)dev->data->port_id, (int)queue_idx);
1804 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1805 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1806 * by the NIC and all descriptors are written back after the NIC
1807 * accumulates WTHRESH descriptors.
1809 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1810 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1811 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1812 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1813 (int)dev->data->port_id, (int)queue_idx);
1817 /* Free memory prior to re-allocation if needed... */
1818 if (dev->data->tx_queues[queue_idx] != NULL) {
1819 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1820 dev->data->tx_queues[queue_idx] = NULL;
1823 /* First allocate the tx queue data structure */
1824 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct igb_tx_queue),
1825 CACHE_LINE_SIZE, socket_id);
1830 * Allocate TX ring hardware descriptors. A memzone large enough to
1831 * handle the maximum ring size is allocated in order to allow for
1832 * resizing in later calls to the queue setup function.
1834 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1835 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1838 ixgbe_tx_queue_release(txq);
1842 txq->nb_tx_desc = nb_desc;
1843 txq->tx_rs_thresh = tx_rs_thresh;
1844 txq->tx_free_thresh = tx_free_thresh;
1845 txq->pthresh = tx_conf->tx_thresh.pthresh;
1846 txq->hthresh = tx_conf->tx_thresh.hthresh;
1847 txq->wthresh = tx_conf->tx_thresh.wthresh;
1848 txq->queue_id = queue_idx;
1849 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1850 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1851 txq->port_id = dev->data->port_id;
1852 txq->txq_flags = tx_conf->txq_flags;
1853 txq->ops = &def_txq_ops;
1854 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1857 * Modification to set VFTDT for virtual function if vf is detected
1859 if (hw->mac.type == ixgbe_mac_82599_vf)
1860 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1862 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1863 #ifndef RTE_LIBRTE_XEN_DOM0
1864 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1866 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1868 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1870 /* Allocate software ring */
1871 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1872 sizeof(struct igb_tx_entry) * nb_desc,
1873 CACHE_LINE_SIZE, socket_id);
1874 if (txq->sw_ring == NULL) {
1875 ixgbe_tx_queue_release(txq);
1878 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1879 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1881 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1882 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
1883 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1884 PMD_INIT_LOG(INFO, "Using simple tx code path");
1885 #ifdef RTE_IXGBE_INC_VECTOR
1886 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1887 ixgbe_txq_vec_setup(txq) == 0) {
1888 PMD_INIT_LOG(INFO, "Vector tx enabled.");
1889 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1893 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1895 PMD_INIT_LOG(INFO, "Using full-featured tx code path");
1896 PMD_INIT_LOG(INFO, " - txq_flags = %lx "
1897 "[IXGBE_SIMPLE_FLAGS=%lx]",
1898 (long unsigned)txq->txq_flags,
1899 (long unsigned)IXGBE_SIMPLE_FLAGS);
1900 PMD_INIT_LOG(INFO, " - tx_rs_thresh = %lu "
1901 "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
1902 (long unsigned)txq->tx_rs_thresh,
1903 (long unsigned)RTE_PMD_IXGBE_TX_MAX_BURST);
1904 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1907 txq->ops->reset(txq);
1909 dev->data->tx_queues[queue_idx] = txq;
1916 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1920 if (rxq->sw_ring != NULL) {
1921 for (i = 0; i < rxq->nb_rx_desc; i++) {
1922 if (rxq->sw_ring[i].mbuf != NULL) {
1923 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1924 rxq->sw_ring[i].mbuf = NULL;
1927 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1928 if (rxq->rx_nb_avail) {
1929 for (i = 0; i < rxq->rx_nb_avail; ++i) {
1930 struct rte_mbuf *mb;
1931 mb = rxq->rx_stage[rxq->rx_next_avail + i];
1932 rte_pktmbuf_free_seg(mb);
1934 rxq->rx_nb_avail = 0;
1941 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
1944 ixgbe_rx_queue_release_mbufs(rxq);
1945 rte_free(rxq->sw_ring);
1951 ixgbe_dev_rx_queue_release(void *rxq)
1953 ixgbe_rx_queue_release(rxq);
1957 * Check if Rx Burst Bulk Alloc function can be used.
1959 * 0: the preconditions are satisfied and the bulk allocation function
1961 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
1962 * function must be used.
1965 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1966 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
1968 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct igb_rx_queue *rxq)
1974 * Make sure the following pre-conditions are satisfied:
1975 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
1976 * rxq->rx_free_thresh < rxq->nb_rx_desc
1977 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
1978 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
1979 * Scattered packets are not supported. This should be checked
1980 * outside of this function.
1982 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1983 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
1984 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
1985 "rxq->rx_free_thresh=%d, "
1986 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
1987 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
1989 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
1990 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
1991 "rxq->rx_free_thresh=%d, "
1992 "rxq->nb_rx_desc=%d",
1993 rxq->rx_free_thresh, rxq->nb_rx_desc);
1995 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
1996 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
1997 "rxq->nb_rx_desc=%d, "
1998 "rxq->rx_free_thresh=%d",
1999 rxq->nb_rx_desc, rxq->rx_free_thresh);
2001 } else if (!(rxq->nb_rx_desc <
2002 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2003 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2004 "rxq->nb_rx_desc=%d, "
2005 "IXGBE_MAX_RING_DESC=%d, "
2006 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2007 rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2008 RTE_PMD_IXGBE_RX_MAX_BURST);
2018 /* Reset dynamic igb_rx_queue fields back to defaults */
2020 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
2022 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
2028 * By default, the Rx queue setup function allocates enough memory for
2029 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2030 * extra memory at the end of the descriptor ring to be zero'd out. A
2031 * pre-condition for using the Rx burst bulk alloc function is that the
2032 * number of descriptors is less than or equal to
2033 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2034 * constraints here to see if we need to zero out memory after the end
2035 * of the H/W descriptor ring.
2037 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2038 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2039 /* zero out extra memory */
2040 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2043 /* do not zero out extra memory */
2044 len = rxq->nb_rx_desc;
2047 * Zero out HW ring memory. Zero out extra memory at the end of
2048 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2049 * reads extra memory as zeros.
2051 for (i = 0; i < len; i++) {
2052 rxq->rx_ring[i] = zeroed_desc;
2055 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2057 * initialize extra software ring entries. Space for these extra
2058 * entries is always allocated
2060 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2061 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2062 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2065 rxq->rx_nb_avail = 0;
2066 rxq->rx_next_avail = 0;
2067 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2068 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2070 rxq->nb_rx_hold = 0;
2071 rxq->pkt_first_seg = NULL;
2072 rxq->pkt_last_seg = NULL;
2076 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2079 unsigned int socket_id,
2080 const struct rte_eth_rxconf *rx_conf,
2081 struct rte_mempool *mp)
2083 const struct rte_memzone *rz;
2084 struct igb_rx_queue *rxq;
2085 struct ixgbe_hw *hw;
2086 int use_def_burst_func = 1;
2089 PMD_INIT_FUNC_TRACE();
2090 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2093 * Validate number of receive descriptors.
2094 * It must not exceed hardware maximum, and must be multiple
2097 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2098 (nb_desc > IXGBE_MAX_RING_DESC) ||
2099 (nb_desc < IXGBE_MIN_RING_DESC)) {
2103 /* Free memory prior to re-allocation if needed... */
2104 if (dev->data->rx_queues[queue_idx] != NULL) {
2105 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2106 dev->data->rx_queues[queue_idx] = NULL;
2109 /* First allocate the rx queue data structure */
2110 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct igb_rx_queue),
2111 CACHE_LINE_SIZE, socket_id);
2115 rxq->nb_rx_desc = nb_desc;
2116 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2117 rxq->queue_id = queue_idx;
2118 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2119 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2120 rxq->port_id = dev->data->port_id;
2121 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2123 rxq->drop_en = rx_conf->rx_drop_en;
2124 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2127 * Allocate RX ring hardware descriptors. A memzone large enough to
2128 * handle the maximum ring size is allocated in order to allow for
2129 * resizing in later calls to the queue setup function.
2131 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2132 RX_RING_SZ, socket_id);
2134 ixgbe_rx_queue_release(rxq);
2139 * Zero init all the descriptors in the ring.
2141 memset (rz->addr, 0, RX_RING_SZ);
2144 * Modified to setup VFRDT for Virtual Function
2146 if (hw->mac.type == ixgbe_mac_82599_vf) {
2148 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2150 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2154 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2156 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2158 #ifndef RTE_LIBRTE_XEN_DOM0
2159 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2161 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2163 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2166 * Allocate software ring. Allow for space at the end of the
2167 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2168 * function does not access an invalid memory region.
2170 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2171 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2175 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2176 sizeof(struct igb_rx_entry) * len,
2177 CACHE_LINE_SIZE, socket_id);
2178 if (rxq->sw_ring == NULL) {
2179 ixgbe_rx_queue_release(rxq);
2182 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2183 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2186 * Certain constraints must be met in order to use the bulk buffer
2187 * allocation Rx burst function.
2189 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2191 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2192 if (!use_def_burst_func && !dev->data->scattered_rx) {
2193 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2194 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2195 "satisfied. Rx Burst Bulk Alloc function will be "
2196 "used on port=%d, queue=%d.",
2197 rxq->port_id, rxq->queue_id);
2198 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2199 #ifdef RTE_IXGBE_INC_VECTOR
2200 if (!ixgbe_rx_vec_condition_check(dev)) {
2201 PMD_INIT_LOG(INFO, "Vector rx enabled, please make "
2202 "sure RX burst size no less than 32.");
2203 ixgbe_rxq_vec_setup(rxq);
2204 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
2209 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2210 "are not satisfied, Scattered Rx is requested, "
2211 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2212 "enabled (port=%d, queue=%d).",
2213 rxq->port_id, rxq->queue_id);
2215 dev->data->rx_queues[queue_idx] = rxq;
2217 ixgbe_reset_rx_queue(rxq);
2223 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2225 #define IXGBE_RXQ_SCAN_INTERVAL 4
2226 volatile union ixgbe_adv_rx_desc *rxdp;
2227 struct igb_rx_queue *rxq;
2230 if (rx_queue_id >= dev->data->nb_rx_queues) {
2231 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2235 rxq = dev->data->rx_queues[rx_queue_id];
2236 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2238 while ((desc < rxq->nb_rx_desc) &&
2239 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2240 desc += IXGBE_RXQ_SCAN_INTERVAL;
2241 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2242 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2243 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2244 desc - rxq->nb_rx_desc]);
2251 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2253 volatile union ixgbe_adv_rx_desc *rxdp;
2254 struct igb_rx_queue *rxq = rx_queue;
2257 if (unlikely(offset >= rxq->nb_rx_desc))
2259 desc = rxq->rx_tail + offset;
2260 if (desc >= rxq->nb_rx_desc)
2261 desc -= rxq->nb_rx_desc;
2263 rxdp = &rxq->rx_ring[desc];
2264 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2268 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2272 PMD_INIT_FUNC_TRACE();
2274 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2275 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2277 txq->ops->release_mbufs(txq);
2278 txq->ops->reset(txq);
2282 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2283 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2285 ixgbe_rx_queue_release_mbufs(rxq);
2286 ixgbe_reset_rx_queue(rxq);
2291 /*********************************************************************
2293 * Device RX/TX init functions
2295 **********************************************************************/
2298 * Receive Side Scaling (RSS)
2299 * See section 7.1.2.8 in the following document:
2300 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2303 * The source and destination IP addresses of the IP header and the source
2304 * and destination ports of TCP/UDP headers, if any, of received packets are
2305 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2306 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2307 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2308 * RSS output index which is used as the RX queue index where to store the
2310 * The following output is supplied in the RX write-back descriptor:
2311 * - 32-bit result of the Microsoft RSS hash function,
2312 * - 4-bit RSS type field.
2316 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2317 * Used as the default key.
2319 static uint8_t rss_intel_key[40] = {
2320 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2321 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2322 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2323 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2324 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2328 ixgbe_rss_disable(struct rte_eth_dev *dev)
2330 struct ixgbe_hw *hw;
2333 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2334 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2335 mrqc &= ~IXGBE_MRQC_RSSEN;
2336 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2340 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2348 hash_key = rss_conf->rss_key;
2349 if (hash_key != NULL) {
2350 /* Fill in RSS hash key */
2351 for (i = 0; i < 10; i++) {
2352 rss_key = hash_key[(i * 4)];
2353 rss_key |= hash_key[(i * 4) + 1] << 8;
2354 rss_key |= hash_key[(i * 4) + 2] << 16;
2355 rss_key |= hash_key[(i * 4) + 3] << 24;
2356 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2360 /* Set configured hashing protocols in MRQC register */
2361 rss_hf = rss_conf->rss_hf;
2362 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2363 if (rss_hf & ETH_RSS_IPV4)
2364 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2365 if (rss_hf & ETH_RSS_IPV4_TCP)
2366 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2367 if (rss_hf & ETH_RSS_IPV6)
2368 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2369 if (rss_hf & ETH_RSS_IPV6_EX)
2370 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2371 if (rss_hf & ETH_RSS_IPV6_TCP)
2372 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2373 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2374 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2375 if (rss_hf & ETH_RSS_IPV4_UDP)
2376 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2377 if (rss_hf & ETH_RSS_IPV6_UDP)
2378 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2379 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2380 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2381 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2385 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2386 struct rte_eth_rss_conf *rss_conf)
2388 struct ixgbe_hw *hw;
2392 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2395 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2396 * "RSS enabling cannot be done dynamically while it must be
2397 * preceded by a software reset"
2398 * Before changing anything, first check that the update RSS operation
2399 * does not attempt to disable RSS, if RSS was enabled at
2400 * initialization time, or does not attempt to enable RSS, if RSS was
2401 * disabled at initialization time.
2403 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2404 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2405 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2406 if (rss_hf != 0) /* Enable RSS */
2408 return 0; /* Nothing to do */
2411 if (rss_hf == 0) /* Disable RSS */
2413 ixgbe_hw_rss_hash_set(hw, rss_conf);
2418 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2419 struct rte_eth_rss_conf *rss_conf)
2421 struct ixgbe_hw *hw;
2428 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2429 hash_key = rss_conf->rss_key;
2430 if (hash_key != NULL) {
2431 /* Return RSS hash key */
2432 for (i = 0; i < 10; i++) {
2433 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2434 hash_key[(i * 4)] = rss_key & 0x000000FF;
2435 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2436 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2437 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2441 /* Get RSS functions configured in MRQC register */
2442 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2443 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2444 rss_conf->rss_hf = 0;
2448 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2449 rss_hf |= ETH_RSS_IPV4;
2450 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2451 rss_hf |= ETH_RSS_IPV4_TCP;
2452 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2453 rss_hf |= ETH_RSS_IPV6;
2454 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2455 rss_hf |= ETH_RSS_IPV6_EX;
2456 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2457 rss_hf |= ETH_RSS_IPV6_TCP;
2458 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2459 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2460 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2461 rss_hf |= ETH_RSS_IPV4_UDP;
2462 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2463 rss_hf |= ETH_RSS_IPV6_UDP;
2464 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2465 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2466 rss_conf->rss_hf = rss_hf;
2471 ixgbe_rss_configure(struct rte_eth_dev *dev)
2473 struct rte_eth_rss_conf rss_conf;
2474 struct ixgbe_hw *hw;
2479 PMD_INIT_FUNC_TRACE();
2480 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2483 * Fill in redirection table
2484 * The byte-swap is needed because NIC registers are in
2485 * little-endian order.
2488 for (i = 0, j = 0; i < 128; i++, j++) {
2489 if (j == dev->data->nb_rx_queues)
2491 reta = (reta << 8) | j;
2493 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2498 * Configure the RSS key and the RSS protocols used to compute
2499 * the RSS hash of input packets.
2501 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2502 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2503 ixgbe_rss_disable(dev);
2506 if (rss_conf.rss_key == NULL)
2507 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2508 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2511 #define NUM_VFTA_REGISTERS 128
2512 #define NIC_RX_BUFFER_SIZE 0x200
2515 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2517 struct rte_eth_vmdq_dcb_conf *cfg;
2518 struct ixgbe_hw *hw;
2519 enum rte_eth_nb_pools num_pools;
2520 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2522 uint8_t nb_tcs; /* number of traffic classes */
2525 PMD_INIT_FUNC_TRACE();
2526 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2527 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2528 num_pools = cfg->nb_queue_pools;
2529 /* Check we have a valid number of pools */
2530 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2531 ixgbe_rss_disable(dev);
2534 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2535 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2539 * split rx buffer up into sections, each for 1 traffic class
2541 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2542 for (i = 0 ; i < nb_tcs; i++) {
2543 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2544 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2545 /* clear 10 bits. */
2546 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2547 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2549 /* zero alloc all unused TCs */
2550 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2551 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2552 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2553 /* clear 10 bits. */
2554 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2557 /* MRQC: enable vmdq and dcb */
2558 mrqc = ((num_pools == ETH_16_POOLS) ? \
2559 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2560 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2562 /* PFVTCTL: turn on virtualisation and set the default pool */
2563 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2564 if (cfg->enable_default_pool) {
2565 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2567 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2570 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2572 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2574 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2576 * mapping is done with 3 bits per priority,
2577 * so shift by i*3 each time
2579 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2581 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2583 /* RTRPCS: DCB related */
2584 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2586 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2587 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2588 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2589 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2591 /* VFTA - enable all vlan filters */
2592 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2593 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2596 /* VFRE: pool enabling for receive - 16 or 32 */
2597 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2598 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2601 * MPSAR - allow pools to read specific mac addresses
2602 * In this case, all pools should be able to read from mac addr 0
2604 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2605 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2607 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2608 for (i = 0; i < cfg->nb_pool_maps; i++) {
2609 /* set vlan id in VF register and set the valid bit */
2610 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2611 (cfg->pool_map[i].vlan_id & 0xFFF)));
2613 * Put the allowed pools in VFB reg. As we only have 16 or 32
2614 * pools, we only need to use the first half of the register
2617 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2622 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2623 * @hw: pointer to hardware structure
2624 * @dcb_config: pointer to ixgbe_dcb_config structure
2627 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2628 struct ixgbe_dcb_config *dcb_config)
2633 PMD_INIT_FUNC_TRACE();
2634 if (hw->mac.type != ixgbe_mac_82598EB) {
2635 /* Disable the Tx desc arbiter so that MTQC can be changed */
2636 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2637 reg |= IXGBE_RTTDCS_ARBDIS;
2638 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2640 /* Enable DCB for Tx with 8 TCs */
2641 if (dcb_config->num_tcs.pg_tcs == 8) {
2642 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2645 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2647 if (dcb_config->vt_mode)
2648 reg |= IXGBE_MTQC_VT_ENA;
2649 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2651 /* Disable drop for all queues */
2652 for (q = 0; q < 128; q++)
2653 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2654 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2656 /* Enable the Tx desc arbiter */
2657 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2658 reg &= ~IXGBE_RTTDCS_ARBDIS;
2659 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2661 /* Enable Security TX Buffer IFG for DCB */
2662 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2663 reg |= IXGBE_SECTX_DCB;
2664 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2670 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2671 * @dev: pointer to rte_eth_dev structure
2672 * @dcb_config: pointer to ixgbe_dcb_config structure
2675 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2676 struct ixgbe_dcb_config *dcb_config)
2678 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2679 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2680 struct ixgbe_hw *hw =
2681 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2683 PMD_INIT_FUNC_TRACE();
2684 if (hw->mac.type != ixgbe_mac_82598EB)
2685 /*PF VF Transmit Enable*/
2686 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2687 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2689 /*Configure general DCB TX parameters*/
2690 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2695 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2696 struct ixgbe_dcb_config *dcb_config)
2698 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2699 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2700 struct ixgbe_dcb_tc_config *tc;
2703 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2704 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2705 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2706 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2709 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2710 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2712 /* User Priority to Traffic Class mapping */
2713 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2714 j = vmdq_rx_conf->dcb_queue[i];
2715 tc = &dcb_config->tc_config[j];
2716 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2722 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2723 struct ixgbe_dcb_config *dcb_config)
2725 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2726 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2727 struct ixgbe_dcb_tc_config *tc;
2730 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2731 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2732 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2733 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2736 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2737 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2740 /* User Priority to Traffic Class mapping */
2741 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2742 j = vmdq_tx_conf->dcb_queue[i];
2743 tc = &dcb_config->tc_config[j];
2744 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2751 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2752 struct ixgbe_dcb_config *dcb_config)
2754 struct rte_eth_dcb_rx_conf *rx_conf =
2755 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2756 struct ixgbe_dcb_tc_config *tc;
2759 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2760 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2762 /* User Priority to Traffic Class mapping */
2763 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2764 j = rx_conf->dcb_queue[i];
2765 tc = &dcb_config->tc_config[j];
2766 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2772 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2773 struct ixgbe_dcb_config *dcb_config)
2775 struct rte_eth_dcb_tx_conf *tx_conf =
2776 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2777 struct ixgbe_dcb_tc_config *tc;
2780 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2781 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2783 /* User Priority to Traffic Class mapping */
2784 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2785 j = tx_conf->dcb_queue[i];
2786 tc = &dcb_config->tc_config[j];
2787 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2793 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2794 * @hw: pointer to hardware structure
2795 * @dcb_config: pointer to ixgbe_dcb_config structure
2798 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2799 struct ixgbe_dcb_config *dcb_config)
2805 PMD_INIT_FUNC_TRACE();
2807 * Disable the arbiter before changing parameters
2808 * (always enable recycle mode; WSP)
2810 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2811 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2813 if (hw->mac.type != ixgbe_mac_82598EB) {
2814 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2815 if (dcb_config->num_tcs.pg_tcs == 4) {
2816 if (dcb_config->vt_mode)
2817 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2818 IXGBE_MRQC_VMDQRT4TCEN;
2820 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2821 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2825 if (dcb_config->num_tcs.pg_tcs == 8) {
2826 if (dcb_config->vt_mode)
2827 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2828 IXGBE_MRQC_VMDQRT8TCEN;
2830 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2831 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2836 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2839 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2840 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2841 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2842 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2844 /* VFTA - enable all vlan filters */
2845 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2846 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2850 * Configure Rx packet plane (recycle mode; WSP) and
2853 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2854 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2860 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2861 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2863 switch (hw->mac.type) {
2864 case ixgbe_mac_82598EB:
2865 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2867 case ixgbe_mac_82599EB:
2868 case ixgbe_mac_X540:
2869 case ixgbe_mac_X550:
2870 case ixgbe_mac_X550EM_x:
2871 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2880 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2881 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2883 switch (hw->mac.type) {
2884 case ixgbe_mac_82598EB:
2885 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2886 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2888 case ixgbe_mac_82599EB:
2889 case ixgbe_mac_X540:
2890 case ixgbe_mac_X550:
2891 case ixgbe_mac_X550EM_x:
2892 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2893 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2900 #define DCB_RX_CONFIG 1
2901 #define DCB_TX_CONFIG 1
2902 #define DCB_TX_PB 1024
2904 * ixgbe_dcb_hw_configure - Enable DCB and configure
2905 * general DCB in VT mode and non-VT mode parameters
2906 * @dev: pointer to rte_eth_dev structure
2907 * @dcb_config: pointer to ixgbe_dcb_config structure
2910 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2911 struct ixgbe_dcb_config *dcb_config)
2914 uint8_t i,pfc_en,nb_tcs;
2916 uint8_t config_dcb_rx = 0;
2917 uint8_t config_dcb_tx = 0;
2918 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2919 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2920 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2921 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2922 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2923 struct ixgbe_dcb_tc_config *tc;
2924 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2925 struct ixgbe_hw *hw =
2926 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2928 switch(dev->data->dev_conf.rxmode.mq_mode){
2929 case ETH_MQ_RX_VMDQ_DCB:
2930 dcb_config->vt_mode = true;
2931 if (hw->mac.type != ixgbe_mac_82598EB) {
2932 config_dcb_rx = DCB_RX_CONFIG;
2934 *get dcb and VT rx configuration parameters
2937 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2938 /*Configure general VMDQ and DCB RX parameters*/
2939 ixgbe_vmdq_dcb_configure(dev);
2943 dcb_config->vt_mode = false;
2944 config_dcb_rx = DCB_RX_CONFIG;
2945 /* Get dcb TX configuration parameters from rte_eth_conf */
2946 ixgbe_dcb_rx_config(dev,dcb_config);
2947 /*Configure general DCB RX parameters*/
2948 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2951 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
2954 switch (dev->data->dev_conf.txmode.mq_mode) {
2955 case ETH_MQ_TX_VMDQ_DCB:
2956 dcb_config->vt_mode = true;
2957 config_dcb_tx = DCB_TX_CONFIG;
2958 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2959 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2960 /*Configure general VMDQ and DCB TX parameters*/
2961 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2965 dcb_config->vt_mode = false;
2966 config_dcb_tx = DCB_TX_CONFIG;
2967 /*get DCB TX configuration parameters from rte_eth_conf*/
2968 ixgbe_dcb_tx_config(dev,dcb_config);
2969 /*Configure general DCB TX parameters*/
2970 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2973 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
2977 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2979 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2980 if(nb_tcs == ETH_4_TCS) {
2981 /* Avoid un-configured priority mapping to TC0 */
2983 uint8_t mask = 0xFF;
2984 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
2985 mask = (uint8_t)(mask & (~ (1 << map[i])));
2986 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
2987 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
2991 /* Re-configure 4 TCs BW */
2992 for (i = 0; i < nb_tcs; i++) {
2993 tc = &dcb_config->tc_config[i];
2994 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
2995 (uint8_t)(100 / nb_tcs);
2996 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
2997 (uint8_t)(100 / nb_tcs);
2999 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3000 tc = &dcb_config->tc_config[i];
3001 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3002 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3007 /* Set RX buffer size */
3008 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3009 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3010 for (i = 0 ; i < nb_tcs; i++) {
3011 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3013 /* zero alloc all unused TCs */
3014 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3015 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3019 /* Only support an equally distributed Tx packet buffer strategy. */
3020 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3021 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3022 for (i = 0; i < nb_tcs; i++) {
3023 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3024 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3026 /* Clear unused TCs, if any, to zero buffer size*/
3027 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3028 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3029 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3033 /*Calculates traffic class credits*/
3034 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3035 IXGBE_DCB_TX_CONFIG);
3036 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3037 IXGBE_DCB_RX_CONFIG);
3040 /* Unpack CEE standard containers */
3041 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3042 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3043 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3044 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3045 /* Configure PG(ETS) RX */
3046 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3050 /* Unpack CEE standard containers */
3051 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3052 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3053 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3054 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3055 /* Configure PG(ETS) TX */
3056 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3059 /*Configure queue statistics registers*/
3060 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3062 /* Check if the PFC is supported */
3063 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3064 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3065 for (i = 0; i < nb_tcs; i++) {
3067 * If the TC count is 8,and the default high_water is 48,
3068 * the low_water is 16 as default.
3070 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3071 hw->fc.low_water[i] = pbsize / 4;
3072 /* Enable pfc for this TC */
3073 tc = &dcb_config->tc_config[i];
3074 tc->pfc = ixgbe_dcb_pfc_enabled;
3076 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3077 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3079 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3086 * ixgbe_configure_dcb - Configure DCB Hardware
3087 * @dev: pointer to rte_eth_dev
3089 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3091 struct ixgbe_dcb_config *dcb_cfg =
3092 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3093 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3095 PMD_INIT_FUNC_TRACE();
3097 /* check support mq_mode for DCB */
3098 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3099 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3102 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3105 /** Configure DCB hardware **/
3106 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3112 * VMDq only support for 10 GbE NIC.
3115 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3117 struct rte_eth_vmdq_rx_conf *cfg;
3118 struct ixgbe_hw *hw;
3119 enum rte_eth_nb_pools num_pools;
3120 uint32_t mrqc, vt_ctl, vlanctrl;
3123 PMD_INIT_FUNC_TRACE();
3124 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3125 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3126 num_pools = cfg->nb_queue_pools;
3128 ixgbe_rss_disable(dev);
3130 /* MRQC: enable vmdq */
3131 mrqc = IXGBE_MRQC_VMDQEN;
3132 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3134 /* PFVTCTL: turn on virtualisation and set the default pool */
3135 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3136 if (cfg->enable_default_pool)
3137 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3139 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3141 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3143 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3144 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3145 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3146 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3148 /* VFTA - enable all vlan filters */
3149 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3150 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3152 /* VFRE: pool enabling for receive - 64 */
3153 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3154 if (num_pools == ETH_64_POOLS)
3155 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3158 * MPSAR - allow pools to read specific mac addresses
3159 * In this case, all pools should be able to read from mac addr 0
3161 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3162 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3164 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3165 for (i = 0; i < cfg->nb_pool_maps; i++) {
3166 /* set vlan id in VF register and set the valid bit */
3167 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3168 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3170 * Put the allowed pools in VFB reg. As we only have 16 or 64
3171 * pools, we only need to use the first half of the register
3174 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3175 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3176 (cfg->pool_map[i].pools & UINT32_MAX));
3178 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3179 ((cfg->pool_map[i].pools >> 32) \
3184 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3185 if (cfg->enable_loop_back) {
3186 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3187 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3188 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3191 IXGBE_WRITE_FLUSH(hw);
3195 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3196 * @hw: pointer to hardware structure
3199 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3204 PMD_INIT_FUNC_TRACE();
3205 /*PF VF Transmit Enable*/
3206 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3207 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3209 /* Disable the Tx desc arbiter so that MTQC can be changed */
3210 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3211 reg |= IXGBE_RTTDCS_ARBDIS;
3212 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3214 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3215 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3217 /* Disable drop for all queues */
3218 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3219 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3220 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3222 /* Enable the Tx desc arbiter */
3223 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3224 reg &= ~IXGBE_RTTDCS_ARBDIS;
3225 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3227 IXGBE_WRITE_FLUSH(hw);
3233 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
3235 struct igb_rx_entry *rxe = rxq->sw_ring;
3239 /* Initialize software ring entries */
3240 for (i = 0; i < rxq->nb_rx_desc; i++) {
3241 volatile union ixgbe_adv_rx_desc *rxd;
3242 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3244 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3245 (unsigned) rxq->queue_id);
3249 rte_mbuf_refcnt_set(mbuf, 1);
3251 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3253 mbuf->port = rxq->port_id;
3256 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3257 rxd = &rxq->rx_ring[i];
3258 rxd->read.hdr_addr = dma_addr;
3259 rxd->read.pkt_addr = dma_addr;
3267 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3269 struct ixgbe_hw *hw =
3270 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3272 if (hw->mac.type == ixgbe_mac_82598EB)
3275 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3277 * SRIOV inactive scheme
3278 * any DCB/RSS w/o VMDq multi-queue setting
3280 switch (dev->data->dev_conf.rxmode.mq_mode) {
3282 ixgbe_rss_configure(dev);
3285 case ETH_MQ_RX_VMDQ_DCB:
3286 ixgbe_vmdq_dcb_configure(dev);
3289 case ETH_MQ_RX_VMDQ_ONLY:
3290 ixgbe_vmdq_rx_hw_configure(dev);
3293 case ETH_MQ_RX_NONE:
3294 /* if mq_mode is none, disable rss mode.*/
3295 default: ixgbe_rss_disable(dev);
3298 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3300 * SRIOV active scheme
3301 * FIXME if support DCB/RSS together with VMDq & SRIOV
3304 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQEN);
3308 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT4TCEN);
3312 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT8TCEN);
3315 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3323 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3325 struct ixgbe_hw *hw =
3326 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3330 if (hw->mac.type == ixgbe_mac_82598EB)
3333 /* disable arbiter before setting MTQC */
3334 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3335 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3336 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3338 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3340 * SRIOV inactive scheme
3341 * any DCB w/o VMDq multi-queue setting
3343 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3344 ixgbe_vmdq_tx_hw_configure(hw);
3346 mtqc = IXGBE_MTQC_64Q_1PB;
3347 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3350 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3353 * SRIOV active scheme
3354 * FIXME if support DCB together with VMDq & SRIOV
3357 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3360 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3363 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3367 mtqc = IXGBE_MTQC_64Q_1PB;
3368 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3370 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3373 /* re-enable arbiter */
3374 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3375 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3381 * Initializes Receive Unit.
3384 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3386 struct ixgbe_hw *hw;
3387 struct igb_rx_queue *rxq;
3388 struct rte_pktmbuf_pool_private *mbp_priv;
3400 PMD_INIT_FUNC_TRACE();
3401 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3404 * Make sure receives are disabled while setting
3405 * up the RX context (registers, descriptor rings, etc.).
3407 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3408 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3410 /* Enable receipt of broadcasted frames */
3411 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3412 fctrl |= IXGBE_FCTRL_BAM;
3413 fctrl |= IXGBE_FCTRL_DPF;
3414 fctrl |= IXGBE_FCTRL_PMCF;
3415 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3418 * Configure CRC stripping, if any.
3420 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3421 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3422 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3424 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3427 * Configure jumbo frame support, if any.
3429 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3430 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3431 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3432 maxfrs &= 0x0000FFFF;
3433 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3434 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3436 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3439 * If loopback mode is configured for 82599, set LPBK bit.
3441 if (hw->mac.type == ixgbe_mac_82599EB &&
3442 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3443 hlreg0 |= IXGBE_HLREG0_LPBK;
3445 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3447 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3449 /* Setup RX queues */
3450 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3451 rxq = dev->data->rx_queues[i];
3454 * Reset crc_len in case it was changed after queue setup by a
3455 * call to configure.
3457 rxq->crc_len = (uint8_t)
3458 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3461 /* Setup the Base and Length of the Rx Descriptor Rings */
3462 bus_addr = rxq->rx_ring_phys_addr;
3463 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3464 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3465 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3466 (uint32_t)(bus_addr >> 32));
3467 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3468 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3469 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3470 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3472 /* Configure the SRRCTL register */
3473 #ifdef RTE_HEADER_SPLIT_ENABLE
3475 * Configure Header Split
3477 if (dev->data->dev_conf.rxmode.header_split) {
3478 if (hw->mac.type == ixgbe_mac_82599EB) {
3479 /* Must setup the PSRTYPE register */
3481 psrtype = IXGBE_PSRTYPE_TCPHDR |
3482 IXGBE_PSRTYPE_UDPHDR |
3483 IXGBE_PSRTYPE_IPV4HDR |
3484 IXGBE_PSRTYPE_IPV6HDR;
3485 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3487 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3488 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3489 IXGBE_SRRCTL_BSIZEHDR_MASK);
3490 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3493 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3495 /* Set if packets are dropped when no descriptors available */
3497 srrctl |= IXGBE_SRRCTL_DROP_EN;
3500 * Configure the RX buffer size in the BSIZEPACKET field of
3501 * the SRRCTL register of the queue.
3502 * The value is in 1 KB resolution. Valid values can be from
3505 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3506 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3507 RTE_PKTMBUF_HEADROOM);
3508 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3509 IXGBE_SRRCTL_BSIZEPKT_MASK);
3510 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3512 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3513 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3515 /* It adds dual VLAN length for supporting dual VLAN */
3516 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3517 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3518 if (!dev->data->scattered_rx)
3519 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
3520 dev->data->scattered_rx = 1;
3521 #ifdef RTE_IXGBE_INC_VECTOR
3522 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3524 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3529 if (dev->data->dev_conf.rxmode.enable_scatter) {
3530 if (!dev->data->scattered_rx)
3531 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
3532 #ifdef RTE_IXGBE_INC_VECTOR
3533 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3535 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3537 dev->data->scattered_rx = 1;
3541 * Device configured with multiple RX queues.
3543 ixgbe_dev_mq_rx_configure(dev);
3546 * Setup the Checksum Register.
3547 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3548 * Enable IP/L4 checkum computation by hardware if requested to do so.
3550 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3551 rxcsum |= IXGBE_RXCSUM_PCSD;
3552 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3553 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3555 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3557 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3559 if (hw->mac.type == ixgbe_mac_82599EB) {
3560 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3561 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3562 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3564 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3565 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3566 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3573 * Initializes Transmit Unit.
3576 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3578 struct ixgbe_hw *hw;
3579 struct igb_tx_queue *txq;
3585 PMD_INIT_FUNC_TRACE();
3586 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3588 /* Enable TX CRC (checksum offload requirement) */
3589 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3590 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
3591 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3593 /* Setup the Base and Length of the Tx Descriptor Rings */
3594 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3595 txq = dev->data->tx_queues[i];
3597 bus_addr = txq->tx_ring_phys_addr;
3598 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3599 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3600 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3601 (uint32_t)(bus_addr >> 32));
3602 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3603 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3604 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3605 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3606 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3609 * Disable Tx Head Writeback RO bit, since this hoses
3610 * bookkeeping if things aren't delivered in order.
3612 switch (hw->mac.type) {
3613 case ixgbe_mac_82598EB:
3614 txctrl = IXGBE_READ_REG(hw,
3615 IXGBE_DCA_TXCTRL(txq->reg_idx));
3616 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3617 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3621 case ixgbe_mac_82599EB:
3622 case ixgbe_mac_X540:
3623 case ixgbe_mac_X550:
3624 case ixgbe_mac_X550EM_x:
3626 txctrl = IXGBE_READ_REG(hw,
3627 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3628 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3629 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3635 /* Device configured with multiple TX queues. */
3636 ixgbe_dev_mq_tx_configure(dev);
3640 * Set up link for 82599 loopback mode Tx->Rx.
3643 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3645 PMD_INIT_FUNC_TRACE();
3647 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3648 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3650 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
3659 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3660 ixgbe_reset_pipeline_82599(hw);
3662 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3668 * Start Transmit and Receive Units.
3671 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3673 struct ixgbe_hw *hw;
3674 struct igb_tx_queue *txq;
3675 struct igb_rx_queue *rxq;
3681 PMD_INIT_FUNC_TRACE();
3682 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3684 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3685 txq = dev->data->tx_queues[i];
3686 /* Setup Transmit Threshold Registers */
3687 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3688 txdctl |= txq->pthresh & 0x7F;
3689 txdctl |= ((txq->hthresh & 0x7F) << 8);
3690 txdctl |= ((txq->wthresh & 0x7F) << 16);
3691 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3694 if (hw->mac.type != ixgbe_mac_82598EB) {
3695 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3696 dmatxctl |= IXGBE_DMATXCTL_TE;
3697 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3700 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3701 txq = dev->data->tx_queues[i];
3702 if (!txq->tx_deferred_start)
3703 ixgbe_dev_tx_queue_start(dev, i);
3706 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3707 rxq = dev->data->rx_queues[i];
3708 if (!rxq->rx_deferred_start)
3709 ixgbe_dev_rx_queue_start(dev, i);
3712 /* Enable Receive engine */
3713 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3714 if (hw->mac.type == ixgbe_mac_82598EB)
3715 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3716 rxctrl |= IXGBE_RXCTRL_RXEN;
3717 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3719 /* If loopback mode is enabled for 82599, set up the link accordingly */
3720 if (hw->mac.type == ixgbe_mac_82599EB &&
3721 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3722 ixgbe_setup_loopback_link_82599(hw);
3727 * Start Receive Units for specified queue.
3730 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3732 struct ixgbe_hw *hw;
3733 struct igb_rx_queue *rxq;
3737 PMD_INIT_FUNC_TRACE();
3738 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3740 if (rx_queue_id < dev->data->nb_rx_queues) {
3741 rxq = dev->data->rx_queues[rx_queue_id];
3743 /* Allocate buffers for descriptor rings */
3744 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
3745 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
3749 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3750 rxdctl |= IXGBE_RXDCTL_ENABLE;
3751 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3753 /* Wait until RX Enable ready */
3754 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3757 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3758 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3760 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
3763 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3764 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3772 * Stop Receive Units for specified queue.
3775 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3777 struct ixgbe_hw *hw;
3778 struct igb_rx_queue *rxq;
3782 PMD_INIT_FUNC_TRACE();
3783 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3785 if (rx_queue_id < dev->data->nb_rx_queues) {
3786 rxq = dev->data->rx_queues[rx_queue_id];
3788 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3789 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3790 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3792 /* Wait until RX Enable ready */
3793 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3796 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3797 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
3799 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
3802 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3804 ixgbe_rx_queue_release_mbufs(rxq);
3805 ixgbe_reset_rx_queue(rxq);
3814 * Start Transmit Units for specified queue.
3817 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3819 struct ixgbe_hw *hw;
3820 struct igb_tx_queue *txq;
3824 PMD_INIT_FUNC_TRACE();
3825 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3827 if (tx_queue_id < dev->data->nb_tx_queues) {
3828 txq = dev->data->tx_queues[tx_queue_id];
3829 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3830 txdctl |= IXGBE_TXDCTL_ENABLE;
3831 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3833 /* Wait until TX Enable ready */
3834 if (hw->mac.type == ixgbe_mac_82599EB) {
3835 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3838 txdctl = IXGBE_READ_REG(hw,
3839 IXGBE_TXDCTL(txq->reg_idx));
3840 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3842 PMD_INIT_LOG(ERR, "Could not enable "
3843 "Tx Queue %d", tx_queue_id);
3846 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3847 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3855 * Stop Transmit Units for specified queue.
3858 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3860 struct ixgbe_hw *hw;
3861 struct igb_tx_queue *txq;
3863 uint32_t txtdh, txtdt;
3866 PMD_INIT_FUNC_TRACE();
3867 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3869 if (tx_queue_id < dev->data->nb_tx_queues) {
3870 txq = dev->data->tx_queues[tx_queue_id];
3872 /* Wait until TX queue is empty */
3873 if (hw->mac.type == ixgbe_mac_82599EB) {
3874 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3876 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3877 txtdh = IXGBE_READ_REG(hw,
3878 IXGBE_TDH(txq->reg_idx));
3879 txtdt = IXGBE_READ_REG(hw,
3880 IXGBE_TDT(txq->reg_idx));
3881 } while (--poll_ms && (txtdh != txtdt));
3883 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
3884 "when stopping.", tx_queue_id);
3887 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3888 txdctl &= ~IXGBE_TXDCTL_ENABLE;
3889 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3891 /* Wait until TX Enable ready */
3892 if (hw->mac.type == ixgbe_mac_82599EB) {
3893 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3896 txdctl = IXGBE_READ_REG(hw,
3897 IXGBE_TXDCTL(txq->reg_idx));
3898 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
3900 PMD_INIT_LOG(ERR, "Could not disable "
3901 "Tx Queue %d", tx_queue_id);
3904 if (txq->ops != NULL) {
3905 txq->ops->release_mbufs(txq);
3906 txq->ops->reset(txq);
3915 * [VF] Initializes Receive Unit.
3918 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3920 struct ixgbe_hw *hw;
3921 struct igb_rx_queue *rxq;
3922 struct rte_pktmbuf_pool_private *mbp_priv;
3929 PMD_INIT_FUNC_TRACE();
3930 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3933 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
3934 * disables the VF receipt of packets if the PF MTU is > 1500.
3935 * This is done to deal with 82599 limitations that imposes
3936 * the PF and all VFs to share the same MTU.
3937 * Then, the PF driver enables again the VF receipt of packet when
3938 * the VF driver issues a IXGBE_VF_SET_LPE request.
3939 * In the meantime, the VF device cannot be used, even if the VF driver
3940 * and the Guest VM network stack are ready to accept packets with a
3941 * size up to the PF MTU.
3942 * As a work-around to this PF behaviour, force the call to
3943 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
3944 * VF packets received can work in all cases.
3946 ixgbevf_rlpml_set_vf(hw,
3947 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
3949 /* Setup RX queues */
3950 dev->rx_pkt_burst = ixgbe_recv_pkts;
3951 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3952 rxq = dev->data->rx_queues[i];
3954 /* Allocate buffers for descriptor rings */
3955 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3959 /* Setup the Base and Length of the Rx Descriptor Rings */
3960 bus_addr = rxq->rx_ring_phys_addr;
3962 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3963 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3964 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3965 (uint32_t)(bus_addr >> 32));
3966 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3967 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3968 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3969 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3972 /* Configure the SRRCTL register */
3973 #ifdef RTE_HEADER_SPLIT_ENABLE
3975 * Configure Header Split
3977 if (dev->data->dev_conf.rxmode.header_split) {
3979 /* Must setup the PSRTYPE register */
3981 psrtype = IXGBE_PSRTYPE_TCPHDR |
3982 IXGBE_PSRTYPE_UDPHDR |
3983 IXGBE_PSRTYPE_IPV4HDR |
3984 IXGBE_PSRTYPE_IPV6HDR;
3986 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
3988 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3989 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3990 IXGBE_SRRCTL_BSIZEHDR_MASK);
3991 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3994 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3996 /* Set if packets are dropped when no descriptors available */
3998 srrctl |= IXGBE_SRRCTL_DROP_EN;
4001 * Configure the RX buffer size in the BSIZEPACKET field of
4002 * the SRRCTL register of the queue.
4003 * The value is in 1 KB resolution. Valid values can be from
4006 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
4007 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
4008 RTE_PKTMBUF_HEADROOM);
4009 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4010 IXGBE_SRRCTL_BSIZEPKT_MASK);
4013 * VF modification to write virtual function SRRCTL register
4015 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
4017 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4018 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4020 /* It adds dual VLAN length for supporting dual VLAN */
4021 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
4022 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
4023 if (!dev->data->scattered_rx)
4024 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4025 dev->data->scattered_rx = 1;
4026 #ifdef RTE_IXGBE_INC_VECTOR
4027 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4029 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
4034 if (dev->data->dev_conf.rxmode.enable_scatter) {
4035 if (!dev->data->scattered_rx)
4036 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4037 #ifdef RTE_IXGBE_INC_VECTOR
4038 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4040 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
4042 dev->data->scattered_rx = 1;
4049 * [VF] Initializes Transmit Unit.
4052 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4054 struct ixgbe_hw *hw;
4055 struct igb_tx_queue *txq;
4060 PMD_INIT_FUNC_TRACE();
4061 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4063 /* Setup the Base and Length of the Tx Descriptor Rings */
4064 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4065 txq = dev->data->tx_queues[i];
4066 bus_addr = txq->tx_ring_phys_addr;
4067 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4068 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4069 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4070 (uint32_t)(bus_addr >> 32));
4071 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4072 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4073 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4074 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4075 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4078 * Disable Tx Head Writeback RO bit, since this hoses
4079 * bookkeeping if things aren't delivered in order.
4081 txctrl = IXGBE_READ_REG(hw,
4082 IXGBE_VFDCA_TXCTRL(i));
4083 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4084 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4090 * [VF] Start Transmit and Receive Units.
4093 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4095 struct ixgbe_hw *hw;
4096 struct igb_tx_queue *txq;
4097 struct igb_rx_queue *rxq;
4103 PMD_INIT_FUNC_TRACE();
4104 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4106 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4107 txq = dev->data->tx_queues[i];
4108 /* Setup Transmit Threshold Registers */
4109 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4110 txdctl |= txq->pthresh & 0x7F;
4111 txdctl |= ((txq->hthresh & 0x7F) << 8);
4112 txdctl |= ((txq->wthresh & 0x7F) << 16);
4113 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4116 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4118 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4119 txdctl |= IXGBE_TXDCTL_ENABLE;
4120 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4123 /* Wait until TX Enable ready */
4126 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4127 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4129 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
4131 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4133 rxq = dev->data->rx_queues[i];
4135 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4136 rxdctl |= IXGBE_RXDCTL_ENABLE;
4137 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4139 /* Wait until RX Enable ready */
4143 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4144 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4146 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
4148 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);