4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5 * Copyright 2014 6WIND S.A.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * * Neither the name of Intel Corporation nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
46 #include <rte_byteorder.h>
47 #include <rte_common.h>
48 #include <rte_cycles.h>
50 #include <rte_debug.h>
51 #include <rte_interrupts.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_launch.h>
56 #include <rte_tailq.h>
58 #include <rte_per_lcore.h>
59 #include <rte_lcore.h>
60 #include <rte_atomic.h>
61 #include <rte_branch_prediction.h>
63 #include <rte_mempool.h>
64 #include <rte_malloc.h>
66 #include <rte_ether.h>
67 #include <rte_ethdev.h>
68 #include <rte_prefetch.h>
72 #include <rte_string_fns.h>
73 #include <rte_errno.h>
75 #include "ixgbe_logs.h"
76 #include "ixgbe/ixgbe_api.h"
77 #include "ixgbe/ixgbe_vf.h"
78 #include "ixgbe_ethdev.h"
79 #include "ixgbe/ixgbe_dcb.h"
80 #include "ixgbe/ixgbe_common.h"
81 #include "ixgbe_rxtx.h"
83 /* Bit Mask to indicate what bits required for building TX context */
84 #define IXGBE_TX_OFFLOAD_MASK ( \
90 static inline struct rte_mbuf *
91 rte_rxmbuf_alloc(struct rte_mempool *mp)
95 m = __rte_mbuf_raw_alloc(mp);
96 __rte_mbuf_sanity_check_raw(m, 0);
102 #define RTE_PMD_USE_PREFETCH
105 #ifdef RTE_PMD_USE_PREFETCH
107 * Prefetch a cache line into all cache levels.
109 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
111 #define rte_ixgbe_prefetch(p) do {} while(0)
114 /*********************************************************************
118 **********************************************************************/
121 * Check for descriptors with their DD bit set and free mbufs.
122 * Return the total number of buffers freed.
124 static inline int __attribute__((always_inline))
125 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
127 struct igb_tx_entry *txep;
131 /* check DD bit on threshold descriptor */
132 status = txq->tx_ring[txq->tx_next_dd].wb.status;
133 if (! (status & IXGBE_ADVTXD_STAT_DD))
137 * first buffer to free from S/W ring is at index
138 * tx_next_dd - (tx_rs_thresh-1)
140 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
142 /* free buffers one at a time */
143 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
144 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
145 txep->mbuf->next = NULL;
146 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
150 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
151 rte_pktmbuf_free_seg(txep->mbuf);
156 /* buffers were freed, update counters */
157 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
158 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
159 if (txq->tx_next_dd >= txq->nb_tx_desc)
160 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
162 return txq->tx_rs_thresh;
165 /* Populate 4 descriptors with data from 4 mbufs */
167 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
169 uint64_t buf_dma_addr;
173 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
174 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
175 pkt_len = (*pkts)->data_len;
177 /* write data to descriptor */
178 txdp->read.buffer_addr = buf_dma_addr;
179 txdp->read.cmd_type_len =
180 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
181 txdp->read.olinfo_status =
182 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
183 rte_prefetch0(&(*pkts)->pool);
187 /* Populate 1 descriptor with data from 1 mbuf */
189 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
191 uint64_t buf_dma_addr;
194 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
195 pkt_len = (*pkts)->data_len;
197 /* write data to descriptor */
198 txdp->read.buffer_addr = buf_dma_addr;
199 txdp->read.cmd_type_len =
200 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
201 txdp->read.olinfo_status =
202 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
203 rte_prefetch0(&(*pkts)->pool);
207 * Fill H/W descriptor ring with mbuf data.
208 * Copy mbuf pointers to the S/W ring.
211 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
214 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
215 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
216 const int N_PER_LOOP = 4;
217 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
218 int mainpart, leftover;
222 * Process most of the packets in chunks of N pkts. Any
223 * leftover packets will get processed one at a time.
225 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
226 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
227 for (i = 0; i < mainpart; i += N_PER_LOOP) {
228 /* Copy N mbuf pointers to the S/W ring */
229 for (j = 0; j < N_PER_LOOP; ++j) {
230 (txep + i + j)->mbuf = *(pkts + i + j);
232 tx4(txdp + i, pkts + i);
235 if (unlikely(leftover > 0)) {
236 for (i = 0; i < leftover; ++i) {
237 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
238 tx1(txdp + mainpart + i, pkts + mainpart + i);
243 static inline uint16_t
244 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
247 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
248 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
252 * Begin scanning the H/W ring for done descriptors when the
253 * number of available descriptors drops below tx_free_thresh. For
254 * each done descriptor, free the associated buffer.
256 if (txq->nb_tx_free < txq->tx_free_thresh)
257 ixgbe_tx_free_bufs(txq);
259 /* Only use descriptors that are available */
260 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
261 if (unlikely(nb_pkts == 0))
264 /* Use exactly nb_pkts descriptors */
265 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
268 * At this point, we know there are enough descriptors in the
269 * ring to transmit all the packets. This assumes that each
270 * mbuf contains a single segment, and that no new offloads
271 * are expected, which would require a new context descriptor.
275 * See if we're going to wrap-around. If so, handle the top
276 * of the descriptor ring first, then do the bottom. If not,
277 * the processing looks just like the "bottom" part anyway...
279 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
280 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
281 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
284 * We know that the last descriptor in the ring will need to
285 * have its RS bit set because tx_rs_thresh has to be
286 * a divisor of the ring size
288 tx_r[txq->tx_next_rs].read.cmd_type_len |=
289 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
290 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
295 /* Fill H/W descriptor ring with mbuf data */
296 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
297 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
300 * Determine if RS bit should be set
301 * This is what we actually want:
302 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
303 * but instead of subtracting 1 and doing >=, we can just do
304 * greater than without subtracting.
306 if (txq->tx_tail > txq->tx_next_rs) {
307 tx_r[txq->tx_next_rs].read.cmd_type_len |=
308 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
309 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
311 if (txq->tx_next_rs >= txq->nb_tx_desc)
312 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
316 * Check for wrap-around. This would only happen if we used
317 * up to the last descriptor in the ring, no more, no less.
319 if (txq->tx_tail >= txq->nb_tx_desc)
322 /* update tail pointer */
324 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
330 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
335 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
336 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
337 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
339 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
343 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
344 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
345 nb_tx = (uint16_t)(nb_tx + ret);
346 nb_pkts = (uint16_t)(nb_pkts - ret);
355 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
356 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
357 uint64_t ol_flags, union ixgbe_tx_offload tx_offload)
359 uint32_t type_tucmd_mlhl;
360 uint32_t mss_l4len_idx = 0;
362 uint32_t vlan_macip_lens;
363 union ixgbe_tx_offload tx_offload_mask;
365 ctx_idx = txq->ctx_curr;
366 tx_offload_mask.data = 0;
369 /* Specify which HW CTX to upload. */
370 mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
372 if (ol_flags & PKT_TX_VLAN_PKT) {
373 tx_offload_mask.vlan_tci |= ~0;
376 /* check if TCP segmentation required for this packet */
377 if (ol_flags & PKT_TX_TCP_SEG) {
378 /* implies IP cksum and TCP cksum */
379 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
380 IXGBE_ADVTXD_TUCMD_L4T_TCP |
381 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
383 tx_offload_mask.l2_len |= ~0;
384 tx_offload_mask.l3_len |= ~0;
385 tx_offload_mask.l4_len |= ~0;
386 tx_offload_mask.tso_segsz |= ~0;
387 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
388 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
389 } else { /* no TSO, check if hardware checksum is needed */
390 if (ol_flags & PKT_TX_IP_CKSUM) {
391 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
392 tx_offload_mask.l2_len |= ~0;
393 tx_offload_mask.l3_len |= ~0;
396 switch (ol_flags & PKT_TX_L4_MASK) {
397 case PKT_TX_UDP_CKSUM:
398 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
399 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
400 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
401 tx_offload_mask.l2_len |= ~0;
402 tx_offload_mask.l3_len |= ~0;
404 case PKT_TX_TCP_CKSUM:
405 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
406 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
407 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
408 tx_offload_mask.l2_len |= ~0;
409 tx_offload_mask.l3_len |= ~0;
410 tx_offload_mask.l4_len |= ~0;
412 case PKT_TX_SCTP_CKSUM:
413 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
414 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
415 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
416 tx_offload_mask.l2_len |= ~0;
417 tx_offload_mask.l3_len |= ~0;
420 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
421 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
426 txq->ctx_cache[ctx_idx].flags = ol_flags;
427 txq->ctx_cache[ctx_idx].tx_offload.data =
428 tx_offload_mask.data & tx_offload.data;
429 txq->ctx_cache[ctx_idx].tx_offload_mask = tx_offload_mask;
431 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
432 vlan_macip_lens = tx_offload.l3_len;
433 vlan_macip_lens |= (tx_offload.l2_len << IXGBE_ADVTXD_MACLEN_SHIFT);
434 vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
435 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
436 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
437 ctx_txd->seqnum_seed = 0;
441 * Check which hardware context can be used. Use the existing match
442 * or create a new context descriptor.
444 static inline uint32_t
445 what_advctx_update(struct igb_tx_queue *txq, uint64_t flags,
446 union ixgbe_tx_offload tx_offload)
448 /* If match with the current used context */
449 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
450 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
451 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
452 return txq->ctx_curr;
455 /* What if match with the next context */
457 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
458 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
459 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
460 return txq->ctx_curr;
463 /* Mismatch, use the previous context */
464 return (IXGBE_CTX_NUM);
467 static inline uint32_t
468 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
471 if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
472 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
473 if (ol_flags & PKT_TX_IP_CKSUM)
474 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
475 if (ol_flags & PKT_TX_TCP_SEG)
476 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
480 static inline uint32_t
481 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
483 uint32_t cmdtype = 0;
484 if (ol_flags & PKT_TX_VLAN_PKT)
485 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
486 if (ol_flags & PKT_TX_TCP_SEG)
487 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
491 /* Default RS bit threshold values */
492 #ifndef DEFAULT_TX_RS_THRESH
493 #define DEFAULT_TX_RS_THRESH 32
495 #ifndef DEFAULT_TX_FREE_THRESH
496 #define DEFAULT_TX_FREE_THRESH 32
499 /* Reset transmit descriptors after they have been used */
501 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
503 struct igb_tx_entry *sw_ring = txq->sw_ring;
504 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
505 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
506 uint16_t nb_tx_desc = txq->nb_tx_desc;
507 uint16_t desc_to_clean_to;
508 uint16_t nb_tx_to_clean;
510 /* Determine the last descriptor needing to be cleaned */
511 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
512 if (desc_to_clean_to >= nb_tx_desc)
513 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
515 /* Check to make sure the last descriptor to clean is done */
516 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
517 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
519 PMD_TX_FREE_LOG(DEBUG,
520 "TX descriptor %4u is not done"
521 "(port=%d queue=%d)",
523 txq->port_id, txq->queue_id);
524 /* Failed to clean any descriptors, better luck next time */
528 /* Figure out how many descriptors will be cleaned */
529 if (last_desc_cleaned > desc_to_clean_to)
530 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
533 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
536 PMD_TX_FREE_LOG(DEBUG,
537 "Cleaning %4u TX descriptors: %4u to %4u "
538 "(port=%d queue=%d)",
539 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
540 txq->port_id, txq->queue_id);
543 * The last descriptor to clean is done, so that means all the
544 * descriptors from the last descriptor that was cleaned
545 * up to the last descriptor with the RS bit set
546 * are done. Only reset the threshold descriptor.
548 txr[desc_to_clean_to].wb.status = 0;
550 /* Update the txq to reflect the last descriptor that was cleaned */
551 txq->last_desc_cleaned = desc_to_clean_to;
552 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
559 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
562 struct igb_tx_queue *txq;
563 struct igb_tx_entry *sw_ring;
564 struct igb_tx_entry *txe, *txn;
565 volatile union ixgbe_adv_tx_desc *txr;
566 volatile union ixgbe_adv_tx_desc *txd;
567 struct rte_mbuf *tx_pkt;
568 struct rte_mbuf *m_seg;
569 uint64_t buf_dma_addr;
570 uint32_t olinfo_status;
571 uint32_t cmd_type_len;
582 union ixgbe_tx_offload tx_offload = { .data = 0 };
585 sw_ring = txq->sw_ring;
587 tx_id = txq->tx_tail;
588 txe = &sw_ring[tx_id];
590 /* Determine if the descriptor ring needs to be cleaned. */
591 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
592 ixgbe_xmit_cleanup(txq);
595 rte_prefetch0(&txe->mbuf->pool);
598 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
601 pkt_len = tx_pkt->pkt_len;
604 * Determine how many (if any) context descriptors
605 * are needed for offload functionality.
607 ol_flags = tx_pkt->ol_flags;
609 /* If hardware offload required */
610 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
612 tx_offload.l2_len = tx_pkt->l2_len;
613 tx_offload.l3_len = tx_pkt->l3_len;
614 tx_offload.l4_len = tx_pkt->l4_len;
615 tx_offload.vlan_tci = tx_pkt->vlan_tci;
616 tx_offload.tso_segsz = tx_pkt->tso_segsz;
618 /* If new context need be built or reuse the exist ctx. */
619 ctx = what_advctx_update(txq, tx_ol_req,
621 /* Only allocate context descriptor if required*/
622 new_ctx = (ctx == IXGBE_CTX_NUM);
627 * Keep track of how many descriptors are used this loop
628 * This will always be the number of segments + the number of
629 * Context descriptors required to transmit the packet
631 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
634 * The number of descriptors that must be allocated for a
635 * packet is the number of segments of that packet, plus 1
636 * Context Descriptor for the hardware offload, if any.
637 * Determine the last TX descriptor to allocate in the TX ring
638 * for the packet, starting from the current position (tx_id)
641 tx_last = (uint16_t) (tx_id + nb_used - 1);
644 if (tx_last >= txq->nb_tx_desc)
645 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
647 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
648 " tx_first=%u tx_last=%u",
649 (unsigned) txq->port_id,
650 (unsigned) txq->queue_id,
656 * Make sure there are enough TX descriptors available to
657 * transmit the entire packet.
658 * nb_used better be less than or equal to txq->tx_rs_thresh
660 if (nb_used > txq->nb_tx_free) {
661 PMD_TX_FREE_LOG(DEBUG,
662 "Not enough free TX descriptors "
663 "nb_used=%4u nb_free=%4u "
664 "(port=%d queue=%d)",
665 nb_used, txq->nb_tx_free,
666 txq->port_id, txq->queue_id);
668 if (ixgbe_xmit_cleanup(txq) != 0) {
669 /* Could not clean any descriptors */
675 /* nb_used better be <= txq->tx_rs_thresh */
676 if (unlikely(nb_used > txq->tx_rs_thresh)) {
677 PMD_TX_FREE_LOG(DEBUG,
678 "The number of descriptors needed to "
679 "transmit the packet exceeds the "
680 "RS bit threshold. This will impact "
682 "nb_used=%4u nb_free=%4u "
684 "(port=%d queue=%d)",
685 nb_used, txq->nb_tx_free,
687 txq->port_id, txq->queue_id);
689 * Loop here until there are enough TX
690 * descriptors or until the ring cannot be
693 while (nb_used > txq->nb_tx_free) {
694 if (ixgbe_xmit_cleanup(txq) != 0) {
696 * Could not clean any
708 * By now there are enough free TX descriptors to transmit
713 * Set common flags of all TX Data Descriptors.
715 * The following bits must be set in all Data Descriptors:
716 * - IXGBE_ADVTXD_DTYP_DATA
717 * - IXGBE_ADVTXD_DCMD_DEXT
719 * The following bits must be set in the first Data Descriptor
720 * and are ignored in the other ones:
721 * - IXGBE_ADVTXD_DCMD_IFCS
722 * - IXGBE_ADVTXD_MAC_1588
723 * - IXGBE_ADVTXD_DCMD_VLE
725 * The following bits must only be set in the last Data
727 * - IXGBE_TXD_CMD_EOP
729 * The following bits can be set in any Data Descriptor, but
730 * are only set in the last Data Descriptor:
733 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
734 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
736 #ifdef RTE_LIBRTE_IEEE1588
737 if (ol_flags & PKT_TX_IEEE1588_TMST)
738 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
744 if (ol_flags & PKT_TX_TCP_SEG) {
745 /* when TSO is on, paylen in descriptor is the
746 * not the packet len but the tcp payload len */
747 pkt_len -= (tx_offload.l2_len +
748 tx_offload.l3_len + tx_offload.l4_len);
752 * Setup the TX Advanced Context Descriptor if required
755 volatile struct ixgbe_adv_tx_context_desc *
758 ctx_txd = (volatile struct
759 ixgbe_adv_tx_context_desc *)
762 txn = &sw_ring[txe->next_id];
763 rte_prefetch0(&txn->mbuf->pool);
765 if (txe->mbuf != NULL) {
766 rte_pktmbuf_free_seg(txe->mbuf);
770 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
773 txe->last_id = tx_last;
774 tx_id = txe->next_id;
779 * Setup the TX Advanced Data Descriptor,
780 * This path will go through
781 * whatever new/reuse the context descriptor
783 cmd_type_len |= tx_desc_ol_flags_to_cmdtype(ol_flags);
784 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
785 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
788 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
793 txn = &sw_ring[txe->next_id];
794 rte_prefetch0(&txn->mbuf->pool);
796 if (txe->mbuf != NULL)
797 rte_pktmbuf_free_seg(txe->mbuf);
801 * Set up Transmit Data Descriptor.
803 slen = m_seg->data_len;
804 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
805 txd->read.buffer_addr =
806 rte_cpu_to_le_64(buf_dma_addr);
807 txd->read.cmd_type_len =
808 rte_cpu_to_le_32(cmd_type_len | slen);
809 txd->read.olinfo_status =
810 rte_cpu_to_le_32(olinfo_status);
811 txe->last_id = tx_last;
812 tx_id = txe->next_id;
815 } while (m_seg != NULL);
818 * The last packet data descriptor needs End Of Packet (EOP)
820 cmd_type_len |= IXGBE_TXD_CMD_EOP;
821 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
822 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
824 /* Set RS bit only on threshold packets' last descriptor */
825 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
826 PMD_TX_FREE_LOG(DEBUG,
827 "Setting RS bit on TXD id="
828 "%4u (port=%d queue=%d)",
829 tx_last, txq->port_id, txq->queue_id);
831 cmd_type_len |= IXGBE_TXD_CMD_RS;
833 /* Update txq RS bit counters */
836 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
842 * Set the Transmit Descriptor Tail (TDT)
844 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
845 (unsigned) txq->port_id, (unsigned) txq->queue_id,
846 (unsigned) tx_id, (unsigned) nb_tx);
847 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
848 txq->tx_tail = tx_id;
853 /*********************************************************************
857 **********************************************************************/
858 static inline uint64_t
859 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
863 static uint64_t ip_pkt_types_map[16] = {
864 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
865 PKT_RX_IPV6_HDR, 0, 0, 0,
866 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
867 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
870 static uint64_t ip_rss_types_map[16] = {
871 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
872 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
873 PKT_RX_RSS_HASH, 0, 0, 0,
874 0, 0, 0, PKT_RX_FDIR,
877 #ifdef RTE_LIBRTE_IEEE1588
878 static uint64_t ip_pkt_etqf_map[8] = {
879 0, 0, 0, PKT_RX_IEEE1588_PTP,
883 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
884 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
885 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
887 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
888 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
891 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
894 static inline uint64_t
895 rx_desc_status_to_pkt_flags(uint32_t rx_status)
900 * Check if VLAN present only.
901 * Do not check whether L3/L4 rx checksum done by NIC or not,
902 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
904 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
906 #ifdef RTE_LIBRTE_IEEE1588
907 if (rx_status & IXGBE_RXD_STAT_TMST)
908 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
913 static inline uint64_t
914 rx_desc_error_to_pkt_flags(uint32_t rx_status)
917 * Bit 31: IPE, IPv4 checksum error
918 * Bit 30: L4I, L4I integrity error
920 static uint64_t error_to_pkt_flags_map[4] = {
921 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
922 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
924 return error_to_pkt_flags_map[(rx_status >>
925 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
928 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
930 * LOOK_AHEAD defines how many desc statuses to check beyond the
931 * current descriptor.
932 * It must be a pound define for optimal performance.
933 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
934 * function only works with LOOK_AHEAD=8.
937 #if (LOOK_AHEAD != 8)
938 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
941 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
943 volatile union ixgbe_adv_rx_desc *rxdp;
944 struct igb_rx_entry *rxep;
948 int s[LOOK_AHEAD], nb_dd;
952 /* get references to current descriptor and S/W ring entry */
953 rxdp = &rxq->rx_ring[rxq->rx_tail];
954 rxep = &rxq->sw_ring[rxq->rx_tail];
956 /* check to make sure there is at least 1 packet to receive */
957 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
961 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
962 * reference packets that are ready to be received.
964 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
965 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
967 /* Read desc statuses backwards to avoid race condition */
968 for (j = LOOK_AHEAD-1; j >= 0; --j)
969 s[j] = rxdp[j].wb.upper.status_error;
971 /* Compute how many status bits were set */
973 for (j = 0; j < LOOK_AHEAD; ++j)
974 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
978 /* Translate descriptor info to mbuf format */
979 for (j = 0; j < nb_dd; ++j) {
981 pkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len);
982 mb->data_len = pkt_len;
983 mb->pkt_len = pkt_len;
984 mb->vlan_tci = rxdp[j].wb.upper.vlan;
985 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
987 /* convert descriptor fields to rte mbuf flags */
988 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(
989 rxdp[j].wb.lower.lo_dword.data);
990 /* reuse status field from scan list */
991 pkt_flags |= rx_desc_status_to_pkt_flags(s[j]);
992 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
993 mb->ol_flags = pkt_flags;
995 if (likely(pkt_flags & PKT_RX_RSS_HASH))
996 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
997 else if (pkt_flags & PKT_RX_FDIR) {
999 (uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum)
1000 & IXGBE_ATR_HASH_MASK);
1001 mb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id;
1005 /* Move mbuf pointers from the S/W ring to the stage */
1006 for (j = 0; j < LOOK_AHEAD; ++j) {
1007 rxq->rx_stage[i + j] = rxep[j].mbuf;
1010 /* stop if all requested packets could not be received */
1011 if (nb_dd != LOOK_AHEAD)
1015 /* clear software ring entries so we can cleanup correctly */
1016 for (i = 0; i < nb_rx; ++i) {
1017 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1025 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
1027 volatile union ixgbe_adv_rx_desc *rxdp;
1028 struct igb_rx_entry *rxep;
1029 struct rte_mbuf *mb;
1034 /* allocate buffers in bulk directly into the S/W ring */
1035 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1036 (rxq->rx_free_thresh - 1));
1037 rxep = &rxq->sw_ring[alloc_idx];
1038 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1039 rxq->rx_free_thresh);
1040 if (unlikely(diag != 0))
1043 rxdp = &rxq->rx_ring[alloc_idx];
1044 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1045 /* populate the static rte mbuf fields */
1047 rte_mbuf_refcnt_set(mb, 1);
1049 mb->data_off = RTE_PKTMBUF_HEADROOM;
1051 mb->port = rxq->port_id;
1053 /* populate the descriptors */
1054 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1055 rxdp[i].read.hdr_addr = dma_addr;
1056 rxdp[i].read.pkt_addr = dma_addr;
1059 /* update tail pointer */
1061 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1063 /* update state of internal queue structure */
1064 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1065 rxq->rx_free_thresh);
1066 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1067 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1073 static inline uint16_t
1074 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1077 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1080 /* how many packets are ready to return? */
1081 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1083 /* copy mbuf pointers to the application's packet list */
1084 for (i = 0; i < nb_pkts; ++i)
1085 rx_pkts[i] = stage[i];
1087 /* update internal queue state */
1088 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1089 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1094 static inline uint16_t
1095 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1098 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1101 /* Any previously recv'd pkts will be returned from the Rx stage */
1102 if (rxq->rx_nb_avail)
1103 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1105 /* Scan the H/W ring for packets to receive */
1106 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1108 /* update internal queue state */
1109 rxq->rx_next_avail = 0;
1110 rxq->rx_nb_avail = nb_rx;
1111 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1113 /* if required, allocate new buffers to replenish descriptors */
1114 if (rxq->rx_tail > rxq->rx_free_trigger) {
1115 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1117 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1118 "queue_id=%u", (unsigned) rxq->port_id,
1119 (unsigned) rxq->queue_id);
1121 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1122 rxq->rx_free_thresh;
1125 * Need to rewind any previous receives if we cannot
1126 * allocate new buffers to replenish the old ones.
1128 rxq->rx_nb_avail = 0;
1129 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1130 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1131 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1137 if (rxq->rx_tail >= rxq->nb_rx_desc)
1140 /* received any packets this loop? */
1141 if (rxq->rx_nb_avail)
1142 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1147 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1149 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1154 if (unlikely(nb_pkts == 0))
1157 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1158 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1160 /* request is relatively large, chunk it up */
1164 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1165 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1166 nb_rx = (uint16_t)(nb_rx + ret);
1167 nb_pkts = (uint16_t)(nb_pkts - ret);
1174 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1177 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1180 struct igb_rx_queue *rxq;
1181 volatile union ixgbe_adv_rx_desc *rx_ring;
1182 volatile union ixgbe_adv_rx_desc *rxdp;
1183 struct igb_rx_entry *sw_ring;
1184 struct igb_rx_entry *rxe;
1185 struct rte_mbuf *rxm;
1186 struct rte_mbuf *nmb;
1187 union ixgbe_adv_rx_desc rxd;
1190 uint32_t hlen_type_rss;
1200 rx_id = rxq->rx_tail;
1201 rx_ring = rxq->rx_ring;
1202 sw_ring = rxq->sw_ring;
1203 while (nb_rx < nb_pkts) {
1205 * The order of operations here is important as the DD status
1206 * bit must not be read after any other descriptor fields.
1207 * rx_ring and rxdp are pointing to volatile data so the order
1208 * of accesses cannot be reordered by the compiler. If they were
1209 * not volatile, they could be reordered which could lead to
1210 * using invalid descriptor fields when read from rxd.
1212 rxdp = &rx_ring[rx_id];
1213 staterr = rxdp->wb.upper.status_error;
1214 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1221 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1222 * is likely to be invalid and to be dropped by the various
1223 * validation checks performed by the network stack.
1225 * Allocate a new mbuf to replenish the RX ring descriptor.
1226 * If the allocation fails:
1227 * - arrange for that RX descriptor to be the first one
1228 * being parsed the next time the receive function is
1229 * invoked [on the same queue].
1231 * - Stop parsing the RX ring and return immediately.
1233 * This policy do not drop the packet received in the RX
1234 * descriptor for which the allocation of a new mbuf failed.
1235 * Thus, it allows that packet to be later retrieved if
1236 * mbuf have been freed in the mean time.
1237 * As a side effect, holding RX descriptors instead of
1238 * systematically giving them back to the NIC may lead to
1239 * RX ring exhaustion situations.
1240 * However, the NIC can gracefully prevent such situations
1241 * to happen by sending specific "back-pressure" flow control
1242 * frames to its peer(s).
1244 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1245 "ext_err_stat=0x%08x pkt_len=%u",
1246 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1247 (unsigned) rx_id, (unsigned) staterr,
1248 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1250 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1252 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1253 "queue_id=%u", (unsigned) rxq->port_id,
1254 (unsigned) rxq->queue_id);
1255 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1260 rxe = &sw_ring[rx_id];
1262 if (rx_id == rxq->nb_rx_desc)
1265 /* Prefetch next mbuf while processing current one. */
1266 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1269 * When next RX descriptor is on a cache-line boundary,
1270 * prefetch the next 4 RX descriptors and the next 8 pointers
1273 if ((rx_id & 0x3) == 0) {
1274 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1275 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1281 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1282 rxdp->read.hdr_addr = dma_addr;
1283 rxdp->read.pkt_addr = dma_addr;
1286 * Initialize the returned mbuf.
1287 * 1) setup generic mbuf fields:
1288 * - number of segments,
1291 * - RX port identifier.
1292 * 2) integrate hardware offload data, if any:
1293 * - RSS flag & hash,
1294 * - IP checksum flag,
1295 * - VLAN TCI, if any,
1298 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1300 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1301 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1304 rxm->pkt_len = pkt_len;
1305 rxm->data_len = pkt_len;
1306 rxm->port = rxq->port_id;
1308 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1309 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1310 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1312 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1313 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1314 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1315 rxm->ol_flags = pkt_flags;
1317 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1318 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1319 else if (pkt_flags & PKT_RX_FDIR) {
1320 rxm->hash.fdir.hash =
1321 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1322 & IXGBE_ATR_HASH_MASK);
1323 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1326 * Store the mbuf address into the next entry of the array
1327 * of returned packets.
1329 rx_pkts[nb_rx++] = rxm;
1331 rxq->rx_tail = rx_id;
1334 * If the number of free RX descriptors is greater than the RX free
1335 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1337 * Update the RDT with the value of the last processed RX descriptor
1338 * minus 1, to guarantee that the RDT register is never equal to the
1339 * RDH register, which creates a "full" ring situtation from the
1340 * hardware point of view...
1342 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1343 if (nb_hold > rxq->rx_free_thresh) {
1344 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1345 "nb_hold=%u nb_rx=%u",
1346 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1347 (unsigned) rx_id, (unsigned) nb_hold,
1349 rx_id = (uint16_t) ((rx_id == 0) ?
1350 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1351 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1354 rxq->nb_rx_hold = nb_hold;
1359 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1362 struct igb_rx_queue *rxq;
1363 volatile union ixgbe_adv_rx_desc *rx_ring;
1364 volatile union ixgbe_adv_rx_desc *rxdp;
1365 struct igb_rx_entry *sw_ring;
1366 struct igb_rx_entry *rxe;
1367 struct rte_mbuf *first_seg;
1368 struct rte_mbuf *last_seg;
1369 struct rte_mbuf *rxm;
1370 struct rte_mbuf *nmb;
1371 union ixgbe_adv_rx_desc rxd;
1372 uint64_t dma; /* Physical address of mbuf data buffer */
1374 uint32_t hlen_type_rss;
1384 rx_id = rxq->rx_tail;
1385 rx_ring = rxq->rx_ring;
1386 sw_ring = rxq->sw_ring;
1389 * Retrieve RX context of current packet, if any.
1391 first_seg = rxq->pkt_first_seg;
1392 last_seg = rxq->pkt_last_seg;
1394 while (nb_rx < nb_pkts) {
1397 * The order of operations here is important as the DD status
1398 * bit must not be read after any other descriptor fields.
1399 * rx_ring and rxdp are pointing to volatile data so the order
1400 * of accesses cannot be reordered by the compiler. If they were
1401 * not volatile, they could be reordered which could lead to
1402 * using invalid descriptor fields when read from rxd.
1404 rxdp = &rx_ring[rx_id];
1405 staterr = rxdp->wb.upper.status_error;
1406 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1413 * Allocate a new mbuf to replenish the RX ring descriptor.
1414 * If the allocation fails:
1415 * - arrange for that RX descriptor to be the first one
1416 * being parsed the next time the receive function is
1417 * invoked [on the same queue].
1419 * - Stop parsing the RX ring and return immediately.
1421 * This policy does not drop the packet received in the RX
1422 * descriptor for which the allocation of a new mbuf failed.
1423 * Thus, it allows that packet to be later retrieved if
1424 * mbuf have been freed in the mean time.
1425 * As a side effect, holding RX descriptors instead of
1426 * systematically giving them back to the NIC may lead to
1427 * RX ring exhaustion situations.
1428 * However, the NIC can gracefully prevent such situations
1429 * to happen by sending specific "back-pressure" flow control
1430 * frames to its peer(s).
1432 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1433 "staterr=0x%x data_len=%u",
1434 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1435 (unsigned) rx_id, (unsigned) staterr,
1436 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1438 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1440 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1441 "queue_id=%u", (unsigned) rxq->port_id,
1442 (unsigned) rxq->queue_id);
1443 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1448 rxe = &sw_ring[rx_id];
1450 if (rx_id == rxq->nb_rx_desc)
1453 /* Prefetch next mbuf while processing current one. */
1454 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1457 * When next RX descriptor is on a cache-line boundary,
1458 * prefetch the next 4 RX descriptors and the next 8 pointers
1461 if ((rx_id & 0x3) == 0) {
1462 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1463 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1467 * Update RX descriptor with the physical address of the new
1468 * data buffer of the new allocated mbuf.
1472 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1473 rxdp->read.hdr_addr = dma;
1474 rxdp->read.pkt_addr = dma;
1477 * Set data length & data buffer address of mbuf.
1479 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1480 rxm->data_len = data_len;
1481 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1484 * If this is the first buffer of the received packet,
1485 * set the pointer to the first mbuf of the packet and
1486 * initialize its context.
1487 * Otherwise, update the total length and the number of segments
1488 * of the current scattered packet, and update the pointer to
1489 * the last mbuf of the current packet.
1491 if (first_seg == NULL) {
1493 first_seg->pkt_len = data_len;
1494 first_seg->nb_segs = 1;
1496 first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
1498 first_seg->nb_segs++;
1499 last_seg->next = rxm;
1503 * If this is not the last buffer of the received packet,
1504 * update the pointer to the last mbuf of the current scattered
1505 * packet and continue to parse the RX ring.
1507 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1513 * This is the last buffer of the received packet.
1514 * If the CRC is not stripped by the hardware:
1515 * - Subtract the CRC length from the total packet length.
1516 * - If the last buffer only contains the whole CRC or a part
1517 * of it, free the mbuf associated to the last buffer.
1518 * If part of the CRC is also contained in the previous
1519 * mbuf, subtract the length of that CRC part from the
1520 * data length of the previous mbuf.
1523 if (unlikely(rxq->crc_len > 0)) {
1524 first_seg->pkt_len -= ETHER_CRC_LEN;
1525 if (data_len <= ETHER_CRC_LEN) {
1526 rte_pktmbuf_free_seg(rxm);
1527 first_seg->nb_segs--;
1528 last_seg->data_len = (uint16_t)
1529 (last_seg->data_len -
1530 (ETHER_CRC_LEN - data_len));
1531 last_seg->next = NULL;
1534 (uint16_t) (data_len - ETHER_CRC_LEN);
1538 * Initialize the first mbuf of the returned packet:
1539 * - RX port identifier,
1540 * - hardware offload data, if any:
1541 * - RSS flag & hash,
1542 * - IP checksum flag,
1543 * - VLAN TCI, if any,
1546 first_seg->port = rxq->port_id;
1549 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1550 * set in the pkt_flags field.
1552 first_seg->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1553 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1554 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1555 pkt_flags = (pkt_flags |
1556 rx_desc_status_to_pkt_flags(staterr));
1557 pkt_flags = (pkt_flags |
1558 rx_desc_error_to_pkt_flags(staterr));
1559 first_seg->ol_flags = pkt_flags;
1561 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1562 first_seg->hash.rss = rxd.wb.lower.hi_dword.rss;
1563 else if (pkt_flags & PKT_RX_FDIR) {
1564 first_seg->hash.fdir.hash =
1565 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1566 & IXGBE_ATR_HASH_MASK);
1567 first_seg->hash.fdir.id =
1568 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1571 /* Prefetch data of first segment, if configured to do so. */
1572 rte_packet_prefetch((char *)first_seg->buf_addr +
1573 first_seg->data_off);
1576 * Store the mbuf address into the next entry of the array
1577 * of returned packets.
1579 rx_pkts[nb_rx++] = first_seg;
1582 * Setup receipt context for a new packet.
1588 * Record index of the next RX descriptor to probe.
1590 rxq->rx_tail = rx_id;
1593 * Save receive context.
1595 rxq->pkt_first_seg = first_seg;
1596 rxq->pkt_last_seg = last_seg;
1599 * If the number of free RX descriptors is greater than the RX free
1600 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1602 * Update the RDT with the value of the last processed RX descriptor
1603 * minus 1, to guarantee that the RDT register is never equal to the
1604 * RDH register, which creates a "full" ring situtation from the
1605 * hardware point of view...
1607 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1608 if (nb_hold > rxq->rx_free_thresh) {
1609 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1610 "nb_hold=%u nb_rx=%u",
1611 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1612 (unsigned) rx_id, (unsigned) nb_hold,
1614 rx_id = (uint16_t) ((rx_id == 0) ?
1615 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1616 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1619 rxq->nb_rx_hold = nb_hold;
1623 /*********************************************************************
1625 * Queue management functions
1627 **********************************************************************/
1630 * Rings setup and release.
1632 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1633 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1634 * also optimize cache line size effect. H/W supports up to cache line size 128.
1636 #define IXGBE_ALIGN 128
1639 * Maximum number of Ring Descriptors.
1641 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1642 * descriptors should meet the following condition:
1643 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1645 #define IXGBE_MIN_RING_DESC 32
1646 #define IXGBE_MAX_RING_DESC 4096
1649 * Create memzone for HW rings. malloc can't be used as the physical address is
1650 * needed. If the memzone is already created, then this function returns a ptr
1653 static const struct rte_memzone *
1654 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1655 uint16_t queue_id, uint32_t ring_size, int socket_id)
1657 char z_name[RTE_MEMZONE_NAMESIZE];
1658 const struct rte_memzone *mz;
1660 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1661 dev->driver->pci_drv.name, ring_name,
1662 dev->data->port_id, queue_id);
1664 mz = rte_memzone_lookup(z_name);
1668 #ifdef RTE_LIBRTE_XEN_DOM0
1669 return rte_memzone_reserve_bounded(z_name, ring_size,
1670 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1672 return rte_memzone_reserve_aligned(z_name, ring_size,
1673 socket_id, 0, IXGBE_ALIGN);
1678 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1682 if (txq->sw_ring != NULL) {
1683 for (i = 0; i < txq->nb_tx_desc; i++) {
1684 if (txq->sw_ring[i].mbuf != NULL) {
1685 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1686 txq->sw_ring[i].mbuf = NULL;
1693 ixgbe_tx_free_swring(struct igb_tx_queue *txq)
1696 txq->sw_ring != NULL)
1697 rte_free(txq->sw_ring);
1701 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1703 if (txq != NULL && txq->ops != NULL) {
1704 txq->ops->release_mbufs(txq);
1705 txq->ops->free_swring(txq);
1711 ixgbe_dev_tx_queue_release(void *txq)
1713 ixgbe_tx_queue_release(txq);
1716 /* (Re)set dynamic igb_tx_queue fields to defaults */
1718 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1720 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1722 struct igb_tx_entry *txe = txq->sw_ring;
1725 /* Zero out HW ring memory */
1726 for (i = 0; i < txq->nb_tx_desc; i++) {
1727 txq->tx_ring[i] = zeroed_desc;
1730 /* Initialize SW ring entries */
1731 prev = (uint16_t) (txq->nb_tx_desc - 1);
1732 for (i = 0; i < txq->nb_tx_desc; i++) {
1733 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1734 txd->wb.status = IXGBE_TXD_STAT_DD;
1737 txe[prev].next_id = i;
1741 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1742 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1745 txq->nb_tx_used = 0;
1747 * Always allow 1 descriptor to be un-allocated to avoid
1748 * a H/W race condition
1750 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1751 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1753 memset((void*)&txq->ctx_cache, 0,
1754 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1757 static struct ixgbe_txq_ops def_txq_ops = {
1758 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1759 .free_swring = ixgbe_tx_free_swring,
1760 .reset = ixgbe_reset_tx_queue,
1763 /* Takes an ethdev and a queue and sets up the tx function to be used based on
1764 * the queue parameters. Used in tx_queue_setup by primary process and then
1765 * in dev_init by secondary process when attaching to an existing ethdev.
1768 set_tx_function(struct rte_eth_dev *dev, struct igb_tx_queue *txq)
1770 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1771 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS)
1772 && (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1773 PMD_INIT_LOG(INFO, "Using simple tx code path");
1774 #ifdef RTE_IXGBE_INC_VECTOR
1775 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1776 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
1777 ixgbe_txq_vec_setup(txq) == 0)) {
1778 PMD_INIT_LOG(INFO, "Vector tx enabled.");
1779 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1782 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1784 PMD_INIT_LOG(INFO, "Using full-featured tx code path");
1786 " - txq_flags = %lx " "[IXGBE_SIMPLE_FLAGS=%lx]",
1787 (unsigned long)txq->txq_flags,
1788 (unsigned long)IXGBE_SIMPLE_FLAGS);
1790 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
1791 (unsigned long)txq->tx_rs_thresh,
1792 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
1793 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1798 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1801 unsigned int socket_id,
1802 const struct rte_eth_txconf *tx_conf)
1804 const struct rte_memzone *tz;
1805 struct igb_tx_queue *txq;
1806 struct ixgbe_hw *hw;
1807 uint16_t tx_rs_thresh, tx_free_thresh;
1809 PMD_INIT_FUNC_TRACE();
1810 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1813 * Validate number of transmit descriptors.
1814 * It must not exceed hardware maximum, and must be multiple
1817 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1818 (nb_desc > IXGBE_MAX_RING_DESC) ||
1819 (nb_desc < IXGBE_MIN_RING_DESC)) {
1824 * The following two parameters control the setting of the RS bit on
1825 * transmit descriptors.
1826 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1827 * descriptors have been used.
1828 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1829 * descriptors are used or if the number of descriptors required
1830 * to transmit a packet is greater than the number of free TX
1832 * The following constraints must be satisfied:
1833 * tx_rs_thresh must be greater than 0.
1834 * tx_rs_thresh must be less than the size of the ring minus 2.
1835 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1836 * tx_rs_thresh must be a divisor of the ring size.
1837 * tx_free_thresh must be greater than 0.
1838 * tx_free_thresh must be less than the size of the ring minus 3.
1839 * One descriptor in the TX ring is used as a sentinel to avoid a
1840 * H/W race condition, hence the maximum threshold constraints.
1841 * When set to zero use default values.
1843 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1844 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1845 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1846 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1847 if (tx_rs_thresh >= (nb_desc - 2)) {
1848 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
1849 "of TX descriptors minus 2. (tx_rs_thresh=%u "
1850 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1851 (int)dev->data->port_id, (int)queue_idx);
1854 if (tx_free_thresh >= (nb_desc - 3)) {
1855 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1856 "tx_free_thresh must be less than the number of "
1857 "TX descriptors minus 3. (tx_free_thresh=%u "
1858 "port=%d queue=%d)",
1859 (unsigned int)tx_free_thresh,
1860 (int)dev->data->port_id, (int)queue_idx);
1863 if (tx_rs_thresh > tx_free_thresh) {
1864 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
1865 "tx_free_thresh. (tx_free_thresh=%u "
1866 "tx_rs_thresh=%u port=%d queue=%d)",
1867 (unsigned int)tx_free_thresh,
1868 (unsigned int)tx_rs_thresh,
1869 (int)dev->data->port_id,
1873 if ((nb_desc % tx_rs_thresh) != 0) {
1874 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1875 "number of TX descriptors. (tx_rs_thresh=%u "
1876 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1877 (int)dev->data->port_id, (int)queue_idx);
1882 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1883 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1884 * by the NIC and all descriptors are written back after the NIC
1885 * accumulates WTHRESH descriptors.
1887 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1888 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1889 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1890 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1891 (int)dev->data->port_id, (int)queue_idx);
1895 /* Free memory prior to re-allocation if needed... */
1896 if (dev->data->tx_queues[queue_idx] != NULL) {
1897 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1898 dev->data->tx_queues[queue_idx] = NULL;
1901 /* First allocate the tx queue data structure */
1902 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct igb_tx_queue),
1903 RTE_CACHE_LINE_SIZE, socket_id);
1908 * Allocate TX ring hardware descriptors. A memzone large enough to
1909 * handle the maximum ring size is allocated in order to allow for
1910 * resizing in later calls to the queue setup function.
1912 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1913 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1916 ixgbe_tx_queue_release(txq);
1920 txq->nb_tx_desc = nb_desc;
1921 txq->tx_rs_thresh = tx_rs_thresh;
1922 txq->tx_free_thresh = tx_free_thresh;
1923 txq->pthresh = tx_conf->tx_thresh.pthresh;
1924 txq->hthresh = tx_conf->tx_thresh.hthresh;
1925 txq->wthresh = tx_conf->tx_thresh.wthresh;
1926 txq->queue_id = queue_idx;
1927 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1928 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1929 txq->port_id = dev->data->port_id;
1930 txq->txq_flags = tx_conf->txq_flags;
1931 txq->ops = &def_txq_ops;
1932 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1935 * Modification to set VFTDT for virtual function if vf is detected
1937 if (hw->mac.type == ixgbe_mac_82599_vf ||
1938 hw->mac.type == ixgbe_mac_X540_vf)
1939 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1941 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1942 #ifndef RTE_LIBRTE_XEN_DOM0
1943 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1945 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1947 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1949 /* Allocate software ring */
1950 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1951 sizeof(struct igb_tx_entry) * nb_desc,
1952 RTE_CACHE_LINE_SIZE, socket_id);
1953 if (txq->sw_ring == NULL) {
1954 ixgbe_tx_queue_release(txq);
1957 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1958 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1960 /* set up vector or scalar TX function as appropriate */
1961 set_tx_function(dev, txq);
1963 txq->ops->reset(txq);
1965 dev->data->tx_queues[queue_idx] = txq;
1972 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1976 if (rxq->sw_ring != NULL) {
1977 for (i = 0; i < rxq->nb_rx_desc; i++) {
1978 if (rxq->sw_ring[i].mbuf != NULL) {
1979 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1980 rxq->sw_ring[i].mbuf = NULL;
1983 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1984 if (rxq->rx_nb_avail) {
1985 for (i = 0; i < rxq->rx_nb_avail; ++i) {
1986 struct rte_mbuf *mb;
1987 mb = rxq->rx_stage[rxq->rx_next_avail + i];
1988 rte_pktmbuf_free_seg(mb);
1990 rxq->rx_nb_avail = 0;
1997 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
2000 ixgbe_rx_queue_release_mbufs(rxq);
2001 rte_free(rxq->sw_ring);
2007 ixgbe_dev_rx_queue_release(void *rxq)
2009 ixgbe_rx_queue_release(rxq);
2013 * Check if Rx Burst Bulk Alloc function can be used.
2015 * 0: the preconditions are satisfied and the bulk allocation function
2017 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2018 * function must be used.
2021 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2022 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
2024 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct igb_rx_queue *rxq)
2030 * Make sure the following pre-conditions are satisfied:
2031 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2032 * rxq->rx_free_thresh < rxq->nb_rx_desc
2033 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2034 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2035 * Scattered packets are not supported. This should be checked
2036 * outside of this function.
2038 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2039 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2040 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2041 "rxq->rx_free_thresh=%d, "
2042 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2043 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2045 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2046 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2047 "rxq->rx_free_thresh=%d, "
2048 "rxq->nb_rx_desc=%d",
2049 rxq->rx_free_thresh, rxq->nb_rx_desc);
2051 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2052 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2053 "rxq->nb_rx_desc=%d, "
2054 "rxq->rx_free_thresh=%d",
2055 rxq->nb_rx_desc, rxq->rx_free_thresh);
2057 } else if (!(rxq->nb_rx_desc <
2058 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2059 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2060 "rxq->nb_rx_desc=%d, "
2061 "IXGBE_MAX_RING_DESC=%d, "
2062 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2063 rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2064 RTE_PMD_IXGBE_RX_MAX_BURST);
2074 /* Reset dynamic igb_rx_queue fields back to defaults */
2076 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
2078 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
2084 * By default, the Rx queue setup function allocates enough memory for
2085 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2086 * extra memory at the end of the descriptor ring to be zero'd out. A
2087 * pre-condition for using the Rx burst bulk alloc function is that the
2088 * number of descriptors is less than or equal to
2089 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2090 * constraints here to see if we need to zero out memory after the end
2091 * of the H/W descriptor ring.
2093 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2094 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2095 /* zero out extra memory */
2096 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2099 /* do not zero out extra memory */
2100 len = rxq->nb_rx_desc;
2103 * Zero out HW ring memory. Zero out extra memory at the end of
2104 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2105 * reads extra memory as zeros.
2107 for (i = 0; i < len; i++) {
2108 rxq->rx_ring[i] = zeroed_desc;
2111 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2113 * initialize extra software ring entries. Space for these extra
2114 * entries is always allocated
2116 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2117 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2118 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2121 rxq->rx_nb_avail = 0;
2122 rxq->rx_next_avail = 0;
2123 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2124 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2126 rxq->nb_rx_hold = 0;
2127 rxq->pkt_first_seg = NULL;
2128 rxq->pkt_last_seg = NULL;
2132 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2135 unsigned int socket_id,
2136 const struct rte_eth_rxconf *rx_conf,
2137 struct rte_mempool *mp)
2139 const struct rte_memzone *rz;
2140 struct igb_rx_queue *rxq;
2141 struct ixgbe_hw *hw;
2142 int use_def_burst_func = 1;
2145 PMD_INIT_FUNC_TRACE();
2146 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2149 * Validate number of receive descriptors.
2150 * It must not exceed hardware maximum, and must be multiple
2153 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2154 (nb_desc > IXGBE_MAX_RING_DESC) ||
2155 (nb_desc < IXGBE_MIN_RING_DESC)) {
2159 /* Free memory prior to re-allocation if needed... */
2160 if (dev->data->rx_queues[queue_idx] != NULL) {
2161 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2162 dev->data->rx_queues[queue_idx] = NULL;
2165 /* First allocate the rx queue data structure */
2166 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct igb_rx_queue),
2167 RTE_CACHE_LINE_SIZE, socket_id);
2171 rxq->nb_rx_desc = nb_desc;
2172 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2173 rxq->queue_id = queue_idx;
2174 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2175 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2176 rxq->port_id = dev->data->port_id;
2177 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2179 rxq->drop_en = rx_conf->rx_drop_en;
2180 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2183 * Allocate RX ring hardware descriptors. A memzone large enough to
2184 * handle the maximum ring size is allocated in order to allow for
2185 * resizing in later calls to the queue setup function.
2187 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2188 RX_RING_SZ, socket_id);
2190 ixgbe_rx_queue_release(rxq);
2195 * Zero init all the descriptors in the ring.
2197 memset (rz->addr, 0, RX_RING_SZ);
2200 * Modified to setup VFRDT for Virtual Function
2202 if (hw->mac.type == ixgbe_mac_82599_vf ||
2203 hw->mac.type == ixgbe_mac_X540_vf) {
2205 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2207 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2211 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2213 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2215 #ifndef RTE_LIBRTE_XEN_DOM0
2216 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2218 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2220 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2223 * Allocate software ring. Allow for space at the end of the
2224 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2225 * function does not access an invalid memory region.
2227 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2228 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2232 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2233 sizeof(struct igb_rx_entry) * len,
2234 RTE_CACHE_LINE_SIZE, socket_id);
2235 if (rxq->sw_ring == NULL) {
2236 ixgbe_rx_queue_release(rxq);
2239 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2240 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2243 * Certain constraints must be met in order to use the bulk buffer
2244 * allocation Rx burst function.
2246 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2248 #ifdef RTE_IXGBE_INC_VECTOR
2249 ixgbe_rxq_vec_setup(rxq);
2251 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2252 if (!use_def_burst_func && !dev->data->scattered_rx) {
2253 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2254 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2255 "satisfied. Rx Burst Bulk Alloc function will be "
2256 "used on port=%d, queue=%d.",
2257 rxq->port_id, rxq->queue_id);
2258 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2259 #ifdef RTE_IXGBE_INC_VECTOR
2260 if (!ixgbe_rx_vec_condition_check(dev) &&
2261 (rte_is_power_of_2(nb_desc))) {
2262 PMD_INIT_LOG(INFO, "Vector rx enabled, please make "
2263 "sure RX burst size no less than 32.");
2264 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
2269 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2270 "are not satisfied, Scattered Rx is requested, "
2271 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2272 "enabled (port=%d, queue=%d).",
2273 rxq->port_id, rxq->queue_id);
2275 dev->data->rx_queues[queue_idx] = rxq;
2277 ixgbe_reset_rx_queue(rxq);
2283 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2285 #define IXGBE_RXQ_SCAN_INTERVAL 4
2286 volatile union ixgbe_adv_rx_desc *rxdp;
2287 struct igb_rx_queue *rxq;
2290 if (rx_queue_id >= dev->data->nb_rx_queues) {
2291 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2295 rxq = dev->data->rx_queues[rx_queue_id];
2296 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2298 while ((desc < rxq->nb_rx_desc) &&
2299 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2300 desc += IXGBE_RXQ_SCAN_INTERVAL;
2301 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2302 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2303 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2304 desc - rxq->nb_rx_desc]);
2311 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2313 volatile union ixgbe_adv_rx_desc *rxdp;
2314 struct igb_rx_queue *rxq = rx_queue;
2317 if (unlikely(offset >= rxq->nb_rx_desc))
2319 desc = rxq->rx_tail + offset;
2320 if (desc >= rxq->nb_rx_desc)
2321 desc -= rxq->nb_rx_desc;
2323 rxdp = &rxq->rx_ring[desc];
2324 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2328 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2332 PMD_INIT_FUNC_TRACE();
2334 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2335 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2337 txq->ops->release_mbufs(txq);
2338 txq->ops->reset(txq);
2342 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2343 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2345 ixgbe_rx_queue_release_mbufs(rxq);
2346 ixgbe_reset_rx_queue(rxq);
2351 /*********************************************************************
2353 * Device RX/TX init functions
2355 **********************************************************************/
2358 * Receive Side Scaling (RSS)
2359 * See section 7.1.2.8 in the following document:
2360 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2363 * The source and destination IP addresses of the IP header and the source
2364 * and destination ports of TCP/UDP headers, if any, of received packets are
2365 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2366 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2367 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2368 * RSS output index which is used as the RX queue index where to store the
2370 * The following output is supplied in the RX write-back descriptor:
2371 * - 32-bit result of the Microsoft RSS hash function,
2372 * - 4-bit RSS type field.
2376 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2377 * Used as the default key.
2379 static uint8_t rss_intel_key[40] = {
2380 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2381 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2382 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2383 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2384 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2388 ixgbe_rss_disable(struct rte_eth_dev *dev)
2390 struct ixgbe_hw *hw;
2393 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2394 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2395 mrqc &= ~IXGBE_MRQC_RSSEN;
2396 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2400 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2408 hash_key = rss_conf->rss_key;
2409 if (hash_key != NULL) {
2410 /* Fill in RSS hash key */
2411 for (i = 0; i < 10; i++) {
2412 rss_key = hash_key[(i * 4)];
2413 rss_key |= hash_key[(i * 4) + 1] << 8;
2414 rss_key |= hash_key[(i * 4) + 2] << 16;
2415 rss_key |= hash_key[(i * 4) + 3] << 24;
2416 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2420 /* Set configured hashing protocols in MRQC register */
2421 rss_hf = rss_conf->rss_hf;
2422 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2423 if (rss_hf & ETH_RSS_IPV4)
2424 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2425 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2426 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2427 if (rss_hf & ETH_RSS_IPV6)
2428 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2429 if (rss_hf & ETH_RSS_IPV6_EX)
2430 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2431 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2432 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2433 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2434 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2435 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2436 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2437 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2438 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2439 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2440 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2441 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2445 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2446 struct rte_eth_rss_conf *rss_conf)
2448 struct ixgbe_hw *hw;
2452 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2455 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2456 * "RSS enabling cannot be done dynamically while it must be
2457 * preceded by a software reset"
2458 * Before changing anything, first check that the update RSS operation
2459 * does not attempt to disable RSS, if RSS was enabled at
2460 * initialization time, or does not attempt to enable RSS, if RSS was
2461 * disabled at initialization time.
2463 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2464 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2465 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2466 if (rss_hf != 0) /* Enable RSS */
2468 return 0; /* Nothing to do */
2471 if (rss_hf == 0) /* Disable RSS */
2473 ixgbe_hw_rss_hash_set(hw, rss_conf);
2478 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2479 struct rte_eth_rss_conf *rss_conf)
2481 struct ixgbe_hw *hw;
2488 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2489 hash_key = rss_conf->rss_key;
2490 if (hash_key != NULL) {
2491 /* Return RSS hash key */
2492 for (i = 0; i < 10; i++) {
2493 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2494 hash_key[(i * 4)] = rss_key & 0x000000FF;
2495 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2496 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2497 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2501 /* Get RSS functions configured in MRQC register */
2502 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2503 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2504 rss_conf->rss_hf = 0;
2508 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2509 rss_hf |= ETH_RSS_IPV4;
2510 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2511 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2512 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2513 rss_hf |= ETH_RSS_IPV6;
2514 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2515 rss_hf |= ETH_RSS_IPV6_EX;
2516 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2517 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2518 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2519 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2520 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2521 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2522 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2523 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2524 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2525 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2526 rss_conf->rss_hf = rss_hf;
2531 ixgbe_rss_configure(struct rte_eth_dev *dev)
2533 struct rte_eth_rss_conf rss_conf;
2534 struct ixgbe_hw *hw;
2539 PMD_INIT_FUNC_TRACE();
2540 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2543 * Fill in redirection table
2544 * The byte-swap is needed because NIC registers are in
2545 * little-endian order.
2548 for (i = 0, j = 0; i < 128; i++, j++) {
2549 if (j == dev->data->nb_rx_queues)
2551 reta = (reta << 8) | j;
2553 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2558 * Configure the RSS key and the RSS protocols used to compute
2559 * the RSS hash of input packets.
2561 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2562 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2563 ixgbe_rss_disable(dev);
2566 if (rss_conf.rss_key == NULL)
2567 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2568 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2571 #define NUM_VFTA_REGISTERS 128
2572 #define NIC_RX_BUFFER_SIZE 0x200
2575 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2577 struct rte_eth_vmdq_dcb_conf *cfg;
2578 struct ixgbe_hw *hw;
2579 enum rte_eth_nb_pools num_pools;
2580 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2582 uint8_t nb_tcs; /* number of traffic classes */
2585 PMD_INIT_FUNC_TRACE();
2586 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2587 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2588 num_pools = cfg->nb_queue_pools;
2589 /* Check we have a valid number of pools */
2590 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2591 ixgbe_rss_disable(dev);
2594 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2595 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2599 * split rx buffer up into sections, each for 1 traffic class
2601 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2602 for (i = 0 ; i < nb_tcs; i++) {
2603 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2604 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2605 /* clear 10 bits. */
2606 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2607 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2609 /* zero alloc all unused TCs */
2610 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2611 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2612 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2613 /* clear 10 bits. */
2614 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2617 /* MRQC: enable vmdq and dcb */
2618 mrqc = ((num_pools == ETH_16_POOLS) ? \
2619 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2620 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2622 /* PFVTCTL: turn on virtualisation and set the default pool */
2623 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2624 if (cfg->enable_default_pool) {
2625 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2627 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2630 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2632 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2634 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2636 * mapping is done with 3 bits per priority,
2637 * so shift by i*3 each time
2639 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2641 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2643 /* RTRPCS: DCB related */
2644 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2646 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2647 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2648 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2649 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2651 /* VFTA - enable all vlan filters */
2652 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2653 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2656 /* VFRE: pool enabling for receive - 16 or 32 */
2657 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2658 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2661 * MPSAR - allow pools to read specific mac addresses
2662 * In this case, all pools should be able to read from mac addr 0
2664 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2665 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2667 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2668 for (i = 0; i < cfg->nb_pool_maps; i++) {
2669 /* set vlan id in VF register and set the valid bit */
2670 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2671 (cfg->pool_map[i].vlan_id & 0xFFF)));
2673 * Put the allowed pools in VFB reg. As we only have 16 or 32
2674 * pools, we only need to use the first half of the register
2677 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2682 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2683 * @hw: pointer to hardware structure
2684 * @dcb_config: pointer to ixgbe_dcb_config structure
2687 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2688 struct ixgbe_dcb_config *dcb_config)
2693 PMD_INIT_FUNC_TRACE();
2694 if (hw->mac.type != ixgbe_mac_82598EB) {
2695 /* Disable the Tx desc arbiter so that MTQC can be changed */
2696 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2697 reg |= IXGBE_RTTDCS_ARBDIS;
2698 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2700 /* Enable DCB for Tx with 8 TCs */
2701 if (dcb_config->num_tcs.pg_tcs == 8) {
2702 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2705 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2707 if (dcb_config->vt_mode)
2708 reg |= IXGBE_MTQC_VT_ENA;
2709 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2711 /* Disable drop for all queues */
2712 for (q = 0; q < 128; q++)
2713 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2714 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2716 /* Enable the Tx desc arbiter */
2717 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2718 reg &= ~IXGBE_RTTDCS_ARBDIS;
2719 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2721 /* Enable Security TX Buffer IFG for DCB */
2722 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2723 reg |= IXGBE_SECTX_DCB;
2724 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2730 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2731 * @dev: pointer to rte_eth_dev structure
2732 * @dcb_config: pointer to ixgbe_dcb_config structure
2735 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2736 struct ixgbe_dcb_config *dcb_config)
2738 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2739 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2740 struct ixgbe_hw *hw =
2741 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2743 PMD_INIT_FUNC_TRACE();
2744 if (hw->mac.type != ixgbe_mac_82598EB)
2745 /*PF VF Transmit Enable*/
2746 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2747 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2749 /*Configure general DCB TX parameters*/
2750 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2755 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2756 struct ixgbe_dcb_config *dcb_config)
2758 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2759 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2760 struct ixgbe_dcb_tc_config *tc;
2763 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2764 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2765 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2766 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2769 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2770 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2772 /* User Priority to Traffic Class mapping */
2773 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2774 j = vmdq_rx_conf->dcb_queue[i];
2775 tc = &dcb_config->tc_config[j];
2776 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2782 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2783 struct ixgbe_dcb_config *dcb_config)
2785 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2786 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2787 struct ixgbe_dcb_tc_config *tc;
2790 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2791 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2792 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2793 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2796 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2797 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2800 /* User Priority to Traffic Class mapping */
2801 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2802 j = vmdq_tx_conf->dcb_queue[i];
2803 tc = &dcb_config->tc_config[j];
2804 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2811 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2812 struct ixgbe_dcb_config *dcb_config)
2814 struct rte_eth_dcb_rx_conf *rx_conf =
2815 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2816 struct ixgbe_dcb_tc_config *tc;
2819 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2820 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2822 /* User Priority to Traffic Class mapping */
2823 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2824 j = rx_conf->dcb_queue[i];
2825 tc = &dcb_config->tc_config[j];
2826 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2832 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2833 struct ixgbe_dcb_config *dcb_config)
2835 struct rte_eth_dcb_tx_conf *tx_conf =
2836 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2837 struct ixgbe_dcb_tc_config *tc;
2840 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2841 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2843 /* User Priority to Traffic Class mapping */
2844 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2845 j = tx_conf->dcb_queue[i];
2846 tc = &dcb_config->tc_config[j];
2847 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2853 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2854 * @hw: pointer to hardware structure
2855 * @dcb_config: pointer to ixgbe_dcb_config structure
2858 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2859 struct ixgbe_dcb_config *dcb_config)
2865 PMD_INIT_FUNC_TRACE();
2867 * Disable the arbiter before changing parameters
2868 * (always enable recycle mode; WSP)
2870 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2871 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2873 if (hw->mac.type != ixgbe_mac_82598EB) {
2874 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2875 if (dcb_config->num_tcs.pg_tcs == 4) {
2876 if (dcb_config->vt_mode)
2877 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2878 IXGBE_MRQC_VMDQRT4TCEN;
2880 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2881 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2885 if (dcb_config->num_tcs.pg_tcs == 8) {
2886 if (dcb_config->vt_mode)
2887 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2888 IXGBE_MRQC_VMDQRT8TCEN;
2890 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2891 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2896 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2899 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2900 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2901 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2902 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2904 /* VFTA - enable all vlan filters */
2905 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2906 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2910 * Configure Rx packet plane (recycle mode; WSP) and
2913 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2914 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2920 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2921 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2923 switch (hw->mac.type) {
2924 case ixgbe_mac_82598EB:
2925 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2927 case ixgbe_mac_82599EB:
2928 case ixgbe_mac_X540:
2929 case ixgbe_mac_X550:
2930 case ixgbe_mac_X550EM_x:
2931 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2940 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2941 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2943 switch (hw->mac.type) {
2944 case ixgbe_mac_82598EB:
2945 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2946 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2948 case ixgbe_mac_82599EB:
2949 case ixgbe_mac_X540:
2950 case ixgbe_mac_X550:
2951 case ixgbe_mac_X550EM_x:
2952 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2953 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2960 #define DCB_RX_CONFIG 1
2961 #define DCB_TX_CONFIG 1
2962 #define DCB_TX_PB 1024
2964 * ixgbe_dcb_hw_configure - Enable DCB and configure
2965 * general DCB in VT mode and non-VT mode parameters
2966 * @dev: pointer to rte_eth_dev structure
2967 * @dcb_config: pointer to ixgbe_dcb_config structure
2970 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2971 struct ixgbe_dcb_config *dcb_config)
2974 uint8_t i,pfc_en,nb_tcs;
2976 uint8_t config_dcb_rx = 0;
2977 uint8_t config_dcb_tx = 0;
2978 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2979 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2980 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2981 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2982 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2983 struct ixgbe_dcb_tc_config *tc;
2984 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2985 struct ixgbe_hw *hw =
2986 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2988 switch(dev->data->dev_conf.rxmode.mq_mode){
2989 case ETH_MQ_RX_VMDQ_DCB:
2990 dcb_config->vt_mode = true;
2991 if (hw->mac.type != ixgbe_mac_82598EB) {
2992 config_dcb_rx = DCB_RX_CONFIG;
2994 *get dcb and VT rx configuration parameters
2997 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2998 /*Configure general VMDQ and DCB RX parameters*/
2999 ixgbe_vmdq_dcb_configure(dev);
3003 dcb_config->vt_mode = false;
3004 config_dcb_rx = DCB_RX_CONFIG;
3005 /* Get dcb TX configuration parameters from rte_eth_conf */
3006 ixgbe_dcb_rx_config(dev,dcb_config);
3007 /*Configure general DCB RX parameters*/
3008 ixgbe_dcb_rx_hw_config(hw, dcb_config);
3011 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3014 switch (dev->data->dev_conf.txmode.mq_mode) {
3015 case ETH_MQ_TX_VMDQ_DCB:
3016 dcb_config->vt_mode = true;
3017 config_dcb_tx = DCB_TX_CONFIG;
3018 /* get DCB and VT TX configuration parameters from rte_eth_conf */
3019 ixgbe_dcb_vt_tx_config(dev,dcb_config);
3020 /*Configure general VMDQ and DCB TX parameters*/
3021 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
3025 dcb_config->vt_mode = false;
3026 config_dcb_tx = DCB_TX_CONFIG;
3027 /*get DCB TX configuration parameters from rte_eth_conf*/
3028 ixgbe_dcb_tx_config(dev,dcb_config);
3029 /*Configure general DCB TX parameters*/
3030 ixgbe_dcb_tx_hw_config(hw, dcb_config);
3033 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3037 nb_tcs = dcb_config->num_tcs.pfc_tcs;
3039 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3040 if(nb_tcs == ETH_4_TCS) {
3041 /* Avoid un-configured priority mapping to TC0 */
3043 uint8_t mask = 0xFF;
3044 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3045 mask = (uint8_t)(mask & (~ (1 << map[i])));
3046 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3047 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3051 /* Re-configure 4 TCs BW */
3052 for (i = 0; i < nb_tcs; i++) {
3053 tc = &dcb_config->tc_config[i];
3054 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3055 (uint8_t)(100 / nb_tcs);
3056 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3057 (uint8_t)(100 / nb_tcs);
3059 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3060 tc = &dcb_config->tc_config[i];
3061 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3062 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3067 /* Set RX buffer size */
3068 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3069 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3070 for (i = 0 ; i < nb_tcs; i++) {
3071 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3073 /* zero alloc all unused TCs */
3074 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3075 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3079 /* Only support an equally distributed Tx packet buffer strategy. */
3080 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3081 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3082 for (i = 0; i < nb_tcs; i++) {
3083 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3084 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3086 /* Clear unused TCs, if any, to zero buffer size*/
3087 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3088 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3089 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3093 /*Calculates traffic class credits*/
3094 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3095 IXGBE_DCB_TX_CONFIG);
3096 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3097 IXGBE_DCB_RX_CONFIG);
3100 /* Unpack CEE standard containers */
3101 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3102 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3103 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3104 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3105 /* Configure PG(ETS) RX */
3106 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3110 /* Unpack CEE standard containers */
3111 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3112 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3113 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3114 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3115 /* Configure PG(ETS) TX */
3116 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3119 /*Configure queue statistics registers*/
3120 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3122 /* Check if the PFC is supported */
3123 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3124 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3125 for (i = 0; i < nb_tcs; i++) {
3127 * If the TC count is 8,and the default high_water is 48,
3128 * the low_water is 16 as default.
3130 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3131 hw->fc.low_water[i] = pbsize / 4;
3132 /* Enable pfc for this TC */
3133 tc = &dcb_config->tc_config[i];
3134 tc->pfc = ixgbe_dcb_pfc_enabled;
3136 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3137 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3139 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3146 * ixgbe_configure_dcb - Configure DCB Hardware
3147 * @dev: pointer to rte_eth_dev
3149 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3151 struct ixgbe_dcb_config *dcb_cfg =
3152 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3153 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3155 PMD_INIT_FUNC_TRACE();
3157 /* check support mq_mode for DCB */
3158 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3159 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3162 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3165 /** Configure DCB hardware **/
3166 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3172 * VMDq only support for 10 GbE NIC.
3175 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3177 struct rte_eth_vmdq_rx_conf *cfg;
3178 struct ixgbe_hw *hw;
3179 enum rte_eth_nb_pools num_pools;
3180 uint32_t mrqc, vt_ctl, vlanctrl;
3184 PMD_INIT_FUNC_TRACE();
3185 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3186 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3187 num_pools = cfg->nb_queue_pools;
3189 ixgbe_rss_disable(dev);
3191 /* MRQC: enable vmdq */
3192 mrqc = IXGBE_MRQC_VMDQEN;
3193 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3195 /* PFVTCTL: turn on virtualisation and set the default pool */
3196 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3197 if (cfg->enable_default_pool)
3198 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3200 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3202 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3204 for (i = 0; i < (int)num_pools; i++) {
3205 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
3206 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
3209 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3210 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3211 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3212 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3214 /* VFTA - enable all vlan filters */
3215 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3216 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3218 /* VFRE: pool enabling for receive - 64 */
3219 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3220 if (num_pools == ETH_64_POOLS)
3221 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3224 * MPSAR - allow pools to read specific mac addresses
3225 * In this case, all pools should be able to read from mac addr 0
3227 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3228 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3230 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3231 for (i = 0; i < cfg->nb_pool_maps; i++) {
3232 /* set vlan id in VF register and set the valid bit */
3233 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3234 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3236 * Put the allowed pools in VFB reg. As we only have 16 or 64
3237 * pools, we only need to use the first half of the register
3240 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3241 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3242 (cfg->pool_map[i].pools & UINT32_MAX));
3244 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3245 ((cfg->pool_map[i].pools >> 32) \
3250 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3251 if (cfg->enable_loop_back) {
3252 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3253 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3254 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3257 IXGBE_WRITE_FLUSH(hw);
3261 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3262 * @hw: pointer to hardware structure
3265 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3270 PMD_INIT_FUNC_TRACE();
3271 /*PF VF Transmit Enable*/
3272 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3273 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3275 /* Disable the Tx desc arbiter so that MTQC can be changed */
3276 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3277 reg |= IXGBE_RTTDCS_ARBDIS;
3278 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3280 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3281 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3283 /* Disable drop for all queues */
3284 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3285 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3286 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3288 /* Enable the Tx desc arbiter */
3289 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3290 reg &= ~IXGBE_RTTDCS_ARBDIS;
3291 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3293 IXGBE_WRITE_FLUSH(hw);
3299 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
3301 struct igb_rx_entry *rxe = rxq->sw_ring;
3305 /* Initialize software ring entries */
3306 for (i = 0; i < rxq->nb_rx_desc; i++) {
3307 volatile union ixgbe_adv_rx_desc *rxd;
3308 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3310 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3311 (unsigned) rxq->queue_id);
3315 rte_mbuf_refcnt_set(mbuf, 1);
3317 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3319 mbuf->port = rxq->port_id;
3322 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3323 rxd = &rxq->rx_ring[i];
3324 rxd->read.hdr_addr = dma_addr;
3325 rxd->read.pkt_addr = dma_addr;
3333 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
3335 struct ixgbe_hw *hw;
3338 ixgbe_rss_configure(dev);
3340 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3342 /* MRQC: enable VF RSS */
3343 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
3344 mrqc &= ~IXGBE_MRQC_MRQE_MASK;
3345 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3347 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
3351 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
3355 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
3359 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3365 ixgbe_config_vf_default(struct rte_eth_dev *dev)
3367 struct ixgbe_hw *hw =
3368 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3370 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3372 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3377 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3378 IXGBE_MRQC_VMDQRT4TCEN);
3382 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3383 IXGBE_MRQC_VMDQRT8TCEN);
3387 "invalid pool number in IOV mode");
3394 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3396 struct ixgbe_hw *hw =
3397 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3399 if (hw->mac.type == ixgbe_mac_82598EB)
3402 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3404 * SRIOV inactive scheme
3405 * any DCB/RSS w/o VMDq multi-queue setting
3407 switch (dev->data->dev_conf.rxmode.mq_mode) {
3409 ixgbe_rss_configure(dev);
3412 case ETH_MQ_RX_VMDQ_DCB:
3413 ixgbe_vmdq_dcb_configure(dev);
3416 case ETH_MQ_RX_VMDQ_ONLY:
3417 ixgbe_vmdq_rx_hw_configure(dev);
3420 case ETH_MQ_RX_NONE:
3421 /* if mq_mode is none, disable rss mode.*/
3422 default: ixgbe_rss_disable(dev);
3426 * SRIOV active scheme
3427 * Support RSS together with VMDq & SRIOV
3429 switch (dev->data->dev_conf.rxmode.mq_mode) {
3431 case ETH_MQ_RX_VMDQ_RSS:
3432 ixgbe_config_vf_rss(dev);
3435 /* FIXME if support DCB/RSS together with VMDq & SRIOV */
3436 case ETH_MQ_RX_VMDQ_DCB:
3437 case ETH_MQ_RX_VMDQ_DCB_RSS:
3439 "Could not support DCB with VMDq & SRIOV");
3442 ixgbe_config_vf_default(dev);
3451 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3453 struct ixgbe_hw *hw =
3454 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3458 if (hw->mac.type == ixgbe_mac_82598EB)
3461 /* disable arbiter before setting MTQC */
3462 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3463 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3464 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3466 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3468 * SRIOV inactive scheme
3469 * any DCB w/o VMDq multi-queue setting
3471 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3472 ixgbe_vmdq_tx_hw_configure(hw);
3474 mtqc = IXGBE_MTQC_64Q_1PB;
3475 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3478 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3481 * SRIOV active scheme
3482 * FIXME if support DCB together with VMDq & SRIOV
3485 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3488 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3491 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3495 mtqc = IXGBE_MTQC_64Q_1PB;
3496 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3498 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3501 /* re-enable arbiter */
3502 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3503 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3509 * Initializes Receive Unit.
3512 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3514 struct ixgbe_hw *hw;
3515 struct igb_rx_queue *rxq;
3516 struct rte_pktmbuf_pool_private *mbp_priv;
3528 PMD_INIT_FUNC_TRACE();
3529 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3532 * Make sure receives are disabled while setting
3533 * up the RX context (registers, descriptor rings, etc.).
3535 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3536 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3538 /* Enable receipt of broadcasted frames */
3539 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3540 fctrl |= IXGBE_FCTRL_BAM;
3541 fctrl |= IXGBE_FCTRL_DPF;
3542 fctrl |= IXGBE_FCTRL_PMCF;
3543 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3546 * Configure CRC stripping, if any.
3548 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3549 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3550 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3552 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3555 * Configure jumbo frame support, if any.
3557 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3558 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3559 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3560 maxfrs &= 0x0000FFFF;
3561 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3562 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3564 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3567 * If loopback mode is configured for 82599, set LPBK bit.
3569 if (hw->mac.type == ixgbe_mac_82599EB &&
3570 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3571 hlreg0 |= IXGBE_HLREG0_LPBK;
3573 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3575 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3577 /* Setup RX queues */
3578 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3579 rxq = dev->data->rx_queues[i];
3582 * Reset crc_len in case it was changed after queue setup by a
3583 * call to configure.
3585 rxq->crc_len = (uint8_t)
3586 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3589 /* Setup the Base and Length of the Rx Descriptor Rings */
3590 bus_addr = rxq->rx_ring_phys_addr;
3591 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3592 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3593 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3594 (uint32_t)(bus_addr >> 32));
3595 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3596 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3597 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3598 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3600 /* Configure the SRRCTL register */
3601 #ifdef RTE_HEADER_SPLIT_ENABLE
3603 * Configure Header Split
3605 if (dev->data->dev_conf.rxmode.header_split) {
3606 if (hw->mac.type == ixgbe_mac_82599EB) {
3607 /* Must setup the PSRTYPE register */
3609 psrtype = IXGBE_PSRTYPE_TCPHDR |
3610 IXGBE_PSRTYPE_UDPHDR |
3611 IXGBE_PSRTYPE_IPV4HDR |
3612 IXGBE_PSRTYPE_IPV6HDR;
3613 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3615 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3616 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3617 IXGBE_SRRCTL_BSIZEHDR_MASK);
3618 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3621 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3623 /* Set if packets are dropped when no descriptors available */
3625 srrctl |= IXGBE_SRRCTL_DROP_EN;
3628 * Configure the RX buffer size in the BSIZEPACKET field of
3629 * the SRRCTL register of the queue.
3630 * The value is in 1 KB resolution. Valid values can be from
3633 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3634 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3635 RTE_PKTMBUF_HEADROOM);
3636 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3637 IXGBE_SRRCTL_BSIZEPKT_MASK);
3638 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3640 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3641 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3643 if (dev->data->dev_conf.rxmode.enable_scatter ||
3644 /* It adds dual VLAN length for supporting dual VLAN */
3645 (dev->data->dev_conf.rxmode.max_rx_pkt_len +
3646 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3647 if (!dev->data->scattered_rx)
3648 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
3649 dev->data->scattered_rx = 1;
3650 #ifdef RTE_IXGBE_INC_VECTOR
3651 if (rte_is_power_of_2(rxq->nb_rx_desc))
3653 ixgbe_recv_scattered_pkts_vec;
3656 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3661 * Device configured with multiple RX queues.
3663 ixgbe_dev_mq_rx_configure(dev);
3666 * Setup the Checksum Register.
3667 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3668 * Enable IP/L4 checkum computation by hardware if requested to do so.
3670 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3671 rxcsum |= IXGBE_RXCSUM_PCSD;
3672 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3673 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3675 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3677 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3679 if (hw->mac.type == ixgbe_mac_82599EB) {
3680 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3681 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3682 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3684 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3685 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3686 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3693 * Initializes Transmit Unit.
3696 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3698 struct ixgbe_hw *hw;
3699 struct igb_tx_queue *txq;
3705 PMD_INIT_FUNC_TRACE();
3706 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3708 /* Enable TX CRC (checksum offload requirement) and hw padding
3709 * (TSO requirement) */
3710 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3711 hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
3712 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3714 /* Setup the Base and Length of the Tx Descriptor Rings */
3715 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3716 txq = dev->data->tx_queues[i];
3718 bus_addr = txq->tx_ring_phys_addr;
3719 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3720 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3721 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3722 (uint32_t)(bus_addr >> 32));
3723 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3724 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3725 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3726 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3727 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3730 * Disable Tx Head Writeback RO bit, since this hoses
3731 * bookkeeping if things aren't delivered in order.
3733 switch (hw->mac.type) {
3734 case ixgbe_mac_82598EB:
3735 txctrl = IXGBE_READ_REG(hw,
3736 IXGBE_DCA_TXCTRL(txq->reg_idx));
3737 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3738 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3742 case ixgbe_mac_82599EB:
3743 case ixgbe_mac_X540:
3744 case ixgbe_mac_X550:
3745 case ixgbe_mac_X550EM_x:
3747 txctrl = IXGBE_READ_REG(hw,
3748 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3749 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3750 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3756 /* Device configured with multiple TX queues. */
3757 ixgbe_dev_mq_tx_configure(dev);
3761 * Set up link for 82599 loopback mode Tx->Rx.
3764 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3766 PMD_INIT_FUNC_TRACE();
3768 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3769 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3771 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
3780 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3781 ixgbe_reset_pipeline_82599(hw);
3783 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3789 * Start Transmit and Receive Units.
3792 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3794 struct ixgbe_hw *hw;
3795 struct igb_tx_queue *txq;
3796 struct igb_rx_queue *rxq;
3803 PMD_INIT_FUNC_TRACE();
3804 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3806 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3807 txq = dev->data->tx_queues[i];
3808 /* Setup Transmit Threshold Registers */
3809 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3810 txdctl |= txq->pthresh & 0x7F;
3811 txdctl |= ((txq->hthresh & 0x7F) << 8);
3812 txdctl |= ((txq->wthresh & 0x7F) << 16);
3813 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3816 if (hw->mac.type != ixgbe_mac_82598EB) {
3817 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3818 dmatxctl |= IXGBE_DMATXCTL_TE;
3819 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3822 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3823 txq = dev->data->tx_queues[i];
3824 if (!txq->tx_deferred_start) {
3825 ret = ixgbe_dev_tx_queue_start(dev, i);
3831 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3832 rxq = dev->data->rx_queues[i];
3833 if (!rxq->rx_deferred_start) {
3834 ret = ixgbe_dev_rx_queue_start(dev, i);
3840 /* Enable Receive engine */
3841 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3842 if (hw->mac.type == ixgbe_mac_82598EB)
3843 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3844 rxctrl |= IXGBE_RXCTRL_RXEN;
3845 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3847 /* If loopback mode is enabled for 82599, set up the link accordingly */
3848 if (hw->mac.type == ixgbe_mac_82599EB &&
3849 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3850 ixgbe_setup_loopback_link_82599(hw);
3856 * Start Receive Units for specified queue.
3859 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3861 struct ixgbe_hw *hw;
3862 struct igb_rx_queue *rxq;
3866 PMD_INIT_FUNC_TRACE();
3867 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3869 if (rx_queue_id < dev->data->nb_rx_queues) {
3870 rxq = dev->data->rx_queues[rx_queue_id];
3872 /* Allocate buffers for descriptor rings */
3873 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
3874 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
3878 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3879 rxdctl |= IXGBE_RXDCTL_ENABLE;
3880 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3882 /* Wait until RX Enable ready */
3883 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3886 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3887 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3889 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
3892 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3893 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3901 * Stop Receive Units for specified queue.
3904 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3906 struct ixgbe_hw *hw;
3907 struct igb_rx_queue *rxq;
3911 PMD_INIT_FUNC_TRACE();
3912 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3914 if (rx_queue_id < dev->data->nb_rx_queues) {
3915 rxq = dev->data->rx_queues[rx_queue_id];
3917 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3918 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3919 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3921 /* Wait until RX Enable ready */
3922 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3925 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3926 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
3928 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
3931 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3933 ixgbe_rx_queue_release_mbufs(rxq);
3934 ixgbe_reset_rx_queue(rxq);
3943 * Start Transmit Units for specified queue.
3946 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3948 struct ixgbe_hw *hw;
3949 struct igb_tx_queue *txq;
3953 PMD_INIT_FUNC_TRACE();
3954 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3956 if (tx_queue_id < dev->data->nb_tx_queues) {
3957 txq = dev->data->tx_queues[tx_queue_id];
3958 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3959 txdctl |= IXGBE_TXDCTL_ENABLE;
3960 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3962 /* Wait until TX Enable ready */
3963 if (hw->mac.type == ixgbe_mac_82599EB) {
3964 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3967 txdctl = IXGBE_READ_REG(hw,
3968 IXGBE_TXDCTL(txq->reg_idx));
3969 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3971 PMD_INIT_LOG(ERR, "Could not enable "
3972 "Tx Queue %d", tx_queue_id);
3975 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3976 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3984 * Stop Transmit Units for specified queue.
3987 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3989 struct ixgbe_hw *hw;
3990 struct igb_tx_queue *txq;
3992 uint32_t txtdh, txtdt;
3995 PMD_INIT_FUNC_TRACE();
3996 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3998 if (tx_queue_id < dev->data->nb_tx_queues) {
3999 txq = dev->data->tx_queues[tx_queue_id];
4001 /* Wait until TX queue is empty */
4002 if (hw->mac.type == ixgbe_mac_82599EB) {
4003 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4005 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4006 txtdh = IXGBE_READ_REG(hw,
4007 IXGBE_TDH(txq->reg_idx));
4008 txtdt = IXGBE_READ_REG(hw,
4009 IXGBE_TDT(txq->reg_idx));
4010 } while (--poll_ms && (txtdh != txtdt));
4012 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
4013 "when stopping.", tx_queue_id);
4016 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4017 txdctl &= ~IXGBE_TXDCTL_ENABLE;
4018 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4020 /* Wait until TX Enable ready */
4021 if (hw->mac.type == ixgbe_mac_82599EB) {
4022 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4025 txdctl = IXGBE_READ_REG(hw,
4026 IXGBE_TXDCTL(txq->reg_idx));
4027 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
4029 PMD_INIT_LOG(ERR, "Could not disable "
4030 "Tx Queue %d", tx_queue_id);
4033 if (txq->ops != NULL) {
4034 txq->ops->release_mbufs(txq);
4035 txq->ops->reset(txq);
4044 * [VF] Initializes Receive Unit.
4047 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
4049 struct ixgbe_hw *hw;
4050 struct igb_rx_queue *rxq;
4051 struct rte_pktmbuf_pool_private *mbp_priv;
4053 uint32_t srrctl, psrtype = 0;
4058 PMD_INIT_FUNC_TRACE();
4059 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4061 if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
4062 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4063 "it should be power of 2");
4067 if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
4068 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4069 "it should be equal to or less than %d",
4070 hw->mac.max_rx_queues);
4075 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
4076 * disables the VF receipt of packets if the PF MTU is > 1500.
4077 * This is done to deal with 82599 limitations that imposes
4078 * the PF and all VFs to share the same MTU.
4079 * Then, the PF driver enables again the VF receipt of packet when
4080 * the VF driver issues a IXGBE_VF_SET_LPE request.
4081 * In the meantime, the VF device cannot be used, even if the VF driver
4082 * and the Guest VM network stack are ready to accept packets with a
4083 * size up to the PF MTU.
4084 * As a work-around to this PF behaviour, force the call to
4085 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
4086 * VF packets received can work in all cases.
4088 ixgbevf_rlpml_set_vf(hw,
4089 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
4091 /* Setup RX queues */
4092 dev->rx_pkt_burst = ixgbe_recv_pkts;
4093 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4094 rxq = dev->data->rx_queues[i];
4096 /* Allocate buffers for descriptor rings */
4097 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
4101 /* Setup the Base and Length of the Rx Descriptor Rings */
4102 bus_addr = rxq->rx_ring_phys_addr;
4104 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
4105 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4106 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
4107 (uint32_t)(bus_addr >> 32));
4108 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
4109 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4110 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
4111 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
4114 /* Configure the SRRCTL register */
4115 #ifdef RTE_HEADER_SPLIT_ENABLE
4117 * Configure Header Split
4119 if (dev->data->dev_conf.rxmode.header_split) {
4120 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
4121 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4122 IXGBE_SRRCTL_BSIZEHDR_MASK);
4123 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4126 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4128 /* Set if packets are dropped when no descriptors available */
4130 srrctl |= IXGBE_SRRCTL_DROP_EN;
4133 * Configure the RX buffer size in the BSIZEPACKET field of
4134 * the SRRCTL register of the queue.
4135 * The value is in 1 KB resolution. Valid values can be from
4138 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
4139 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
4140 RTE_PKTMBUF_HEADROOM);
4141 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4142 IXGBE_SRRCTL_BSIZEPKT_MASK);
4145 * VF modification to write virtual function SRRCTL register
4147 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
4149 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4150 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4152 if (dev->data->dev_conf.rxmode.enable_scatter ||
4153 /* It adds dual VLAN length for supporting dual VLAN */
4154 (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4155 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
4156 if (!dev->data->scattered_rx)
4157 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4158 dev->data->scattered_rx = 1;
4159 #ifdef RTE_IXGBE_INC_VECTOR
4160 if (rte_is_power_of_2(rxq->nb_rx_desc))
4162 ixgbe_recv_scattered_pkts_vec;
4165 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
4169 #ifdef RTE_HEADER_SPLIT_ENABLE
4170 if (dev->data->dev_conf.rxmode.header_split)
4171 /* Must setup the PSRTYPE register */
4172 psrtype = IXGBE_PSRTYPE_TCPHDR |
4173 IXGBE_PSRTYPE_UDPHDR |
4174 IXGBE_PSRTYPE_IPV4HDR |
4175 IXGBE_PSRTYPE_IPV6HDR;
4178 /* Set RQPL for VF RSS according to max Rx queue */
4179 psrtype |= (dev->data->nb_rx_queues >> 1) <<
4180 IXGBE_PSRTYPE_RQPL_SHIFT;
4181 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
4187 * [VF] Initializes Transmit Unit.
4190 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4192 struct ixgbe_hw *hw;
4193 struct igb_tx_queue *txq;
4198 PMD_INIT_FUNC_TRACE();
4199 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4201 /* Setup the Base and Length of the Tx Descriptor Rings */
4202 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4203 txq = dev->data->tx_queues[i];
4204 bus_addr = txq->tx_ring_phys_addr;
4205 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4206 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4207 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4208 (uint32_t)(bus_addr >> 32));
4209 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4210 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4211 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4212 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4213 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4216 * Disable Tx Head Writeback RO bit, since this hoses
4217 * bookkeeping if things aren't delivered in order.
4219 txctrl = IXGBE_READ_REG(hw,
4220 IXGBE_VFDCA_TXCTRL(i));
4221 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4222 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4228 * [VF] Start Transmit and Receive Units.
4231 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4233 struct ixgbe_hw *hw;
4234 struct igb_tx_queue *txq;
4235 struct igb_rx_queue *rxq;
4241 PMD_INIT_FUNC_TRACE();
4242 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4244 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4245 txq = dev->data->tx_queues[i];
4246 /* Setup Transmit Threshold Registers */
4247 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4248 txdctl |= txq->pthresh & 0x7F;
4249 txdctl |= ((txq->hthresh & 0x7F) << 8);
4250 txdctl |= ((txq->wthresh & 0x7F) << 16);
4251 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4254 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4256 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4257 txdctl |= IXGBE_TXDCTL_ENABLE;
4258 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4261 /* Wait until TX Enable ready */
4264 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4265 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4267 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
4269 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4271 rxq = dev->data->rx_queues[i];
4273 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4274 rxdctl |= IXGBE_RXDCTL_ENABLE;
4275 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4277 /* Wait until RX Enable ready */
4281 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4282 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4284 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
4286 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);