4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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34 #include <sys/queue.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
47 #include <rte_cycles.h>
49 #include <rte_debug.h>
50 #include <rte_interrupts.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_launch.h>
55 #include <rte_tailq.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
82 #include "ixgbe_rxtx.h"
85 static inline struct rte_mbuf *
86 rte_rxmbuf_alloc(struct rte_mempool *mp)
90 m = __rte_mbuf_raw_alloc(mp);
91 __rte_mbuf_sanity_check_raw(m, RTE_MBUF_PKT, 0);
97 #define RTE_PMD_USE_PREFETCH
100 #ifdef RTE_PMD_USE_PREFETCH
102 * Prefetch a cache line into all cache levels.
104 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
106 #define rte_ixgbe_prefetch(p) do {} while(0)
109 /*********************************************************************
113 **********************************************************************/
116 * Check for descriptors with their DD bit set and free mbufs.
117 * Return the total number of buffers freed.
119 static inline int __attribute__((always_inline))
120 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
122 struct igb_tx_entry *txep;
126 /* check DD bit on threshold descriptor */
127 status = txq->tx_ring[txq->tx_next_dd].wb.status;
128 if (! (status & IXGBE_ADVTXD_STAT_DD))
132 * first buffer to free from S/W ring is at index
133 * tx_next_dd - (tx_rs_thresh-1)
135 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
137 /* prefetch the mbufs that are about to be freed */
138 for (i = 0; i < txq->tx_rs_thresh; ++i)
139 rte_prefetch0((txep + i)->mbuf);
141 /* free buffers one at a time */
142 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
143 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
144 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
148 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
149 rte_pktmbuf_free_seg(txep->mbuf);
154 /* buffers were freed, update counters */
155 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
156 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
157 if (txq->tx_next_dd >= txq->nb_tx_desc)
158 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
160 return txq->tx_rs_thresh;
163 /* Populate 4 descriptors with data from 4 mbufs */
165 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
167 uint64_t buf_dma_addr;
171 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
172 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
173 pkt_len = (*pkts)->pkt.data_len;
175 /* write data to descriptor */
176 txdp->read.buffer_addr = buf_dma_addr;
177 txdp->read.cmd_type_len =
178 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
179 txdp->read.olinfo_status =
180 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
184 /* Populate 1 descriptor with data from 1 mbuf */
186 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
188 uint64_t buf_dma_addr;
191 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
192 pkt_len = (*pkts)->pkt.data_len;
194 /* write data to descriptor */
195 txdp->read.buffer_addr = buf_dma_addr;
196 txdp->read.cmd_type_len =
197 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
198 txdp->read.olinfo_status =
199 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
203 * Fill H/W descriptor ring with mbuf data.
204 * Copy mbuf pointers to the S/W ring.
207 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
210 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
211 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
212 const int N_PER_LOOP = 4;
213 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
214 int mainpart, leftover;
218 * Process most of the packets in chunks of N pkts. Any
219 * leftover packets will get processed one at a time.
221 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
222 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
223 for (i = 0; i < mainpart; i += N_PER_LOOP) {
224 /* Copy N mbuf pointers to the S/W ring */
225 for (j = 0; j < N_PER_LOOP; ++j) {
226 (txep + i + j)->mbuf = *(pkts + i + j);
228 tx4(txdp + i, pkts + i);
231 if (unlikely(leftover > 0)) {
232 for (i = 0; i < leftover; ++i) {
233 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
234 tx1(txdp + mainpart + i, pkts + mainpart + i);
239 static inline uint16_t
240 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
243 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
244 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
248 * Begin scanning the H/W ring for done descriptors when the
249 * number of available descriptors drops below tx_free_thresh. For
250 * each done descriptor, free the associated buffer.
252 if (txq->nb_tx_free < txq->tx_free_thresh)
253 ixgbe_tx_free_bufs(txq);
255 /* Only use descriptors that are available */
256 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
257 if (unlikely(nb_pkts == 0))
260 /* Use exactly nb_pkts descriptors */
261 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
264 * At this point, we know there are enough descriptors in the
265 * ring to transmit all the packets. This assumes that each
266 * mbuf contains a single segment, and that no new offloads
267 * are expected, which would require a new context descriptor.
271 * See if we're going to wrap-around. If so, handle the top
272 * of the descriptor ring first, then do the bottom. If not,
273 * the processing looks just like the "bottom" part anyway...
275 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
276 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
277 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
280 * We know that the last descriptor in the ring will need to
281 * have its RS bit set because tx_rs_thresh has to be
282 * a divisor of the ring size
284 tx_r[txq->tx_next_rs].read.cmd_type_len |=
285 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
286 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
291 /* Fill H/W descriptor ring with mbuf data */
292 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
293 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
296 * Determine if RS bit should be set
297 * This is what we actually want:
298 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
299 * but instead of subtracting 1 and doing >=, we can just do
300 * greater than without subtracting.
302 if (txq->tx_tail > txq->tx_next_rs) {
303 tx_r[txq->tx_next_rs].read.cmd_type_len |=
304 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
305 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
307 if (txq->tx_next_rs >= txq->nb_tx_desc)
308 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
312 * Check for wrap-around. This would only happen if we used
313 * up to the last descriptor in the ring, no more, no less.
315 if (txq->tx_tail >= txq->nb_tx_desc)
318 /* update tail pointer */
320 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
326 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
331 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
332 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
333 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
335 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
339 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
340 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
341 nb_tx = (uint16_t)(nb_tx + ret);
342 nb_pkts = (uint16_t)(nb_pkts - ret);
351 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
352 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
353 uint16_t ol_flags, uint32_t vlan_macip_lens)
355 uint32_t type_tucmd_mlhl;
356 uint32_t mss_l4len_idx;
360 ctx_idx = txq->ctx_curr;
364 if (ol_flags & PKT_TX_VLAN_PKT) {
365 cmp_mask |= TX_VLAN_CMP_MASK;
368 if (ol_flags & PKT_TX_IP_CKSUM) {
369 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
370 cmp_mask |= TX_MAC_LEN_CMP_MASK;
373 /* Specify which HW CTX to upload. */
374 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
375 switch (ol_flags & PKT_TX_L4_MASK) {
376 case PKT_TX_UDP_CKSUM:
377 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
378 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
379 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
380 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
382 case PKT_TX_TCP_CKSUM:
383 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
384 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
385 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
386 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
388 case PKT_TX_SCTP_CKSUM:
389 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
390 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
391 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
392 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
395 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
396 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
400 txq->ctx_cache[ctx_idx].flags = ol_flags;
401 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
402 txq->ctx_cache[ctx_idx].vlan_macip_lens.data =
403 vlan_macip_lens & cmp_mask;
405 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
406 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
407 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
408 ctx_txd->seqnum_seed = 0;
412 * Check which hardware context can be used. Use the existing match
413 * or create a new context descriptor.
415 static inline uint32_t
416 what_advctx_update(struct igb_tx_queue *txq, uint16_t flags,
417 uint32_t vlan_macip_lens)
419 /* If match with the current used context */
420 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
421 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
422 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
423 return txq->ctx_curr;
426 /* What if match with the next context */
428 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
429 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
430 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
431 return txq->ctx_curr;
434 /* Mismatch, use the previous context */
435 return (IXGBE_CTX_NUM);
438 static inline uint32_t
439 tx_desc_cksum_flags_to_olinfo(uint16_t ol_flags)
441 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
442 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
445 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
446 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
450 static inline uint32_t
451 tx_desc_vlan_flags_to_cmdtype(uint16_t ol_flags)
453 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
454 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
457 /* Default RS bit threshold values */
458 #ifndef DEFAULT_TX_RS_THRESH
459 #define DEFAULT_TX_RS_THRESH 32
461 #ifndef DEFAULT_TX_FREE_THRESH
462 #define DEFAULT_TX_FREE_THRESH 32
465 /* Reset transmit descriptors after they have been used */
467 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
469 struct igb_tx_entry *sw_ring = txq->sw_ring;
470 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
471 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
472 uint16_t nb_tx_desc = txq->nb_tx_desc;
473 uint16_t desc_to_clean_to;
474 uint16_t nb_tx_to_clean;
476 /* Determine the last descriptor needing to be cleaned */
477 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
478 if (desc_to_clean_to >= nb_tx_desc)
479 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
481 /* Check to make sure the last descriptor to clean is done */
482 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
483 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
485 PMD_TX_FREE_LOG(DEBUG,
486 "TX descriptor %4u is not done"
487 "(port=%d queue=%d)",
489 txq->port_id, txq->queue_id);
490 /* Failed to clean any descriptors, better luck next time */
494 /* Figure out how many descriptors will be cleaned */
495 if (last_desc_cleaned > desc_to_clean_to)
496 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
499 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
502 PMD_TX_FREE_LOG(DEBUG,
503 "Cleaning %4u TX descriptors: %4u to %4u "
504 "(port=%d queue=%d)",
505 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
506 txq->port_id, txq->queue_id);
509 * The last descriptor to clean is done, so that means all the
510 * descriptors from the last descriptor that was cleaned
511 * up to the last descriptor with the RS bit set
512 * are done. Only reset the threshold descriptor.
514 txr[desc_to_clean_to].wb.status = 0;
516 /* Update the txq to reflect the last descriptor that was cleaned */
517 txq->last_desc_cleaned = desc_to_clean_to;
518 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
525 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
528 struct igb_tx_queue *txq;
529 struct igb_tx_entry *sw_ring;
530 struct igb_tx_entry *txe, *txn;
531 volatile union ixgbe_adv_tx_desc *txr;
532 volatile union ixgbe_adv_tx_desc *txd;
533 struct rte_mbuf *tx_pkt;
534 struct rte_mbuf *m_seg;
535 uint64_t buf_dma_addr;
536 uint32_t olinfo_status;
537 uint32_t cmd_type_len;
546 uint32_t vlan_macip_lens;
551 sw_ring = txq->sw_ring;
553 tx_id = txq->tx_tail;
554 txe = &sw_ring[tx_id];
556 /* Determine if the descriptor ring needs to be cleaned. */
557 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
558 ixgbe_xmit_cleanup(txq);
562 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
565 pkt_len = tx_pkt->pkt.pkt_len;
567 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
570 * Determine how many (if any) context descriptors
571 * are needed for offload functionality.
573 ol_flags = tx_pkt->ol_flags;
574 vlan_macip_lens = tx_pkt->pkt.vlan_macip.data;
576 /* If hardware offload required */
577 tx_ol_req = (uint16_t)(ol_flags & PKT_TX_OFFLOAD_MASK);
579 /* If new context need be built or reuse the exist ctx. */
580 ctx = what_advctx_update(txq, tx_ol_req,
582 /* Only allocate context descriptor if required*/
583 new_ctx = (ctx == IXGBE_CTX_NUM);
588 * Keep track of how many descriptors are used this loop
589 * This will always be the number of segments + the number of
590 * Context descriptors required to transmit the packet
592 nb_used = (uint16_t)(tx_pkt->pkt.nb_segs + new_ctx);
595 * The number of descriptors that must be allocated for a
596 * packet is the number of segments of that packet, plus 1
597 * Context Descriptor for the hardware offload, if any.
598 * Determine the last TX descriptor to allocate in the TX ring
599 * for the packet, starting from the current position (tx_id)
602 tx_last = (uint16_t) (tx_id + nb_used - 1);
605 if (tx_last >= txq->nb_tx_desc)
606 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
608 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
609 " tx_first=%u tx_last=%u\n",
610 (unsigned) txq->port_id,
611 (unsigned) txq->queue_id,
617 * Make sure there are enough TX descriptors available to
618 * transmit the entire packet.
619 * nb_used better be less than or equal to txq->tx_rs_thresh
621 if (nb_used > txq->nb_tx_free) {
622 PMD_TX_FREE_LOG(DEBUG,
623 "Not enough free TX descriptors "
624 "nb_used=%4u nb_free=%4u "
625 "(port=%d queue=%d)",
626 nb_used, txq->nb_tx_free,
627 txq->port_id, txq->queue_id);
629 if (ixgbe_xmit_cleanup(txq) != 0) {
630 /* Could not clean any descriptors */
636 /* nb_used better be <= txq->tx_rs_thresh */
637 if (unlikely(nb_used > txq->tx_rs_thresh)) {
638 PMD_TX_FREE_LOG(DEBUG,
639 "The number of descriptors needed to "
640 "transmit the packet exceeds the "
641 "RS bit threshold. This will impact "
643 "nb_used=%4u nb_free=%4u "
645 "(port=%d queue=%d)",
646 nb_used, txq->nb_tx_free,
648 txq->port_id, txq->queue_id);
650 * Loop here until there are enough TX
651 * descriptors or until the ring cannot be
654 while (nb_used > txq->nb_tx_free) {
655 if (ixgbe_xmit_cleanup(txq) != 0) {
657 * Could not clean any
669 * By now there are enough free TX descriptors to transmit
674 * Set common flags of all TX Data Descriptors.
676 * The following bits must be set in all Data Descriptors:
677 * - IXGBE_ADVTXD_DTYP_DATA
678 * - IXGBE_ADVTXD_DCMD_DEXT
680 * The following bits must be set in the first Data Descriptor
681 * and are ignored in the other ones:
682 * - IXGBE_ADVTXD_DCMD_IFCS
683 * - IXGBE_ADVTXD_MAC_1588
684 * - IXGBE_ADVTXD_DCMD_VLE
686 * The following bits must only be set in the last Data
688 * - IXGBE_TXD_CMD_EOP
690 * The following bits can be set in any Data Descriptor, but
691 * are only set in the last Data Descriptor:
694 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
695 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
696 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
697 #ifdef RTE_LIBRTE_IEEE1588
698 if (ol_flags & PKT_TX_IEEE1588_TMST)
699 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
704 * Setup the TX Advanced Context Descriptor if required
707 volatile struct ixgbe_adv_tx_context_desc *
710 ctx_txd = (volatile struct
711 ixgbe_adv_tx_context_desc *)
714 txn = &sw_ring[txe->next_id];
715 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
717 if (txe->mbuf != NULL) {
718 rte_pktmbuf_free_seg(txe->mbuf);
722 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
725 txe->last_id = tx_last;
726 tx_id = txe->next_id;
731 * Setup the TX Advanced Data Descriptor,
732 * This path will go through
733 * whatever new/reuse the context descriptor
735 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
736 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
737 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
743 txn = &sw_ring[txe->next_id];
745 if (txe->mbuf != NULL)
746 rte_pktmbuf_free_seg(txe->mbuf);
750 * Set up Transmit Data Descriptor.
752 slen = m_seg->pkt.data_len;
753 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
754 txd->read.buffer_addr =
755 rte_cpu_to_le_64(buf_dma_addr);
756 txd->read.cmd_type_len =
757 rte_cpu_to_le_32(cmd_type_len | slen);
758 txd->read.olinfo_status =
759 rte_cpu_to_le_32(olinfo_status);
760 txe->last_id = tx_last;
761 tx_id = txe->next_id;
763 m_seg = m_seg->pkt.next;
764 } while (m_seg != NULL);
767 * The last packet data descriptor needs End Of Packet (EOP)
769 cmd_type_len |= IXGBE_TXD_CMD_EOP;
770 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
771 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
773 /* Set RS bit only on threshold packets' last descriptor */
774 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
775 PMD_TX_FREE_LOG(DEBUG,
776 "Setting RS bit on TXD id="
777 "%4u (port=%d queue=%d)",
778 tx_last, txq->port_id, txq->queue_id);
780 cmd_type_len |= IXGBE_TXD_CMD_RS;
782 /* Update txq RS bit counters */
785 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
791 * Set the Transmit Descriptor Tail (TDT)
793 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
794 (unsigned) txq->port_id, (unsigned) txq->queue_id,
795 (unsigned) tx_id, (unsigned) nb_tx);
796 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
797 txq->tx_tail = tx_id;
802 /*********************************************************************
806 **********************************************************************/
807 static inline uint16_t
808 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
812 static uint16_t ip_pkt_types_map[16] = {
813 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
814 PKT_RX_IPV6_HDR, 0, 0, 0,
815 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
816 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
819 static uint16_t ip_rss_types_map[16] = {
820 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
821 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
822 PKT_RX_RSS_HASH, 0, 0, 0,
823 0, 0, 0, PKT_RX_FDIR,
826 #ifdef RTE_LIBRTE_IEEE1588
827 static uint32_t ip_pkt_etqf_map[8] = {
828 0, 0, 0, PKT_RX_IEEE1588_PTP,
832 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
833 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
834 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
836 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
837 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
840 return (uint16_t)(pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF]);
843 static inline uint16_t
844 rx_desc_status_to_pkt_flags(uint32_t rx_status)
849 * Check if VLAN present only.
850 * Do not check whether L3/L4 rx checksum done by NIC or not,
851 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
853 pkt_flags = (uint16_t)((rx_status & IXGBE_RXD_STAT_VP) ?
854 PKT_RX_VLAN_PKT : 0);
856 #ifdef RTE_LIBRTE_IEEE1588
857 if (rx_status & IXGBE_RXD_STAT_TMST)
858 pkt_flags = (uint16_t)(pkt_flags | PKT_RX_IEEE1588_TMST);
863 static inline uint16_t
864 rx_desc_error_to_pkt_flags(uint32_t rx_status)
867 * Bit 31: IPE, IPv4 checksum error
868 * Bit 30: L4I, L4I integrity error
870 static uint16_t error_to_pkt_flags_map[4] = {
871 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
872 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
874 return error_to_pkt_flags_map[(rx_status >>
875 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
878 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
880 * LOOK_AHEAD defines how many desc statuses to check beyond the
881 * current descriptor.
882 * It must be a pound define for optimal performance.
883 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
884 * function only works with LOOK_AHEAD=8.
887 #if (LOOK_AHEAD != 8)
888 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
891 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
893 volatile union ixgbe_adv_rx_desc *rxdp;
894 struct igb_rx_entry *rxep;
897 int s[LOOK_AHEAD], nb_dd;
901 /* get references to current descriptor and S/W ring entry */
902 rxdp = &rxq->rx_ring[rxq->rx_tail];
903 rxep = &rxq->sw_ring[rxq->rx_tail];
905 /* check to make sure there is at least 1 packet to receive */
906 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
910 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
911 * reference packets that are ready to be received.
913 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
914 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
916 /* Read desc statuses backwards to avoid race condition */
917 for (j = LOOK_AHEAD-1; j >= 0; --j)
918 s[j] = rxdp[j].wb.upper.status_error;
920 /* Compute how many status bits were set */
922 for (j = 0; j < LOOK_AHEAD; ++j)
923 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
927 /* Translate descriptor info to mbuf format */
928 for (j = 0; j < nb_dd; ++j) {
930 pkt_len = (uint16_t)(rxdp[j].wb.upper.length -
932 mb->pkt.data_len = pkt_len;
933 mb->pkt.pkt_len = pkt_len;
934 mb->pkt.vlan_macip.f.vlan_tci = rxdp[j].wb.upper.vlan;
935 mb->pkt.hash.rss = rxdp[j].wb.lower.hi_dword.rss;
937 /* convert descriptor fields to rte mbuf flags */
938 mb->ol_flags = rx_desc_hlen_type_rss_to_pkt_flags(
939 rxdp[j].wb.lower.lo_dword.data);
940 /* reuse status field from scan list */
941 mb->ol_flags = (uint16_t)(mb->ol_flags |
942 rx_desc_status_to_pkt_flags(s[j]));
943 mb->ol_flags = (uint16_t)(mb->ol_flags |
944 rx_desc_error_to_pkt_flags(s[j]));
947 /* Move mbuf pointers from the S/W ring to the stage */
948 for (j = 0; j < LOOK_AHEAD; ++j) {
949 rxq->rx_stage[i + j] = rxep[j].mbuf;
952 /* stop if all requested packets could not be received */
953 if (nb_dd != LOOK_AHEAD)
957 /* clear software ring entries so we can cleanup correctly */
958 for (i = 0; i < nb_rx; ++i) {
959 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
967 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
969 volatile union ixgbe_adv_rx_desc *rxdp;
970 struct igb_rx_entry *rxep;
976 /* allocate buffers in bulk directly into the S/W ring */
977 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
978 (rxq->rx_free_thresh - 1));
979 rxep = &rxq->sw_ring[alloc_idx];
980 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
981 rxq->rx_free_thresh);
982 if (unlikely(diag != 0))
985 rxdp = &rxq->rx_ring[alloc_idx];
986 for (i = 0; i < rxq->rx_free_thresh; ++i) {
987 /* populate the static rte mbuf fields */
989 rte_mbuf_refcnt_set(mb, 1);
990 mb->type = RTE_MBUF_PKT;
992 mb->pkt.data = (char *)mb->buf_addr + RTE_PKTMBUF_HEADROOM;
994 mb->pkt.in_port = rxq->port_id;
996 /* populate the descriptors */
997 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
998 rxdp[i].read.hdr_addr = dma_addr;
999 rxdp[i].read.pkt_addr = dma_addr;
1002 /* update tail pointer */
1004 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1006 /* update state of internal queue structure */
1007 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1008 rxq->rx_free_thresh);
1009 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1010 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1016 static inline uint16_t
1017 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1020 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1023 /* how many packets are ready to return? */
1024 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1026 /* copy mbuf pointers to the application's packet list */
1027 for (i = 0; i < nb_pkts; ++i)
1028 rx_pkts[i] = stage[i];
1030 /* update internal queue state */
1031 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1032 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1037 static inline uint16_t
1038 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1041 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1044 /* Any previously recv'd pkts will be returned from the Rx stage */
1045 if (rxq->rx_nb_avail)
1046 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1048 /* Scan the H/W ring for packets to receive */
1049 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1051 /* update internal queue state */
1052 rxq->rx_next_avail = 0;
1053 rxq->rx_nb_avail = nb_rx;
1054 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1056 /* if required, allocate new buffers to replenish descriptors */
1057 if (rxq->rx_tail > rxq->rx_free_trigger) {
1058 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1060 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1061 "queue_id=%u\n", (unsigned) rxq->port_id,
1062 (unsigned) rxq->queue_id);
1064 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1065 rxq->rx_free_thresh;
1068 * Need to rewind any previous receives if we cannot
1069 * allocate new buffers to replenish the old ones.
1071 rxq->rx_nb_avail = 0;
1072 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1073 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1074 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1080 if (rxq->rx_tail >= rxq->nb_rx_desc)
1083 /* received any packets this loop? */
1084 if (rxq->rx_nb_avail)
1085 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1090 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1092 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1097 if (unlikely(nb_pkts == 0))
1100 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1101 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1103 /* request is relatively large, chunk it up */
1107 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1108 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1109 nb_rx = (uint16_t)(nb_rx + ret);
1110 nb_pkts = (uint16_t)(nb_pkts - ret);
1117 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1120 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1123 struct igb_rx_queue *rxq;
1124 volatile union ixgbe_adv_rx_desc *rx_ring;
1125 volatile union ixgbe_adv_rx_desc *rxdp;
1126 struct igb_rx_entry *sw_ring;
1127 struct igb_rx_entry *rxe;
1128 struct rte_mbuf *rxm;
1129 struct rte_mbuf *nmb;
1130 union ixgbe_adv_rx_desc rxd;
1133 uint32_t hlen_type_rss;
1143 rx_id = rxq->rx_tail;
1144 rx_ring = rxq->rx_ring;
1145 sw_ring = rxq->sw_ring;
1146 while (nb_rx < nb_pkts) {
1148 * The order of operations here is important as the DD status
1149 * bit must not be read after any other descriptor fields.
1150 * rx_ring and rxdp are pointing to volatile data so the order
1151 * of accesses cannot be reordered by the compiler. If they were
1152 * not volatile, they could be reordered which could lead to
1153 * using invalid descriptor fields when read from rxd.
1155 rxdp = &rx_ring[rx_id];
1156 staterr = rxdp->wb.upper.status_error;
1157 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1164 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1165 * is likely to be invalid and to be dropped by the various
1166 * validation checks performed by the network stack.
1168 * Allocate a new mbuf to replenish the RX ring descriptor.
1169 * If the allocation fails:
1170 * - arrange for that RX descriptor to be the first one
1171 * being parsed the next time the receive function is
1172 * invoked [on the same queue].
1174 * - Stop parsing the RX ring and return immediately.
1176 * This policy do not drop the packet received in the RX
1177 * descriptor for which the allocation of a new mbuf failed.
1178 * Thus, it allows that packet to be later retrieved if
1179 * mbuf have been freed in the mean time.
1180 * As a side effect, holding RX descriptors instead of
1181 * systematically giving them back to the NIC may lead to
1182 * RX ring exhaustion situations.
1183 * However, the NIC can gracefully prevent such situations
1184 * to happen by sending specific "back-pressure" flow control
1185 * frames to its peer(s).
1187 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1188 "ext_err_stat=0x%08x pkt_len=%u\n",
1189 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1190 (unsigned) rx_id, (unsigned) staterr,
1191 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1193 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1195 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1196 "queue_id=%u\n", (unsigned) rxq->port_id,
1197 (unsigned) rxq->queue_id);
1198 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1203 rxe = &sw_ring[rx_id];
1205 if (rx_id == rxq->nb_rx_desc)
1208 /* Prefetch next mbuf while processing current one. */
1209 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1212 * When next RX descriptor is on a cache-line boundary,
1213 * prefetch the next 4 RX descriptors and the next 8 pointers
1216 if ((rx_id & 0x3) == 0) {
1217 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1218 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1224 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1225 rxdp->read.hdr_addr = dma_addr;
1226 rxdp->read.pkt_addr = dma_addr;
1229 * Initialize the returned mbuf.
1230 * 1) setup generic mbuf fields:
1231 * - number of segments,
1234 * - RX port identifier.
1235 * 2) integrate hardware offload data, if any:
1236 * - RSS flag & hash,
1237 * - IP checksum flag,
1238 * - VLAN TCI, if any,
1241 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1243 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1244 rte_packet_prefetch(rxm->pkt.data);
1245 rxm->pkt.nb_segs = 1;
1246 rxm->pkt.next = NULL;
1247 rxm->pkt.pkt_len = pkt_len;
1248 rxm->pkt.data_len = pkt_len;
1249 rxm->pkt.in_port = rxq->port_id;
1251 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1252 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1253 rxm->pkt.vlan_macip.f.vlan_tci =
1254 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1256 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1257 pkt_flags = (uint16_t)(pkt_flags |
1258 rx_desc_status_to_pkt_flags(staterr));
1259 pkt_flags = (uint16_t)(pkt_flags |
1260 rx_desc_error_to_pkt_flags(staterr));
1261 rxm->ol_flags = pkt_flags;
1263 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1264 rxm->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1265 else if (pkt_flags & PKT_RX_FDIR) {
1266 rxm->pkt.hash.fdir.hash =
1267 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1268 & IXGBE_ATR_HASH_MASK);
1269 rxm->pkt.hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1272 * Store the mbuf address into the next entry of the array
1273 * of returned packets.
1275 rx_pkts[nb_rx++] = rxm;
1277 rxq->rx_tail = rx_id;
1280 * If the number of free RX descriptors is greater than the RX free
1281 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1283 * Update the RDT with the value of the last processed RX descriptor
1284 * minus 1, to guarantee that the RDT register is never equal to the
1285 * RDH register, which creates a "full" ring situtation from the
1286 * hardware point of view...
1288 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1289 if (nb_hold > rxq->rx_free_thresh) {
1290 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1291 "nb_hold=%u nb_rx=%u\n",
1292 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1293 (unsigned) rx_id, (unsigned) nb_hold,
1295 rx_id = (uint16_t) ((rx_id == 0) ?
1296 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1297 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1300 rxq->nb_rx_hold = nb_hold;
1305 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1308 struct igb_rx_queue *rxq;
1309 volatile union ixgbe_adv_rx_desc *rx_ring;
1310 volatile union ixgbe_adv_rx_desc *rxdp;
1311 struct igb_rx_entry *sw_ring;
1312 struct igb_rx_entry *rxe;
1313 struct rte_mbuf *first_seg;
1314 struct rte_mbuf *last_seg;
1315 struct rte_mbuf *rxm;
1316 struct rte_mbuf *nmb;
1317 union ixgbe_adv_rx_desc rxd;
1318 uint64_t dma; /* Physical address of mbuf data buffer */
1320 uint32_t hlen_type_rss;
1330 rx_id = rxq->rx_tail;
1331 rx_ring = rxq->rx_ring;
1332 sw_ring = rxq->sw_ring;
1335 * Retrieve RX context of current packet, if any.
1337 first_seg = rxq->pkt_first_seg;
1338 last_seg = rxq->pkt_last_seg;
1340 while (nb_rx < nb_pkts) {
1343 * The order of operations here is important as the DD status
1344 * bit must not be read after any other descriptor fields.
1345 * rx_ring and rxdp are pointing to volatile data so the order
1346 * of accesses cannot be reordered by the compiler. If they were
1347 * not volatile, they could be reordered which could lead to
1348 * using invalid descriptor fields when read from rxd.
1350 rxdp = &rx_ring[rx_id];
1351 staterr = rxdp->wb.upper.status_error;
1352 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1359 * Allocate a new mbuf to replenish the RX ring descriptor.
1360 * If the allocation fails:
1361 * - arrange for that RX descriptor to be the first one
1362 * being parsed the next time the receive function is
1363 * invoked [on the same queue].
1365 * - Stop parsing the RX ring and return immediately.
1367 * This policy does not drop the packet received in the RX
1368 * descriptor for which the allocation of a new mbuf failed.
1369 * Thus, it allows that packet to be later retrieved if
1370 * mbuf have been freed in the mean time.
1371 * As a side effect, holding RX descriptors instead of
1372 * systematically giving them back to the NIC may lead to
1373 * RX ring exhaustion situations.
1374 * However, the NIC can gracefully prevent such situations
1375 * to happen by sending specific "back-pressure" flow control
1376 * frames to its peer(s).
1378 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
1379 "staterr=0x%x data_len=%u\n",
1380 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1381 (unsigned) rx_id, (unsigned) staterr,
1382 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1384 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1386 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1387 "queue_id=%u\n", (unsigned) rxq->port_id,
1388 (unsigned) rxq->queue_id);
1389 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1394 rxe = &sw_ring[rx_id];
1396 if (rx_id == rxq->nb_rx_desc)
1399 /* Prefetch next mbuf while processing current one. */
1400 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1403 * When next RX descriptor is on a cache-line boundary,
1404 * prefetch the next 4 RX descriptors and the next 8 pointers
1407 if ((rx_id & 0x3) == 0) {
1408 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1409 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1413 * Update RX descriptor with the physical address of the new
1414 * data buffer of the new allocated mbuf.
1418 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1419 rxdp->read.hdr_addr = dma;
1420 rxdp->read.pkt_addr = dma;
1423 * Set data length & data buffer address of mbuf.
1425 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1426 rxm->pkt.data_len = data_len;
1427 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1430 * If this is the first buffer of the received packet,
1431 * set the pointer to the first mbuf of the packet and
1432 * initialize its context.
1433 * Otherwise, update the total length and the number of segments
1434 * of the current scattered packet, and update the pointer to
1435 * the last mbuf of the current packet.
1437 if (first_seg == NULL) {
1439 first_seg->pkt.pkt_len = data_len;
1440 first_seg->pkt.nb_segs = 1;
1442 first_seg->pkt.pkt_len = (uint16_t)(first_seg->pkt.pkt_len
1444 first_seg->pkt.nb_segs++;
1445 last_seg->pkt.next = rxm;
1449 * If this is not the last buffer of the received packet,
1450 * update the pointer to the last mbuf of the current scattered
1451 * packet and continue to parse the RX ring.
1453 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1459 * This is the last buffer of the received packet.
1460 * If the CRC is not stripped by the hardware:
1461 * - Subtract the CRC length from the total packet length.
1462 * - If the last buffer only contains the whole CRC or a part
1463 * of it, free the mbuf associated to the last buffer.
1464 * If part of the CRC is also contained in the previous
1465 * mbuf, subtract the length of that CRC part from the
1466 * data length of the previous mbuf.
1468 rxm->pkt.next = NULL;
1469 if (unlikely(rxq->crc_len > 0)) {
1470 first_seg->pkt.pkt_len -= ETHER_CRC_LEN;
1471 if (data_len <= ETHER_CRC_LEN) {
1472 rte_pktmbuf_free_seg(rxm);
1473 first_seg->pkt.nb_segs--;
1474 last_seg->pkt.data_len = (uint16_t)
1475 (last_seg->pkt.data_len -
1476 (ETHER_CRC_LEN - data_len));
1477 last_seg->pkt.next = NULL;
1480 (uint16_t) (data_len - ETHER_CRC_LEN);
1484 * Initialize the first mbuf of the returned packet:
1485 * - RX port identifier,
1486 * - hardware offload data, if any:
1487 * - RSS flag & hash,
1488 * - IP checksum flag,
1489 * - VLAN TCI, if any,
1492 first_seg->pkt.in_port = rxq->port_id;
1495 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1496 * set in the pkt_flags field.
1498 first_seg->pkt.vlan_macip.f.vlan_tci =
1499 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1500 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1501 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1502 pkt_flags = (uint16_t)(pkt_flags |
1503 rx_desc_status_to_pkt_flags(staterr));
1504 pkt_flags = (uint16_t)(pkt_flags |
1505 rx_desc_error_to_pkt_flags(staterr));
1506 first_seg->ol_flags = pkt_flags;
1508 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1509 first_seg->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1510 else if (pkt_flags & PKT_RX_FDIR) {
1511 first_seg->pkt.hash.fdir.hash =
1512 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1513 & IXGBE_ATR_HASH_MASK);
1514 first_seg->pkt.hash.fdir.id =
1515 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1518 /* Prefetch data of first segment, if configured to do so. */
1519 rte_packet_prefetch(first_seg->pkt.data);
1522 * Store the mbuf address into the next entry of the array
1523 * of returned packets.
1525 rx_pkts[nb_rx++] = first_seg;
1528 * Setup receipt context for a new packet.
1534 * Record index of the next RX descriptor to probe.
1536 rxq->rx_tail = rx_id;
1539 * Save receive context.
1541 rxq->pkt_first_seg = first_seg;
1542 rxq->pkt_last_seg = last_seg;
1545 * If the number of free RX descriptors is greater than the RX free
1546 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1548 * Update the RDT with the value of the last processed RX descriptor
1549 * minus 1, to guarantee that the RDT register is never equal to the
1550 * RDH register, which creates a "full" ring situtation from the
1551 * hardware point of view...
1553 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1554 if (nb_hold > rxq->rx_free_thresh) {
1555 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1556 "nb_hold=%u nb_rx=%u\n",
1557 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1558 (unsigned) rx_id, (unsigned) nb_hold,
1560 rx_id = (uint16_t) ((rx_id == 0) ?
1561 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1562 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1565 rxq->nb_rx_hold = nb_hold;
1569 /*********************************************************************
1571 * Queue management functions
1573 **********************************************************************/
1576 * Rings setup and release.
1578 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1579 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1580 * also optimize cache line size effect. H/W supports up to cache line size 128.
1582 #define IXGBE_ALIGN 128
1585 * Maximum number of Ring Descriptors.
1587 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1588 * descriptors should meet the following condition:
1589 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1591 #define IXGBE_MIN_RING_DESC 64
1592 #define IXGBE_MAX_RING_DESC 4096
1595 * Create memzone for HW rings. malloc can't be used as the physical address is
1596 * needed. If the memzone is already created, then this function returns a ptr
1599 static const struct rte_memzone *
1600 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1601 uint16_t queue_id, uint32_t ring_size, int socket_id)
1603 char z_name[RTE_MEMZONE_NAMESIZE];
1604 const struct rte_memzone *mz;
1606 rte_snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1607 dev->driver->pci_drv.name, ring_name,
1608 dev->data->port_id, queue_id);
1610 mz = rte_memzone_lookup(z_name);
1614 #ifdef RTE_LIBRTE_XEN_DOM0
1615 return rte_memzone_reserve_bounded(z_name, ring_size,
1616 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1618 return rte_memzone_reserve_aligned(z_name, ring_size,
1619 socket_id, 0, IXGBE_ALIGN);
1624 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1628 if (txq->sw_ring != NULL) {
1629 for (i = 0; i < txq->nb_tx_desc; i++) {
1630 if (txq->sw_ring[i].mbuf != NULL) {
1631 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1632 txq->sw_ring[i].mbuf = NULL;
1639 ixgbe_tx_free_swring(struct igb_tx_queue *txq)
1642 txq->sw_ring != NULL)
1643 rte_free(txq->sw_ring);
1647 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1649 if (txq != NULL && txq->ops != NULL) {
1650 txq->ops->release_mbufs(txq);
1651 txq->ops->free_swring(txq);
1657 ixgbe_dev_tx_queue_release(void *txq)
1659 ixgbe_tx_queue_release(txq);
1662 /* (Re)set dynamic igb_tx_queue fields to defaults */
1664 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1666 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1668 struct igb_tx_entry *txe = txq->sw_ring;
1671 /* Zero out HW ring memory */
1672 for (i = 0; i < txq->nb_tx_desc; i++) {
1673 txq->tx_ring[i] = zeroed_desc;
1676 /* Initialize SW ring entries */
1677 prev = (uint16_t) (txq->nb_tx_desc - 1);
1678 for (i = 0; i < txq->nb_tx_desc; i++) {
1679 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1680 txd->wb.status = IXGBE_TXD_STAT_DD;
1683 txe[prev].next_id = i;
1687 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1688 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1691 txq->nb_tx_used = 0;
1693 * Always allow 1 descriptor to be un-allocated to avoid
1694 * a H/W race condition
1696 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1697 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1699 memset((void*)&txq->ctx_cache, 0,
1700 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1703 static struct ixgbe_txq_ops def_txq_ops = {
1704 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1705 .free_swring = ixgbe_tx_free_swring,
1706 .reset = ixgbe_reset_tx_queue,
1710 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1713 unsigned int socket_id,
1714 const struct rte_eth_txconf *tx_conf)
1716 const struct rte_memzone *tz;
1717 struct igb_tx_queue *txq;
1718 struct ixgbe_hw *hw;
1719 uint16_t tx_rs_thresh, tx_free_thresh;
1721 PMD_INIT_FUNC_TRACE();
1722 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1725 * Validate number of transmit descriptors.
1726 * It must not exceed hardware maximum, and must be multiple
1729 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1730 (nb_desc > IXGBE_MAX_RING_DESC) ||
1731 (nb_desc < IXGBE_MIN_RING_DESC)) {
1736 * The following two parameters control the setting of the RS bit on
1737 * transmit descriptors.
1738 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1739 * descriptors have been used.
1740 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1741 * descriptors are used or if the number of descriptors required
1742 * to transmit a packet is greater than the number of free TX
1744 * The following constraints must be satisfied:
1745 * tx_rs_thresh must be greater than 0.
1746 * tx_rs_thresh must be less than the size of the ring minus 2.
1747 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1748 * tx_rs_thresh must be a divisor of the ring size.
1749 * tx_free_thresh must be greater than 0.
1750 * tx_free_thresh must be less than the size of the ring minus 3.
1751 * One descriptor in the TX ring is used as a sentinel to avoid a
1752 * H/W race condition, hence the maximum threshold constraints.
1753 * When set to zero use default values.
1755 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1756 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1757 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1758 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1759 if (tx_rs_thresh >= (nb_desc - 2)) {
1760 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the number "
1761 "of TX descriptors minus 2. (tx_rs_thresh=%u port=%d "
1762 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1763 (int)dev->data->port_id, (int)queue_idx);
1766 if (tx_free_thresh >= (nb_desc - 3)) {
1767 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the "
1768 "tx_free_thresh must be less than the number of TX "
1769 "descriptors minus 3. (tx_free_thresh=%u port=%d "
1770 "queue=%d)\n", (unsigned int)tx_free_thresh,
1771 (int)dev->data->port_id, (int)queue_idx);
1774 if (tx_rs_thresh > tx_free_thresh) {
1775 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than or equal to "
1776 "tx_free_thresh. (tx_free_thresh=%u tx_rs_thresh=%u "
1777 "port=%d queue=%d)\n", (unsigned int)tx_free_thresh,
1778 (unsigned int)tx_rs_thresh, (int)dev->data->port_id,
1782 if ((nb_desc % tx_rs_thresh) != 0) {
1783 RTE_LOG(ERR, PMD, "tx_rs_thresh must be a divisor of the "
1784 "number of TX descriptors. (tx_rs_thresh=%u port=%d "
1785 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1786 (int)dev->data->port_id, (int)queue_idx);
1791 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1792 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1793 * by the NIC and all descriptors are written back after the NIC
1794 * accumulates WTHRESH descriptors.
1796 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1797 RTE_LOG(ERR, PMD, "TX WTHRESH must be set to 0 if "
1798 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1799 "port=%d queue=%d)\n", (unsigned int)tx_rs_thresh,
1800 (int)dev->data->port_id, (int)queue_idx);
1804 /* Free memory prior to re-allocation if needed... */
1805 if (dev->data->tx_queues[queue_idx] != NULL)
1806 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1808 /* First allocate the tx queue data structure */
1809 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct igb_tx_queue),
1810 CACHE_LINE_SIZE, socket_id);
1815 * Allocate TX ring hardware descriptors. A memzone large enough to
1816 * handle the maximum ring size is allocated in order to allow for
1817 * resizing in later calls to the queue setup function.
1819 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1820 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1823 ixgbe_tx_queue_release(txq);
1827 txq->nb_tx_desc = nb_desc;
1828 txq->tx_rs_thresh = tx_rs_thresh;
1829 txq->tx_free_thresh = tx_free_thresh;
1830 txq->pthresh = tx_conf->tx_thresh.pthresh;
1831 txq->hthresh = tx_conf->tx_thresh.hthresh;
1832 txq->wthresh = tx_conf->tx_thresh.wthresh;
1833 txq->queue_id = queue_idx;
1834 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1835 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1836 txq->port_id = dev->data->port_id;
1837 txq->txq_flags = tx_conf->txq_flags;
1838 txq->ops = &def_txq_ops;
1841 * Modification to set VFTDT for virtual function if vf is detected
1843 if (hw->mac.type == ixgbe_mac_82599_vf)
1844 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1846 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1847 #ifndef RTE_LIBRTE_XEN_DOM0
1848 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1850 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1852 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1854 /* Allocate software ring */
1855 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1856 sizeof(struct igb_tx_entry) * nb_desc,
1857 CACHE_LINE_SIZE, socket_id);
1858 if (txq->sw_ring == NULL) {
1859 ixgbe_tx_queue_release(txq);
1862 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1863 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1865 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1866 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
1867 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1868 PMD_INIT_LOG(INFO, "Using simple tx code path\n");
1869 #ifdef RTE_IXGBE_INC_VECTOR
1870 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1871 ixgbe_txq_vec_setup(txq, socket_id) == 0) {
1872 PMD_INIT_LOG(INFO, "Vector tx enabled.\n");
1873 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1877 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1879 PMD_INIT_LOG(INFO, "Using full-featured tx code path\n");
1880 PMD_INIT_LOG(INFO, " - txq_flags = %lx [IXGBE_SIMPLE_FLAGS=%lx]\n", (long unsigned)txq->txq_flags, (long unsigned)IXGBE_SIMPLE_FLAGS);
1881 PMD_INIT_LOG(INFO, " - tx_rs_thresh = %lu [RTE_PMD_IXGBE_TX_MAX_BURST=%lu]\n", (long unsigned)txq->tx_rs_thresh, (long unsigned)RTE_PMD_IXGBE_TX_MAX_BURST);
1882 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1885 txq->ops->reset(txq);
1887 dev->data->tx_queues[queue_idx] = txq;
1894 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1898 if (rxq->sw_ring != NULL) {
1899 for (i = 0; i < rxq->nb_rx_desc; i++) {
1900 if (rxq->sw_ring[i].mbuf != NULL) {
1901 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1902 rxq->sw_ring[i].mbuf = NULL;
1905 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1906 if (rxq->rx_nb_avail) {
1907 for (i = 0; i < rxq->rx_nb_avail; ++i) {
1908 struct rte_mbuf *mb;
1909 mb = rxq->rx_stage[rxq->rx_next_avail + i];
1910 rte_pktmbuf_free_seg(mb);
1912 rxq->rx_nb_avail = 0;
1919 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
1922 ixgbe_rx_queue_release_mbufs(rxq);
1923 rte_free(rxq->sw_ring);
1929 ixgbe_dev_rx_queue_release(void *rxq)
1931 ixgbe_rx_queue_release(rxq);
1935 * Check if Rx Burst Bulk Alloc function can be used.
1937 * 0: the preconditions are satisfied and the bulk allocation function
1939 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
1940 * function must be used.
1943 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1944 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
1946 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct igb_rx_queue *rxq)
1952 * Make sure the following pre-conditions are satisfied:
1953 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
1954 * rxq->rx_free_thresh < rxq->nb_rx_desc
1955 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
1956 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
1957 * Scattered packets are not supported. This should be checked
1958 * outside of this function.
1960 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1961 if (! (rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST))
1963 else if (! (rxq->rx_free_thresh < rxq->nb_rx_desc))
1965 else if (! ((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0))
1967 else if (! (rxq->nb_rx_desc <
1968 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST)))
1977 /* Reset dynamic igb_rx_queue fields back to defaults */
1979 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
1981 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
1987 * By default, the Rx queue setup function allocates enough memory for
1988 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
1989 * extra memory at the end of the descriptor ring to be zero'd out. A
1990 * pre-condition for using the Rx burst bulk alloc function is that the
1991 * number of descriptors is less than or equal to
1992 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
1993 * constraints here to see if we need to zero out memory after the end
1994 * of the H/W descriptor ring.
1996 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1997 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
1998 /* zero out extra memory */
1999 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2002 /* do not zero out extra memory */
2003 len = rxq->nb_rx_desc;
2006 * Zero out HW ring memory. Zero out extra memory at the end of
2007 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2008 * reads extra memory as zeros.
2010 for (i = 0; i < len; i++) {
2011 rxq->rx_ring[i] = zeroed_desc;
2014 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2016 * initialize extra software ring entries. Space for these extra
2017 * entries is always allocated
2019 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2020 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2021 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2024 rxq->rx_nb_avail = 0;
2025 rxq->rx_next_avail = 0;
2026 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2027 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2029 rxq->nb_rx_hold = 0;
2030 rxq->pkt_first_seg = NULL;
2031 rxq->pkt_last_seg = NULL;
2035 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2038 unsigned int socket_id,
2039 const struct rte_eth_rxconf *rx_conf,
2040 struct rte_mempool *mp)
2042 const struct rte_memzone *rz;
2043 struct igb_rx_queue *rxq;
2044 struct ixgbe_hw *hw;
2045 int use_def_burst_func = 1;
2048 PMD_INIT_FUNC_TRACE();
2049 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2052 * Validate number of receive descriptors.
2053 * It must not exceed hardware maximum, and must be multiple
2056 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2057 (nb_desc > IXGBE_MAX_RING_DESC) ||
2058 (nb_desc < IXGBE_MIN_RING_DESC)) {
2062 /* Free memory prior to re-allocation if needed... */
2063 if (dev->data->rx_queues[queue_idx] != NULL)
2064 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2066 /* First allocate the rx queue data structure */
2067 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct igb_rx_queue),
2068 CACHE_LINE_SIZE, socket_id);
2072 rxq->nb_rx_desc = nb_desc;
2073 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2074 rxq->queue_id = queue_idx;
2075 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2076 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2077 rxq->port_id = dev->data->port_id;
2078 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2080 rxq->drop_en = rx_conf->rx_drop_en;
2083 * Allocate RX ring hardware descriptors. A memzone large enough to
2084 * handle the maximum ring size is allocated in order to allow for
2085 * resizing in later calls to the queue setup function.
2087 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2088 RX_RING_SZ, socket_id);
2090 ixgbe_rx_queue_release(rxq);
2095 * Zero init all the descriptors in the ring.
2097 memset (rz->addr, 0, RX_RING_SZ);
2100 * Modified to setup VFRDT for Virtual Function
2102 if (hw->mac.type == ixgbe_mac_82599_vf) {
2104 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2106 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2110 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2112 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2114 #ifndef RTE_LIBRTE_XEN_DOM0
2115 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2117 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2119 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2122 * Allocate software ring. Allow for space at the end of the
2123 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2124 * function does not access an invalid memory region.
2126 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2127 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2131 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2132 sizeof(struct igb_rx_entry) * len,
2133 CACHE_LINE_SIZE, socket_id);
2134 if (rxq->sw_ring == NULL) {
2135 ixgbe_rx_queue_release(rxq);
2138 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
2139 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2142 * Certain constraints must be met in order to use the bulk buffer
2143 * allocation Rx burst function.
2145 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2147 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2148 if (!use_def_burst_func && !dev->data->scattered_rx) {
2149 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2150 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2151 "satisfied. Rx Burst Bulk Alloc function will be "
2152 "used on port=%d, queue=%d.\n",
2153 rxq->port_id, rxq->queue_id);
2154 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2155 #ifdef RTE_IXGBE_INC_VECTOR
2156 if (!ixgbe_rx_vec_condition_check(dev)) {
2157 PMD_INIT_LOG(INFO, "Vector rx enabled.\n");
2158 ixgbe_rxq_vec_setup(rxq, socket_id);
2159 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
2164 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2165 "are not satisfied, Scattered Rx is requested, "
2166 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2167 "enabled (port=%d, queue=%d).\n",
2168 rxq->port_id, rxq->queue_id);
2170 dev->data->rx_queues[queue_idx] = rxq;
2172 ixgbe_reset_rx_queue(rxq);
2178 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2180 #define IXGBE_RXQ_SCAN_INTERVAL 4
2181 volatile union ixgbe_adv_rx_desc *rxdp;
2182 struct igb_rx_queue *rxq;
2185 if (rx_queue_id >= dev->data->nb_rx_queues) {
2186 PMD_RX_LOG(ERR, "Invalid RX queue id=%d\n", rx_queue_id);
2190 rxq = dev->data->rx_queues[rx_queue_id];
2191 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2193 while ((desc < rxq->nb_rx_desc) &&
2194 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2195 desc += IXGBE_RXQ_SCAN_INTERVAL;
2196 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2197 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2198 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2199 desc - rxq->nb_rx_desc]);
2206 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2208 volatile union ixgbe_adv_rx_desc *rxdp;
2209 struct igb_rx_queue *rxq = rx_queue;
2212 if (unlikely(offset >= rxq->nb_rx_desc))
2214 desc = rxq->rx_tail + offset;
2215 if (desc >= rxq->nb_rx_desc)
2216 desc -= rxq->nb_rx_desc;
2218 rxdp = &rxq->rx_ring[desc];
2219 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2223 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2227 PMD_INIT_FUNC_TRACE();
2229 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2230 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2232 txq->ops->release_mbufs(txq);
2233 txq->ops->reset(txq);
2237 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2238 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2240 ixgbe_rx_queue_release_mbufs(rxq);
2241 ixgbe_reset_rx_queue(rxq);
2246 /*********************************************************************
2248 * Device RX/TX init functions
2250 **********************************************************************/
2253 * Receive Side Scaling (RSS)
2254 * See section 7.1.2.8 in the following document:
2255 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2258 * The source and destination IP addresses of the IP header and the source
2259 * and destination ports of TCP/UDP headers, if any, of received packets are
2260 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2261 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2262 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2263 * RSS output index which is used as the RX queue index where to store the
2265 * The following output is supplied in the RX write-back descriptor:
2266 * - 32-bit result of the Microsoft RSS hash function,
2267 * - 4-bit RSS type field.
2271 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2272 * Used as the default key.
2274 static uint8_t rss_intel_key[40] = {
2275 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2276 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2277 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2278 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2279 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2283 ixgbe_rss_disable(struct rte_eth_dev *dev)
2285 struct ixgbe_hw *hw;
2288 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2289 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2290 mrqc &= ~IXGBE_MRQC_RSSEN;
2291 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2295 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2303 hash_key = rss_conf->rss_key;
2304 if (hash_key != NULL) {
2305 /* Fill in RSS hash key */
2306 for (i = 0; i < 10; i++) {
2307 rss_key = hash_key[(i * 4)];
2308 rss_key |= hash_key[(i * 4) + 1] << 8;
2309 rss_key |= hash_key[(i * 4) + 2] << 16;
2310 rss_key |= hash_key[(i * 4) + 3] << 24;
2311 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2315 /* Set configured hashing protocols in MRQC register */
2316 rss_hf = rss_conf->rss_hf;
2317 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2318 if (rss_hf & ETH_RSS_IPV4)
2319 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2320 if (rss_hf & ETH_RSS_IPV4_TCP)
2321 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2322 if (rss_hf & ETH_RSS_IPV6)
2323 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2324 if (rss_hf & ETH_RSS_IPV6_EX)
2325 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2326 if (rss_hf & ETH_RSS_IPV6_TCP)
2327 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2328 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2329 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2330 if (rss_hf & ETH_RSS_IPV4_UDP)
2331 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2332 if (rss_hf & ETH_RSS_IPV6_UDP)
2333 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2334 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2335 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2336 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2340 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2341 struct rte_eth_rss_conf *rss_conf)
2343 struct ixgbe_hw *hw;
2347 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2350 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2351 * "RSS enabling cannot be done dynamically while it must be
2352 * preceded by a software reset"
2353 * Before changing anything, first check that the update RSS operation
2354 * does not attempt to disable RSS, if RSS was enabled at
2355 * initialization time, or does not attempt to enable RSS, if RSS was
2356 * disabled at initialization time.
2358 rss_hf = rss_conf->rss_hf;
2359 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2360 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2361 if (rss_hf != 0) /* Enable RSS */
2363 return 0; /* Nothing to do */
2366 if (rss_hf == 0) /* Disable RSS */
2368 ixgbe_hw_rss_hash_set(hw, rss_conf);
2373 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2374 struct rte_eth_rss_conf *rss_conf)
2376 struct ixgbe_hw *hw;
2383 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2384 hash_key = rss_conf->rss_key;
2385 if (hash_key != NULL) {
2386 /* Return RSS hash key */
2387 for (i = 0; i < 10; i++) {
2388 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2389 hash_key[(i * 4)] = rss_key & 0x000000FF;
2390 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2391 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2392 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2396 /* Get RSS functions configured in MRQC register */
2397 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2398 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2399 rss_conf->rss_hf = 0;
2403 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2404 rss_hf |= ETH_RSS_IPV4;
2405 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2406 rss_hf |= ETH_RSS_IPV4_TCP;
2407 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2408 rss_hf |= ETH_RSS_IPV6;
2409 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2410 rss_hf |= ETH_RSS_IPV6_EX;
2411 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2412 rss_hf |= ETH_RSS_IPV6_TCP;
2413 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2414 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2415 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2416 rss_hf |= ETH_RSS_IPV4_UDP;
2417 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2418 rss_hf |= ETH_RSS_IPV6_UDP;
2419 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2420 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2421 rss_conf->rss_hf = rss_hf;
2426 ixgbe_rss_configure(struct rte_eth_dev *dev)
2428 struct rte_eth_rss_conf rss_conf;
2429 struct ixgbe_hw *hw;
2434 PMD_INIT_FUNC_TRACE();
2435 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2438 * Fill in redirection table
2439 * The byte-swap is needed because NIC registers are in
2440 * little-endian order.
2443 for (i = 0, j = 0; i < 128; i++, j++) {
2444 if (j == dev->data->nb_rx_queues)
2446 reta = (reta << 8) | j;
2448 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2453 * Configure the RSS key and the RSS protocols used to compute
2454 * the RSS hash of input packets.
2456 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2457 if (rss_conf.rss_hf == 0) {
2458 ixgbe_rss_disable(dev);
2461 if (rss_conf.rss_key == NULL)
2462 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2463 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2466 #define NUM_VFTA_REGISTERS 128
2467 #define NIC_RX_BUFFER_SIZE 0x200
2470 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2472 struct rte_eth_vmdq_dcb_conf *cfg;
2473 struct ixgbe_hw *hw;
2474 enum rte_eth_nb_pools num_pools;
2475 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2477 uint8_t nb_tcs; /* number of traffic classes */
2480 PMD_INIT_FUNC_TRACE();
2481 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2482 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2483 num_pools = cfg->nb_queue_pools;
2484 /* Check we have a valid number of pools */
2485 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2486 ixgbe_rss_disable(dev);
2489 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2490 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2494 * split rx buffer up into sections, each for 1 traffic class
2496 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2497 for (i = 0 ; i < nb_tcs; i++) {
2498 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2499 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2500 /* clear 10 bits. */
2501 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2502 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2504 /* zero alloc all unused TCs */
2505 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2506 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2507 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2508 /* clear 10 bits. */
2509 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2512 /* MRQC: enable vmdq and dcb */
2513 mrqc = ((num_pools == ETH_16_POOLS) ? \
2514 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2515 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2517 /* PFVTCTL: turn on virtualisation and set the default pool */
2518 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2519 if (cfg->enable_default_pool) {
2520 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2522 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2525 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2527 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2529 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2531 * mapping is done with 3 bits per priority,
2532 * so shift by i*3 each time
2534 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2536 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2538 /* RTRPCS: DCB related */
2539 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2541 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2542 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2543 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2544 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2546 /* VFTA - enable all vlan filters */
2547 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2548 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2551 /* VFRE: pool enabling for receive - 16 or 32 */
2552 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2553 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2556 * MPSAR - allow pools to read specific mac addresses
2557 * In this case, all pools should be able to read from mac addr 0
2559 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2560 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2562 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2563 for (i = 0; i < cfg->nb_pool_maps; i++) {
2564 /* set vlan id in VF register and set the valid bit */
2565 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2566 (cfg->pool_map[i].vlan_id & 0xFFF)));
2568 * Put the allowed pools in VFB reg. As we only have 16 or 32
2569 * pools, we only need to use the first half of the register
2572 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2577 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2578 * @hw: pointer to hardware structure
2579 * @dcb_config: pointer to ixgbe_dcb_config structure
2582 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2583 struct ixgbe_dcb_config *dcb_config)
2588 PMD_INIT_FUNC_TRACE();
2589 if (hw->mac.type != ixgbe_mac_82598EB) {
2590 /* Disable the Tx desc arbiter so that MTQC can be changed */
2591 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2592 reg |= IXGBE_RTTDCS_ARBDIS;
2593 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2595 /* Enable DCB for Tx with 8 TCs */
2596 if (dcb_config->num_tcs.pg_tcs == 8) {
2597 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2600 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2602 if (dcb_config->vt_mode)
2603 reg |= IXGBE_MTQC_VT_ENA;
2604 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2606 /* Disable drop for all queues */
2607 for (q = 0; q < 128; q++)
2608 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2609 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2611 /* Enable the Tx desc arbiter */
2612 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2613 reg &= ~IXGBE_RTTDCS_ARBDIS;
2614 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2616 /* Enable Security TX Buffer IFG for DCB */
2617 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2618 reg |= IXGBE_SECTX_DCB;
2619 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2625 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2626 * @dev: pointer to rte_eth_dev structure
2627 * @dcb_config: pointer to ixgbe_dcb_config structure
2630 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2631 struct ixgbe_dcb_config *dcb_config)
2633 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2634 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2635 struct ixgbe_hw *hw =
2636 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2638 PMD_INIT_FUNC_TRACE();
2639 if (hw->mac.type != ixgbe_mac_82598EB)
2640 /*PF VF Transmit Enable*/
2641 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2642 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2644 /*Configure general DCB TX parameters*/
2645 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2650 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2651 struct ixgbe_dcb_config *dcb_config)
2653 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2654 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2655 struct ixgbe_dcb_tc_config *tc;
2658 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2659 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2660 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2661 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2664 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2665 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2667 /* User Priority to Traffic Class mapping */
2668 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2669 j = vmdq_rx_conf->dcb_queue[i];
2670 tc = &dcb_config->tc_config[j];
2671 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2677 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2678 struct ixgbe_dcb_config *dcb_config)
2680 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2681 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2682 struct ixgbe_dcb_tc_config *tc;
2685 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2686 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2687 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2688 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2691 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2692 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2695 /* User Priority to Traffic Class mapping */
2696 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2697 j = vmdq_tx_conf->dcb_queue[i];
2698 tc = &dcb_config->tc_config[j];
2699 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2706 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2707 struct ixgbe_dcb_config *dcb_config)
2709 struct rte_eth_dcb_rx_conf *rx_conf =
2710 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2711 struct ixgbe_dcb_tc_config *tc;
2714 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2715 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2717 /* User Priority to Traffic Class mapping */
2718 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2719 j = rx_conf->dcb_queue[i];
2720 tc = &dcb_config->tc_config[j];
2721 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2727 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2728 struct ixgbe_dcb_config *dcb_config)
2730 struct rte_eth_dcb_tx_conf *tx_conf =
2731 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2732 struct ixgbe_dcb_tc_config *tc;
2735 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2736 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2738 /* User Priority to Traffic Class mapping */
2739 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2740 j = tx_conf->dcb_queue[i];
2741 tc = &dcb_config->tc_config[j];
2742 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2748 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2749 * @hw: pointer to hardware structure
2750 * @dcb_config: pointer to ixgbe_dcb_config structure
2753 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2754 struct ixgbe_dcb_config *dcb_config)
2760 PMD_INIT_FUNC_TRACE();
2762 * Disable the arbiter before changing parameters
2763 * (always enable recycle mode; WSP)
2765 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2766 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2768 if (hw->mac.type != ixgbe_mac_82598EB) {
2769 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2770 if (dcb_config->num_tcs.pg_tcs == 4) {
2771 if (dcb_config->vt_mode)
2772 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2773 IXGBE_MRQC_VMDQRT4TCEN;
2775 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2776 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2780 if (dcb_config->num_tcs.pg_tcs == 8) {
2781 if (dcb_config->vt_mode)
2782 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2783 IXGBE_MRQC_VMDQRT8TCEN;
2785 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2786 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2791 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2794 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2795 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2796 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2797 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2799 /* VFTA - enable all vlan filters */
2800 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2801 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2805 * Configure Rx packet plane (recycle mode; WSP) and
2808 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2809 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2815 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2816 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2818 switch (hw->mac.type) {
2819 case ixgbe_mac_82598EB:
2820 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2822 case ixgbe_mac_82599EB:
2823 case ixgbe_mac_X540:
2824 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2833 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2834 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2836 switch (hw->mac.type) {
2837 case ixgbe_mac_82598EB:
2838 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2839 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2841 case ixgbe_mac_82599EB:
2842 case ixgbe_mac_X540:
2843 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2844 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2851 #define DCB_RX_CONFIG 1
2852 #define DCB_TX_CONFIG 1
2853 #define DCB_TX_PB 1024
2855 * ixgbe_dcb_hw_configure - Enable DCB and configure
2856 * general DCB in VT mode and non-VT mode parameters
2857 * @dev: pointer to rte_eth_dev structure
2858 * @dcb_config: pointer to ixgbe_dcb_config structure
2861 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2862 struct ixgbe_dcb_config *dcb_config)
2865 uint8_t i,pfc_en,nb_tcs;
2867 uint8_t config_dcb_rx = 0;
2868 uint8_t config_dcb_tx = 0;
2869 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2870 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2871 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2872 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2873 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2874 struct ixgbe_dcb_tc_config *tc;
2875 uint32_t max_frame = dev->data->max_frame_size;
2876 struct ixgbe_hw *hw =
2877 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2879 switch(dev->data->dev_conf.rxmode.mq_mode){
2880 case ETH_MQ_RX_VMDQ_DCB:
2881 dcb_config->vt_mode = true;
2882 if (hw->mac.type != ixgbe_mac_82598EB) {
2883 config_dcb_rx = DCB_RX_CONFIG;
2885 *get dcb and VT rx configuration parameters
2888 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2889 /*Configure general VMDQ and DCB RX parameters*/
2890 ixgbe_vmdq_dcb_configure(dev);
2894 dcb_config->vt_mode = false;
2895 config_dcb_rx = DCB_RX_CONFIG;
2896 /* Get dcb TX configuration parameters from rte_eth_conf */
2897 ixgbe_dcb_rx_config(dev,dcb_config);
2898 /*Configure general DCB RX parameters*/
2899 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2902 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration\n");
2905 switch (dev->data->dev_conf.txmode.mq_mode) {
2906 case ETH_MQ_TX_VMDQ_DCB:
2907 dcb_config->vt_mode = true;
2908 config_dcb_tx = DCB_TX_CONFIG;
2909 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2910 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2911 /*Configure general VMDQ and DCB TX parameters*/
2912 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2916 dcb_config->vt_mode = false;
2917 config_dcb_tx = DCB_TX_CONFIG;
2918 /*get DCB TX configuration parameters from rte_eth_conf*/
2919 ixgbe_dcb_tx_config(dev,dcb_config);
2920 /*Configure general DCB TX parameters*/
2921 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2924 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration\n");
2928 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2930 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2931 if(nb_tcs == ETH_4_TCS) {
2932 /* Avoid un-configured priority mapping to TC0 */
2934 uint8_t mask = 0xFF;
2935 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
2936 mask = (uint8_t)(mask & (~ (1 << map[i])));
2937 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
2938 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
2942 /* Re-configure 4 TCs BW */
2943 for (i = 0; i < nb_tcs; i++) {
2944 tc = &dcb_config->tc_config[i];
2945 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
2946 (uint8_t)(100 / nb_tcs);
2947 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
2948 (uint8_t)(100 / nb_tcs);
2950 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2951 tc = &dcb_config->tc_config[i];
2952 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
2953 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
2958 /* Set RX buffer size */
2959 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2960 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
2961 for (i = 0 ; i < nb_tcs; i++) {
2962 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2964 /* zero alloc all unused TCs */
2965 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2966 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
2970 /* Only support an equally distributed Tx packet buffer strategy. */
2971 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
2972 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
2973 for (i = 0; i < nb_tcs; i++) {
2974 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
2975 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
2977 /* Clear unused TCs, if any, to zero buffer size*/
2978 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2979 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
2980 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
2984 /*Calculates traffic class credits*/
2985 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2986 IXGBE_DCB_TX_CONFIG);
2987 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2988 IXGBE_DCB_RX_CONFIG);
2991 /* Unpack CEE standard containers */
2992 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
2993 ixgbe_dcb_unpack_max_cee(dcb_config, max);
2994 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
2995 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
2996 /* Configure PG(ETS) RX */
2997 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3001 /* Unpack CEE standard containers */
3002 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3003 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3004 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3005 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3006 /* Configure PG(ETS) TX */
3007 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3010 /*Configure queue statistics registers*/
3011 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3013 /* Check if the PFC is supported */
3014 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3015 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3016 for (i = 0; i < nb_tcs; i++) {
3018 * If the TC count is 8,and the default high_water is 48,
3019 * the low_water is 16 as default.
3021 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3022 hw->fc.low_water[i] = pbsize / 4;
3023 /* Enable pfc for this TC */
3024 tc = &dcb_config->tc_config[i];
3025 tc->pfc = ixgbe_dcb_pfc_enabled;
3027 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3028 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3030 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3037 * ixgbe_configure_dcb - Configure DCB Hardware
3038 * @dev: pointer to rte_eth_dev
3040 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3042 struct ixgbe_dcb_config *dcb_cfg =
3043 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3044 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3046 PMD_INIT_FUNC_TRACE();
3048 /* check support mq_mode for DCB */
3049 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3050 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3053 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3056 /** Configure DCB hardware **/
3057 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3063 * VMDq only support for 10 GbE NIC.
3066 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3068 struct rte_eth_vmdq_rx_conf *cfg;
3069 struct ixgbe_hw *hw;
3070 enum rte_eth_nb_pools num_pools;
3071 uint32_t mrqc, vt_ctl, vlanctrl;
3074 PMD_INIT_FUNC_TRACE();
3075 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3076 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3077 num_pools = cfg->nb_queue_pools;
3079 ixgbe_rss_disable(dev);
3081 /* MRQC: enable vmdq */
3082 mrqc = IXGBE_MRQC_VMDQEN;
3083 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3085 /* PFVTCTL: turn on virtualisation and set the default pool */
3086 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3087 if (cfg->enable_default_pool)
3088 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3090 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3092 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3094 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3095 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3096 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3097 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3099 /* VFTA - enable all vlan filters */
3100 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3101 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3103 /* VFRE: pool enabling for receive - 64 */
3104 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3105 if (num_pools == ETH_64_POOLS)
3106 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3109 * MPSAR - allow pools to read specific mac addresses
3110 * In this case, all pools should be able to read from mac addr 0
3112 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3113 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3115 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3116 for (i = 0; i < cfg->nb_pool_maps; i++) {
3117 /* set vlan id in VF register and set the valid bit */
3118 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3119 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3121 * Put the allowed pools in VFB reg. As we only have 16 or 64
3122 * pools, we only need to use the first half of the register
3125 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3126 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3127 (cfg->pool_map[i].pools & UINT32_MAX));
3129 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3130 ((cfg->pool_map[i].pools >> 32) \
3135 IXGBE_WRITE_FLUSH(hw);
3139 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3140 * @hw: pointer to hardware structure
3143 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3148 PMD_INIT_FUNC_TRACE();
3149 /*PF VF Transmit Enable*/
3150 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3151 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3153 /* Disable the Tx desc arbiter so that MTQC can be changed */
3154 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3155 reg |= IXGBE_RTTDCS_ARBDIS;
3156 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3158 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3159 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3161 /* Disable drop for all queues */
3162 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3163 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3164 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3166 /* Enable the Tx desc arbiter */
3167 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3168 reg &= ~IXGBE_RTTDCS_ARBDIS;
3169 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3171 IXGBE_WRITE_FLUSH(hw);
3177 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
3179 struct igb_rx_entry *rxe = rxq->sw_ring;
3183 /* Initialize software ring entries */
3184 for (i = 0; i < rxq->nb_rx_desc; i++) {
3185 volatile union ixgbe_adv_rx_desc *rxd;
3186 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3188 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u\n",
3189 (unsigned) rxq->queue_id);
3193 rte_mbuf_refcnt_set(mbuf, 1);
3194 mbuf->type = RTE_MBUF_PKT;
3195 mbuf->pkt.next = NULL;
3196 mbuf->pkt.data = (char *)mbuf->buf_addr + RTE_PKTMBUF_HEADROOM;
3197 mbuf->pkt.nb_segs = 1;
3198 mbuf->pkt.in_port = rxq->port_id;
3201 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3202 rxd = &rxq->rx_ring[i];
3203 rxd->read.hdr_addr = dma_addr;
3204 rxd->read.pkt_addr = dma_addr;
3212 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3214 struct ixgbe_hw *hw =
3215 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3217 if (hw->mac.type == ixgbe_mac_82598EB)
3220 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3222 * SRIOV inactive scheme
3223 * any DCB/RSS w/o VMDq multi-queue setting
3225 switch (dev->data->dev_conf.rxmode.mq_mode) {
3227 ixgbe_rss_configure(dev);
3230 case ETH_MQ_RX_VMDQ_DCB:
3231 ixgbe_vmdq_dcb_configure(dev);
3234 case ETH_MQ_RX_VMDQ_ONLY:
3235 ixgbe_vmdq_rx_hw_configure(dev);
3238 case ETH_MQ_RX_NONE:
3239 /* if mq_mode is none, disable rss mode.*/
3240 default: ixgbe_rss_disable(dev);
3243 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3245 * SRIOV active scheme
3246 * FIXME if support DCB/RSS together with VMDq & SRIOV
3249 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQEN);
3253 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT4TCEN);
3257 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT8TCEN);
3260 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3268 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3270 struct ixgbe_hw *hw =
3271 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3275 if (hw->mac.type == ixgbe_mac_82598EB)
3278 /* disable arbiter before setting MTQC */
3279 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3280 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3281 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3283 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3285 * SRIOV inactive scheme
3286 * any DCB w/o VMDq multi-queue setting
3288 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3289 ixgbe_vmdq_tx_hw_configure(hw);
3291 mtqc = IXGBE_MTQC_64Q_1PB;
3292 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3295 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3298 * SRIOV active scheme
3299 * FIXME if support DCB together with VMDq & SRIOV
3302 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3305 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3308 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3312 mtqc = IXGBE_MTQC_64Q_1PB;
3313 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3315 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3318 /* re-enable arbiter */
3319 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3320 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3326 * Initializes Receive Unit.
3329 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3331 struct ixgbe_hw *hw;
3332 struct igb_rx_queue *rxq;
3333 struct rte_pktmbuf_pool_private *mbp_priv;
3346 PMD_INIT_FUNC_TRACE();
3347 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3350 * Make sure receives are disabled while setting
3351 * up the RX context (registers, descriptor rings, etc.).
3353 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3354 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3356 /* Enable receipt of broadcasted frames */
3357 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3358 fctrl |= IXGBE_FCTRL_BAM;
3359 fctrl |= IXGBE_FCTRL_DPF;
3360 fctrl |= IXGBE_FCTRL_PMCF;
3361 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3364 * Configure CRC stripping, if any.
3366 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3367 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3368 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3370 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3373 * Configure jumbo frame support, if any.
3375 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3376 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3377 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3378 maxfrs &= 0x0000FFFF;
3379 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3380 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3382 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3385 * If loopback mode is configured for 82599, set LPBK bit.
3387 if (hw->mac.type == ixgbe_mac_82599EB &&
3388 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3389 hlreg0 |= IXGBE_HLREG0_LPBK;
3391 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3393 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3395 /* Setup RX queues */
3396 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3397 rxq = dev->data->rx_queues[i];
3399 /* Allocate buffers for descriptor rings */
3400 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3405 * Reset crc_len in case it was changed after queue setup by a
3406 * call to configure.
3408 rxq->crc_len = (uint8_t)
3409 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3412 /* Setup the Base and Length of the Rx Descriptor Rings */
3413 bus_addr = rxq->rx_ring_phys_addr;
3414 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3415 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3416 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3417 (uint32_t)(bus_addr >> 32));
3418 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3419 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3420 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3421 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3423 /* Configure the SRRCTL register */
3424 #ifdef RTE_HEADER_SPLIT_ENABLE
3426 * Configure Header Split
3428 if (dev->data->dev_conf.rxmode.header_split) {
3429 if (hw->mac.type == ixgbe_mac_82599EB) {
3430 /* Must setup the PSRTYPE register */
3432 psrtype = IXGBE_PSRTYPE_TCPHDR |
3433 IXGBE_PSRTYPE_UDPHDR |
3434 IXGBE_PSRTYPE_IPV4HDR |
3435 IXGBE_PSRTYPE_IPV6HDR;
3436 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3438 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3439 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3440 IXGBE_SRRCTL_BSIZEHDR_MASK);
3441 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3444 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3446 /* Set if packets are dropped when no descriptors available */
3448 srrctl |= IXGBE_SRRCTL_DROP_EN;
3451 * Configure the RX buffer size in the BSIZEPACKET field of
3452 * the SRRCTL register of the queue.
3453 * The value is in 1 KB resolution. Valid values can be from
3456 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3457 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3458 RTE_PKTMBUF_HEADROOM);
3459 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3460 IXGBE_SRRCTL_BSIZEPKT_MASK);
3461 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3463 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3464 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3466 /* It adds dual VLAN length for supporting dual VLAN */
3467 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3468 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3469 dev->data->scattered_rx = 1;
3470 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3475 * Device configured with multiple RX queues.
3477 ixgbe_dev_mq_rx_configure(dev);
3480 * Setup the Checksum Register.
3481 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3482 * Enable IP/L4 checkum computation by hardware if requested to do so.
3484 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3485 rxcsum |= IXGBE_RXCSUM_PCSD;
3486 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3487 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3489 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3491 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3493 if (hw->mac.type == ixgbe_mac_82599EB) {
3494 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3495 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3496 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3498 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3499 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3500 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3507 * Initializes Transmit Unit.
3510 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3512 struct ixgbe_hw *hw;
3513 struct igb_tx_queue *txq;
3519 PMD_INIT_FUNC_TRACE();
3520 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3522 /* Enable TX CRC (checksum offload requirement) */
3523 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3524 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
3525 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3527 /* Setup the Base and Length of the Tx Descriptor Rings */
3528 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3529 txq = dev->data->tx_queues[i];
3531 bus_addr = txq->tx_ring_phys_addr;
3532 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3533 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3534 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3535 (uint32_t)(bus_addr >> 32));
3536 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3537 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3538 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3539 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3540 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3543 * Disable Tx Head Writeback RO bit, since this hoses
3544 * bookkeeping if things aren't delivered in order.
3546 switch (hw->mac.type) {
3547 case ixgbe_mac_82598EB:
3548 txctrl = IXGBE_READ_REG(hw,
3549 IXGBE_DCA_TXCTRL(txq->reg_idx));
3550 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3551 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3555 case ixgbe_mac_82599EB:
3556 case ixgbe_mac_X540:
3558 txctrl = IXGBE_READ_REG(hw,
3559 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3560 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3561 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3567 /* Device configured with multiple TX queues. */
3568 ixgbe_dev_mq_tx_configure(dev);
3572 * Set up link for 82599 loopback mode Tx->Rx.
3575 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3577 DEBUGFUNC("ixgbe_setup_loopback_link_82599");
3579 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3580 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3582 PMD_INIT_LOG(ERR, "Could not enable loopback mode\n");
3591 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3592 ixgbe_reset_pipeline_82599(hw);
3594 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3600 * Start Transmit and Receive Units.
3603 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3605 struct ixgbe_hw *hw;
3606 struct igb_tx_queue *txq;
3607 struct igb_rx_queue *rxq;
3615 PMD_INIT_FUNC_TRACE();
3616 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3618 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3619 txq = dev->data->tx_queues[i];
3620 /* Setup Transmit Threshold Registers */
3621 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3622 txdctl |= txq->pthresh & 0x7F;
3623 txdctl |= ((txq->hthresh & 0x7F) << 8);
3624 txdctl |= ((txq->wthresh & 0x7F) << 16);
3625 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3628 if (hw->mac.type != ixgbe_mac_82598EB) {
3629 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3630 dmatxctl |= IXGBE_DMATXCTL_TE;
3631 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3634 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3635 txq = dev->data->tx_queues[i];
3636 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3637 txdctl |= IXGBE_TXDCTL_ENABLE;
3638 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3640 /* Wait until TX Enable ready */
3641 if (hw->mac.type == ixgbe_mac_82599EB) {
3645 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3646 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3648 PMD_INIT_LOG(ERR, "Could not enable "
3649 "Tx Queue %d\n", i);
3652 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3653 rxq = dev->data->rx_queues[i];
3654 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3655 rxdctl |= IXGBE_RXDCTL_ENABLE;
3656 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3658 /* Wait until RX Enable ready */
3662 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3663 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3665 PMD_INIT_LOG(ERR, "Could not enable "
3666 "Rx Queue %d\n", i);
3668 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3671 /* Enable Receive engine */
3672 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3673 if (hw->mac.type == ixgbe_mac_82598EB)
3674 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3675 rxctrl |= IXGBE_RXCTRL_RXEN;
3676 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3678 /* If loopback mode is enabled for 82599, set up the link accordingly */
3679 if (hw->mac.type == ixgbe_mac_82599EB &&
3680 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3681 ixgbe_setup_loopback_link_82599(hw);
3687 * [VF] Initializes Receive Unit.
3690 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3692 struct ixgbe_hw *hw;
3693 struct igb_rx_queue *rxq;
3694 struct rte_pktmbuf_pool_private *mbp_priv;
3701 PMD_INIT_FUNC_TRACE();
3702 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3705 ixgbevf_rlpml_set_vf(hw,
3706 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
3708 /* Setup RX queues */
3709 dev->rx_pkt_burst = ixgbe_recv_pkts;
3710 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3711 rxq = dev->data->rx_queues[i];
3713 /* Allocate buffers for descriptor rings */
3714 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3718 /* Setup the Base and Length of the Rx Descriptor Rings */
3719 bus_addr = rxq->rx_ring_phys_addr;
3721 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3722 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3723 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3724 (uint32_t)(bus_addr >> 32));
3725 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3726 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3727 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3728 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3731 /* Configure the SRRCTL register */
3732 #ifdef RTE_HEADER_SPLIT_ENABLE
3734 * Configure Header Split
3736 if (dev->data->dev_conf.rxmode.header_split) {
3738 /* Must setup the PSRTYPE register */
3740 psrtype = IXGBE_PSRTYPE_TCPHDR |
3741 IXGBE_PSRTYPE_UDPHDR |
3742 IXGBE_PSRTYPE_IPV4HDR |
3743 IXGBE_PSRTYPE_IPV6HDR;
3745 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
3747 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3748 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3749 IXGBE_SRRCTL_BSIZEHDR_MASK);
3750 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3753 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3755 /* Set if packets are dropped when no descriptors available */
3757 srrctl |= IXGBE_SRRCTL_DROP_EN;
3760 * Configure the RX buffer size in the BSIZEPACKET field of
3761 * the SRRCTL register of the queue.
3762 * The value is in 1 KB resolution. Valid values can be from
3765 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3766 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3767 RTE_PKTMBUF_HEADROOM);
3768 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3769 IXGBE_SRRCTL_BSIZEPKT_MASK);
3772 * VF modification to write virtual function SRRCTL register
3774 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
3776 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3777 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3779 /* It adds dual VLAN length for supporting dual VLAN */
3780 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3781 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
3782 dev->data->scattered_rx = 1;
3783 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3791 * [VF] Initializes Transmit Unit.
3794 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
3796 struct ixgbe_hw *hw;
3797 struct igb_tx_queue *txq;
3802 PMD_INIT_FUNC_TRACE();
3803 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3805 /* Setup the Base and Length of the Tx Descriptor Rings */
3806 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3807 txq = dev->data->tx_queues[i];
3808 bus_addr = txq->tx_ring_phys_addr;
3809 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
3810 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3811 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
3812 (uint32_t)(bus_addr >> 32));
3813 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
3814 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3815 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3816 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
3817 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
3820 * Disable Tx Head Writeback RO bit, since this hoses
3821 * bookkeeping if things aren't delivered in order.
3823 txctrl = IXGBE_READ_REG(hw,
3824 IXGBE_VFDCA_TXCTRL(i));
3825 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3826 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
3832 * [VF] Start Transmit and Receive Units.
3835 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
3837 struct ixgbe_hw *hw;
3838 struct igb_tx_queue *txq;
3839 struct igb_rx_queue *rxq;
3845 PMD_INIT_FUNC_TRACE();
3846 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3848 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3849 txq = dev->data->tx_queues[i];
3850 /* Setup Transmit Threshold Registers */
3851 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3852 txdctl |= txq->pthresh & 0x7F;
3853 txdctl |= ((txq->hthresh & 0x7F) << 8);
3854 txdctl |= ((txq->wthresh & 0x7F) << 16);
3855 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
3858 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3860 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3861 txdctl |= IXGBE_TXDCTL_ENABLE;
3862 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
3865 /* Wait until TX Enable ready */
3868 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3869 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3871 PMD_INIT_LOG(ERR, "Could not enable "
3872 "Tx Queue %d\n", i);
3874 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3876 rxq = dev->data->rx_queues[i];
3878 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
3879 rxdctl |= IXGBE_RXDCTL_ENABLE;
3880 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
3882 /* Wait until RX Enable ready */
3886 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
3887 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3889 PMD_INIT_LOG(ERR, "Could not enable "
3890 "Rx Queue %d\n", i);
3892 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);