4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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34 #include <sys/queue.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
47 #include <rte_cycles.h>
49 #include <rte_debug.h>
50 #include <rte_interrupts.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_launch.h>
55 #include <rte_tailq.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
82 #define RTE_PMD_IXGBE_TX_MAX_BURST 32
84 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
85 #define RTE_PMD_IXGBE_RX_MAX_BURST 32
88 static inline struct rte_mbuf *
89 rte_rxmbuf_alloc(struct rte_mempool *mp)
93 m = __rte_mbuf_raw_alloc(mp);
94 __rte_mbuf_sanity_check_raw(m, RTE_MBUF_PKT, 0);
98 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
99 (uint64_t) ((mb)->buf_physaddr + (uint64_t)((char *)((mb)->pkt.data) - \
100 (char *)(mb)->buf_addr))
102 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
103 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
106 * Structure associated with each descriptor of the RX ring of a RX queue.
108 struct igb_rx_entry {
109 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
113 * Structure associated with each descriptor of the TX ring of a TX queue.
115 struct igb_tx_entry {
116 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
117 uint16_t next_id; /**< Index of next descriptor in ring. */
118 uint16_t last_id; /**< Index of last scattered descriptor. */
122 * Structure associated with each RX queue.
124 struct igb_rx_queue {
125 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
126 volatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
127 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
128 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
129 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
130 struct igb_rx_entry *sw_ring; /**< address of RX software ring. */
131 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
132 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
133 uint16_t nb_rx_desc; /**< number of RX descriptors. */
134 uint16_t rx_tail; /**< current value of RDT register. */
135 uint16_t nb_rx_hold; /**< number of held free RX desc. */
136 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
137 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
138 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
139 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
141 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
142 uint16_t queue_id; /**< RX queue index. */
143 uint16_t reg_idx; /**< RX queue register index. */
144 uint8_t port_id; /**< Device port identifier. */
145 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
146 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
147 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
148 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */
149 struct rte_mbuf fake_mbuf;
150 /** hold packets to return to application */
151 struct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2];
156 * IXGBE CTX Constants
158 enum ixgbe_advctx_num {
159 IXGBE_CTX_0 = 0, /**< CTX0 */
160 IXGBE_CTX_1 = 1, /**< CTX1 */
161 IXGBE_CTX_NUM = 2, /**< CTX NUMBER */
165 * Structure to check if new context need be built
168 struct ixgbe_advctx_info {
169 uint16_t flags; /**< ol_flags for context build. */
170 uint32_t cmp_mask; /**< compare mask for vlan_macip_lens */
171 union rte_vlan_macip vlan_macip_lens; /**< vlan, mac ip length. */
175 * Structure associated with each TX queue.
177 struct igb_tx_queue {
178 /** TX ring virtual address. */
179 volatile union ixgbe_adv_tx_desc *tx_ring;
180 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
181 struct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */
182 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
183 uint16_t nb_tx_desc; /**< number of TX descriptors. */
184 uint16_t tx_tail; /**< current value of TDT reg. */
185 uint16_t tx_free_thresh;/**< minimum TX before freeing. */
186 /** Number of TX descriptors to use before RS bit is set. */
187 uint16_t tx_rs_thresh;
188 /** Number of TX descriptors used since RS bit was set. */
190 /** Index to last TX descriptor to have been cleaned. */
191 uint16_t last_desc_cleaned;
192 /** Total number of TX descriptors ready to be allocated. */
194 uint16_t tx_next_dd; /**< next desc to scan for DD bit */
195 uint16_t tx_next_rs; /**< next desc to set RS bit */
196 uint16_t queue_id; /**< TX queue index. */
197 uint16_t reg_idx; /**< TX queue register index. */
198 uint8_t port_id; /**< Device port identifier. */
199 uint8_t pthresh; /**< Prefetch threshold register. */
200 uint8_t hthresh; /**< Host threshold register. */
201 uint8_t wthresh; /**< Write-back threshold reg. */
202 uint32_t txq_flags; /**< Holds flags for this TXq */
203 uint32_t ctx_curr; /**< Hardware context states. */
204 /** Hardware context0 history. */
205 struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM];
210 #define RTE_PMD_USE_PREFETCH
213 #ifdef RTE_PMD_USE_PREFETCH
215 * Prefetch a cache line into all cache levels.
217 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
219 #define rte_ixgbe_prefetch(p) do {} while(0)
222 #ifdef RTE_PMD_PACKET_PREFETCH
223 #define rte_packet_prefetch(p) rte_prefetch1(p)
225 #define rte_packet_prefetch(p) do {} while(0)
228 /*********************************************************************
232 **********************************************************************/
235 * The "simple" TX queue functions require that the following
236 * flags are set when the TX queue is configured:
237 * - ETH_TXQ_FLAGS_NOMULTSEGS
238 * - ETH_TXQ_FLAGS_NOVLANOFFL
239 * - ETH_TXQ_FLAGS_NOXSUMSCTP
240 * - ETH_TXQ_FLAGS_NOXSUMUDP
241 * - ETH_TXQ_FLAGS_NOXSUMTCP
242 * and that the RS bit threshold (tx_rs_thresh) is at least equal to
243 * RTE_PMD_IXGBE_TX_MAX_BURST.
245 #define IXGBE_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
246 ETH_TXQ_FLAGS_NOOFFLOADS)
249 * Check for descriptors with their DD bit set and free mbufs.
250 * Return the total number of buffers freed.
252 static inline int __attribute__((always_inline))
253 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
255 struct igb_tx_entry *txep;
259 /* check DD bit on threshold descriptor */
260 status = txq->tx_ring[txq->tx_next_dd].wb.status;
261 if (! (status & IXGBE_ADVTXD_STAT_DD))
265 * first buffer to free from S/W ring is at index
266 * tx_next_dd - (tx_rs_thresh-1)
268 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
270 /* prefetch the mbufs that are about to be freed */
271 for (i = 0; i < txq->tx_rs_thresh; ++i)
272 rte_prefetch0((txep + i)->mbuf);
274 /* free buffers one at a time */
275 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
276 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
277 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
281 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
282 rte_pktmbuf_free_seg(txep->mbuf);
287 /* buffers were freed, update counters */
288 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
289 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
290 if (txq->tx_next_dd >= txq->nb_tx_desc)
291 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
293 return txq->tx_rs_thresh;
297 * Populate descriptors with the following info:
298 * 1.) buffer_addr = phys_addr + headroom
299 * 2.) cmd_type_len = DCMD_DTYP_FLAGS | pkt_len
300 * 3.) olinfo_status = pkt_len << PAYLEN_SHIFT
303 /* Defines for Tx descriptor */
304 #define DCMD_DTYP_FLAGS (IXGBE_ADVTXD_DTYP_DATA |\
305 IXGBE_ADVTXD_DCMD_IFCS |\
306 IXGBE_ADVTXD_DCMD_DEXT |\
307 IXGBE_ADVTXD_DCMD_EOP)
309 /* Populate 4 descriptors with data from 4 mbufs */
311 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
313 uint64_t buf_dma_addr;
317 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
318 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
319 pkt_len = (*pkts)->pkt.data_len;
321 /* write data to descriptor */
322 txdp->read.buffer_addr = buf_dma_addr;
323 txdp->read.cmd_type_len =
324 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
325 txdp->read.olinfo_status =
326 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
330 /* Populate 1 descriptor with data from 1 mbuf */
332 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
334 uint64_t buf_dma_addr;
337 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
338 pkt_len = (*pkts)->pkt.data_len;
340 /* write data to descriptor */
341 txdp->read.buffer_addr = buf_dma_addr;
342 txdp->read.cmd_type_len =
343 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
344 txdp->read.olinfo_status =
345 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
349 * Fill H/W descriptor ring with mbuf data.
350 * Copy mbuf pointers to the S/W ring.
353 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
356 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
357 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
358 const int N_PER_LOOP = 4;
359 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
360 int mainpart, leftover;
364 * Process most of the packets in chunks of N pkts. Any
365 * leftover packets will get processed one at a time.
367 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
368 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
369 for (i = 0; i < mainpart; i += N_PER_LOOP) {
370 /* Copy N mbuf pointers to the S/W ring */
371 for (j = 0; j < N_PER_LOOP; ++j) {
372 (txep + i + j)->mbuf = *(pkts + i + j);
374 tx4(txdp + i, pkts + i);
377 if (unlikely(leftover > 0)) {
378 for (i = 0; i < leftover; ++i) {
379 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
380 tx1(txdp + mainpart + i, pkts + mainpart + i);
385 static inline uint16_t
386 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
389 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
390 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
394 * Begin scanning the H/W ring for done descriptors when the
395 * number of available descriptors drops below tx_free_thresh. For
396 * each done descriptor, free the associated buffer.
398 if (txq->nb_tx_free < txq->tx_free_thresh)
399 ixgbe_tx_free_bufs(txq);
401 /* Only use descriptors that are available */
402 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
403 if (unlikely(nb_pkts == 0))
406 /* Use exactly nb_pkts descriptors */
407 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
410 * At this point, we know there are enough descriptors in the
411 * ring to transmit all the packets. This assumes that each
412 * mbuf contains a single segment, and that no new offloads
413 * are expected, which would require a new context descriptor.
417 * See if we're going to wrap-around. If so, handle the top
418 * of the descriptor ring first, then do the bottom. If not,
419 * the processing looks just like the "bottom" part anyway...
421 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
422 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
423 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
426 * We know that the last descriptor in the ring will need to
427 * have its RS bit set because tx_rs_thresh has to be
428 * a divisor of the ring size
430 tx_r[txq->tx_next_rs].read.cmd_type_len |=
431 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
432 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
437 /* Fill H/W descriptor ring with mbuf data */
438 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
439 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
442 * Determine if RS bit should be set
443 * This is what we actually want:
444 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
445 * but instead of subtracting 1 and doing >=, we can just do
446 * greater than without subtracting.
448 if (txq->tx_tail > txq->tx_next_rs) {
449 tx_r[txq->tx_next_rs].read.cmd_type_len |=
450 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
451 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
453 if (txq->tx_next_rs >= txq->nb_tx_desc)
454 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
458 * Check for wrap-around. This would only happen if we used
459 * up to the last descriptor in the ring, no more, no less.
461 if (txq->tx_tail >= txq->nb_tx_desc)
464 /* update tail pointer */
466 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
472 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
477 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
478 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
479 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
481 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
485 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
486 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
487 nb_tx = (uint16_t)(nb_tx + ret);
488 nb_pkts = (uint16_t)(nb_pkts - ret);
497 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
498 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
499 uint16_t ol_flags, uint32_t vlan_macip_lens)
501 uint32_t type_tucmd_mlhl;
502 uint32_t mss_l4len_idx;
506 ctx_idx = txq->ctx_curr;
510 if (ol_flags & PKT_TX_VLAN_PKT) {
511 cmp_mask |= TX_VLAN_CMP_MASK;
514 if (ol_flags & PKT_TX_IP_CKSUM) {
515 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
516 cmp_mask |= TX_MAC_LEN_CMP_MASK;
519 /* Specify which HW CTX to upload. */
520 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
521 switch (ol_flags & PKT_TX_L4_MASK) {
522 case PKT_TX_UDP_CKSUM:
523 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
524 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
525 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
526 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
528 case PKT_TX_TCP_CKSUM:
529 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
530 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
531 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
532 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
534 case PKT_TX_SCTP_CKSUM:
535 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
536 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
537 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
538 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
541 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
542 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
546 txq->ctx_cache[ctx_idx].flags = ol_flags;
547 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
548 txq->ctx_cache[ctx_idx].vlan_macip_lens.data =
549 vlan_macip_lens & cmp_mask;
551 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
552 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
553 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
554 ctx_txd->seqnum_seed = 0;
558 * Check which hardware context can be used. Use the existing match
559 * or create a new context descriptor.
561 static inline uint32_t
562 what_advctx_update(struct igb_tx_queue *txq, uint16_t flags,
563 uint32_t vlan_macip_lens)
565 /* If match with the current used context */
566 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
567 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
568 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
569 return txq->ctx_curr;
572 /* What if match with the next context */
574 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
575 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
576 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
577 return txq->ctx_curr;
580 /* Mismatch, use the previous context */
581 return (IXGBE_CTX_NUM);
584 static inline uint32_t
585 tx_desc_cksum_flags_to_olinfo(uint16_t ol_flags)
587 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
588 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
591 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
592 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
596 static inline uint32_t
597 tx_desc_vlan_flags_to_cmdtype(uint16_t ol_flags)
599 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
600 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
603 /* Default RS bit threshold values */
604 #ifndef DEFAULT_TX_RS_THRESH
605 #define DEFAULT_TX_RS_THRESH 32
607 #ifndef DEFAULT_TX_FREE_THRESH
608 #define DEFAULT_TX_FREE_THRESH 32
611 /* Reset transmit descriptors after they have been used */
613 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
615 struct igb_tx_entry *sw_ring = txq->sw_ring;
616 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
617 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
618 uint16_t nb_tx_desc = txq->nb_tx_desc;
619 uint16_t desc_to_clean_to;
620 uint16_t nb_tx_to_clean;
622 /* Determine the last descriptor needing to be cleaned */
623 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
624 if (desc_to_clean_to >= nb_tx_desc)
625 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
627 /* Check to make sure the last descriptor to clean is done */
628 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
629 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
631 PMD_TX_FREE_LOG(DEBUG,
632 "TX descriptor %4u is not done"
633 "(port=%d queue=%d)",
635 txq->port_id, txq->queue_id);
636 /* Failed to clean any descriptors, better luck next time */
640 /* Figure out how many descriptors will be cleaned */
641 if (last_desc_cleaned > desc_to_clean_to)
642 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
645 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
648 PMD_TX_FREE_LOG(DEBUG,
649 "Cleaning %4u TX descriptors: %4u to %4u "
650 "(port=%d queue=%d)",
651 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
652 txq->port_id, txq->queue_id);
655 * The last descriptor to clean is done, so that means all the
656 * descriptors from the last descriptor that was cleaned
657 * up to the last descriptor with the RS bit set
658 * are done. Only reset the threshold descriptor.
660 txr[desc_to_clean_to].wb.status = 0;
662 /* Update the txq to reflect the last descriptor that was cleaned */
663 txq->last_desc_cleaned = desc_to_clean_to;
664 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
671 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
674 struct igb_tx_queue *txq;
675 struct igb_tx_entry *sw_ring;
676 struct igb_tx_entry *txe, *txn;
677 volatile union ixgbe_adv_tx_desc *txr;
678 volatile union ixgbe_adv_tx_desc *txd;
679 struct rte_mbuf *tx_pkt;
680 struct rte_mbuf *m_seg;
681 uint64_t buf_dma_addr;
682 uint32_t olinfo_status;
683 uint32_t cmd_type_len;
692 uint32_t vlan_macip_lens;
697 sw_ring = txq->sw_ring;
699 tx_id = txq->tx_tail;
700 txe = &sw_ring[tx_id];
702 /* Determine if the descriptor ring needs to be cleaned. */
703 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
704 ixgbe_xmit_cleanup(txq);
708 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
711 pkt_len = tx_pkt->pkt.pkt_len;
713 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
716 * Determine how many (if any) context descriptors
717 * are needed for offload functionality.
719 ol_flags = tx_pkt->ol_flags;
720 vlan_macip_lens = tx_pkt->pkt.vlan_macip.data;
722 /* If hardware offload required */
723 tx_ol_req = (uint16_t)(ol_flags & PKT_TX_OFFLOAD_MASK);
725 /* If new context need be built or reuse the exist ctx. */
726 ctx = what_advctx_update(txq, tx_ol_req,
728 /* Only allocate context descriptor if required*/
729 new_ctx = (ctx == IXGBE_CTX_NUM);
734 * Keep track of how many descriptors are used this loop
735 * This will always be the number of segments + the number of
736 * Context descriptors required to transmit the packet
738 nb_used = (uint16_t)(tx_pkt->pkt.nb_segs + new_ctx);
741 * The number of descriptors that must be allocated for a
742 * packet is the number of segments of that packet, plus 1
743 * Context Descriptor for the hardware offload, if any.
744 * Determine the last TX descriptor to allocate in the TX ring
745 * for the packet, starting from the current position (tx_id)
748 tx_last = (uint16_t) (tx_id + nb_used - 1);
751 if (tx_last >= txq->nb_tx_desc)
752 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
754 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
755 " tx_first=%u tx_last=%u\n",
756 (unsigned) txq->port_id,
757 (unsigned) txq->queue_id,
763 * Make sure there are enough TX descriptors available to
764 * transmit the entire packet.
765 * nb_used better be less than or equal to txq->tx_rs_thresh
767 if (nb_used > txq->nb_tx_free) {
768 PMD_TX_FREE_LOG(DEBUG,
769 "Not enough free TX descriptors "
770 "nb_used=%4u nb_free=%4u "
771 "(port=%d queue=%d)",
772 nb_used, txq->nb_tx_free,
773 txq->port_id, txq->queue_id);
775 if (ixgbe_xmit_cleanup(txq) != 0) {
776 /* Could not clean any descriptors */
782 /* nb_used better be <= txq->tx_rs_thresh */
783 if (unlikely(nb_used > txq->tx_rs_thresh)) {
784 PMD_TX_FREE_LOG(DEBUG,
785 "The number of descriptors needed to "
786 "transmit the packet exceeds the "
787 "RS bit threshold. This will impact "
789 "nb_used=%4u nb_free=%4u "
791 "(port=%d queue=%d)",
792 nb_used, txq->nb_tx_free,
794 txq->port_id, txq->queue_id);
796 * Loop here until there are enough TX
797 * descriptors or until the ring cannot be
800 while (nb_used > txq->nb_tx_free) {
801 if (ixgbe_xmit_cleanup(txq) != 0) {
803 * Could not clean any
815 * By now there are enough free TX descriptors to transmit
820 * Set common flags of all TX Data Descriptors.
822 * The following bits must be set in all Data Descriptors:
823 * - IXGBE_ADVTXD_DTYP_DATA
824 * - IXGBE_ADVTXD_DCMD_DEXT
826 * The following bits must be set in the first Data Descriptor
827 * and are ignored in the other ones:
828 * - IXGBE_ADVTXD_DCMD_IFCS
829 * - IXGBE_ADVTXD_MAC_1588
830 * - IXGBE_ADVTXD_DCMD_VLE
832 * The following bits must only be set in the last Data
834 * - IXGBE_TXD_CMD_EOP
836 * The following bits can be set in any Data Descriptor, but
837 * are only set in the last Data Descriptor:
840 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
841 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
842 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
843 #ifdef RTE_LIBRTE_IEEE1588
844 if (ol_flags & PKT_TX_IEEE1588_TMST)
845 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
850 * Setup the TX Advanced Context Descriptor if required
853 volatile struct ixgbe_adv_tx_context_desc *
856 ctx_txd = (volatile struct
857 ixgbe_adv_tx_context_desc *)
860 txn = &sw_ring[txe->next_id];
861 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
863 if (txe->mbuf != NULL) {
864 rte_pktmbuf_free_seg(txe->mbuf);
868 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
871 txe->last_id = tx_last;
872 tx_id = txe->next_id;
877 * Setup the TX Advanced Data Descriptor,
878 * This path will go through
879 * whatever new/reuse the context descriptor
881 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
882 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
883 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
889 txn = &sw_ring[txe->next_id];
891 if (txe->mbuf != NULL)
892 rte_pktmbuf_free_seg(txe->mbuf);
896 * Set up Transmit Data Descriptor.
898 slen = m_seg->pkt.data_len;
899 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
900 txd->read.buffer_addr =
901 rte_cpu_to_le_64(buf_dma_addr);
902 txd->read.cmd_type_len =
903 rte_cpu_to_le_32(cmd_type_len | slen);
904 txd->read.olinfo_status =
905 rte_cpu_to_le_32(olinfo_status);
906 txe->last_id = tx_last;
907 tx_id = txe->next_id;
909 m_seg = m_seg->pkt.next;
910 } while (m_seg != NULL);
913 * The last packet data descriptor needs End Of Packet (EOP)
915 cmd_type_len |= IXGBE_TXD_CMD_EOP;
916 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
917 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
919 /* Set RS bit only on threshold packets' last descriptor */
920 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
921 PMD_TX_FREE_LOG(DEBUG,
922 "Setting RS bit on TXD id="
923 "%4u (port=%d queue=%d)",
924 tx_last, txq->port_id, txq->queue_id);
926 cmd_type_len |= IXGBE_TXD_CMD_RS;
928 /* Update txq RS bit counters */
931 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
937 * Set the Transmit Descriptor Tail (TDT)
939 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
940 (unsigned) txq->port_id, (unsigned) txq->queue_id,
941 (unsigned) tx_id, (unsigned) nb_tx);
942 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
943 txq->tx_tail = tx_id;
948 /*********************************************************************
952 **********************************************************************/
953 static inline uint16_t
954 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
958 static uint16_t ip_pkt_types_map[16] = {
959 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
960 PKT_RX_IPV6_HDR, 0, 0, 0,
961 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
962 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
965 static uint16_t ip_rss_types_map[16] = {
966 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
967 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
968 PKT_RX_RSS_HASH, 0, 0, 0,
969 0, 0, 0, PKT_RX_FDIR,
972 #ifdef RTE_LIBRTE_IEEE1588
973 static uint32_t ip_pkt_etqf_map[8] = {
974 0, 0, 0, PKT_RX_IEEE1588_PTP,
978 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
979 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
980 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
982 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
983 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
986 return (uint16_t)(pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF]);
989 static inline uint16_t
990 rx_desc_status_to_pkt_flags(uint32_t rx_status)
995 * Check if VLAN present only.
996 * Do not check whether L3/L4 rx checksum done by NIC or not,
997 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
999 pkt_flags = (uint16_t)((rx_status & IXGBE_RXD_STAT_VP) ?
1000 PKT_RX_VLAN_PKT : 0);
1002 #ifdef RTE_LIBRTE_IEEE1588
1003 if (rx_status & IXGBE_RXD_STAT_TMST)
1004 pkt_flags = (uint16_t)(pkt_flags | PKT_RX_IEEE1588_TMST);
1009 static inline uint16_t
1010 rx_desc_error_to_pkt_flags(uint32_t rx_status)
1013 * Bit 31: IPE, IPv4 checksum error
1014 * Bit 30: L4I, L4I integrity error
1016 static uint16_t error_to_pkt_flags_map[4] = {
1017 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
1018 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1020 return error_to_pkt_flags_map[(rx_status >>
1021 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1024 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1026 * LOOK_AHEAD defines how many desc statuses to check beyond the
1027 * current descriptor.
1028 * It must be a pound define for optimal performance.
1029 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1030 * function only works with LOOK_AHEAD=8.
1032 #define LOOK_AHEAD 8
1033 #if (LOOK_AHEAD != 8)
1034 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1037 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
1039 volatile union ixgbe_adv_rx_desc *rxdp;
1040 struct igb_rx_entry *rxep;
1041 struct rte_mbuf *mb;
1043 int s[LOOK_AHEAD], nb_dd;
1044 int i, j, nb_rx = 0;
1047 /* get references to current descriptor and S/W ring entry */
1048 rxdp = &rxq->rx_ring[rxq->rx_tail];
1049 rxep = &rxq->sw_ring[rxq->rx_tail];
1051 /* check to make sure there is at least 1 packet to receive */
1052 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
1056 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1057 * reference packets that are ready to be received.
1059 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1060 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
1062 /* Read desc statuses backwards to avoid race condition */
1063 for (j = LOOK_AHEAD-1; j >= 0; --j)
1064 s[j] = rxdp[j].wb.upper.status_error;
1066 /* Compute how many status bits were set */
1068 for (j = 0; j < LOOK_AHEAD; ++j)
1069 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
1073 /* Translate descriptor info to mbuf format */
1074 for (j = 0; j < nb_dd; ++j) {
1076 pkt_len = (uint16_t)(rxdp[j].wb.upper.length -
1078 mb->pkt.data_len = pkt_len;
1079 mb->pkt.pkt_len = pkt_len;
1080 mb->pkt.vlan_macip.f.vlan_tci = rxdp[j].wb.upper.vlan;
1081 mb->pkt.hash.rss = rxdp[j].wb.lower.hi_dword.rss;
1083 /* convert descriptor fields to rte mbuf flags */
1084 mb->ol_flags = rx_desc_hlen_type_rss_to_pkt_flags(
1085 rxdp[j].wb.lower.lo_dword.data);
1086 /* reuse status field from scan list */
1087 mb->ol_flags = (uint16_t)(mb->ol_flags |
1088 rx_desc_status_to_pkt_flags(s[j]));
1089 mb->ol_flags = (uint16_t)(mb->ol_flags |
1090 rx_desc_error_to_pkt_flags(s[j]));
1093 /* Move mbuf pointers from the S/W ring to the stage */
1094 for (j = 0; j < LOOK_AHEAD; ++j) {
1095 rxq->rx_stage[i + j] = rxep[j].mbuf;
1098 /* stop if all requested packets could not be received */
1099 if (nb_dd != LOOK_AHEAD)
1103 /* clear software ring entries so we can cleanup correctly */
1104 for (i = 0; i < nb_rx; ++i) {
1105 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1113 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
1115 volatile union ixgbe_adv_rx_desc *rxdp;
1116 struct igb_rx_entry *rxep;
1117 struct rte_mbuf *mb;
1122 /* allocate buffers in bulk directly into the S/W ring */
1123 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1124 (rxq->rx_free_thresh - 1));
1125 rxep = &rxq->sw_ring[alloc_idx];
1126 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1127 rxq->rx_free_thresh);
1128 if (unlikely(diag != 0))
1131 rxdp = &rxq->rx_ring[alloc_idx];
1132 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1133 /* populate the static rte mbuf fields */
1135 rte_mbuf_refcnt_set(mb, 1);
1136 mb->type = RTE_MBUF_PKT;
1137 mb->pkt.next = NULL;
1138 mb->pkt.data = (char *)mb->buf_addr + RTE_PKTMBUF_HEADROOM;
1139 mb->pkt.nb_segs = 1;
1140 mb->pkt.in_port = rxq->port_id;
1142 /* populate the descriptors */
1143 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1144 rxdp[i].read.hdr_addr = dma_addr;
1145 rxdp[i].read.pkt_addr = dma_addr;
1148 /* update tail pointer */
1150 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1152 /* update state of internal queue structure */
1153 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1154 rxq->rx_free_thresh);
1155 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1156 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1162 static inline uint16_t
1163 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1166 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1169 /* how many packets are ready to return? */
1170 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1172 /* copy mbuf pointers to the application's packet list */
1173 for (i = 0; i < nb_pkts; ++i)
1174 rx_pkts[i] = stage[i];
1176 /* update internal queue state */
1177 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1178 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1183 static inline uint16_t
1184 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1187 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1190 /* Any previously recv'd pkts will be returned from the Rx stage */
1191 if (rxq->rx_nb_avail)
1192 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1194 /* Scan the H/W ring for packets to receive */
1195 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1197 /* update internal queue state */
1198 rxq->rx_next_avail = 0;
1199 rxq->rx_nb_avail = nb_rx;
1200 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1202 /* if required, allocate new buffers to replenish descriptors */
1203 if (rxq->rx_tail > rxq->rx_free_trigger) {
1204 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1206 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1207 "queue_id=%u\n", (unsigned) rxq->port_id,
1208 (unsigned) rxq->queue_id);
1210 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1211 rxq->rx_free_thresh;
1214 * Need to rewind any previous receives if we cannot
1215 * allocate new buffers to replenish the old ones.
1217 rxq->rx_nb_avail = 0;
1218 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1219 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1220 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1226 if (rxq->rx_tail >= rxq->nb_rx_desc)
1229 /* received any packets this loop? */
1230 if (rxq->rx_nb_avail)
1231 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1236 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1238 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1243 if (unlikely(nb_pkts == 0))
1246 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1247 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1249 /* request is relatively large, chunk it up */
1253 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1254 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1255 nb_rx = (uint16_t)(nb_rx + ret);
1256 nb_pkts = (uint16_t)(nb_pkts - ret);
1263 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1266 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1269 struct igb_rx_queue *rxq;
1270 volatile union ixgbe_adv_rx_desc *rx_ring;
1271 volatile union ixgbe_adv_rx_desc *rxdp;
1272 struct igb_rx_entry *sw_ring;
1273 struct igb_rx_entry *rxe;
1274 struct rte_mbuf *rxm;
1275 struct rte_mbuf *nmb;
1276 union ixgbe_adv_rx_desc rxd;
1279 uint32_t hlen_type_rss;
1289 rx_id = rxq->rx_tail;
1290 rx_ring = rxq->rx_ring;
1291 sw_ring = rxq->sw_ring;
1292 while (nb_rx < nb_pkts) {
1294 * The order of operations here is important as the DD status
1295 * bit must not be read after any other descriptor fields.
1296 * rx_ring and rxdp are pointing to volatile data so the order
1297 * of accesses cannot be reordered by the compiler. If they were
1298 * not volatile, they could be reordered which could lead to
1299 * using invalid descriptor fields when read from rxd.
1301 rxdp = &rx_ring[rx_id];
1302 staterr = rxdp->wb.upper.status_error;
1303 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1310 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1311 * is likely to be invalid and to be dropped by the various
1312 * validation checks performed by the network stack.
1314 * Allocate a new mbuf to replenish the RX ring descriptor.
1315 * If the allocation fails:
1316 * - arrange for that RX descriptor to be the first one
1317 * being parsed the next time the receive function is
1318 * invoked [on the same queue].
1320 * - Stop parsing the RX ring and return immediately.
1322 * This policy do not drop the packet received in the RX
1323 * descriptor for which the allocation of a new mbuf failed.
1324 * Thus, it allows that packet to be later retrieved if
1325 * mbuf have been freed in the mean time.
1326 * As a side effect, holding RX descriptors instead of
1327 * systematically giving them back to the NIC may lead to
1328 * RX ring exhaustion situations.
1329 * However, the NIC can gracefully prevent such situations
1330 * to happen by sending specific "back-pressure" flow control
1331 * frames to its peer(s).
1333 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1334 "ext_err_stat=0x%08x pkt_len=%u\n",
1335 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1336 (unsigned) rx_id, (unsigned) staterr,
1337 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1339 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1341 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1342 "queue_id=%u\n", (unsigned) rxq->port_id,
1343 (unsigned) rxq->queue_id);
1344 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1349 rxe = &sw_ring[rx_id];
1351 if (rx_id == rxq->nb_rx_desc)
1354 /* Prefetch next mbuf while processing current one. */
1355 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1358 * When next RX descriptor is on a cache-line boundary,
1359 * prefetch the next 4 RX descriptors and the next 8 pointers
1362 if ((rx_id & 0x3) == 0) {
1363 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1364 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1370 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1371 rxdp->read.hdr_addr = dma_addr;
1372 rxdp->read.pkt_addr = dma_addr;
1375 * Initialize the returned mbuf.
1376 * 1) setup generic mbuf fields:
1377 * - number of segments,
1380 * - RX port identifier.
1381 * 2) integrate hardware offload data, if any:
1382 * - RSS flag & hash,
1383 * - IP checksum flag,
1384 * - VLAN TCI, if any,
1387 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1389 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1390 rte_packet_prefetch(rxm->pkt.data);
1391 rxm->pkt.nb_segs = 1;
1392 rxm->pkt.next = NULL;
1393 rxm->pkt.pkt_len = pkt_len;
1394 rxm->pkt.data_len = pkt_len;
1395 rxm->pkt.in_port = rxq->port_id;
1397 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1398 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1399 rxm->pkt.vlan_macip.f.vlan_tci =
1400 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1402 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1403 pkt_flags = (uint16_t)(pkt_flags |
1404 rx_desc_status_to_pkt_flags(staterr));
1405 pkt_flags = (uint16_t)(pkt_flags |
1406 rx_desc_error_to_pkt_flags(staterr));
1407 rxm->ol_flags = pkt_flags;
1409 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1410 rxm->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1411 else if (pkt_flags & PKT_RX_FDIR) {
1412 rxm->pkt.hash.fdir.hash =
1413 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1414 & IXGBE_ATR_HASH_MASK);
1415 rxm->pkt.hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1418 * Store the mbuf address into the next entry of the array
1419 * of returned packets.
1421 rx_pkts[nb_rx++] = rxm;
1423 rxq->rx_tail = rx_id;
1426 * If the number of free RX descriptors is greater than the RX free
1427 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1429 * Update the RDT with the value of the last processed RX descriptor
1430 * minus 1, to guarantee that the RDT register is never equal to the
1431 * RDH register, which creates a "full" ring situtation from the
1432 * hardware point of view...
1434 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1435 if (nb_hold > rxq->rx_free_thresh) {
1436 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1437 "nb_hold=%u nb_rx=%u\n",
1438 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1439 (unsigned) rx_id, (unsigned) nb_hold,
1441 rx_id = (uint16_t) ((rx_id == 0) ?
1442 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1443 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1446 rxq->nb_rx_hold = nb_hold;
1451 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1454 struct igb_rx_queue *rxq;
1455 volatile union ixgbe_adv_rx_desc *rx_ring;
1456 volatile union ixgbe_adv_rx_desc *rxdp;
1457 struct igb_rx_entry *sw_ring;
1458 struct igb_rx_entry *rxe;
1459 struct rte_mbuf *first_seg;
1460 struct rte_mbuf *last_seg;
1461 struct rte_mbuf *rxm;
1462 struct rte_mbuf *nmb;
1463 union ixgbe_adv_rx_desc rxd;
1464 uint64_t dma; /* Physical address of mbuf data buffer */
1466 uint32_t hlen_type_rss;
1476 rx_id = rxq->rx_tail;
1477 rx_ring = rxq->rx_ring;
1478 sw_ring = rxq->sw_ring;
1481 * Retrieve RX context of current packet, if any.
1483 first_seg = rxq->pkt_first_seg;
1484 last_seg = rxq->pkt_last_seg;
1486 while (nb_rx < nb_pkts) {
1489 * The order of operations here is important as the DD status
1490 * bit must not be read after any other descriptor fields.
1491 * rx_ring and rxdp are pointing to volatile data so the order
1492 * of accesses cannot be reordered by the compiler. If they were
1493 * not volatile, they could be reordered which could lead to
1494 * using invalid descriptor fields when read from rxd.
1496 rxdp = &rx_ring[rx_id];
1497 staterr = rxdp->wb.upper.status_error;
1498 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1505 * Allocate a new mbuf to replenish the RX ring descriptor.
1506 * If the allocation fails:
1507 * - arrange for that RX descriptor to be the first one
1508 * being parsed the next time the receive function is
1509 * invoked [on the same queue].
1511 * - Stop parsing the RX ring and return immediately.
1513 * This policy does not drop the packet received in the RX
1514 * descriptor for which the allocation of a new mbuf failed.
1515 * Thus, it allows that packet to be later retrieved if
1516 * mbuf have been freed in the mean time.
1517 * As a side effect, holding RX descriptors instead of
1518 * systematically giving them back to the NIC may lead to
1519 * RX ring exhaustion situations.
1520 * However, the NIC can gracefully prevent such situations
1521 * to happen by sending specific "back-pressure" flow control
1522 * frames to its peer(s).
1524 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
1525 "staterr=0x%x data_len=%u\n",
1526 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1527 (unsigned) rx_id, (unsigned) staterr,
1528 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1530 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1532 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1533 "queue_id=%u\n", (unsigned) rxq->port_id,
1534 (unsigned) rxq->queue_id);
1535 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1540 rxe = &sw_ring[rx_id];
1542 if (rx_id == rxq->nb_rx_desc)
1545 /* Prefetch next mbuf while processing current one. */
1546 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1549 * When next RX descriptor is on a cache-line boundary,
1550 * prefetch the next 4 RX descriptors and the next 8 pointers
1553 if ((rx_id & 0x3) == 0) {
1554 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1555 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1559 * Update RX descriptor with the physical address of the new
1560 * data buffer of the new allocated mbuf.
1564 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1565 rxdp->read.hdr_addr = dma;
1566 rxdp->read.pkt_addr = dma;
1569 * Set data length & data buffer address of mbuf.
1571 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1572 rxm->pkt.data_len = data_len;
1573 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1576 * If this is the first buffer of the received packet,
1577 * set the pointer to the first mbuf of the packet and
1578 * initialize its context.
1579 * Otherwise, update the total length and the number of segments
1580 * of the current scattered packet, and update the pointer to
1581 * the last mbuf of the current packet.
1583 if (first_seg == NULL) {
1585 first_seg->pkt.pkt_len = data_len;
1586 first_seg->pkt.nb_segs = 1;
1588 first_seg->pkt.pkt_len = (uint16_t)(first_seg->pkt.pkt_len
1590 first_seg->pkt.nb_segs++;
1591 last_seg->pkt.next = rxm;
1595 * If this is not the last buffer of the received packet,
1596 * update the pointer to the last mbuf of the current scattered
1597 * packet and continue to parse the RX ring.
1599 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1605 * This is the last buffer of the received packet.
1606 * If the CRC is not stripped by the hardware:
1607 * - Subtract the CRC length from the total packet length.
1608 * - If the last buffer only contains the whole CRC or a part
1609 * of it, free the mbuf associated to the last buffer.
1610 * If part of the CRC is also contained in the previous
1611 * mbuf, subtract the length of that CRC part from the
1612 * data length of the previous mbuf.
1614 rxm->pkt.next = NULL;
1615 if (unlikely(rxq->crc_len > 0)) {
1616 first_seg->pkt.pkt_len -= ETHER_CRC_LEN;
1617 if (data_len <= ETHER_CRC_LEN) {
1618 rte_pktmbuf_free_seg(rxm);
1619 first_seg->pkt.nb_segs--;
1620 last_seg->pkt.data_len = (uint16_t)
1621 (last_seg->pkt.data_len -
1622 (ETHER_CRC_LEN - data_len));
1623 last_seg->pkt.next = NULL;
1626 (uint16_t) (data_len - ETHER_CRC_LEN);
1630 * Initialize the first mbuf of the returned packet:
1631 * - RX port identifier,
1632 * - hardware offload data, if any:
1633 * - RSS flag & hash,
1634 * - IP checksum flag,
1635 * - VLAN TCI, if any,
1638 first_seg->pkt.in_port = rxq->port_id;
1641 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1642 * set in the pkt_flags field.
1644 first_seg->pkt.vlan_macip.f.vlan_tci =
1645 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1646 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1647 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1648 pkt_flags = (uint16_t)(pkt_flags |
1649 rx_desc_status_to_pkt_flags(staterr));
1650 pkt_flags = (uint16_t)(pkt_flags |
1651 rx_desc_error_to_pkt_flags(staterr));
1652 first_seg->ol_flags = pkt_flags;
1654 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1655 first_seg->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1656 else if (pkt_flags & PKT_RX_FDIR) {
1657 first_seg->pkt.hash.fdir.hash =
1658 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1659 & IXGBE_ATR_HASH_MASK);
1660 first_seg->pkt.hash.fdir.id =
1661 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1664 /* Prefetch data of first segment, if configured to do so. */
1665 rte_packet_prefetch(first_seg->pkt.data);
1668 * Store the mbuf address into the next entry of the array
1669 * of returned packets.
1671 rx_pkts[nb_rx++] = first_seg;
1674 * Setup receipt context for a new packet.
1680 * Record index of the next RX descriptor to probe.
1682 rxq->rx_tail = rx_id;
1685 * Save receive context.
1687 rxq->pkt_first_seg = first_seg;
1688 rxq->pkt_last_seg = last_seg;
1691 * If the number of free RX descriptors is greater than the RX free
1692 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1694 * Update the RDT with the value of the last processed RX descriptor
1695 * minus 1, to guarantee that the RDT register is never equal to the
1696 * RDH register, which creates a "full" ring situtation from the
1697 * hardware point of view...
1699 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1700 if (nb_hold > rxq->rx_free_thresh) {
1701 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1702 "nb_hold=%u nb_rx=%u\n",
1703 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1704 (unsigned) rx_id, (unsigned) nb_hold,
1706 rx_id = (uint16_t) ((rx_id == 0) ?
1707 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1708 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1711 rxq->nb_rx_hold = nb_hold;
1715 /*********************************************************************
1717 * Queue management functions
1719 **********************************************************************/
1722 * Rings setup and release.
1724 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1725 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1726 * also optimize cache line size effect. H/W supports up to cache line size 128.
1728 #define IXGBE_ALIGN 128
1731 * Maximum number of Ring Descriptors.
1733 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1734 * descriptors should meet the following condition:
1735 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1737 #define IXGBE_MIN_RING_DESC 64
1738 #define IXGBE_MAX_RING_DESC 4096
1741 * Create memzone for HW rings. malloc can't be used as the physical address is
1742 * needed. If the memzone is already created, then this function returns a ptr
1745 static const struct rte_memzone *
1746 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1747 uint16_t queue_id, uint32_t ring_size, int socket_id)
1749 char z_name[RTE_MEMZONE_NAMESIZE];
1750 const struct rte_memzone *mz;
1752 rte_snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1753 dev->driver->pci_drv.name, ring_name,
1754 dev->data->port_id, queue_id);
1756 mz = rte_memzone_lookup(z_name);
1760 #ifdef RTE_LIBRTE_XEN_DOM0
1761 return rte_memzone_reserve_bounded(z_name, ring_size,
1762 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1764 return rte_memzone_reserve_aligned(z_name, ring_size,
1765 socket_id, 0, IXGBE_ALIGN);
1770 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1774 if (txq->sw_ring != NULL) {
1775 for (i = 0; i < txq->nb_tx_desc; i++) {
1776 if (txq->sw_ring[i].mbuf != NULL) {
1777 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1778 txq->sw_ring[i].mbuf = NULL;
1785 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1788 ixgbe_tx_queue_release_mbufs(txq);
1789 rte_free(txq->sw_ring);
1795 ixgbe_dev_tx_queue_release(void *txq)
1797 ixgbe_tx_queue_release(txq);
1800 /* (Re)set dynamic igb_tx_queue fields to defaults */
1802 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1804 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1806 struct igb_tx_entry *txe = txq->sw_ring;
1809 /* Zero out HW ring memory */
1810 for (i = 0; i < txq->nb_tx_desc; i++) {
1811 txq->tx_ring[i] = zeroed_desc;
1814 /* Initialize SW ring entries */
1815 prev = (uint16_t) (txq->nb_tx_desc - 1);
1816 for (i = 0; i < txq->nb_tx_desc; i++) {
1817 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1818 txd->wb.status = IXGBE_TXD_STAT_DD;
1820 txe[i].last_id = (uint16_t)i;
1821 txe[prev].next_id = (uint16_t)i;
1825 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1826 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1829 txq->nb_tx_used = 0;
1831 * Always allow 1 descriptor to be un-allocated to avoid
1832 * a H/W race condition
1834 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1835 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1837 memset((void*)&txq->ctx_cache, 0,
1838 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1842 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1845 unsigned int socket_id,
1846 const struct rte_eth_txconf *tx_conf)
1848 const struct rte_memzone *tz;
1849 struct igb_tx_queue *txq;
1850 struct ixgbe_hw *hw;
1851 uint16_t tx_rs_thresh, tx_free_thresh;
1853 PMD_INIT_FUNC_TRACE();
1854 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1857 * Validate number of transmit descriptors.
1858 * It must not exceed hardware maximum, and must be multiple
1861 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1862 (nb_desc > IXGBE_MAX_RING_DESC) ||
1863 (nb_desc < IXGBE_MIN_RING_DESC)) {
1868 * The following two parameters control the setting of the RS bit on
1869 * transmit descriptors.
1870 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1871 * descriptors have been used.
1872 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1873 * descriptors are used or if the number of descriptors required
1874 * to transmit a packet is greater than the number of free TX
1876 * The following constraints must be satisfied:
1877 * tx_rs_thresh must be greater than 0.
1878 * tx_rs_thresh must be less than the size of the ring minus 2.
1879 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1880 * tx_rs_thresh must be a divisor of the ring size.
1881 * tx_free_thresh must be greater than 0.
1882 * tx_free_thresh must be less than the size of the ring minus 3.
1883 * One descriptor in the TX ring is used as a sentinel to avoid a
1884 * H/W race condition, hence the maximum threshold constraints.
1885 * When set to zero use default values.
1887 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1888 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1889 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1890 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1891 if (tx_rs_thresh >= (nb_desc - 2)) {
1892 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the number "
1893 "of TX descriptors minus 2. (tx_rs_thresh=%u port=%d "
1894 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1895 (int)dev->data->port_id, (int)queue_idx);
1898 if (tx_free_thresh >= (nb_desc - 3)) {
1899 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the "
1900 "tx_free_thresh must be less than the number of TX "
1901 "descriptors minus 3. (tx_free_thresh=%u port=%d "
1902 "queue=%d)\n", (unsigned int)tx_free_thresh,
1903 (int)dev->data->port_id, (int)queue_idx);
1906 if (tx_rs_thresh > tx_free_thresh) {
1907 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than or equal to "
1908 "tx_free_thresh. (tx_free_thresh=%u tx_rs_thresh=%u "
1909 "port=%d queue=%d)\n", (unsigned int)tx_free_thresh,
1910 (unsigned int)tx_rs_thresh, (int)dev->data->port_id,
1914 if ((nb_desc % tx_rs_thresh) != 0) {
1915 RTE_LOG(ERR, PMD, "tx_rs_thresh must be a divisor of the "
1916 "number of TX descriptors. (tx_rs_thresh=%u port=%d "
1917 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1918 (int)dev->data->port_id, (int)queue_idx);
1923 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1924 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1925 * by the NIC and all descriptors are written back after the NIC
1926 * accumulates WTHRESH descriptors.
1928 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1929 RTE_LOG(ERR, PMD, "TX WTHRESH must be set to 0 if "
1930 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1931 "port=%d queue=%d)\n", (unsigned int)tx_rs_thresh,
1932 (int)dev->data->port_id, (int)queue_idx);
1936 /* Free memory prior to re-allocation if needed... */
1937 if (dev->data->tx_queues[queue_idx] != NULL)
1938 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1940 /* First allocate the tx queue data structure */
1941 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct igb_tx_queue),
1942 CACHE_LINE_SIZE, socket_id);
1947 * Allocate TX ring hardware descriptors. A memzone large enough to
1948 * handle the maximum ring size is allocated in order to allow for
1949 * resizing in later calls to the queue setup function.
1951 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1952 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1955 ixgbe_tx_queue_release(txq);
1959 txq->nb_tx_desc = nb_desc;
1960 txq->tx_rs_thresh = tx_rs_thresh;
1961 txq->tx_free_thresh = tx_free_thresh;
1962 txq->pthresh = tx_conf->tx_thresh.pthresh;
1963 txq->hthresh = tx_conf->tx_thresh.hthresh;
1964 txq->wthresh = tx_conf->tx_thresh.wthresh;
1965 txq->queue_id = queue_idx;
1966 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1967 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1968 txq->port_id = dev->data->port_id;
1969 txq->txq_flags = tx_conf->txq_flags;
1972 * Modification to set VFTDT for virtual function if vf is detected
1974 if (hw->mac.type == ixgbe_mac_82599_vf)
1975 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1977 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1978 #ifndef RTE_LIBRTE_XEN_DOM0
1979 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1981 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1983 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1985 /* Allocate software ring */
1986 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1987 sizeof(struct igb_tx_entry) * nb_desc,
1988 CACHE_LINE_SIZE, socket_id);
1989 if (txq->sw_ring == NULL) {
1990 ixgbe_tx_queue_release(txq);
1993 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1994 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1996 ixgbe_reset_tx_queue(txq);
1998 dev->data->tx_queues[queue_idx] = txq;
2000 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2001 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
2002 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
2003 PMD_INIT_LOG(INFO, "Using simple tx code path\n");
2004 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
2006 PMD_INIT_LOG(INFO, "Using full-featured tx code path\n");
2007 PMD_INIT_LOG(INFO, " - txq_flags = %lx [IXGBE_SIMPLE_FLAGS=%lx]\n", (long unsigned)txq->txq_flags, (long unsigned)IXGBE_SIMPLE_FLAGS);
2008 PMD_INIT_LOG(INFO, " - tx_rs_thresh = %lu [RTE_PMD_IXGBE_TX_MAX_BURST=%lu]\n", (long unsigned)txq->tx_rs_thresh, (long unsigned)RTE_PMD_IXGBE_TX_MAX_BURST);
2009 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2016 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
2020 if (rxq->sw_ring != NULL) {
2021 for (i = 0; i < rxq->nb_rx_desc; i++) {
2022 if (rxq->sw_ring[i].mbuf != NULL) {
2023 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2024 rxq->sw_ring[i].mbuf = NULL;
2027 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2028 if (rxq->rx_nb_avail) {
2029 for (i = 0; i < rxq->rx_nb_avail; ++i) {
2030 struct rte_mbuf *mb;
2031 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2032 rte_pktmbuf_free_seg(mb);
2034 rxq->rx_nb_avail = 0;
2041 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
2044 ixgbe_rx_queue_release_mbufs(rxq);
2045 rte_free(rxq->sw_ring);
2051 ixgbe_dev_rx_queue_release(void *rxq)
2053 ixgbe_rx_queue_release(rxq);
2057 * Check if Rx Burst Bulk Alloc function can be used.
2059 * 0: the preconditions are satisfied and the bulk allocation function
2061 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2062 * function must be used.
2065 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2066 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
2068 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct igb_rx_queue *rxq)
2074 * Make sure the following pre-conditions are satisfied:
2075 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2076 * rxq->rx_free_thresh < rxq->nb_rx_desc
2077 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2078 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2079 * Scattered packets are not supported. This should be checked
2080 * outside of this function.
2082 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2083 if (! (rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST))
2085 else if (! (rxq->rx_free_thresh < rxq->nb_rx_desc))
2087 else if (! ((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0))
2089 else if (! (rxq->nb_rx_desc <
2090 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST)))
2099 /* Reset dynamic igb_rx_queue fields back to defaults */
2101 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
2103 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
2109 * By default, the Rx queue setup function allocates enough memory for
2110 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2111 * extra memory at the end of the descriptor ring to be zero'd out. A
2112 * pre-condition for using the Rx burst bulk alloc function is that the
2113 * number of descriptors is less than or equal to
2114 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2115 * constraints here to see if we need to zero out memory after the end
2116 * of the H/W descriptor ring.
2118 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2119 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2120 /* zero out extra memory */
2121 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2124 /* do not zero out extra memory */
2125 len = rxq->nb_rx_desc;
2128 * Zero out HW ring memory. Zero out extra memory at the end of
2129 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2130 * reads extra memory as zeros.
2132 for (i = 0; i < len; i++) {
2133 rxq->rx_ring[i] = zeroed_desc;
2136 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2138 * initialize extra software ring entries. Space for these extra
2139 * entries is always allocated
2141 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2142 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2143 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2146 rxq->rx_nb_avail = 0;
2147 rxq->rx_next_avail = 0;
2148 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2149 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2151 rxq->nb_rx_hold = 0;
2152 rxq->pkt_first_seg = NULL;
2153 rxq->pkt_last_seg = NULL;
2157 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2160 unsigned int socket_id,
2161 const struct rte_eth_rxconf *rx_conf,
2162 struct rte_mempool *mp)
2164 const struct rte_memzone *rz;
2165 struct igb_rx_queue *rxq;
2166 struct ixgbe_hw *hw;
2167 int use_def_burst_func = 1;
2170 PMD_INIT_FUNC_TRACE();
2171 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2174 * Validate number of receive descriptors.
2175 * It must not exceed hardware maximum, and must be multiple
2178 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2179 (nb_desc > IXGBE_MAX_RING_DESC) ||
2180 (nb_desc < IXGBE_MIN_RING_DESC)) {
2184 /* Free memory prior to re-allocation if needed... */
2185 if (dev->data->rx_queues[queue_idx] != NULL)
2186 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2188 /* First allocate the rx queue data structure */
2189 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct igb_rx_queue),
2190 CACHE_LINE_SIZE, socket_id);
2194 rxq->nb_rx_desc = nb_desc;
2195 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2196 rxq->queue_id = queue_idx;
2197 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2198 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2199 rxq->port_id = dev->data->port_id;
2200 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2202 rxq->drop_en = rx_conf->rx_drop_en;
2205 * Allocate RX ring hardware descriptors. A memzone large enough to
2206 * handle the maximum ring size is allocated in order to allow for
2207 * resizing in later calls to the queue setup function.
2209 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2210 IXGBE_MAX_RING_DESC * sizeof(union ixgbe_adv_rx_desc),
2213 ixgbe_rx_queue_release(rxq);
2217 * Modified to setup VFRDT for Virtual Function
2219 if (hw->mac.type == ixgbe_mac_82599_vf) {
2221 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2223 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2227 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2229 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2231 #ifndef RTE_LIBRTE_XEN_DOM0
2232 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2234 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2236 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2239 * Allocate software ring. Allow for space at the end of the
2240 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2241 * function does not access an invalid memory region.
2243 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2244 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2248 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2249 sizeof(struct igb_rx_entry) * len,
2250 CACHE_LINE_SIZE, socket_id);
2251 if (rxq->sw_ring == NULL) {
2252 ixgbe_rx_queue_release(rxq);
2255 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
2256 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2259 * Certain constaints must be met in order to use the bulk buffer
2260 * allocation Rx burst function.
2262 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2264 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2265 if (!use_def_burst_func && !dev->data->scattered_rx) {
2266 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2267 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2268 "satisfied. Rx Burst Bulk Alloc function will be "
2269 "used on port=%d, queue=%d.\n",
2270 rxq->port_id, rxq->queue_id);
2271 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2274 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2275 "are not satisfied, Scattered Rx is requested, "
2276 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2277 "enabled (port=%d, queue=%d).\n",
2278 rxq->port_id, rxq->queue_id);
2280 dev->data->rx_queues[queue_idx] = rxq;
2282 ixgbe_reset_rx_queue(rxq);
2288 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2290 #define IXGBE_RXQ_SCAN_INTERVAL 4
2291 volatile union ixgbe_adv_rx_desc *rxdp;
2292 struct igb_rx_queue *rxq;
2295 if (rx_queue_id >= dev->data->nb_rx_queues) {
2296 PMD_RX_LOG(ERR, "Invalid RX queue id=%d\n", rx_queue_id);
2300 rxq = dev->data->rx_queues[rx_queue_id];
2301 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2303 while ((desc < rxq->nb_rx_desc) &&
2304 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2305 desc += IXGBE_RXQ_SCAN_INTERVAL;
2306 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2307 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2308 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2309 desc - rxq->nb_rx_desc]);
2316 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2318 volatile union ixgbe_adv_rx_desc *rxdp;
2319 struct igb_rx_queue *rxq = rx_queue;
2322 if (unlikely(offset >= rxq->nb_rx_desc))
2324 desc = rxq->rx_tail + offset;
2325 if (desc >= rxq->nb_rx_desc)
2326 desc -= rxq->nb_rx_desc;
2328 rxdp = &rxq->rx_ring[desc];
2329 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2333 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2337 PMD_INIT_FUNC_TRACE();
2339 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2340 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2342 ixgbe_tx_queue_release_mbufs(txq);
2343 ixgbe_reset_tx_queue(txq);
2347 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2348 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2350 ixgbe_rx_queue_release_mbufs(rxq);
2351 ixgbe_reset_rx_queue(rxq);
2356 /*********************************************************************
2358 * Device RX/TX init functions
2360 **********************************************************************/
2363 * Receive Side Scaling (RSS)
2364 * See section 7.1.2.8 in the following document:
2365 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2368 * The source and destination IP addresses of the IP header and the source
2369 * and destination ports of TCP/UDP headers, if any, of received packets are
2370 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2371 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2372 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2373 * RSS output index which is used as the RX queue index where to store the
2375 * The following output is supplied in the RX write-back descriptor:
2376 * - 32-bit result of the Microsoft RSS hash function,
2377 * - 4-bit RSS type field.
2381 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2382 * Used as the default key.
2384 static uint8_t rss_intel_key[40] = {
2385 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2386 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2387 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2388 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2389 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2393 ixgbe_rss_disable(struct rte_eth_dev *dev)
2395 struct ixgbe_hw *hw;
2398 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2399 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2400 mrqc &= ~IXGBE_MRQC_RSSEN;
2401 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2405 ixgbe_rss_configure(struct rte_eth_dev *dev)
2407 struct ixgbe_hw *hw;
2416 PMD_INIT_FUNC_TRACE();
2417 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2419 rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
2420 if (rss_hf == 0) { /* Disable RSS */
2421 ixgbe_rss_disable(dev);
2424 hash_key = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key;
2425 if (hash_key == NULL)
2426 hash_key = rss_intel_key; /* Default hash key */
2428 /* Fill in RSS hash key */
2429 for (i = 0; i < 10; i++) {
2430 rss_key = hash_key[(i * 4)];
2431 rss_key |= hash_key[(i * 4) + 1] << 8;
2432 rss_key |= hash_key[(i * 4) + 2] << 16;
2433 rss_key |= hash_key[(i * 4) + 3] << 24;
2434 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2437 /* Fill in redirection table */
2439 for (i = 0, j = 0; i < 128; i++, j++) {
2440 if (j == dev->data->nb_rx_queues) j = 0;
2441 reta = (reta << 8) | j;
2443 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), rte_bswap32(reta));
2446 /* Set configured hashing functions in MRQC register */
2447 mrqc = IXGBE_MRQC_RSSEN; /* RSS enable */
2448 if (rss_hf & ETH_RSS_IPV4)
2449 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2450 if (rss_hf & ETH_RSS_IPV4_TCP)
2451 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2452 if (rss_hf & ETH_RSS_IPV6)
2453 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2454 if (rss_hf & ETH_RSS_IPV6_EX)
2455 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2456 if (rss_hf & ETH_RSS_IPV6_TCP)
2457 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2458 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2459 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2460 if (rss_hf & ETH_RSS_IPV4_UDP)
2461 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2462 if (rss_hf & ETH_RSS_IPV6_UDP)
2463 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2464 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2465 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2466 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2469 #define NUM_VFTA_REGISTERS 128
2470 #define NIC_RX_BUFFER_SIZE 0x200
2473 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2475 struct rte_eth_vmdq_dcb_conf *cfg;
2476 struct ixgbe_hw *hw;
2477 enum rte_eth_nb_pools num_pools;
2478 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2480 uint8_t nb_tcs; /* number of traffic classes */
2483 PMD_INIT_FUNC_TRACE();
2484 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2485 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2486 num_pools = cfg->nb_queue_pools;
2487 /* Check we have a valid number of pools */
2488 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2489 ixgbe_rss_disable(dev);
2492 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2493 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2497 * split rx buffer up into sections, each for 1 traffic class
2499 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2500 for (i = 0 ; i < nb_tcs; i++) {
2501 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2502 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2503 /* clear 10 bits. */
2504 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2505 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2507 /* zero alloc all unused TCs */
2508 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2509 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2510 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2511 /* clear 10 bits. */
2512 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2515 /* MRQC: enable vmdq and dcb */
2516 mrqc = ((num_pools == ETH_16_POOLS) ? \
2517 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2518 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2520 /* PFVTCTL: turn on virtualisation and set the default pool */
2521 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2522 if (cfg->enable_default_pool) {
2523 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2525 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2528 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2530 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2532 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2534 * mapping is done with 3 bits per priority,
2535 * so shift by i*3 each time
2537 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2539 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2541 /* RTRPCS: DCB related */
2542 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2544 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2545 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2546 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2547 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2549 /* VFTA - enable all vlan filters */
2550 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2551 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2554 /* VFRE: pool enabling for receive - 16 or 32 */
2555 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2556 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2559 * MPSAR - allow pools to read specific mac addresses
2560 * In this case, all pools should be able to read from mac addr 0
2562 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2563 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2565 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2566 for (i = 0; i < cfg->nb_pool_maps; i++) {
2567 /* set vlan id in VF register and set the valid bit */
2568 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2569 (cfg->pool_map[i].vlan_id & 0xFFF)));
2571 * Put the allowed pools in VFB reg. As we only have 16 or 32
2572 * pools, we only need to use the first half of the register
2575 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2580 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2581 * @hw: pointer to hardware structure
2582 * @dcb_config: pointer to ixgbe_dcb_config structure
2585 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2586 struct ixgbe_dcb_config *dcb_config)
2591 PMD_INIT_FUNC_TRACE();
2592 if (hw->mac.type != ixgbe_mac_82598EB) {
2593 /* Disable the Tx desc arbiter so that MTQC can be changed */
2594 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2595 reg |= IXGBE_RTTDCS_ARBDIS;
2596 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2598 /* Enable DCB for Tx with 8 TCs */
2599 if (dcb_config->num_tcs.pg_tcs == 8) {
2600 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2603 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2605 if (dcb_config->vt_mode)
2606 reg |= IXGBE_MTQC_VT_ENA;
2607 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2609 /* Disable drop for all queues */
2610 for (q = 0; q < 128; q++)
2611 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2612 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2614 /* Enable the Tx desc arbiter */
2615 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2616 reg &= ~IXGBE_RTTDCS_ARBDIS;
2617 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2619 /* Enable Security TX Buffer IFG for DCB */
2620 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2621 reg |= IXGBE_SECTX_DCB;
2622 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2628 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2629 * @dev: pointer to rte_eth_dev structure
2630 * @dcb_config: pointer to ixgbe_dcb_config structure
2633 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2634 struct ixgbe_dcb_config *dcb_config)
2636 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2637 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2638 struct ixgbe_hw *hw =
2639 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2641 PMD_INIT_FUNC_TRACE();
2642 if (hw->mac.type != ixgbe_mac_82598EB)
2643 /*PF VF Transmit Enable*/
2644 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2645 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2647 /*Configure general DCB TX parameters*/
2648 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2653 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2654 struct ixgbe_dcb_config *dcb_config)
2656 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2657 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2658 struct ixgbe_dcb_tc_config *tc;
2661 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2662 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2663 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2664 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2667 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2668 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2670 /* User Priority to Traffic Class mapping */
2671 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2672 j = vmdq_rx_conf->dcb_queue[i];
2673 tc = &dcb_config->tc_config[j];
2674 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2680 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2681 struct ixgbe_dcb_config *dcb_config)
2683 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2684 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2685 struct ixgbe_dcb_tc_config *tc;
2688 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2689 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2690 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2691 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2694 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2695 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2698 /* User Priority to Traffic Class mapping */
2699 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2700 j = vmdq_tx_conf->dcb_queue[i];
2701 tc = &dcb_config->tc_config[j];
2702 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2709 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2710 struct ixgbe_dcb_config *dcb_config)
2712 struct rte_eth_dcb_rx_conf *rx_conf =
2713 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2714 struct ixgbe_dcb_tc_config *tc;
2717 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2718 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2720 /* User Priority to Traffic Class mapping */
2721 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2722 j = rx_conf->dcb_queue[i];
2723 tc = &dcb_config->tc_config[j];
2724 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2730 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2731 struct ixgbe_dcb_config *dcb_config)
2733 struct rte_eth_dcb_tx_conf *tx_conf =
2734 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2735 struct ixgbe_dcb_tc_config *tc;
2738 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2739 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2741 /* User Priority to Traffic Class mapping */
2742 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2743 j = tx_conf->dcb_queue[i];
2744 tc = &dcb_config->tc_config[j];
2745 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2751 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2752 * @hw: pointer to hardware structure
2753 * @dcb_config: pointer to ixgbe_dcb_config structure
2756 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2757 struct ixgbe_dcb_config *dcb_config)
2763 PMD_INIT_FUNC_TRACE();
2765 * Disable the arbiter before changing parameters
2766 * (always enable recycle mode; WSP)
2768 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2769 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2771 if (hw->mac.type != ixgbe_mac_82598EB) {
2772 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2773 if (dcb_config->num_tcs.pg_tcs == 4) {
2774 if (dcb_config->vt_mode)
2775 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2776 IXGBE_MRQC_VMDQRT4TCEN;
2778 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2779 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2783 if (dcb_config->num_tcs.pg_tcs == 8) {
2784 if (dcb_config->vt_mode)
2785 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2786 IXGBE_MRQC_VMDQRT8TCEN;
2788 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2789 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2794 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2797 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2798 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2799 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2800 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2802 /* VFTA - enable all vlan filters */
2803 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2804 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2808 * Configure Rx packet plane (recycle mode; WSP) and
2811 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2812 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2818 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2819 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2821 switch (hw->mac.type) {
2822 case ixgbe_mac_82598EB:
2823 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2825 case ixgbe_mac_82599EB:
2826 case ixgbe_mac_X540:
2827 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2836 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2837 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2839 switch (hw->mac.type) {
2840 case ixgbe_mac_82598EB:
2841 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2842 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2844 case ixgbe_mac_82599EB:
2845 case ixgbe_mac_X540:
2846 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2847 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2854 #define DCB_RX_CONFIG 1
2855 #define DCB_TX_CONFIG 1
2856 #define DCB_TX_PB 1024
2858 * ixgbe_dcb_hw_configure - Enable DCB and configure
2859 * general DCB in VT mode and non-VT mode parameters
2860 * @dev: pointer to rte_eth_dev structure
2861 * @dcb_config: pointer to ixgbe_dcb_config structure
2864 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2865 struct ixgbe_dcb_config *dcb_config)
2868 uint8_t i,pfc_en,nb_tcs;
2870 uint8_t config_dcb_rx = 0;
2871 uint8_t config_dcb_tx = 0;
2872 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2873 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2874 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2875 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2876 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2877 struct ixgbe_dcb_tc_config *tc;
2878 uint32_t max_frame = dev->data->max_frame_size;
2879 struct ixgbe_hw *hw =
2880 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2882 switch(dev->data->dev_conf.rxmode.mq_mode){
2883 case ETH_MQ_RX_VMDQ_DCB:
2884 dcb_config->vt_mode = true;
2885 if (hw->mac.type != ixgbe_mac_82598EB) {
2886 config_dcb_rx = DCB_RX_CONFIG;
2888 *get dcb and VT rx configuration parameters
2891 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2892 /*Configure general VMDQ and DCB RX parameters*/
2893 ixgbe_vmdq_dcb_configure(dev);
2897 dcb_config->vt_mode = false;
2898 config_dcb_rx = DCB_RX_CONFIG;
2899 /* Get dcb TX configuration parameters from rte_eth_conf */
2900 ixgbe_dcb_rx_config(dev,dcb_config);
2901 /*Configure general DCB RX parameters*/
2902 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2905 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration\n");
2908 switch (dev->data->dev_conf.txmode.mq_mode) {
2909 case ETH_MQ_TX_VMDQ_DCB:
2910 dcb_config->vt_mode = true;
2911 config_dcb_tx = DCB_TX_CONFIG;
2912 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2913 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2914 /*Configure general VMDQ and DCB TX parameters*/
2915 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2919 dcb_config->vt_mode = false;
2920 config_dcb_tx = DCB_TX_CONFIG;
2921 /*get DCB TX configuration parameters from rte_eth_conf*/
2922 ixgbe_dcb_tx_config(dev,dcb_config);
2923 /*Configure general DCB TX parameters*/
2924 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2927 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration\n");
2931 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2933 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2934 if(nb_tcs == ETH_4_TCS) {
2935 /* Avoid un-configured priority mapping to TC0 */
2937 uint8_t mask = 0xFF;
2938 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
2939 mask = (uint8_t)(mask & (~ (1 << map[i])));
2940 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
2941 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
2945 /* Re-configure 4 TCs BW */
2946 for (i = 0; i < nb_tcs; i++) {
2947 tc = &dcb_config->tc_config[i];
2948 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
2949 (uint8_t)(100 / nb_tcs);
2950 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
2951 (uint8_t)(100 / nb_tcs);
2953 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2954 tc = &dcb_config->tc_config[i];
2955 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
2956 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
2961 /* Set RX buffer size */
2962 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2963 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
2964 for (i = 0 ; i < nb_tcs; i++) {
2965 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2967 /* zero alloc all unused TCs */
2968 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2969 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
2973 /* Only support an equally distributed Tx packet buffer strategy. */
2974 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
2975 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
2976 for (i = 0; i < nb_tcs; i++) {
2977 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
2978 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
2980 /* Clear unused TCs, if any, to zero buffer size*/
2981 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2982 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
2983 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
2987 /*Calculates traffic class credits*/
2988 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2989 IXGBE_DCB_TX_CONFIG);
2990 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2991 IXGBE_DCB_RX_CONFIG);
2994 /* Unpack CEE standard containers */
2995 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
2996 ixgbe_dcb_unpack_max_cee(dcb_config, max);
2997 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
2998 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
2999 /* Configure PG(ETS) RX */
3000 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3004 /* Unpack CEE standard containers */
3005 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3006 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3007 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3008 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3009 /* Configure PG(ETS) TX */
3010 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3013 /*Configure queue statistics registers*/
3014 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3016 /* Check if the PFC is supported */
3017 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3018 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3019 for (i = 0; i < nb_tcs; i++) {
3021 * If the TC count is 8,and the default high_water is 48,
3022 * the low_water is 16 as default.
3024 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3025 hw->fc.low_water[i] = pbsize / 4;
3026 /* Enable pfc for this TC */
3027 tc = &dcb_config->tc_config[i];
3028 tc->pfc = ixgbe_dcb_pfc_enabled;
3030 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3031 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3033 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3040 * ixgbe_configure_dcb - Configure DCB Hardware
3041 * @dev: pointer to rte_eth_dev
3043 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3045 struct ixgbe_dcb_config *dcb_cfg =
3046 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3047 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3049 PMD_INIT_FUNC_TRACE();
3051 /* check support mq_mode for DCB */
3052 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3053 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3056 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3059 /** Configure DCB hardware **/
3060 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3066 * VMDq only support for 10 GbE NIC.
3069 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3071 struct rte_eth_vmdq_rx_conf *cfg;
3072 struct ixgbe_hw *hw;
3073 enum rte_eth_nb_pools num_pools;
3074 uint32_t mrqc, vt_ctl, vlanctrl;
3077 PMD_INIT_FUNC_TRACE();
3078 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3079 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3080 num_pools = cfg->nb_queue_pools;
3082 ixgbe_rss_disable(dev);
3084 /* MRQC: enable vmdq */
3085 mrqc = IXGBE_MRQC_VMDQEN;
3086 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3088 /* PFVTCTL: turn on virtualisation and set the default pool */
3089 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3090 if (cfg->enable_default_pool)
3091 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3093 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3095 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3097 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3098 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3099 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3100 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3102 /* VFTA - enable all vlan filters */
3103 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3104 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3106 /* VFRE: pool enabling for receive - 64 */
3107 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3108 if (num_pools == ETH_64_POOLS)
3109 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3112 * MPSAR - allow pools to read specific mac addresses
3113 * In this case, all pools should be able to read from mac addr 0
3115 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3116 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3118 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3119 for (i = 0; i < cfg->nb_pool_maps; i++) {
3120 /* set vlan id in VF register and set the valid bit */
3121 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3122 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3124 * Put the allowed pools in VFB reg. As we only have 16 or 64
3125 * pools, we only need to use the first half of the register
3128 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3129 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3130 (cfg->pool_map[i].pools & UINT32_MAX));
3132 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3133 ((cfg->pool_map[i].pools >> 32) \
3138 IXGBE_WRITE_FLUSH(hw);
3142 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3143 * @hw: pointer to hardware structure
3146 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3151 PMD_INIT_FUNC_TRACE();
3152 /*PF VF Transmit Enable*/
3153 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3154 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3156 /* Disable the Tx desc arbiter so that MTQC can be changed */
3157 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3158 reg |= IXGBE_RTTDCS_ARBDIS;
3159 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3161 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3162 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3164 /* Disable drop for all queues */
3165 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3166 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3167 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3169 /* Enable the Tx desc arbiter */
3170 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3171 reg &= ~IXGBE_RTTDCS_ARBDIS;
3172 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3174 IXGBE_WRITE_FLUSH(hw);
3180 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
3182 struct igb_rx_entry *rxe = rxq->sw_ring;
3186 /* Initialize software ring entries */
3187 for (i = 0; i < rxq->nb_rx_desc; i++) {
3188 volatile union ixgbe_adv_rx_desc *rxd;
3189 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3191 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u\n",
3192 (unsigned) rxq->queue_id);
3196 rte_mbuf_refcnt_set(mbuf, 1);
3197 mbuf->type = RTE_MBUF_PKT;
3198 mbuf->pkt.next = NULL;
3199 mbuf->pkt.data = (char *)mbuf->buf_addr + RTE_PKTMBUF_HEADROOM;
3200 mbuf->pkt.nb_segs = 1;
3201 mbuf->pkt.in_port = rxq->port_id;
3204 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3205 rxd = &rxq->rx_ring[i];
3206 rxd->read.hdr_addr = dma_addr;
3207 rxd->read.pkt_addr = dma_addr;
3215 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3217 struct ixgbe_hw *hw =
3218 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3220 if (hw->mac.type == ixgbe_mac_82598EB)
3223 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3225 * SRIOV inactive scheme
3226 * any DCB/RSS w/o VMDq multi-queue setting
3228 switch (dev->data->dev_conf.rxmode.mq_mode) {
3230 ixgbe_rss_configure(dev);
3233 case ETH_MQ_RX_VMDQ_DCB:
3234 ixgbe_vmdq_dcb_configure(dev);
3237 case ETH_MQ_RX_VMDQ_ONLY:
3238 ixgbe_vmdq_rx_hw_configure(dev);
3241 case ETH_MQ_RX_NONE:
3242 /* if mq_mode is none, disable rss mode.*/
3243 default: ixgbe_rss_disable(dev);
3246 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3248 * SRIOV active scheme
3249 * FIXME if support DCB/RSS together with VMDq & SRIOV
3252 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQEN);
3256 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT4TCEN);
3260 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT8TCEN);
3263 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3271 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3273 struct ixgbe_hw *hw =
3274 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3278 if (hw->mac.type == ixgbe_mac_82598EB)
3281 /* disable arbiter before setting MTQC */
3282 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3283 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3284 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3286 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3288 * SRIOV inactive scheme
3289 * any DCB w/o VMDq multi-queue setting
3291 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3292 ixgbe_vmdq_tx_hw_configure(hw);
3294 mtqc = IXGBE_MTQC_64Q_1PB;
3295 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3298 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3301 * SRIOV active scheme
3302 * FIXME if support DCB together with VMDq & SRIOV
3305 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3308 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3311 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3315 mtqc = IXGBE_MTQC_64Q_1PB;
3316 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3318 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3321 /* re-enable arbiter */
3322 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3323 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3329 * Initializes Receive Unit.
3332 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3334 struct ixgbe_hw *hw;
3335 struct igb_rx_queue *rxq;
3336 struct rte_pktmbuf_pool_private *mbp_priv;
3349 PMD_INIT_FUNC_TRACE();
3350 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3353 * Make sure receives are disabled while setting
3354 * up the RX context (registers, descriptor rings, etc.).
3356 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3357 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3359 /* Enable receipt of broadcasted frames */
3360 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3361 fctrl |= IXGBE_FCTRL_BAM;
3362 fctrl |= IXGBE_FCTRL_DPF;
3363 fctrl |= IXGBE_FCTRL_PMCF;
3364 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3367 * Configure CRC stripping, if any.
3369 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3370 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3371 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3373 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3376 * Configure jumbo frame support, if any.
3378 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3379 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3380 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3381 maxfrs &= 0x0000FFFF;
3382 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3383 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3385 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3388 * If loopback mode is configured for 82599, set LPBK bit.
3390 if (hw->mac.type == ixgbe_mac_82599EB &&
3391 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3392 hlreg0 |= IXGBE_HLREG0_LPBK;
3394 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3396 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3398 /* Setup RX queues */
3399 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3400 rxq = dev->data->rx_queues[i];
3402 /* Allocate buffers for descriptor rings */
3403 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3408 * Reset crc_len in case it was changed after queue setup by a
3409 * call to configure.
3411 rxq->crc_len = (uint8_t)
3412 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3415 /* Setup the Base and Length of the Rx Descriptor Rings */
3416 bus_addr = rxq->rx_ring_phys_addr;
3417 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3418 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3419 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3420 (uint32_t)(bus_addr >> 32));
3421 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3422 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3423 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3424 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3426 /* Configure the SRRCTL register */
3427 #ifdef RTE_HEADER_SPLIT_ENABLE
3429 * Configure Header Split
3431 if (dev->data->dev_conf.rxmode.header_split) {
3432 if (hw->mac.type == ixgbe_mac_82599EB) {
3433 /* Must setup the PSRTYPE register */
3435 psrtype = IXGBE_PSRTYPE_TCPHDR |
3436 IXGBE_PSRTYPE_UDPHDR |
3437 IXGBE_PSRTYPE_IPV4HDR |
3438 IXGBE_PSRTYPE_IPV6HDR;
3439 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3441 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3442 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3443 IXGBE_SRRCTL_BSIZEHDR_MASK);
3444 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3447 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3449 /* Set if packets are dropped when no descriptors available */
3451 srrctl |= IXGBE_SRRCTL_DROP_EN;
3454 * Configure the RX buffer size in the BSIZEPACKET field of
3455 * the SRRCTL register of the queue.
3456 * The value is in 1 KB resolution. Valid values can be from
3459 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3460 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3461 RTE_PKTMBUF_HEADROOM);
3462 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3463 IXGBE_SRRCTL_BSIZEPKT_MASK);
3464 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3466 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3467 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3469 /* It adds dual VLAN length for supporting dual VLAN */
3470 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3471 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3472 dev->data->scattered_rx = 1;
3473 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3478 * Device configured with multiple RX queues.
3480 ixgbe_dev_mq_rx_configure(dev);
3483 * Setup the Checksum Register.
3484 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3485 * Enable IP/L4 checkum computation by hardware if requested to do so.
3487 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3488 rxcsum |= IXGBE_RXCSUM_PCSD;
3489 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3490 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3492 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3494 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3496 if (hw->mac.type == ixgbe_mac_82599EB) {
3497 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3498 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3499 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3501 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3502 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3503 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3510 * Initializes Transmit Unit.
3513 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3515 struct ixgbe_hw *hw;
3516 struct igb_tx_queue *txq;
3522 PMD_INIT_FUNC_TRACE();
3523 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3525 /* Enable TX CRC (checksum offload requirement) */
3526 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3527 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
3528 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3530 /* Setup the Base and Length of the Tx Descriptor Rings */
3531 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3532 txq = dev->data->tx_queues[i];
3534 bus_addr = txq->tx_ring_phys_addr;
3535 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3536 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3537 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3538 (uint32_t)(bus_addr >> 32));
3539 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3540 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3541 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3542 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3543 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3546 * Disable Tx Head Writeback RO bit, since this hoses
3547 * bookkeeping if things aren't delivered in order.
3549 switch (hw->mac.type) {
3550 case ixgbe_mac_82598EB:
3551 txctrl = IXGBE_READ_REG(hw,
3552 IXGBE_DCA_TXCTRL(txq->reg_idx));
3553 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3554 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3558 case ixgbe_mac_82599EB:
3559 case ixgbe_mac_X540:
3561 txctrl = IXGBE_READ_REG(hw,
3562 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3563 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3564 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3570 /* Device configured with multiple TX queues. */
3571 ixgbe_dev_mq_tx_configure(dev);
3575 * Set up link for 82599 loopback mode Tx->Rx.
3578 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3580 DEBUGFUNC("ixgbe_setup_loopback_link_82599");
3582 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3583 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3585 PMD_INIT_LOG(ERR, "Could not enable loopback mode\n");
3594 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3595 ixgbe_reset_pipeline_82599(hw);
3597 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3603 * Start Transmit and Receive Units.
3606 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3608 struct ixgbe_hw *hw;
3609 struct igb_tx_queue *txq;
3610 struct igb_rx_queue *rxq;
3618 PMD_INIT_FUNC_TRACE();
3619 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3621 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3622 txq = dev->data->tx_queues[i];
3623 /* Setup Transmit Threshold Registers */
3624 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3625 txdctl |= txq->pthresh & 0x7F;
3626 txdctl |= ((txq->hthresh & 0x7F) << 8);
3627 txdctl |= ((txq->wthresh & 0x7F) << 16);
3628 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3631 if (hw->mac.type != ixgbe_mac_82598EB) {
3632 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3633 dmatxctl |= IXGBE_DMATXCTL_TE;
3634 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3637 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3638 txq = dev->data->tx_queues[i];
3639 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3640 txdctl |= IXGBE_TXDCTL_ENABLE;
3641 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3643 /* Wait until TX Enable ready */
3644 if (hw->mac.type == ixgbe_mac_82599EB) {
3648 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3649 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3651 PMD_INIT_LOG(ERR, "Could not enable "
3652 "Tx Queue %d\n", i);
3655 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3656 rxq = dev->data->rx_queues[i];
3657 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3658 rxdctl |= IXGBE_RXDCTL_ENABLE;
3659 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3661 /* Wait until RX Enable ready */
3665 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3666 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3668 PMD_INIT_LOG(ERR, "Could not enable "
3669 "Rx Queue %d\n", i);
3671 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3674 /* Enable Receive engine */
3675 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3676 if (hw->mac.type == ixgbe_mac_82598EB)
3677 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3678 rxctrl |= IXGBE_RXCTRL_RXEN;
3679 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3681 /* If loopback mode is enabled for 82599, set up the link accordingly */
3682 if (hw->mac.type == ixgbe_mac_82599EB &&
3683 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3684 ixgbe_setup_loopback_link_82599(hw);
3690 * [VF] Initializes Receive Unit.
3693 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3695 struct ixgbe_hw *hw;
3696 struct igb_rx_queue *rxq;
3697 struct rte_pktmbuf_pool_private *mbp_priv;
3704 PMD_INIT_FUNC_TRACE();
3705 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3707 /* Setup RX queues */
3708 dev->rx_pkt_burst = ixgbe_recv_pkts;
3709 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3710 rxq = dev->data->rx_queues[i];
3712 /* Allocate buffers for descriptor rings */
3713 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3717 /* Setup the Base and Length of the Rx Descriptor Rings */
3718 bus_addr = rxq->rx_ring_phys_addr;
3720 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3721 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3722 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3723 (uint32_t)(bus_addr >> 32));
3724 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3725 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3726 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3727 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3730 /* Configure the SRRCTL register */
3731 #ifdef RTE_HEADER_SPLIT_ENABLE
3733 * Configure Header Split
3735 if (dev->data->dev_conf.rxmode.header_split) {
3737 /* Must setup the PSRTYPE register */
3739 psrtype = IXGBE_PSRTYPE_TCPHDR |
3740 IXGBE_PSRTYPE_UDPHDR |
3741 IXGBE_PSRTYPE_IPV4HDR |
3742 IXGBE_PSRTYPE_IPV6HDR;
3744 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
3746 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3747 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3748 IXGBE_SRRCTL_BSIZEHDR_MASK);
3749 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3752 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3754 /* Set if packets are dropped when no descriptors available */
3756 srrctl |= IXGBE_SRRCTL_DROP_EN;
3759 * Configure the RX buffer size in the BSIZEPACKET field of
3760 * the SRRCTL register of the queue.
3761 * The value is in 1 KB resolution. Valid values can be from
3764 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3765 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3766 RTE_PKTMBUF_HEADROOM);
3767 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3768 IXGBE_SRRCTL_BSIZEPKT_MASK);
3771 * VF modification to write virtual function SRRCTL register
3773 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
3775 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3776 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3778 /* It adds dual VLAN length for supporting dual VLAN */
3779 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3780 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
3781 dev->data->scattered_rx = 1;
3782 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3790 * [VF] Initializes Transmit Unit.
3793 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
3795 struct ixgbe_hw *hw;
3796 struct igb_tx_queue *txq;
3801 PMD_INIT_FUNC_TRACE();
3802 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3804 /* Setup the Base and Length of the Tx Descriptor Rings */
3805 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3806 txq = dev->data->tx_queues[i];
3807 bus_addr = txq->tx_ring_phys_addr;
3808 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
3809 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3810 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
3811 (uint32_t)(bus_addr >> 32));
3812 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
3813 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3814 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3815 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
3816 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
3819 * Disable Tx Head Writeback RO bit, since this hoses
3820 * bookkeeping if things aren't delivered in order.
3822 txctrl = IXGBE_READ_REG(hw,
3823 IXGBE_VFDCA_TXCTRL(i));
3824 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3825 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
3831 * [VF] Start Transmit and Receive Units.
3834 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
3836 struct ixgbe_hw *hw;
3837 struct igb_tx_queue *txq;
3838 struct igb_rx_queue *rxq;
3844 PMD_INIT_FUNC_TRACE();
3845 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3847 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3848 txq = dev->data->tx_queues[i];
3849 /* Setup Transmit Threshold Registers */
3850 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3851 txdctl |= txq->pthresh & 0x7F;
3852 txdctl |= ((txq->hthresh & 0x7F) << 8);
3853 txdctl |= ((txq->wthresh & 0x7F) << 16);
3854 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
3857 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3859 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3860 txdctl |= IXGBE_TXDCTL_ENABLE;
3861 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
3864 /* Wait until TX Enable ready */
3867 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3868 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3870 PMD_INIT_LOG(ERR, "Could not enable "
3871 "Tx Queue %d\n", i);
3873 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3875 rxq = dev->data->rx_queues[i];
3877 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
3878 rxdctl |= IXGBE_RXDCTL_ENABLE;
3879 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
3881 /* Wait until RX Enable ready */
3885 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
3886 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3888 PMD_INIT_LOG(ERR, "Could not enable "
3889 "Rx Queue %d\n", i);
3891 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);