4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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34 #include <sys/queue.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
47 #include <rte_cycles.h>
49 #include <rte_debug.h>
50 #include <rte_interrupts.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_launch.h>
55 #include <rte_tailq.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
82 #define RTE_PMD_IXGBE_TX_MAX_BURST 32
84 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
85 #define RTE_PMD_IXGBE_RX_MAX_BURST 32
88 static inline struct rte_mbuf *
89 rte_rxmbuf_alloc(struct rte_mempool *mp)
93 m = __rte_mbuf_raw_alloc(mp);
94 __rte_mbuf_sanity_check_raw(m, RTE_MBUF_PKT, 0);
98 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
99 (uint64_t) ((mb)->buf_physaddr + (uint64_t)((char *)((mb)->pkt.data) - \
100 (char *)(mb)->buf_addr))
102 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
103 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
106 * Structure associated with each descriptor of the RX ring of a RX queue.
108 struct igb_rx_entry {
109 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
113 * Structure associated with each descriptor of the TX ring of a TX queue.
115 struct igb_tx_entry {
116 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
117 uint16_t next_id; /**< Index of next descriptor in ring. */
118 uint16_t last_id; /**< Index of last scattered descriptor. */
122 * Structure associated with each RX queue.
124 struct igb_rx_queue {
125 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
126 volatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
127 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
128 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
129 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
130 struct igb_rx_entry *sw_ring; /**< address of RX software ring. */
131 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
132 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
133 uint16_t nb_rx_desc; /**< number of RX descriptors. */
134 uint16_t rx_tail; /**< current value of RDT register. */
135 uint16_t nb_rx_hold; /**< number of held free RX desc. */
136 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
137 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
138 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
139 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
141 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
142 uint16_t queue_id; /**< RX queue index. */
143 uint16_t reg_idx; /**< RX queue register index. */
144 uint8_t port_id; /**< Device port identifier. */
145 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
146 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
147 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
148 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */
149 struct rte_mbuf fake_mbuf;
150 /** hold packets to return to application */
151 struct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2];
156 * IXGBE CTX Constants
158 enum ixgbe_advctx_num {
159 IXGBE_CTX_0 = 0, /**< CTX0 */
160 IXGBE_CTX_1 = 1, /**< CTX1 */
161 IXGBE_CTX_NUM = 2, /**< CTX NUMBER */
165 * Structure to check if new context need be built
168 struct ixgbe_advctx_info {
169 uint16_t flags; /**< ol_flags for context build. */
170 uint32_t cmp_mask; /**< compare mask for vlan_macip_lens */
171 union rte_vlan_macip vlan_macip_lens; /**< vlan, mac ip length. */
175 * Structure associated with each TX queue.
177 struct igb_tx_queue {
178 /** TX ring virtual address. */
179 volatile union ixgbe_adv_tx_desc *tx_ring;
180 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
181 struct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */
182 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
183 uint16_t nb_tx_desc; /**< number of TX descriptors. */
184 uint16_t tx_tail; /**< current value of TDT reg. */
185 uint16_t tx_free_thresh;/**< minimum TX before freeing. */
186 /** Number of TX descriptors to use before RS bit is set. */
187 uint16_t tx_rs_thresh;
188 /** Number of TX descriptors used since RS bit was set. */
190 /** Index to last TX descriptor to have been cleaned. */
191 uint16_t last_desc_cleaned;
192 /** Total number of TX descriptors ready to be allocated. */
194 uint16_t tx_next_dd; /**< next desc to scan for DD bit */
195 uint16_t tx_next_rs; /**< next desc to set RS bit */
196 uint16_t queue_id; /**< TX queue index. */
197 uint16_t reg_idx; /**< TX queue register index. */
198 uint8_t port_id; /**< Device port identifier. */
199 uint8_t pthresh; /**< Prefetch threshold register. */
200 uint8_t hthresh; /**< Host threshold register. */
201 uint8_t wthresh; /**< Write-back threshold reg. */
202 uint32_t txq_flags; /**< Holds flags for this TXq */
203 uint32_t ctx_curr; /**< Hardware context states. */
204 /** Hardware context0 history. */
205 struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM];
210 #define RTE_PMD_USE_PREFETCH
213 #ifdef RTE_PMD_USE_PREFETCH
215 * Prefetch a cache line into all cache levels.
217 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
219 #define rte_ixgbe_prefetch(p) do {} while(0)
222 #ifdef RTE_PMD_PACKET_PREFETCH
223 #define rte_packet_prefetch(p) rte_prefetch1(p)
225 #define rte_packet_prefetch(p) do {} while(0)
228 /*********************************************************************
232 **********************************************************************/
235 * The "simple" TX queue functions require that the following
236 * flags are set when the TX queue is configured:
237 * - ETH_TXQ_FLAGS_NOMULTSEGS
238 * - ETH_TXQ_FLAGS_NOVLANOFFL
239 * - ETH_TXQ_FLAGS_NOXSUMSCTP
240 * - ETH_TXQ_FLAGS_NOXSUMUDP
241 * - ETH_TXQ_FLAGS_NOXSUMTCP
242 * and that the RS bit threshold (tx_rs_thresh) is at least equal to
243 * RTE_PMD_IXGBE_TX_MAX_BURST.
245 #define IXGBE_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
246 ETH_TXQ_FLAGS_NOOFFLOADS)
249 * Check for descriptors with their DD bit set and free mbufs.
250 * Return the total number of buffers freed.
252 static inline int __attribute__((always_inline))
253 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
255 struct igb_tx_entry *txep;
259 /* check DD bit on threshold descriptor */
260 status = txq->tx_ring[txq->tx_next_dd].wb.status;
261 if (! (status & IXGBE_ADVTXD_STAT_DD))
265 * first buffer to free from S/W ring is at index
266 * tx_next_dd - (tx_rs_thresh-1)
268 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
270 /* prefetch the mbufs that are about to be freed */
271 for (i = 0; i < txq->tx_rs_thresh; ++i)
272 rte_prefetch0((txep + i)->mbuf);
274 /* free buffers one at a time */
275 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
276 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
277 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
281 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
282 rte_pktmbuf_free_seg(txep->mbuf);
287 /* buffers were freed, update counters */
288 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
289 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
290 if (txq->tx_next_dd >= txq->nb_tx_desc)
291 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
293 return txq->tx_rs_thresh;
297 * Populate descriptors with the following info:
298 * 1.) buffer_addr = phys_addr + headroom
299 * 2.) cmd_type_len = DCMD_DTYP_FLAGS | pkt_len
300 * 3.) olinfo_status = pkt_len << PAYLEN_SHIFT
303 /* Defines for Tx descriptor */
304 #define DCMD_DTYP_FLAGS (IXGBE_ADVTXD_DTYP_DATA |\
305 IXGBE_ADVTXD_DCMD_IFCS |\
306 IXGBE_ADVTXD_DCMD_DEXT |\
307 IXGBE_ADVTXD_DCMD_EOP)
309 /* Populate 4 descriptors with data from 4 mbufs */
311 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
313 uint64_t buf_dma_addr;
317 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
318 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
319 pkt_len = (*pkts)->pkt.data_len;
321 /* write data to descriptor */
322 txdp->read.buffer_addr = buf_dma_addr;
323 txdp->read.cmd_type_len =
324 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
325 txdp->read.olinfo_status =
326 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
330 /* Populate 1 descriptor with data from 1 mbuf */
332 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
334 uint64_t buf_dma_addr;
337 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
338 pkt_len = (*pkts)->pkt.data_len;
340 /* write data to descriptor */
341 txdp->read.buffer_addr = buf_dma_addr;
342 txdp->read.cmd_type_len =
343 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
344 txdp->read.olinfo_status =
345 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
349 * Fill H/W descriptor ring with mbuf data.
350 * Copy mbuf pointers to the S/W ring.
353 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
356 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
357 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
358 const int N_PER_LOOP = 4;
359 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
360 int mainpart, leftover;
364 * Process most of the packets in chunks of N pkts. Any
365 * leftover packets will get processed one at a time.
367 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
368 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
369 for (i = 0; i < mainpart; i += N_PER_LOOP) {
370 /* Copy N mbuf pointers to the S/W ring */
371 for (j = 0; j < N_PER_LOOP; ++j) {
372 (txep + i + j)->mbuf = *(pkts + i + j);
374 tx4(txdp + i, pkts + i);
377 if (unlikely(leftover > 0)) {
378 for (i = 0; i < leftover; ++i) {
379 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
380 tx1(txdp + mainpart + i, pkts + mainpart + i);
385 static inline uint16_t
386 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
389 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
390 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
394 * Begin scanning the H/W ring for done descriptors when the
395 * number of available descriptors drops below tx_free_thresh. For
396 * each done descriptor, free the associated buffer.
398 if (txq->nb_tx_free < txq->tx_free_thresh)
399 ixgbe_tx_free_bufs(txq);
401 /* Only use descriptors that are available */
402 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
403 if (unlikely(nb_pkts == 0))
406 /* Use exactly nb_pkts descriptors */
407 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
410 * At this point, we know there are enough descriptors in the
411 * ring to transmit all the packets. This assumes that each
412 * mbuf contains a single segment, and that no new offloads
413 * are expected, which would require a new context descriptor.
417 * See if we're going to wrap-around. If so, handle the top
418 * of the descriptor ring first, then do the bottom. If not,
419 * the processing looks just like the "bottom" part anyway...
421 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
422 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
423 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
426 * We know that the last descriptor in the ring will need to
427 * have its RS bit set because tx_rs_thresh has to be
428 * a divisor of the ring size
430 tx_r[txq->tx_next_rs].read.cmd_type_len |=
431 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
432 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
437 /* Fill H/W descriptor ring with mbuf data */
438 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
439 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
442 * Determine if RS bit should be set
443 * This is what we actually want:
444 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
445 * but instead of subtracting 1 and doing >=, we can just do
446 * greater than without subtracting.
448 if (txq->tx_tail > txq->tx_next_rs) {
449 tx_r[txq->tx_next_rs].read.cmd_type_len |=
450 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
451 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
453 if (txq->tx_next_rs >= txq->nb_tx_desc)
454 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
458 * Check for wrap-around. This would only happen if we used
459 * up to the last descriptor in the ring, no more, no less.
461 if (txq->tx_tail >= txq->nb_tx_desc)
464 /* update tail pointer */
466 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
472 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
477 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
478 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
479 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
481 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
485 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
486 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
487 nb_tx = (uint16_t)(nb_tx + ret);
488 nb_pkts = (uint16_t)(nb_pkts - ret);
497 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
498 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
499 uint16_t ol_flags, uint32_t vlan_macip_lens)
501 uint32_t type_tucmd_mlhl;
502 uint32_t mss_l4len_idx;
506 ctx_idx = txq->ctx_curr;
510 if (ol_flags & PKT_TX_VLAN_PKT) {
511 cmp_mask |= TX_VLAN_CMP_MASK;
514 if (ol_flags & PKT_TX_IP_CKSUM) {
515 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
516 cmp_mask |= TX_MAC_LEN_CMP_MASK;
519 /* Specify which HW CTX to upload. */
520 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
521 switch (ol_flags & PKT_TX_L4_MASK) {
522 case PKT_TX_UDP_CKSUM:
523 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
524 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
525 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
526 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
528 case PKT_TX_TCP_CKSUM:
529 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
530 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
531 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
532 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
534 case PKT_TX_SCTP_CKSUM:
535 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
536 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
537 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
538 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
541 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
542 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
546 txq->ctx_cache[ctx_idx].flags = ol_flags;
547 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
548 txq->ctx_cache[ctx_idx].vlan_macip_lens.data =
549 vlan_macip_lens & cmp_mask;
551 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
552 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
553 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
554 ctx_txd->seqnum_seed = 0;
558 * Check which hardware context can be used. Use the existing match
559 * or create a new context descriptor.
561 static inline uint32_t
562 what_advctx_update(struct igb_tx_queue *txq, uint16_t flags,
563 uint32_t vlan_macip_lens)
565 /* If match with the current used context */
566 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
567 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
568 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
569 return txq->ctx_curr;
572 /* What if match with the next context */
574 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
575 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
576 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
577 return txq->ctx_curr;
580 /* Mismatch, use the previous context */
581 return (IXGBE_CTX_NUM);
584 static inline uint32_t
585 tx_desc_cksum_flags_to_olinfo(uint16_t ol_flags)
587 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
588 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
591 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
592 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
596 static inline uint32_t
597 tx_desc_vlan_flags_to_cmdtype(uint16_t ol_flags)
599 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
600 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
603 /* Default RS bit threshold values */
604 #ifndef DEFAULT_TX_RS_THRESH
605 #define DEFAULT_TX_RS_THRESH 32
607 #ifndef DEFAULT_TX_FREE_THRESH
608 #define DEFAULT_TX_FREE_THRESH 32
611 /* Reset transmit descriptors after they have been used */
613 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
615 struct igb_tx_entry *sw_ring = txq->sw_ring;
616 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
617 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
618 uint16_t nb_tx_desc = txq->nb_tx_desc;
619 uint16_t desc_to_clean_to;
620 uint16_t nb_tx_to_clean;
622 /* Determine the last descriptor needing to be cleaned */
623 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
624 if (desc_to_clean_to >= nb_tx_desc)
625 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
627 /* Check to make sure the last descriptor to clean is done */
628 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
629 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
631 PMD_TX_FREE_LOG(DEBUG,
632 "TX descriptor %4u is not done"
633 "(port=%d queue=%d)",
635 txq->port_id, txq->queue_id);
636 /* Failed to clean any descriptors, better luck next time */
640 /* Figure out how many descriptors will be cleaned */
641 if (last_desc_cleaned > desc_to_clean_to)
642 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
645 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
648 PMD_TX_FREE_LOG(DEBUG,
649 "Cleaning %4u TX descriptors: %4u to %4u "
650 "(port=%d queue=%d)",
651 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
652 txq->port_id, txq->queue_id);
655 * The last descriptor to clean is done, so that means all the
656 * descriptors from the last descriptor that was cleaned
657 * up to the last descriptor with the RS bit set
658 * are done. Only reset the threshold descriptor.
660 txr[desc_to_clean_to].wb.status = 0;
662 /* Update the txq to reflect the last descriptor that was cleaned */
663 txq->last_desc_cleaned = desc_to_clean_to;
664 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
671 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
674 struct igb_tx_queue *txq;
675 struct igb_tx_entry *sw_ring;
676 struct igb_tx_entry *txe, *txn;
677 volatile union ixgbe_adv_tx_desc *txr;
678 volatile union ixgbe_adv_tx_desc *txd;
679 struct rte_mbuf *tx_pkt;
680 struct rte_mbuf *m_seg;
681 uint64_t buf_dma_addr;
682 uint32_t olinfo_status;
683 uint32_t cmd_type_len;
692 uint32_t vlan_macip_lens;
697 sw_ring = txq->sw_ring;
699 tx_id = txq->tx_tail;
700 txe = &sw_ring[tx_id];
702 /* Determine if the descriptor ring needs to be cleaned. */
703 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
704 ixgbe_xmit_cleanup(txq);
708 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
711 pkt_len = tx_pkt->pkt.pkt_len;
713 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
716 * Determine how many (if any) context descriptors
717 * are needed for offload functionality.
719 ol_flags = tx_pkt->ol_flags;
720 vlan_macip_lens = tx_pkt->pkt.vlan_macip.data;
722 /* If hardware offload required */
723 tx_ol_req = (uint16_t)(ol_flags & PKT_TX_OFFLOAD_MASK);
725 /* If new context need be built or reuse the exist ctx. */
726 ctx = what_advctx_update(txq, tx_ol_req,
728 /* Only allocate context descriptor if required*/
729 new_ctx = (ctx == IXGBE_CTX_NUM);
734 * Keep track of how many descriptors are used this loop
735 * This will always be the number of segments + the number of
736 * Context descriptors required to transmit the packet
738 nb_used = (uint16_t)(tx_pkt->pkt.nb_segs + new_ctx);
741 * The number of descriptors that must be allocated for a
742 * packet is the number of segments of that packet, plus 1
743 * Context Descriptor for the hardware offload, if any.
744 * Determine the last TX descriptor to allocate in the TX ring
745 * for the packet, starting from the current position (tx_id)
748 tx_last = (uint16_t) (tx_id + nb_used - 1);
751 if (tx_last >= txq->nb_tx_desc)
752 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
754 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
755 " tx_first=%u tx_last=%u\n",
756 (unsigned) txq->port_id,
757 (unsigned) txq->queue_id,
763 * Make sure there are enough TX descriptors available to
764 * transmit the entire packet.
765 * nb_used better be less than or equal to txq->tx_rs_thresh
767 if (nb_used > txq->nb_tx_free) {
768 PMD_TX_FREE_LOG(DEBUG,
769 "Not enough free TX descriptors "
770 "nb_used=%4u nb_free=%4u "
771 "(port=%d queue=%d)",
772 nb_used, txq->nb_tx_free,
773 txq->port_id, txq->queue_id);
775 if (ixgbe_xmit_cleanup(txq) != 0) {
776 /* Could not clean any descriptors */
782 /* nb_used better be <= txq->tx_rs_thresh */
783 if (unlikely(nb_used > txq->tx_rs_thresh)) {
784 PMD_TX_FREE_LOG(DEBUG,
785 "The number of descriptors needed to "
786 "transmit the packet exceeds the "
787 "RS bit threshold. This will impact "
789 "nb_used=%4u nb_free=%4u "
791 "(port=%d queue=%d)",
792 nb_used, txq->nb_tx_free,
794 txq->port_id, txq->queue_id);
796 * Loop here until there are enough TX
797 * descriptors or until the ring cannot be
800 while (nb_used > txq->nb_tx_free) {
801 if (ixgbe_xmit_cleanup(txq) != 0) {
803 * Could not clean any
815 * By now there are enough free TX descriptors to transmit
820 * Set common flags of all TX Data Descriptors.
822 * The following bits must be set in all Data Descriptors:
823 * - IXGBE_ADVTXD_DTYP_DATA
824 * - IXGBE_ADVTXD_DCMD_DEXT
826 * The following bits must be set in the first Data Descriptor
827 * and are ignored in the other ones:
828 * - IXGBE_ADVTXD_DCMD_IFCS
829 * - IXGBE_ADVTXD_MAC_1588
830 * - IXGBE_ADVTXD_DCMD_VLE
832 * The following bits must only be set in the last Data
834 * - IXGBE_TXD_CMD_EOP
836 * The following bits can be set in any Data Descriptor, but
837 * are only set in the last Data Descriptor:
840 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
841 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
842 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
843 #ifdef RTE_LIBRTE_IEEE1588
844 if (ol_flags & PKT_TX_IEEE1588_TMST)
845 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
850 * Setup the TX Advanced Context Descriptor if required
853 volatile struct ixgbe_adv_tx_context_desc *
856 ctx_txd = (volatile struct
857 ixgbe_adv_tx_context_desc *)
860 txn = &sw_ring[txe->next_id];
861 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
863 if (txe->mbuf != NULL) {
864 rte_pktmbuf_free_seg(txe->mbuf);
868 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
871 txe->last_id = tx_last;
872 tx_id = txe->next_id;
877 * Setup the TX Advanced Data Descriptor,
878 * This path will go through
879 * whatever new/reuse the context descriptor
881 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
882 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
883 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
889 txn = &sw_ring[txe->next_id];
891 if (txe->mbuf != NULL)
892 rte_pktmbuf_free_seg(txe->mbuf);
896 * Set up Transmit Data Descriptor.
898 slen = m_seg->pkt.data_len;
899 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
900 txd->read.buffer_addr =
901 rte_cpu_to_le_64(buf_dma_addr);
902 txd->read.cmd_type_len =
903 rte_cpu_to_le_32(cmd_type_len | slen);
904 txd->read.olinfo_status =
905 rte_cpu_to_le_32(olinfo_status);
906 txe->last_id = tx_last;
907 tx_id = txe->next_id;
909 m_seg = m_seg->pkt.next;
910 } while (m_seg != NULL);
913 * The last packet data descriptor needs End Of Packet (EOP)
915 cmd_type_len |= IXGBE_TXD_CMD_EOP;
916 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
917 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
919 /* Set RS bit only on threshold packets' last descriptor */
920 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
921 PMD_TX_FREE_LOG(DEBUG,
922 "Setting RS bit on TXD id="
923 "%4u (port=%d queue=%d)",
924 tx_last, txq->port_id, txq->queue_id);
926 cmd_type_len |= IXGBE_TXD_CMD_RS;
928 /* Update txq RS bit counters */
931 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
937 * Set the Transmit Descriptor Tail (TDT)
939 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
940 (unsigned) txq->port_id, (unsigned) txq->queue_id,
941 (unsigned) tx_id, (unsigned) nb_tx);
942 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
943 txq->tx_tail = tx_id;
948 /*********************************************************************
952 **********************************************************************/
953 static inline uint16_t
954 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
958 static uint16_t ip_pkt_types_map[16] = {
959 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
960 PKT_RX_IPV6_HDR, 0, 0, 0,
961 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
962 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
965 static uint16_t ip_rss_types_map[16] = {
966 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
967 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
968 PKT_RX_RSS_HASH, 0, 0, 0,
969 0, 0, 0, PKT_RX_FDIR,
972 #ifdef RTE_LIBRTE_IEEE1588
973 static uint32_t ip_pkt_etqf_map[8] = {
974 0, 0, 0, PKT_RX_IEEE1588_PTP,
978 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
979 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
980 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
982 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
983 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
986 return (uint16_t)(pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF]);
989 static inline uint16_t
990 rx_desc_status_to_pkt_flags(uint32_t rx_status)
995 * Check if VLAN present only.
996 * Do not check whether L3/L4 rx checksum done by NIC or not,
997 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
999 pkt_flags = (uint16_t)((rx_status & IXGBE_RXD_STAT_VP) ?
1000 PKT_RX_VLAN_PKT : 0);
1002 #ifdef RTE_LIBRTE_IEEE1588
1003 if (rx_status & IXGBE_RXD_STAT_TMST)
1004 pkt_flags = (uint16_t)(pkt_flags | PKT_RX_IEEE1588_TMST);
1009 static inline uint16_t
1010 rx_desc_error_to_pkt_flags(uint32_t rx_status)
1013 * Bit 31: IPE, IPv4 checksum error
1014 * Bit 30: L4I, L4I integrity error
1016 static uint16_t error_to_pkt_flags_map[4] = {
1017 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
1018 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1020 return error_to_pkt_flags_map[(rx_status >>
1021 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1024 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1026 * LOOK_AHEAD defines how many desc statuses to check beyond the
1027 * current descriptor.
1028 * It must be a pound define for optimal performance.
1029 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1030 * function only works with LOOK_AHEAD=8.
1032 #define LOOK_AHEAD 8
1033 #if (LOOK_AHEAD != 8)
1034 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1037 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
1039 volatile union ixgbe_adv_rx_desc *rxdp;
1040 struct igb_rx_entry *rxep;
1041 struct rte_mbuf *mb;
1043 uint32_t s[LOOK_AHEAD];
1045 int i, j, nb_rx = 0;
1048 /* get references to current descriptor and S/W ring entry */
1049 rxdp = &rxq->rx_ring[rxq->rx_tail];
1050 rxep = &rxq->sw_ring[rxq->rx_tail];
1052 /* check to make sure there is at least 1 packet to receive */
1053 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
1057 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1058 * reference packets that are ready to be received.
1060 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1061 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
1063 /* Read desc statuses backwards to avoid race condition */
1064 for (j = LOOK_AHEAD-1; j >= 0; --j)
1065 s[j] = rxdp[j].wb.upper.status_error;
1068 /* add to nd_dd when the status bit is set (LSB) */
1069 for (j = 0; j < LOOK_AHEAD; ++j) {
1070 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
1075 /* Translate descriptor info to mbuf format */
1076 for (j = 0; j < nb_dd; ++j) {
1078 pkt_len = (uint16_t)(rxdp[j].wb.upper.length -
1080 mb->pkt.data_len = pkt_len;
1081 mb->pkt.pkt_len = pkt_len;
1082 mb->pkt.vlan_macip.f.vlan_tci = rxdp[j].wb.upper.vlan;
1083 mb->pkt.hash.rss = rxdp[j].wb.lower.hi_dword.rss;
1085 /* convert descriptor fields to rte mbuf flags */
1086 mb->ol_flags = rx_desc_hlen_type_rss_to_pkt_flags(
1087 rxdp[j].wb.lower.lo_dword.data);
1088 /* reuse status field from scan list */
1089 mb->ol_flags = (uint16_t)(mb->ol_flags |
1090 rx_desc_status_to_pkt_flags(s[j]));
1091 mb->ol_flags = (uint16_t)(mb->ol_flags |
1092 rx_desc_error_to_pkt_flags(s[j]));
1095 /* Move mbuf pointers from the S/W ring to the stage */
1096 for (j = 0; j < LOOK_AHEAD; ++j) {
1097 rxq->rx_stage[i + j] = rxep[j].mbuf;
1100 /* stop if all requested packets could not be received */
1101 if (nb_dd != LOOK_AHEAD)
1105 /* clear software ring entries so we can cleanup correctly */
1106 for (i = 0; i < nb_rx; ++i) {
1107 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1115 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
1117 volatile union ixgbe_adv_rx_desc *rxdp;
1118 struct igb_rx_entry *rxep;
1119 struct rte_mbuf *mb;
1124 /* allocate buffers in bulk directly into the S/W ring */
1125 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1126 (rxq->rx_free_thresh - 1));
1127 rxep = &rxq->sw_ring[alloc_idx];
1128 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1129 rxq->rx_free_thresh);
1130 if (unlikely(diag != 0))
1133 rxdp = &rxq->rx_ring[alloc_idx];
1134 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1135 /* populate the static rte mbuf fields */
1137 rte_mbuf_refcnt_set(mb, 1);
1138 mb->type = RTE_MBUF_PKT;
1139 mb->pkt.next = NULL;
1140 mb->pkt.data = (char *)mb->buf_addr + RTE_PKTMBUF_HEADROOM;
1141 mb->pkt.nb_segs = 1;
1142 mb->pkt.in_port = rxq->port_id;
1144 /* populate the descriptors */
1145 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1146 rxdp[i].read.hdr_addr = dma_addr;
1147 rxdp[i].read.pkt_addr = dma_addr;
1150 /* update tail pointer */
1152 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1154 /* update state of internal queue structure */
1155 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1156 rxq->rx_free_thresh);
1157 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1158 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1164 static inline uint16_t
1165 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1168 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1171 /* how many packets are ready to return? */
1172 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1174 /* copy mbuf pointers to the application's packet list */
1175 for (i = 0; i < nb_pkts; ++i)
1176 rx_pkts[i] = stage[i];
1178 /* update internal queue state */
1179 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1180 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1185 static inline uint16_t
1186 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1189 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1192 /* Any previously recv'd pkts will be returned from the Rx stage */
1193 if (rxq->rx_nb_avail)
1194 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1196 /* Scan the H/W ring for packets to receive */
1197 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1199 /* update internal queue state */
1200 rxq->rx_next_avail = 0;
1201 rxq->rx_nb_avail = nb_rx;
1202 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1204 /* if required, allocate new buffers to replenish descriptors */
1205 if (rxq->rx_tail > rxq->rx_free_trigger) {
1206 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1208 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1209 "queue_id=%u\n", (unsigned) rxq->port_id,
1210 (unsigned) rxq->queue_id);
1212 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1213 rxq->rx_free_thresh;
1216 * Need to rewind any previous receives if we cannot
1217 * allocate new buffers to replenish the old ones.
1219 rxq->rx_nb_avail = 0;
1220 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1221 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1222 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1228 if (rxq->rx_tail >= rxq->nb_rx_desc)
1231 /* received any packets this loop? */
1232 if (rxq->rx_nb_avail)
1233 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1238 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1240 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1245 if (unlikely(nb_pkts == 0))
1248 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1249 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1251 /* request is relatively large, chunk it up */
1255 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1256 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1257 nb_rx = (uint16_t)(nb_rx + ret);
1258 nb_pkts = (uint16_t)(nb_pkts - ret);
1265 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1268 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1271 struct igb_rx_queue *rxq;
1272 volatile union ixgbe_adv_rx_desc *rx_ring;
1273 volatile union ixgbe_adv_rx_desc *rxdp;
1274 struct igb_rx_entry *sw_ring;
1275 struct igb_rx_entry *rxe;
1276 struct rte_mbuf *rxm;
1277 struct rte_mbuf *nmb;
1278 union ixgbe_adv_rx_desc rxd;
1281 uint32_t hlen_type_rss;
1291 rx_id = rxq->rx_tail;
1292 rx_ring = rxq->rx_ring;
1293 sw_ring = rxq->sw_ring;
1294 while (nb_rx < nb_pkts) {
1296 * The order of operations here is important as the DD status
1297 * bit must not be read after any other descriptor fields.
1298 * rx_ring and rxdp are pointing to volatile data so the order
1299 * of accesses cannot be reordered by the compiler. If they were
1300 * not volatile, they could be reordered which could lead to
1301 * using invalid descriptor fields when read from rxd.
1303 rxdp = &rx_ring[rx_id];
1304 staterr = rxdp->wb.upper.status_error;
1305 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1312 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1313 * is likely to be invalid and to be dropped by the various
1314 * validation checks performed by the network stack.
1316 * Allocate a new mbuf to replenish the RX ring descriptor.
1317 * If the allocation fails:
1318 * - arrange for that RX descriptor to be the first one
1319 * being parsed the next time the receive function is
1320 * invoked [on the same queue].
1322 * - Stop parsing the RX ring and return immediately.
1324 * This policy do not drop the packet received in the RX
1325 * descriptor for which the allocation of a new mbuf failed.
1326 * Thus, it allows that packet to be later retrieved if
1327 * mbuf have been freed in the mean time.
1328 * As a side effect, holding RX descriptors instead of
1329 * systematically giving them back to the NIC may lead to
1330 * RX ring exhaustion situations.
1331 * However, the NIC can gracefully prevent such situations
1332 * to happen by sending specific "back-pressure" flow control
1333 * frames to its peer(s).
1335 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1336 "ext_err_stat=0x%08x pkt_len=%u\n",
1337 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1338 (unsigned) rx_id, (unsigned) staterr,
1339 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1341 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1343 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1344 "queue_id=%u\n", (unsigned) rxq->port_id,
1345 (unsigned) rxq->queue_id);
1346 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1351 rxe = &sw_ring[rx_id];
1353 if (rx_id == rxq->nb_rx_desc)
1356 /* Prefetch next mbuf while processing current one. */
1357 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1360 * When next RX descriptor is on a cache-line boundary,
1361 * prefetch the next 4 RX descriptors and the next 8 pointers
1364 if ((rx_id & 0x3) == 0) {
1365 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1366 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1372 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1373 rxdp->read.hdr_addr = dma_addr;
1374 rxdp->read.pkt_addr = dma_addr;
1377 * Initialize the returned mbuf.
1378 * 1) setup generic mbuf fields:
1379 * - number of segments,
1382 * - RX port identifier.
1383 * 2) integrate hardware offload data, if any:
1384 * - RSS flag & hash,
1385 * - IP checksum flag,
1386 * - VLAN TCI, if any,
1389 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1391 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1392 rte_packet_prefetch(rxm->pkt.data);
1393 rxm->pkt.nb_segs = 1;
1394 rxm->pkt.next = NULL;
1395 rxm->pkt.pkt_len = pkt_len;
1396 rxm->pkt.data_len = pkt_len;
1397 rxm->pkt.in_port = rxq->port_id;
1399 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1400 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1401 rxm->pkt.vlan_macip.f.vlan_tci =
1402 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1404 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1405 pkt_flags = (uint16_t)(pkt_flags |
1406 rx_desc_status_to_pkt_flags(staterr));
1407 pkt_flags = (uint16_t)(pkt_flags |
1408 rx_desc_error_to_pkt_flags(staterr));
1409 rxm->ol_flags = pkt_flags;
1411 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1412 rxm->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1413 else if (pkt_flags & PKT_RX_FDIR) {
1414 rxm->pkt.hash.fdir.hash =
1415 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1416 & IXGBE_ATR_HASH_MASK);
1417 rxm->pkt.hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1420 * Store the mbuf address into the next entry of the array
1421 * of returned packets.
1423 rx_pkts[nb_rx++] = rxm;
1425 rxq->rx_tail = rx_id;
1428 * If the number of free RX descriptors is greater than the RX free
1429 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1431 * Update the RDT with the value of the last processed RX descriptor
1432 * minus 1, to guarantee that the RDT register is never equal to the
1433 * RDH register, which creates a "full" ring situtation from the
1434 * hardware point of view...
1436 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1437 if (nb_hold > rxq->rx_free_thresh) {
1438 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1439 "nb_hold=%u nb_rx=%u\n",
1440 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1441 (unsigned) rx_id, (unsigned) nb_hold,
1443 rx_id = (uint16_t) ((rx_id == 0) ?
1444 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1445 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1448 rxq->nb_rx_hold = nb_hold;
1453 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1456 struct igb_rx_queue *rxq;
1457 volatile union ixgbe_adv_rx_desc *rx_ring;
1458 volatile union ixgbe_adv_rx_desc *rxdp;
1459 struct igb_rx_entry *sw_ring;
1460 struct igb_rx_entry *rxe;
1461 struct rte_mbuf *first_seg;
1462 struct rte_mbuf *last_seg;
1463 struct rte_mbuf *rxm;
1464 struct rte_mbuf *nmb;
1465 union ixgbe_adv_rx_desc rxd;
1466 uint64_t dma; /* Physical address of mbuf data buffer */
1468 uint32_t hlen_type_rss;
1478 rx_id = rxq->rx_tail;
1479 rx_ring = rxq->rx_ring;
1480 sw_ring = rxq->sw_ring;
1483 * Retrieve RX context of current packet, if any.
1485 first_seg = rxq->pkt_first_seg;
1486 last_seg = rxq->pkt_last_seg;
1488 while (nb_rx < nb_pkts) {
1491 * The order of operations here is important as the DD status
1492 * bit must not be read after any other descriptor fields.
1493 * rx_ring and rxdp are pointing to volatile data so the order
1494 * of accesses cannot be reordered by the compiler. If they were
1495 * not volatile, they could be reordered which could lead to
1496 * using invalid descriptor fields when read from rxd.
1498 rxdp = &rx_ring[rx_id];
1499 staterr = rxdp->wb.upper.status_error;
1500 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1507 * Allocate a new mbuf to replenish the RX ring descriptor.
1508 * If the allocation fails:
1509 * - arrange for that RX descriptor to be the first one
1510 * being parsed the next time the receive function is
1511 * invoked [on the same queue].
1513 * - Stop parsing the RX ring and return immediately.
1515 * This policy does not drop the packet received in the RX
1516 * descriptor for which the allocation of a new mbuf failed.
1517 * Thus, it allows that packet to be later retrieved if
1518 * mbuf have been freed in the mean time.
1519 * As a side effect, holding RX descriptors instead of
1520 * systematically giving them back to the NIC may lead to
1521 * RX ring exhaustion situations.
1522 * However, the NIC can gracefully prevent such situations
1523 * to happen by sending specific "back-pressure" flow control
1524 * frames to its peer(s).
1526 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
1527 "staterr=0x%x data_len=%u\n",
1528 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1529 (unsigned) rx_id, (unsigned) staterr,
1530 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1532 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1534 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1535 "queue_id=%u\n", (unsigned) rxq->port_id,
1536 (unsigned) rxq->queue_id);
1537 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1542 rxe = &sw_ring[rx_id];
1544 if (rx_id == rxq->nb_rx_desc)
1547 /* Prefetch next mbuf while processing current one. */
1548 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1551 * When next RX descriptor is on a cache-line boundary,
1552 * prefetch the next 4 RX descriptors and the next 8 pointers
1555 if ((rx_id & 0x3) == 0) {
1556 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1557 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1561 * Update RX descriptor with the physical address of the new
1562 * data buffer of the new allocated mbuf.
1566 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1567 rxdp->read.hdr_addr = dma;
1568 rxdp->read.pkt_addr = dma;
1571 * Set data length & data buffer address of mbuf.
1573 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1574 rxm->pkt.data_len = data_len;
1575 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1578 * If this is the first buffer of the received packet,
1579 * set the pointer to the first mbuf of the packet and
1580 * initialize its context.
1581 * Otherwise, update the total length and the number of segments
1582 * of the current scattered packet, and update the pointer to
1583 * the last mbuf of the current packet.
1585 if (first_seg == NULL) {
1587 first_seg->pkt.pkt_len = data_len;
1588 first_seg->pkt.nb_segs = 1;
1590 first_seg->pkt.pkt_len = (uint16_t)(first_seg->pkt.pkt_len
1592 first_seg->pkt.nb_segs++;
1593 last_seg->pkt.next = rxm;
1597 * If this is not the last buffer of the received packet,
1598 * update the pointer to the last mbuf of the current scattered
1599 * packet and continue to parse the RX ring.
1601 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1607 * This is the last buffer of the received packet.
1608 * If the CRC is not stripped by the hardware:
1609 * - Subtract the CRC length from the total packet length.
1610 * - If the last buffer only contains the whole CRC or a part
1611 * of it, free the mbuf associated to the last buffer.
1612 * If part of the CRC is also contained in the previous
1613 * mbuf, subtract the length of that CRC part from the
1614 * data length of the previous mbuf.
1616 rxm->pkt.next = NULL;
1617 if (unlikely(rxq->crc_len > 0)) {
1618 first_seg->pkt.pkt_len -= ETHER_CRC_LEN;
1619 if (data_len <= ETHER_CRC_LEN) {
1620 rte_pktmbuf_free_seg(rxm);
1621 first_seg->pkt.nb_segs--;
1622 last_seg->pkt.data_len = (uint16_t)
1623 (last_seg->pkt.data_len -
1624 (ETHER_CRC_LEN - data_len));
1625 last_seg->pkt.next = NULL;
1628 (uint16_t) (data_len - ETHER_CRC_LEN);
1632 * Initialize the first mbuf of the returned packet:
1633 * - RX port identifier,
1634 * - hardware offload data, if any:
1635 * - RSS flag & hash,
1636 * - IP checksum flag,
1637 * - VLAN TCI, if any,
1640 first_seg->pkt.in_port = rxq->port_id;
1643 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1644 * set in the pkt_flags field.
1646 first_seg->pkt.vlan_macip.f.vlan_tci =
1647 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1648 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1649 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1650 pkt_flags = (uint16_t)(pkt_flags |
1651 rx_desc_status_to_pkt_flags(staterr));
1652 pkt_flags = (uint16_t)(pkt_flags |
1653 rx_desc_error_to_pkt_flags(staterr));
1654 first_seg->ol_flags = pkt_flags;
1656 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1657 first_seg->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1658 else if (pkt_flags & PKT_RX_FDIR) {
1659 first_seg->pkt.hash.fdir.hash =
1660 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1661 & IXGBE_ATR_HASH_MASK);
1662 first_seg->pkt.hash.fdir.id =
1663 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1666 /* Prefetch data of first segment, if configured to do so. */
1667 rte_packet_prefetch(first_seg->pkt.data);
1670 * Store the mbuf address into the next entry of the array
1671 * of returned packets.
1673 rx_pkts[nb_rx++] = first_seg;
1676 * Setup receipt context for a new packet.
1682 * Record index of the next RX descriptor to probe.
1684 rxq->rx_tail = rx_id;
1687 * Save receive context.
1689 rxq->pkt_first_seg = first_seg;
1690 rxq->pkt_last_seg = last_seg;
1693 * If the number of free RX descriptors is greater than the RX free
1694 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1696 * Update the RDT with the value of the last processed RX descriptor
1697 * minus 1, to guarantee that the RDT register is never equal to the
1698 * RDH register, which creates a "full" ring situtation from the
1699 * hardware point of view...
1701 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1702 if (nb_hold > rxq->rx_free_thresh) {
1703 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1704 "nb_hold=%u nb_rx=%u\n",
1705 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1706 (unsigned) rx_id, (unsigned) nb_hold,
1708 rx_id = (uint16_t) ((rx_id == 0) ?
1709 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1710 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1713 rxq->nb_rx_hold = nb_hold;
1717 /*********************************************************************
1719 * Queue management functions
1721 **********************************************************************/
1724 * Rings setup and release.
1726 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1727 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1728 * also optimize cache line size effect. H/W supports up to cache line size 128.
1730 #define IXGBE_ALIGN 128
1733 * Maximum number of Ring Descriptors.
1735 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1736 * descriptors should meet the following condition:
1737 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1739 #define IXGBE_MIN_RING_DESC 64
1740 #define IXGBE_MAX_RING_DESC 4096
1743 * Create memzone for HW rings. malloc can't be used as the physical address is
1744 * needed. If the memzone is already created, then this function returns a ptr
1747 static const struct rte_memzone *
1748 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1749 uint16_t queue_id, uint32_t ring_size, int socket_id)
1751 char z_name[RTE_MEMZONE_NAMESIZE];
1752 const struct rte_memzone *mz;
1754 rte_snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1755 dev->driver->pci_drv.name, ring_name,
1756 dev->data->port_id, queue_id);
1758 mz = rte_memzone_lookup(z_name);
1762 #ifdef RTE_LIBRTE_XEN_DOM0
1763 return rte_memzone_reserve_bounded(z_name, ring_size,
1764 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1766 return rte_memzone_reserve_aligned(z_name, ring_size,
1767 socket_id, 0, IXGBE_ALIGN);
1772 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1776 if (txq->sw_ring != NULL) {
1777 for (i = 0; i < txq->nb_tx_desc; i++) {
1778 if (txq->sw_ring[i].mbuf != NULL) {
1779 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1780 txq->sw_ring[i].mbuf = NULL;
1787 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1790 ixgbe_tx_queue_release_mbufs(txq);
1791 rte_free(txq->sw_ring);
1797 ixgbe_dev_tx_queue_release(void *txq)
1799 ixgbe_tx_queue_release(txq);
1802 /* (Re)set dynamic igb_tx_queue fields to defaults */
1804 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1806 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1808 struct igb_tx_entry *txe = txq->sw_ring;
1811 /* Zero out HW ring memory */
1812 for (i = 0; i < txq->nb_tx_desc; i++) {
1813 txq->tx_ring[i] = zeroed_desc;
1816 /* Initialize SW ring entries */
1817 prev = (uint16_t) (txq->nb_tx_desc - 1);
1818 for (i = 0; i < txq->nb_tx_desc; i++) {
1819 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1820 txd->wb.status = IXGBE_TXD_STAT_DD;
1822 txe[i].last_id = (uint16_t)i;
1823 txe[prev].next_id = (uint16_t)i;
1827 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1828 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1831 txq->nb_tx_used = 0;
1833 * Always allow 1 descriptor to be un-allocated to avoid
1834 * a H/W race condition
1836 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1837 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1839 memset((void*)&txq->ctx_cache, 0,
1840 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1844 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1847 unsigned int socket_id,
1848 const struct rte_eth_txconf *tx_conf)
1850 const struct rte_memzone *tz;
1851 struct igb_tx_queue *txq;
1852 struct ixgbe_hw *hw;
1853 uint16_t tx_rs_thresh, tx_free_thresh;
1855 PMD_INIT_FUNC_TRACE();
1856 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1859 * Validate number of transmit descriptors.
1860 * It must not exceed hardware maximum, and must be multiple
1863 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1864 (nb_desc > IXGBE_MAX_RING_DESC) ||
1865 (nb_desc < IXGBE_MIN_RING_DESC)) {
1870 * The following two parameters control the setting of the RS bit on
1871 * transmit descriptors.
1872 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1873 * descriptors have been used.
1874 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1875 * descriptors are used or if the number of descriptors required
1876 * to transmit a packet is greater than the number of free TX
1878 * The following constraints must be satisfied:
1879 * tx_rs_thresh must be greater than 0.
1880 * tx_rs_thresh must be less than the size of the ring minus 2.
1881 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1882 * tx_rs_thresh must be a divisor of the ring size.
1883 * tx_free_thresh must be greater than 0.
1884 * tx_free_thresh must be less than the size of the ring minus 3.
1885 * One descriptor in the TX ring is used as a sentinel to avoid a
1886 * H/W race condition, hence the maximum threshold constraints.
1887 * When set to zero use default values.
1889 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1890 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1891 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1892 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1893 if (tx_rs_thresh >= (nb_desc - 2)) {
1894 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the number "
1895 "of TX descriptors minus 2. (tx_rs_thresh=%u port=%d "
1896 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1897 (int)dev->data->port_id, (int)queue_idx);
1900 if (tx_free_thresh >= (nb_desc - 3)) {
1901 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the "
1902 "tx_free_thresh must be less than the number of TX "
1903 "descriptors minus 3. (tx_free_thresh=%u port=%d "
1904 "queue=%d)\n", (unsigned int)tx_free_thresh,
1905 (int)dev->data->port_id, (int)queue_idx);
1908 if (tx_rs_thresh > tx_free_thresh) {
1909 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than or equal to "
1910 "tx_free_thresh. (tx_free_thresh=%u tx_rs_thresh=%u "
1911 "port=%d queue=%d)\n", (unsigned int)tx_free_thresh,
1912 (unsigned int)tx_rs_thresh, (int)dev->data->port_id,
1916 if ((nb_desc % tx_rs_thresh) != 0) {
1917 RTE_LOG(ERR, PMD, "tx_rs_thresh must be a divisor of the "
1918 "number of TX descriptors. (tx_rs_thresh=%u port=%d "
1919 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1920 (int)dev->data->port_id, (int)queue_idx);
1925 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1926 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1927 * by the NIC and all descriptors are written back after the NIC
1928 * accumulates WTHRESH descriptors.
1930 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1931 RTE_LOG(ERR, PMD, "TX WTHRESH must be set to 0 if "
1932 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1933 "port=%d queue=%d)\n", (unsigned int)tx_rs_thresh,
1934 (int)dev->data->port_id, (int)queue_idx);
1938 /* Free memory prior to re-allocation if needed... */
1939 if (dev->data->tx_queues[queue_idx] != NULL)
1940 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1942 /* First allocate the tx queue data structure */
1943 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct igb_tx_queue),
1944 CACHE_LINE_SIZE, socket_id);
1949 * Allocate TX ring hardware descriptors. A memzone large enough to
1950 * handle the maximum ring size is allocated in order to allow for
1951 * resizing in later calls to the queue setup function.
1953 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1954 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1957 ixgbe_tx_queue_release(txq);
1961 txq->nb_tx_desc = nb_desc;
1962 txq->tx_rs_thresh = tx_rs_thresh;
1963 txq->tx_free_thresh = tx_free_thresh;
1964 txq->pthresh = tx_conf->tx_thresh.pthresh;
1965 txq->hthresh = tx_conf->tx_thresh.hthresh;
1966 txq->wthresh = tx_conf->tx_thresh.wthresh;
1967 txq->queue_id = queue_idx;
1968 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1969 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1970 txq->port_id = dev->data->port_id;
1971 txq->txq_flags = tx_conf->txq_flags;
1974 * Modification to set VFTDT for virtual function if vf is detected
1976 if (hw->mac.type == ixgbe_mac_82599_vf)
1977 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1979 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1980 #ifndef RTE_LIBRTE_XEN_DOM0
1981 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1983 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1985 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1987 /* Allocate software ring */
1988 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1989 sizeof(struct igb_tx_entry) * nb_desc,
1990 CACHE_LINE_SIZE, socket_id);
1991 if (txq->sw_ring == NULL) {
1992 ixgbe_tx_queue_release(txq);
1995 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1996 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1998 ixgbe_reset_tx_queue(txq);
2000 dev->data->tx_queues[queue_idx] = txq;
2002 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2003 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
2004 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
2005 PMD_INIT_LOG(INFO, "Using simple tx code path\n");
2006 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
2008 PMD_INIT_LOG(INFO, "Using full-featured tx code path\n");
2009 PMD_INIT_LOG(INFO, " - txq_flags = %lx [IXGBE_SIMPLE_FLAGS=%lx]\n", (long unsigned)txq->txq_flags, (long unsigned)IXGBE_SIMPLE_FLAGS);
2010 PMD_INIT_LOG(INFO, " - tx_rs_thresh = %lu [RTE_PMD_IXGBE_TX_MAX_BURST=%lu]\n", (long unsigned)txq->tx_rs_thresh, (long unsigned)RTE_PMD_IXGBE_TX_MAX_BURST);
2011 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2018 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
2022 if (rxq->sw_ring != NULL) {
2023 for (i = 0; i < rxq->nb_rx_desc; i++) {
2024 if (rxq->sw_ring[i].mbuf != NULL) {
2025 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2026 rxq->sw_ring[i].mbuf = NULL;
2029 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2030 if (rxq->rx_nb_avail) {
2031 for (i = 0; i < rxq->rx_nb_avail; ++i) {
2032 struct rte_mbuf *mb;
2033 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2034 rte_pktmbuf_free_seg(mb);
2036 rxq->rx_nb_avail = 0;
2043 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
2046 ixgbe_rx_queue_release_mbufs(rxq);
2047 rte_free(rxq->sw_ring);
2053 ixgbe_dev_rx_queue_release(void *rxq)
2055 ixgbe_rx_queue_release(rxq);
2059 * Check if Rx Burst Bulk Alloc function can be used.
2061 * 0: the preconditions are satisfied and the bulk allocation function
2063 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2064 * function must be used.
2067 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2068 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
2070 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct igb_rx_queue *rxq)
2076 * Make sure the following pre-conditions are satisfied:
2077 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2078 * rxq->rx_free_thresh < rxq->nb_rx_desc
2079 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2080 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2081 * Scattered packets are not supported. This should be checked
2082 * outside of this function.
2084 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2085 if (! (rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST))
2087 else if (! (rxq->rx_free_thresh < rxq->nb_rx_desc))
2089 else if (! ((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0))
2091 else if (! (rxq->nb_rx_desc <
2092 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST)))
2101 /* Reset dynamic igb_rx_queue fields back to defaults */
2103 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
2105 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
2111 * By default, the Rx queue setup function allocates enough memory for
2112 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2113 * extra memory at the end of the descriptor ring to be zero'd out. A
2114 * pre-condition for using the Rx burst bulk alloc function is that the
2115 * number of descriptors is less than or equal to
2116 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2117 * constraints here to see if we need to zero out memory after the end
2118 * of the H/W descriptor ring.
2120 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2121 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2122 /* zero out extra memory */
2123 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2126 /* do not zero out extra memory */
2127 len = rxq->nb_rx_desc;
2130 * Zero out HW ring memory. Zero out extra memory at the end of
2131 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2132 * reads extra memory as zeros.
2134 for (i = 0; i < len; i++) {
2135 rxq->rx_ring[i] = zeroed_desc;
2138 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2140 * initialize extra software ring entries. Space for these extra
2141 * entries is always allocated
2143 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2144 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2145 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2148 rxq->rx_nb_avail = 0;
2149 rxq->rx_next_avail = 0;
2150 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2151 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2153 rxq->nb_rx_hold = 0;
2154 rxq->pkt_first_seg = NULL;
2155 rxq->pkt_last_seg = NULL;
2159 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2162 unsigned int socket_id,
2163 const struct rte_eth_rxconf *rx_conf,
2164 struct rte_mempool *mp)
2166 const struct rte_memzone *rz;
2167 struct igb_rx_queue *rxq;
2168 struct ixgbe_hw *hw;
2169 int use_def_burst_func = 1;
2172 PMD_INIT_FUNC_TRACE();
2173 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2176 * Validate number of receive descriptors.
2177 * It must not exceed hardware maximum, and must be multiple
2180 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2181 (nb_desc > IXGBE_MAX_RING_DESC) ||
2182 (nb_desc < IXGBE_MIN_RING_DESC)) {
2186 /* Free memory prior to re-allocation if needed... */
2187 if (dev->data->rx_queues[queue_idx] != NULL)
2188 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2190 /* First allocate the rx queue data structure */
2191 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct igb_rx_queue),
2192 CACHE_LINE_SIZE, socket_id);
2196 rxq->nb_rx_desc = nb_desc;
2197 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2198 rxq->queue_id = queue_idx;
2199 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2200 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2201 rxq->port_id = dev->data->port_id;
2202 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2204 rxq->drop_en = rx_conf->rx_drop_en;
2207 * Allocate RX ring hardware descriptors. A memzone large enough to
2208 * handle the maximum ring size is allocated in order to allow for
2209 * resizing in later calls to the queue setup function.
2211 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2212 IXGBE_MAX_RING_DESC * sizeof(union ixgbe_adv_rx_desc),
2215 ixgbe_rx_queue_release(rxq);
2219 * Modified to setup VFRDT for Virtual Function
2221 if (hw->mac.type == ixgbe_mac_82599_vf) {
2223 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2225 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2229 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2231 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2233 #ifndef RTE_LIBRTE_XEN_DOM0
2234 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2236 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2238 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2241 * Allocate software ring. Allow for space at the end of the
2242 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2243 * function does not access an invalid memory region.
2245 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2246 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2250 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2251 sizeof(struct igb_rx_entry) * len,
2252 CACHE_LINE_SIZE, socket_id);
2253 if (rxq->sw_ring == NULL) {
2254 ixgbe_rx_queue_release(rxq);
2257 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
2258 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2261 * Certain constaints must be met in order to use the bulk buffer
2262 * allocation Rx burst function.
2264 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2266 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2267 if (!use_def_burst_func && !dev->data->scattered_rx) {
2268 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2269 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2270 "satisfied. Rx Burst Bulk Alloc function will be "
2271 "used on port=%d, queue=%d.\n",
2272 rxq->port_id, rxq->queue_id);
2273 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2276 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2277 "are not satisfied, Scattered Rx is requested, "
2278 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2279 "enabled (port=%d, queue=%d).\n",
2280 rxq->port_id, rxq->queue_id);
2282 dev->data->rx_queues[queue_idx] = rxq;
2284 ixgbe_reset_rx_queue(rxq);
2290 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2292 #define IXGBE_RXQ_SCAN_INTERVAL 4
2293 volatile union ixgbe_adv_rx_desc *rxdp;
2294 struct igb_rx_queue *rxq;
2297 if (rx_queue_id >= dev->data->nb_rx_queues) {
2298 PMD_RX_LOG(ERR, "Invalid RX queue id=%d\n", rx_queue_id);
2302 rxq = dev->data->rx_queues[rx_queue_id];
2303 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2305 while ((desc < rxq->nb_rx_desc) &&
2306 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2307 desc += IXGBE_RXQ_SCAN_INTERVAL;
2308 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2309 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2310 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2311 desc - rxq->nb_rx_desc]);
2318 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2320 volatile union ixgbe_adv_rx_desc *rxdp;
2321 struct igb_rx_queue *rxq = rx_queue;
2324 if (unlikely(offset >= rxq->nb_rx_desc))
2326 desc = rxq->rx_tail + offset;
2327 if (desc >= rxq->nb_rx_desc)
2328 desc -= rxq->nb_rx_desc;
2330 rxdp = &rxq->rx_ring[desc];
2331 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2335 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2339 PMD_INIT_FUNC_TRACE();
2341 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2342 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2344 ixgbe_tx_queue_release_mbufs(txq);
2345 ixgbe_reset_tx_queue(txq);
2349 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2350 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2352 ixgbe_rx_queue_release_mbufs(rxq);
2353 ixgbe_reset_rx_queue(rxq);
2358 /*********************************************************************
2360 * Device RX/TX init functions
2362 **********************************************************************/
2365 * Receive Side Scaling (RSS)
2366 * See section 7.1.2.8 in the following document:
2367 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2370 * The source and destination IP addresses of the IP header and the source
2371 * and destination ports of TCP/UDP headers, if any, of received packets are
2372 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2373 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2374 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2375 * RSS output index which is used as the RX queue index where to store the
2377 * The following output is supplied in the RX write-back descriptor:
2378 * - 32-bit result of the Microsoft RSS hash function,
2379 * - 4-bit RSS type field.
2383 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2384 * Used as the default key.
2386 static uint8_t rss_intel_key[40] = {
2387 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2388 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2389 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2390 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2391 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2395 ixgbe_rss_disable(struct rte_eth_dev *dev)
2397 struct ixgbe_hw *hw;
2400 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2401 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2402 mrqc &= ~IXGBE_MRQC_RSSEN;
2403 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2407 ixgbe_rss_configure(struct rte_eth_dev *dev)
2409 struct ixgbe_hw *hw;
2418 PMD_INIT_FUNC_TRACE();
2419 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2421 rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
2422 if (rss_hf == 0) { /* Disable RSS */
2423 ixgbe_rss_disable(dev);
2426 hash_key = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key;
2427 if (hash_key == NULL)
2428 hash_key = rss_intel_key; /* Default hash key */
2430 /* Fill in RSS hash key */
2431 for (i = 0; i < 10; i++) {
2432 rss_key = hash_key[(i * 4)];
2433 rss_key |= hash_key[(i * 4) + 1] << 8;
2434 rss_key |= hash_key[(i * 4) + 2] << 16;
2435 rss_key |= hash_key[(i * 4) + 3] << 24;
2436 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2439 /* Fill in redirection table */
2441 for (i = 0, j = 0; i < 128; i++, j++) {
2442 if (j == dev->data->nb_rx_queues) j = 0;
2443 reta = (reta << 8) | j;
2445 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), rte_bswap32(reta));
2448 /* Set configured hashing functions in MRQC register */
2449 mrqc = IXGBE_MRQC_RSSEN; /* RSS enable */
2450 if (rss_hf & ETH_RSS_IPV4)
2451 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2452 if (rss_hf & ETH_RSS_IPV4_TCP)
2453 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2454 if (rss_hf & ETH_RSS_IPV6)
2455 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2456 if (rss_hf & ETH_RSS_IPV6_EX)
2457 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2458 if (rss_hf & ETH_RSS_IPV6_TCP)
2459 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2460 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2461 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2462 if (rss_hf & ETH_RSS_IPV4_UDP)
2463 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2464 if (rss_hf & ETH_RSS_IPV6_UDP)
2465 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2466 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2467 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2468 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2471 #define NUM_VFTA_REGISTERS 128
2472 #define NIC_RX_BUFFER_SIZE 0x200
2475 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2477 struct rte_eth_vmdq_dcb_conf *cfg;
2478 struct ixgbe_hw *hw;
2479 enum rte_eth_nb_pools num_pools;
2480 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2482 uint8_t nb_tcs; /* number of traffic classes */
2485 PMD_INIT_FUNC_TRACE();
2486 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2487 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2488 num_pools = cfg->nb_queue_pools;
2489 /* Check we have a valid number of pools */
2490 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2491 ixgbe_rss_disable(dev);
2494 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2495 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2499 * split rx buffer up into sections, each for 1 traffic class
2501 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2502 for (i = 0 ; i < nb_tcs; i++) {
2503 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2504 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2505 /* clear 10 bits. */
2506 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2507 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2509 /* zero alloc all unused TCs */
2510 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2511 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2512 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2513 /* clear 10 bits. */
2514 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2517 /* MRQC: enable vmdq and dcb */
2518 mrqc = ((num_pools == ETH_16_POOLS) ? \
2519 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2520 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2522 /* PFVTCTL: turn on virtualisation and set the default pool */
2523 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2524 if (cfg->enable_default_pool) {
2525 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2527 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2530 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2532 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2534 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2536 * mapping is done with 3 bits per priority,
2537 * so shift by i*3 each time
2539 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2541 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2543 /* RTRPCS: DCB related */
2544 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2546 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2547 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2548 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2549 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2551 /* VFTA - enable all vlan filters */
2552 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2553 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2556 /* VFRE: pool enabling for receive - 16 or 32 */
2557 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2558 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2561 * MPSAR - allow pools to read specific mac addresses
2562 * In this case, all pools should be able to read from mac addr 0
2564 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2565 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2567 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2568 for (i = 0; i < cfg->nb_pool_maps; i++) {
2569 /* set vlan id in VF register and set the valid bit */
2570 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2571 (cfg->pool_map[i].vlan_id & 0xFFF)));
2573 * Put the allowed pools in VFB reg. As we only have 16 or 32
2574 * pools, we only need to use the first half of the register
2577 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2582 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2583 * @hw: pointer to hardware structure
2584 * @dcb_config: pointer to ixgbe_dcb_config structure
2587 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2588 struct ixgbe_dcb_config *dcb_config)
2593 PMD_INIT_FUNC_TRACE();
2594 if (hw->mac.type != ixgbe_mac_82598EB) {
2595 /* Disable the Tx desc arbiter so that MTQC can be changed */
2596 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2597 reg |= IXGBE_RTTDCS_ARBDIS;
2598 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2600 /* Enable DCB for Tx with 8 TCs */
2601 if (dcb_config->num_tcs.pg_tcs == 8) {
2602 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2605 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2607 if (dcb_config->vt_mode)
2608 reg |= IXGBE_MTQC_VT_ENA;
2609 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2611 /* Disable drop for all queues */
2612 for (q = 0; q < 128; q++)
2613 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2614 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2616 /* Enable the Tx desc arbiter */
2617 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2618 reg &= ~IXGBE_RTTDCS_ARBDIS;
2619 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2621 /* Enable Security TX Buffer IFG for DCB */
2622 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2623 reg |= IXGBE_SECTX_DCB;
2624 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2630 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2631 * @dev: pointer to rte_eth_dev structure
2632 * @dcb_config: pointer to ixgbe_dcb_config structure
2635 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2636 struct ixgbe_dcb_config *dcb_config)
2638 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2639 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2640 struct ixgbe_hw *hw =
2641 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2643 PMD_INIT_FUNC_TRACE();
2644 if (hw->mac.type != ixgbe_mac_82598EB)
2645 /*PF VF Transmit Enable*/
2646 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2647 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2649 /*Configure general DCB TX parameters*/
2650 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2655 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2656 struct ixgbe_dcb_config *dcb_config)
2658 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2659 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2660 struct ixgbe_dcb_tc_config *tc;
2663 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2664 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2665 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2666 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2669 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2670 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2672 /* User Priority to Traffic Class mapping */
2673 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2674 j = vmdq_rx_conf->dcb_queue[i];
2675 tc = &dcb_config->tc_config[j];
2676 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2682 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2683 struct ixgbe_dcb_config *dcb_config)
2685 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2686 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2687 struct ixgbe_dcb_tc_config *tc;
2690 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2691 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2692 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2693 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2696 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2697 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2700 /* User Priority to Traffic Class mapping */
2701 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2702 j = vmdq_tx_conf->dcb_queue[i];
2703 tc = &dcb_config->tc_config[j];
2704 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2711 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2712 struct ixgbe_dcb_config *dcb_config)
2714 struct rte_eth_dcb_rx_conf *rx_conf =
2715 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2716 struct ixgbe_dcb_tc_config *tc;
2719 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2720 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2722 /* User Priority to Traffic Class mapping */
2723 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2724 j = rx_conf->dcb_queue[i];
2725 tc = &dcb_config->tc_config[j];
2726 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2732 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2733 struct ixgbe_dcb_config *dcb_config)
2735 struct rte_eth_dcb_tx_conf *tx_conf =
2736 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2737 struct ixgbe_dcb_tc_config *tc;
2740 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2741 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2743 /* User Priority to Traffic Class mapping */
2744 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2745 j = tx_conf->dcb_queue[i];
2746 tc = &dcb_config->tc_config[j];
2747 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2753 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2754 * @hw: pointer to hardware structure
2755 * @dcb_config: pointer to ixgbe_dcb_config structure
2758 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2759 struct ixgbe_dcb_config *dcb_config)
2765 PMD_INIT_FUNC_TRACE();
2767 * Disable the arbiter before changing parameters
2768 * (always enable recycle mode; WSP)
2770 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2771 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2773 if (hw->mac.type != ixgbe_mac_82598EB) {
2774 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2775 if (dcb_config->num_tcs.pg_tcs == 4) {
2776 if (dcb_config->vt_mode)
2777 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2778 IXGBE_MRQC_VMDQRT4TCEN;
2780 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2781 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2785 if (dcb_config->num_tcs.pg_tcs == 8) {
2786 if (dcb_config->vt_mode)
2787 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2788 IXGBE_MRQC_VMDQRT8TCEN;
2790 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2791 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2796 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2799 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2800 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2801 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2802 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2804 /* VFTA - enable all vlan filters */
2805 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2806 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2810 * Configure Rx packet plane (recycle mode; WSP) and
2813 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2814 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2820 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2821 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2823 switch (hw->mac.type) {
2824 case ixgbe_mac_82598EB:
2825 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2827 case ixgbe_mac_82599EB:
2828 case ixgbe_mac_X540:
2829 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2838 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2839 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2841 switch (hw->mac.type) {
2842 case ixgbe_mac_82598EB:
2843 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2844 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2846 case ixgbe_mac_82599EB:
2847 case ixgbe_mac_X540:
2848 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2849 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2856 #define DCB_RX_CONFIG 1
2857 #define DCB_TX_CONFIG 1
2858 #define DCB_TX_PB 1024
2860 * ixgbe_dcb_hw_configure - Enable DCB and configure
2861 * general DCB in VT mode and non-VT mode parameters
2862 * @dev: pointer to rte_eth_dev structure
2863 * @dcb_config: pointer to ixgbe_dcb_config structure
2866 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2867 struct ixgbe_dcb_config *dcb_config)
2870 uint8_t i,pfc_en,nb_tcs;
2872 uint8_t config_dcb_rx = 0;
2873 uint8_t config_dcb_tx = 0;
2874 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2875 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2876 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2877 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2878 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2879 struct ixgbe_dcb_tc_config *tc;
2880 uint32_t max_frame = dev->data->max_frame_size;
2881 struct ixgbe_hw *hw =
2882 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2884 switch(dev->data->dev_conf.rxmode.mq_mode){
2885 case ETH_MQ_RX_VMDQ_DCB:
2886 dcb_config->vt_mode = true;
2887 if (hw->mac.type != ixgbe_mac_82598EB) {
2888 config_dcb_rx = DCB_RX_CONFIG;
2890 *get dcb and VT rx configuration parameters
2893 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2894 /*Configure general VMDQ and DCB RX parameters*/
2895 ixgbe_vmdq_dcb_configure(dev);
2899 dcb_config->vt_mode = false;
2900 config_dcb_rx = DCB_RX_CONFIG;
2901 /* Get dcb TX configuration parameters from rte_eth_conf */
2902 ixgbe_dcb_rx_config(dev,dcb_config);
2903 /*Configure general DCB RX parameters*/
2904 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2907 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration\n");
2910 switch (dev->data->dev_conf.txmode.mq_mode) {
2911 case ETH_MQ_TX_VMDQ_DCB:
2912 dcb_config->vt_mode = true;
2913 config_dcb_tx = DCB_TX_CONFIG;
2914 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2915 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2916 /*Configure general VMDQ and DCB TX parameters*/
2917 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2921 dcb_config->vt_mode = false;
2922 config_dcb_tx = DCB_TX_CONFIG;
2923 /*get DCB TX configuration parameters from rte_eth_conf*/
2924 ixgbe_dcb_tx_config(dev,dcb_config);
2925 /*Configure general DCB TX parameters*/
2926 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2929 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration\n");
2933 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2935 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2936 if(nb_tcs == ETH_4_TCS) {
2937 /* Avoid un-configured priority mapping to TC0 */
2939 uint8_t mask = 0xFF;
2940 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
2941 mask = (uint8_t)(mask & (~ (1 << map[i])));
2942 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
2943 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
2947 /* Re-configure 4 TCs BW */
2948 for (i = 0; i < nb_tcs; i++) {
2949 tc = &dcb_config->tc_config[i];
2950 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
2951 (uint8_t)(100 / nb_tcs);
2952 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
2953 (uint8_t)(100 / nb_tcs);
2955 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2956 tc = &dcb_config->tc_config[i];
2957 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
2958 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
2963 /* Set RX buffer size */
2964 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2965 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
2966 for (i = 0 ; i < nb_tcs; i++) {
2967 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2969 /* zero alloc all unused TCs */
2970 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2971 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
2975 /* Only support an equally distributed Tx packet buffer strategy. */
2976 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
2977 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
2978 for (i = 0; i < nb_tcs; i++) {
2979 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
2980 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
2982 /* Clear unused TCs, if any, to zero buffer size*/
2983 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2984 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
2985 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
2989 /*Calculates traffic class credits*/
2990 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2991 IXGBE_DCB_TX_CONFIG);
2992 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2993 IXGBE_DCB_RX_CONFIG);
2996 /* Unpack CEE standard containers */
2997 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
2998 ixgbe_dcb_unpack_max_cee(dcb_config, max);
2999 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3000 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3001 /* Configure PG(ETS) RX */
3002 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3006 /* Unpack CEE standard containers */
3007 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3008 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3009 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3010 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3011 /* Configure PG(ETS) TX */
3012 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3015 /*Configure queue statistics registers*/
3016 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3018 /* Check if the PFC is supported */
3019 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3020 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3021 for (i = 0; i < nb_tcs; i++) {
3023 * If the TC count is 8,and the default high_water is 48,
3024 * the low_water is 16 as default.
3026 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3027 hw->fc.low_water[i] = pbsize / 4;
3028 /* Enable pfc for this TC */
3029 tc = &dcb_config->tc_config[i];
3030 tc->pfc = ixgbe_dcb_pfc_enabled;
3032 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3033 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3035 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3042 * ixgbe_configure_dcb - Configure DCB Hardware
3043 * @dev: pointer to rte_eth_dev
3045 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3047 struct ixgbe_dcb_config *dcb_cfg =
3048 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3049 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3051 PMD_INIT_FUNC_TRACE();
3053 /* check support mq_mode for DCB */
3054 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3055 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3058 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3061 /** Configure DCB hardware **/
3062 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3068 * VMDq only support for 10 GbE NIC.
3071 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3073 struct rte_eth_vmdq_rx_conf *cfg;
3074 struct ixgbe_hw *hw;
3075 enum rte_eth_nb_pools num_pools;
3076 uint32_t mrqc, vt_ctl, vlanctrl;
3079 PMD_INIT_FUNC_TRACE();
3080 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3081 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3082 num_pools = cfg->nb_queue_pools;
3084 ixgbe_rss_disable(dev);
3086 /* MRQC: enable vmdq */
3087 mrqc = IXGBE_MRQC_VMDQEN;
3088 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3090 /* PFVTCTL: turn on virtualisation and set the default pool */
3091 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3092 if (cfg->enable_default_pool)
3093 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3095 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3097 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3099 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3100 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3101 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3102 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3104 /* VFTA - enable all vlan filters */
3105 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3106 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3108 /* VFRE: pool enabling for receive - 64 */
3109 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3110 if (num_pools == ETH_64_POOLS)
3111 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3114 * MPSAR - allow pools to read specific mac addresses
3115 * In this case, all pools should be able to read from mac addr 0
3117 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3118 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3120 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3121 for (i = 0; i < cfg->nb_pool_maps; i++) {
3122 /* set vlan id in VF register and set the valid bit */
3123 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3124 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3126 * Put the allowed pools in VFB reg. As we only have 16 or 64
3127 * pools, we only need to use the first half of the register
3130 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3131 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3132 (cfg->pool_map[i].pools & UINT32_MAX));
3134 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3135 ((cfg->pool_map[i].pools >> 32) \
3140 IXGBE_WRITE_FLUSH(hw);
3144 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3145 * @hw: pointer to hardware structure
3148 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3153 PMD_INIT_FUNC_TRACE();
3154 /*PF VF Transmit Enable*/
3155 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3156 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3158 /* Disable the Tx desc arbiter so that MTQC can be changed */
3159 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3160 reg |= IXGBE_RTTDCS_ARBDIS;
3161 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3163 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3164 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3166 /* Disable drop for all queues */
3167 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3168 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3169 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3171 /* Enable the Tx desc arbiter */
3172 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3173 reg &= ~IXGBE_RTTDCS_ARBDIS;
3174 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3176 IXGBE_WRITE_FLUSH(hw);
3182 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
3184 struct igb_rx_entry *rxe = rxq->sw_ring;
3188 /* Initialize software ring entries */
3189 for (i = 0; i < rxq->nb_rx_desc; i++) {
3190 volatile union ixgbe_adv_rx_desc *rxd;
3191 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3193 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u\n",
3194 (unsigned) rxq->queue_id);
3198 rte_mbuf_refcnt_set(mbuf, 1);
3199 mbuf->type = RTE_MBUF_PKT;
3200 mbuf->pkt.next = NULL;
3201 mbuf->pkt.data = (char *)mbuf->buf_addr + RTE_PKTMBUF_HEADROOM;
3202 mbuf->pkt.nb_segs = 1;
3203 mbuf->pkt.in_port = rxq->port_id;
3206 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3207 rxd = &rxq->rx_ring[i];
3208 rxd->read.hdr_addr = dma_addr;
3209 rxd->read.pkt_addr = dma_addr;
3217 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3219 struct ixgbe_hw *hw =
3220 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3222 if (hw->mac.type == ixgbe_mac_82598EB)
3225 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3227 * SRIOV inactive scheme
3228 * any DCB/RSS w/o VMDq multi-queue setting
3230 switch (dev->data->dev_conf.rxmode.mq_mode) {
3232 ixgbe_rss_configure(dev);
3235 case ETH_MQ_RX_VMDQ_DCB:
3236 ixgbe_vmdq_dcb_configure(dev);
3239 case ETH_MQ_RX_VMDQ_ONLY:
3240 ixgbe_vmdq_rx_hw_configure(dev);
3243 case ETH_MQ_RX_NONE:
3244 /* if mq_mode is none, disable rss mode.*/
3245 default: ixgbe_rss_disable(dev);
3248 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3250 * SRIOV active scheme
3251 * FIXME if support DCB/RSS together with VMDq & SRIOV
3254 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQEN);
3258 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT4TCEN);
3262 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT8TCEN);
3265 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3273 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3275 struct ixgbe_hw *hw =
3276 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3280 if (hw->mac.type == ixgbe_mac_82598EB)
3283 /* disable arbiter before setting MTQC */
3284 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3285 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3286 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3288 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3290 * SRIOV inactive scheme
3291 * any DCB w/o VMDq multi-queue setting
3293 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3294 ixgbe_vmdq_tx_hw_configure(hw);
3296 mtqc = IXGBE_MTQC_64Q_1PB;
3297 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3300 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3303 * SRIOV active scheme
3304 * FIXME if support DCB together with VMDq & SRIOV
3307 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3310 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3313 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3317 mtqc = IXGBE_MTQC_64Q_1PB;
3318 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3320 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3323 /* re-enable arbiter */
3324 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3325 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3331 * Initializes Receive Unit.
3334 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3336 struct ixgbe_hw *hw;
3337 struct igb_rx_queue *rxq;
3338 struct rte_pktmbuf_pool_private *mbp_priv;
3351 PMD_INIT_FUNC_TRACE();
3352 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3355 * Make sure receives are disabled while setting
3356 * up the RX context (registers, descriptor rings, etc.).
3358 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3359 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3361 /* Enable receipt of broadcasted frames */
3362 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3363 fctrl |= IXGBE_FCTRL_BAM;
3364 fctrl |= IXGBE_FCTRL_DPF;
3365 fctrl |= IXGBE_FCTRL_PMCF;
3366 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3369 * Configure CRC stripping, if any.
3371 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3372 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3373 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3375 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3378 * Configure jumbo frame support, if any.
3380 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3381 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3382 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3383 maxfrs &= 0x0000FFFF;
3384 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3385 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3387 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3390 * If loopback mode is configured for 82599, set LPBK bit.
3392 if (hw->mac.type == ixgbe_mac_82599EB &&
3393 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3394 hlreg0 |= IXGBE_HLREG0_LPBK;
3396 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3398 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3400 /* Setup RX queues */
3401 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3402 rxq = dev->data->rx_queues[i];
3404 /* Allocate buffers for descriptor rings */
3405 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3410 * Reset crc_len in case it was changed after queue setup by a
3411 * call to configure.
3413 rxq->crc_len = (uint8_t)
3414 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3417 /* Setup the Base and Length of the Rx Descriptor Rings */
3418 bus_addr = rxq->rx_ring_phys_addr;
3419 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3420 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3421 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3422 (uint32_t)(bus_addr >> 32));
3423 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3424 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3425 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3426 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3428 /* Configure the SRRCTL register */
3429 #ifdef RTE_HEADER_SPLIT_ENABLE
3431 * Configure Header Split
3433 if (dev->data->dev_conf.rxmode.header_split) {
3434 if (hw->mac.type == ixgbe_mac_82599EB) {
3435 /* Must setup the PSRTYPE register */
3437 psrtype = IXGBE_PSRTYPE_TCPHDR |
3438 IXGBE_PSRTYPE_UDPHDR |
3439 IXGBE_PSRTYPE_IPV4HDR |
3440 IXGBE_PSRTYPE_IPV6HDR;
3441 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3443 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3444 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3445 IXGBE_SRRCTL_BSIZEHDR_MASK);
3446 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3449 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3451 /* Set if packets are dropped when no descriptors available */
3453 srrctl |= IXGBE_SRRCTL_DROP_EN;
3456 * Configure the RX buffer size in the BSIZEPACKET field of
3457 * the SRRCTL register of the queue.
3458 * The value is in 1 KB resolution. Valid values can be from
3461 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3462 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3463 RTE_PKTMBUF_HEADROOM);
3464 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3465 IXGBE_SRRCTL_BSIZEPKT_MASK);
3466 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3468 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3469 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3471 /* It adds dual VLAN length for supporting dual VLAN */
3472 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3473 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3474 dev->data->scattered_rx = 1;
3475 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3480 * Device configured with multiple RX queues.
3482 ixgbe_dev_mq_rx_configure(dev);
3485 * Setup the Checksum Register.
3486 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3487 * Enable IP/L4 checkum computation by hardware if requested to do so.
3489 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3490 rxcsum |= IXGBE_RXCSUM_PCSD;
3491 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3492 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3494 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3496 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3498 if (hw->mac.type == ixgbe_mac_82599EB) {
3499 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3500 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3501 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3503 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3504 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3505 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3512 * Initializes Transmit Unit.
3515 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3517 struct ixgbe_hw *hw;
3518 struct igb_tx_queue *txq;
3524 PMD_INIT_FUNC_TRACE();
3525 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3527 /* Enable TX CRC (checksum offload requirement) */
3528 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3529 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
3530 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3532 /* Setup the Base and Length of the Tx Descriptor Rings */
3533 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3534 txq = dev->data->tx_queues[i];
3536 bus_addr = txq->tx_ring_phys_addr;
3537 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3538 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3539 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3540 (uint32_t)(bus_addr >> 32));
3541 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3542 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3543 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3544 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3545 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3548 * Disable Tx Head Writeback RO bit, since this hoses
3549 * bookkeeping if things aren't delivered in order.
3551 switch (hw->mac.type) {
3552 case ixgbe_mac_82598EB:
3553 txctrl = IXGBE_READ_REG(hw,
3554 IXGBE_DCA_TXCTRL(txq->reg_idx));
3555 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3556 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3560 case ixgbe_mac_82599EB:
3561 case ixgbe_mac_X540:
3563 txctrl = IXGBE_READ_REG(hw,
3564 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3565 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3566 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3572 /* Device configured with multiple TX queues. */
3573 ixgbe_dev_mq_tx_configure(dev);
3577 * Set up link for 82599 loopback mode Tx->Rx.
3580 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3582 DEBUGFUNC("ixgbe_setup_loopback_link_82599");
3584 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3585 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3587 PMD_INIT_LOG(ERR, "Could not enable loopback mode\n");
3596 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3597 ixgbe_reset_pipeline_82599(hw);
3599 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3605 * Start Transmit and Receive Units.
3608 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3610 struct ixgbe_hw *hw;
3611 struct igb_tx_queue *txq;
3612 struct igb_rx_queue *rxq;
3620 PMD_INIT_FUNC_TRACE();
3621 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3623 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3624 txq = dev->data->tx_queues[i];
3625 /* Setup Transmit Threshold Registers */
3626 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3627 txdctl |= txq->pthresh & 0x7F;
3628 txdctl |= ((txq->hthresh & 0x7F) << 8);
3629 txdctl |= ((txq->wthresh & 0x7F) << 16);
3630 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3633 if (hw->mac.type != ixgbe_mac_82598EB) {
3634 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3635 dmatxctl |= IXGBE_DMATXCTL_TE;
3636 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3639 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3640 txq = dev->data->tx_queues[i];
3641 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3642 txdctl |= IXGBE_TXDCTL_ENABLE;
3643 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3645 /* Wait until TX Enable ready */
3646 if (hw->mac.type == ixgbe_mac_82599EB) {
3650 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3651 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3653 PMD_INIT_LOG(ERR, "Could not enable "
3654 "Tx Queue %d\n", i);
3657 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3658 rxq = dev->data->rx_queues[i];
3659 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3660 rxdctl |= IXGBE_RXDCTL_ENABLE;
3661 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3663 /* Wait until RX Enable ready */
3667 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3668 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3670 PMD_INIT_LOG(ERR, "Could not enable "
3671 "Rx Queue %d\n", i);
3673 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3676 /* Enable Receive engine */
3677 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3678 if (hw->mac.type == ixgbe_mac_82598EB)
3679 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3680 rxctrl |= IXGBE_RXCTRL_RXEN;
3681 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3683 /* If loopback mode is enabled for 82599, set up the link accordingly */
3684 if (hw->mac.type == ixgbe_mac_82599EB &&
3685 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3686 ixgbe_setup_loopback_link_82599(hw);
3692 * [VF] Initializes Receive Unit.
3695 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3697 struct ixgbe_hw *hw;
3698 struct igb_rx_queue *rxq;
3699 struct rte_pktmbuf_pool_private *mbp_priv;
3706 PMD_INIT_FUNC_TRACE();
3707 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3709 /* Setup RX queues */
3710 dev->rx_pkt_burst = ixgbe_recv_pkts;
3711 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3712 rxq = dev->data->rx_queues[i];
3714 /* Allocate buffers for descriptor rings */
3715 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3719 /* Setup the Base and Length of the Rx Descriptor Rings */
3720 bus_addr = rxq->rx_ring_phys_addr;
3722 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3723 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3724 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3725 (uint32_t)(bus_addr >> 32));
3726 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3727 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3728 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3729 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3732 /* Configure the SRRCTL register */
3733 #ifdef RTE_HEADER_SPLIT_ENABLE
3735 * Configure Header Split
3737 if (dev->data->dev_conf.rxmode.header_split) {
3739 /* Must setup the PSRTYPE register */
3741 psrtype = IXGBE_PSRTYPE_TCPHDR |
3742 IXGBE_PSRTYPE_UDPHDR |
3743 IXGBE_PSRTYPE_IPV4HDR |
3744 IXGBE_PSRTYPE_IPV6HDR;
3746 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
3748 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3749 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3750 IXGBE_SRRCTL_BSIZEHDR_MASK);
3751 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3754 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3756 /* Set if packets are dropped when no descriptors available */
3758 srrctl |= IXGBE_SRRCTL_DROP_EN;
3761 * Configure the RX buffer size in the BSIZEPACKET field of
3762 * the SRRCTL register of the queue.
3763 * The value is in 1 KB resolution. Valid values can be from
3766 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3767 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3768 RTE_PKTMBUF_HEADROOM);
3769 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3770 IXGBE_SRRCTL_BSIZEPKT_MASK);
3773 * VF modification to write virtual function SRRCTL register
3775 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
3777 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3778 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3780 /* It adds dual VLAN length for supporting dual VLAN */
3781 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3782 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
3783 dev->data->scattered_rx = 1;
3784 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3792 * [VF] Initializes Transmit Unit.
3795 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
3797 struct ixgbe_hw *hw;
3798 struct igb_tx_queue *txq;
3803 PMD_INIT_FUNC_TRACE();
3804 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3806 /* Setup the Base and Length of the Tx Descriptor Rings */
3807 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3808 txq = dev->data->tx_queues[i];
3809 bus_addr = txq->tx_ring_phys_addr;
3810 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
3811 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3812 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
3813 (uint32_t)(bus_addr >> 32));
3814 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
3815 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3816 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3817 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
3818 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
3821 * Disable Tx Head Writeback RO bit, since this hoses
3822 * bookkeeping if things aren't delivered in order.
3824 txctrl = IXGBE_READ_REG(hw,
3825 IXGBE_VFDCA_TXCTRL(i));
3826 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3827 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
3833 * [VF] Start Transmit and Receive Units.
3836 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
3838 struct ixgbe_hw *hw;
3839 struct igb_tx_queue *txq;
3840 struct igb_rx_queue *rxq;
3846 PMD_INIT_FUNC_TRACE();
3847 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3849 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3850 txq = dev->data->tx_queues[i];
3851 /* Setup Transmit Threshold Registers */
3852 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3853 txdctl |= txq->pthresh & 0x7F;
3854 txdctl |= ((txq->hthresh & 0x7F) << 8);
3855 txdctl |= ((txq->wthresh & 0x7F) << 16);
3856 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
3859 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3861 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3862 txdctl |= IXGBE_TXDCTL_ENABLE;
3863 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
3866 /* Wait until TX Enable ready */
3869 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3870 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3872 PMD_INIT_LOG(ERR, "Could not enable "
3873 "Tx Queue %d\n", i);
3875 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3877 rxq = dev->data->rx_queues[i];
3879 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
3880 rxdctl |= IXGBE_RXDCTL_ENABLE;
3881 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
3883 /* Wait until RX Enable ready */
3887 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
3888 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3890 PMD_INIT_LOG(ERR, "Could not enable "
3891 "Rx Queue %d\n", i);
3893 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);