4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
47 #include <rte_cycles.h>
49 #include <rte_debug.h>
50 #include <rte_interrupts.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_launch.h>
55 #include <rte_tailq.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
80 #include "ixgbe_rxtx.h"
82 #define IXGBE_RSS_OFFLOAD_ALL ( \
88 ETH_RSS_IPV6_TCP_EX | \
93 static inline struct rte_mbuf *
94 rte_rxmbuf_alloc(struct rte_mempool *mp)
98 m = __rte_mbuf_raw_alloc(mp);
99 __rte_mbuf_sanity_check_raw(m, 0);
105 #define RTE_PMD_USE_PREFETCH
108 #ifdef RTE_PMD_USE_PREFETCH
110 * Prefetch a cache line into all cache levels.
112 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
114 #define rte_ixgbe_prefetch(p) do {} while(0)
117 /*********************************************************************
121 **********************************************************************/
124 * Check for descriptors with their DD bit set and free mbufs.
125 * Return the total number of buffers freed.
127 static inline int __attribute__((always_inline))
128 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
130 struct igb_tx_entry *txep;
134 /* check DD bit on threshold descriptor */
135 status = txq->tx_ring[txq->tx_next_dd].wb.status;
136 if (! (status & IXGBE_ADVTXD_STAT_DD))
140 * first buffer to free from S/W ring is at index
141 * tx_next_dd - (tx_rs_thresh-1)
143 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
145 /* free buffers one at a time */
146 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
147 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
148 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
152 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
153 rte_pktmbuf_free_seg(txep->mbuf);
158 /* buffers were freed, update counters */
159 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
160 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
161 if (txq->tx_next_dd >= txq->nb_tx_desc)
162 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
164 return txq->tx_rs_thresh;
167 /* Populate 4 descriptors with data from 4 mbufs */
169 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
171 uint64_t buf_dma_addr;
175 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
176 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
177 pkt_len = (*pkts)->data_len;
179 /* write data to descriptor */
180 txdp->read.buffer_addr = buf_dma_addr;
181 txdp->read.cmd_type_len =
182 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
183 txdp->read.olinfo_status =
184 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
185 rte_prefetch0(&(*pkts)->pool);
189 /* Populate 1 descriptor with data from 1 mbuf */
191 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
193 uint64_t buf_dma_addr;
196 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
197 pkt_len = (*pkts)->data_len;
199 /* write data to descriptor */
200 txdp->read.buffer_addr = buf_dma_addr;
201 txdp->read.cmd_type_len =
202 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
203 txdp->read.olinfo_status =
204 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
205 rte_prefetch0(&(*pkts)->pool);
209 * Fill H/W descriptor ring with mbuf data.
210 * Copy mbuf pointers to the S/W ring.
213 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
216 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
217 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
218 const int N_PER_LOOP = 4;
219 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
220 int mainpart, leftover;
224 * Process most of the packets in chunks of N pkts. Any
225 * leftover packets will get processed one at a time.
227 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
228 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
229 for (i = 0; i < mainpart; i += N_PER_LOOP) {
230 /* Copy N mbuf pointers to the S/W ring */
231 for (j = 0; j < N_PER_LOOP; ++j) {
232 (txep + i + j)->mbuf = *(pkts + i + j);
234 tx4(txdp + i, pkts + i);
237 if (unlikely(leftover > 0)) {
238 for (i = 0; i < leftover; ++i) {
239 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
240 tx1(txdp + mainpart + i, pkts + mainpart + i);
245 static inline uint16_t
246 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
249 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
250 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
254 * Begin scanning the H/W ring for done descriptors when the
255 * number of available descriptors drops below tx_free_thresh. For
256 * each done descriptor, free the associated buffer.
258 if (txq->nb_tx_free < txq->tx_free_thresh)
259 ixgbe_tx_free_bufs(txq);
261 /* Only use descriptors that are available */
262 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
263 if (unlikely(nb_pkts == 0))
266 /* Use exactly nb_pkts descriptors */
267 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
270 * At this point, we know there are enough descriptors in the
271 * ring to transmit all the packets. This assumes that each
272 * mbuf contains a single segment, and that no new offloads
273 * are expected, which would require a new context descriptor.
277 * See if we're going to wrap-around. If so, handle the top
278 * of the descriptor ring first, then do the bottom. If not,
279 * the processing looks just like the "bottom" part anyway...
281 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
282 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
283 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
286 * We know that the last descriptor in the ring will need to
287 * have its RS bit set because tx_rs_thresh has to be
288 * a divisor of the ring size
290 tx_r[txq->tx_next_rs].read.cmd_type_len |=
291 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
292 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
297 /* Fill H/W descriptor ring with mbuf data */
298 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
299 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
302 * Determine if RS bit should be set
303 * This is what we actually want:
304 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
305 * but instead of subtracting 1 and doing >=, we can just do
306 * greater than without subtracting.
308 if (txq->tx_tail > txq->tx_next_rs) {
309 tx_r[txq->tx_next_rs].read.cmd_type_len |=
310 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
311 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
313 if (txq->tx_next_rs >= txq->nb_tx_desc)
314 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
318 * Check for wrap-around. This would only happen if we used
319 * up to the last descriptor in the ring, no more, no less.
321 if (txq->tx_tail >= txq->nb_tx_desc)
324 /* update tail pointer */
326 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
332 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
337 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
338 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
339 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
341 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
345 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
346 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
347 nb_tx = (uint16_t)(nb_tx + ret);
348 nb_pkts = (uint16_t)(nb_pkts - ret);
357 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
358 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
359 uint64_t ol_flags, uint32_t vlan_macip_lens)
361 uint32_t type_tucmd_mlhl;
362 uint32_t mss_l4len_idx;
366 ctx_idx = txq->ctx_curr;
370 if (ol_flags & PKT_TX_VLAN_PKT) {
371 cmp_mask |= TX_VLAN_CMP_MASK;
374 if (ol_flags & PKT_TX_IP_CKSUM) {
375 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
376 cmp_mask |= TX_MAC_LEN_CMP_MASK;
379 /* Specify which HW CTX to upload. */
380 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
381 switch (ol_flags & PKT_TX_L4_MASK) {
382 case PKT_TX_UDP_CKSUM:
383 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
384 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
385 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
386 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
388 case PKT_TX_TCP_CKSUM:
389 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
390 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
391 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
392 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
394 case PKT_TX_SCTP_CKSUM:
395 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
396 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
397 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
398 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
401 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
402 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
406 txq->ctx_cache[ctx_idx].flags = ol_flags;
407 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
408 txq->ctx_cache[ctx_idx].vlan_macip_lens.data =
409 vlan_macip_lens & cmp_mask;
411 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
412 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
413 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
414 ctx_txd->seqnum_seed = 0;
418 * Check which hardware context can be used. Use the existing match
419 * or create a new context descriptor.
421 static inline uint32_t
422 what_advctx_update(struct igb_tx_queue *txq, uint64_t flags,
423 uint32_t vlan_macip_lens)
425 /* If match with the current used context */
426 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
427 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
428 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
429 return txq->ctx_curr;
432 /* What if match with the next context */
434 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
435 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
436 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
437 return txq->ctx_curr;
440 /* Mismatch, use the previous context */
441 return (IXGBE_CTX_NUM);
444 static inline uint32_t
445 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
447 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
448 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
451 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
452 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
456 static inline uint32_t
457 tx_desc_vlan_flags_to_cmdtype(uint64_t ol_flags)
459 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
460 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
463 /* Default RS bit threshold values */
464 #ifndef DEFAULT_TX_RS_THRESH
465 #define DEFAULT_TX_RS_THRESH 32
467 #ifndef DEFAULT_TX_FREE_THRESH
468 #define DEFAULT_TX_FREE_THRESH 32
471 /* Reset transmit descriptors after they have been used */
473 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
475 struct igb_tx_entry *sw_ring = txq->sw_ring;
476 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
477 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
478 uint16_t nb_tx_desc = txq->nb_tx_desc;
479 uint16_t desc_to_clean_to;
480 uint16_t nb_tx_to_clean;
482 /* Determine the last descriptor needing to be cleaned */
483 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
484 if (desc_to_clean_to >= nb_tx_desc)
485 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
487 /* Check to make sure the last descriptor to clean is done */
488 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
489 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
491 PMD_TX_FREE_LOG(DEBUG,
492 "TX descriptor %4u is not done"
493 "(port=%d queue=%d)",
495 txq->port_id, txq->queue_id);
496 /* Failed to clean any descriptors, better luck next time */
500 /* Figure out how many descriptors will be cleaned */
501 if (last_desc_cleaned > desc_to_clean_to)
502 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
505 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
508 PMD_TX_FREE_LOG(DEBUG,
509 "Cleaning %4u TX descriptors: %4u to %4u "
510 "(port=%d queue=%d)",
511 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
512 txq->port_id, txq->queue_id);
515 * The last descriptor to clean is done, so that means all the
516 * descriptors from the last descriptor that was cleaned
517 * up to the last descriptor with the RS bit set
518 * are done. Only reset the threshold descriptor.
520 txr[desc_to_clean_to].wb.status = 0;
522 /* Update the txq to reflect the last descriptor that was cleaned */
523 txq->last_desc_cleaned = desc_to_clean_to;
524 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
531 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
534 struct igb_tx_queue *txq;
535 struct igb_tx_entry *sw_ring;
536 struct igb_tx_entry *txe, *txn;
537 volatile union ixgbe_adv_tx_desc *txr;
538 volatile union ixgbe_adv_tx_desc *txd;
539 struct rte_mbuf *tx_pkt;
540 struct rte_mbuf *m_seg;
541 union ixgbe_vlan_macip vlan_macip_lens;
542 uint64_t buf_dma_addr;
543 uint32_t olinfo_status;
544 uint32_t cmd_type_len;
557 sw_ring = txq->sw_ring;
559 tx_id = txq->tx_tail;
560 txe = &sw_ring[tx_id];
562 /* Determine if the descriptor ring needs to be cleaned. */
563 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
564 ixgbe_xmit_cleanup(txq);
568 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
571 pkt_len = tx_pkt->pkt_len;
573 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
576 * Determine how many (if any) context descriptors
577 * are needed for offload functionality.
579 ol_flags = tx_pkt->ol_flags;
580 vlan_macip_lens.f.vlan_tci = tx_pkt->vlan_tci;
581 vlan_macip_lens.f.l2_l3_len = tx_pkt->l2_l3_len;
583 /* If hardware offload required */
584 tx_ol_req = ol_flags & PKT_TX_OFFLOAD_MASK;
586 /* If new context need be built or reuse the exist ctx. */
587 ctx = what_advctx_update(txq, tx_ol_req,
588 vlan_macip_lens.data);
589 /* Only allocate context descriptor if required*/
590 new_ctx = (ctx == IXGBE_CTX_NUM);
595 * Keep track of how many descriptors are used this loop
596 * This will always be the number of segments + the number of
597 * Context descriptors required to transmit the packet
599 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
602 * The number of descriptors that must be allocated for a
603 * packet is the number of segments of that packet, plus 1
604 * Context Descriptor for the hardware offload, if any.
605 * Determine the last TX descriptor to allocate in the TX ring
606 * for the packet, starting from the current position (tx_id)
609 tx_last = (uint16_t) (tx_id + nb_used - 1);
612 if (tx_last >= txq->nb_tx_desc)
613 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
615 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
616 " tx_first=%u tx_last=%u\n",
617 (unsigned) txq->port_id,
618 (unsigned) txq->queue_id,
624 * Make sure there are enough TX descriptors available to
625 * transmit the entire packet.
626 * nb_used better be less than or equal to txq->tx_rs_thresh
628 if (nb_used > txq->nb_tx_free) {
629 PMD_TX_FREE_LOG(DEBUG,
630 "Not enough free TX descriptors "
631 "nb_used=%4u nb_free=%4u "
632 "(port=%d queue=%d)",
633 nb_used, txq->nb_tx_free,
634 txq->port_id, txq->queue_id);
636 if (ixgbe_xmit_cleanup(txq) != 0) {
637 /* Could not clean any descriptors */
643 /* nb_used better be <= txq->tx_rs_thresh */
644 if (unlikely(nb_used > txq->tx_rs_thresh)) {
645 PMD_TX_FREE_LOG(DEBUG,
646 "The number of descriptors needed to "
647 "transmit the packet exceeds the "
648 "RS bit threshold. This will impact "
650 "nb_used=%4u nb_free=%4u "
652 "(port=%d queue=%d)",
653 nb_used, txq->nb_tx_free,
655 txq->port_id, txq->queue_id);
657 * Loop here until there are enough TX
658 * descriptors or until the ring cannot be
661 while (nb_used > txq->nb_tx_free) {
662 if (ixgbe_xmit_cleanup(txq) != 0) {
664 * Could not clean any
676 * By now there are enough free TX descriptors to transmit
681 * Set common flags of all TX Data Descriptors.
683 * The following bits must be set in all Data Descriptors:
684 * - IXGBE_ADVTXD_DTYP_DATA
685 * - IXGBE_ADVTXD_DCMD_DEXT
687 * The following bits must be set in the first Data Descriptor
688 * and are ignored in the other ones:
689 * - IXGBE_ADVTXD_DCMD_IFCS
690 * - IXGBE_ADVTXD_MAC_1588
691 * - IXGBE_ADVTXD_DCMD_VLE
693 * The following bits must only be set in the last Data
695 * - IXGBE_TXD_CMD_EOP
697 * The following bits can be set in any Data Descriptor, but
698 * are only set in the last Data Descriptor:
701 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
702 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
703 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
704 #ifdef RTE_LIBRTE_IEEE1588
705 if (ol_flags & PKT_TX_IEEE1588_TMST)
706 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
711 * Setup the TX Advanced Context Descriptor if required
714 volatile struct ixgbe_adv_tx_context_desc *
717 ctx_txd = (volatile struct
718 ixgbe_adv_tx_context_desc *)
721 txn = &sw_ring[txe->next_id];
722 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
724 if (txe->mbuf != NULL) {
725 rte_pktmbuf_free_seg(txe->mbuf);
729 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
730 vlan_macip_lens.data);
732 txe->last_id = tx_last;
733 tx_id = txe->next_id;
738 * Setup the TX Advanced Data Descriptor,
739 * This path will go through
740 * whatever new/reuse the context descriptor
742 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
743 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
744 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
750 txn = &sw_ring[txe->next_id];
752 if (txe->mbuf != NULL)
753 rte_pktmbuf_free_seg(txe->mbuf);
757 * Set up Transmit Data Descriptor.
759 slen = m_seg->data_len;
760 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
761 txd->read.buffer_addr =
762 rte_cpu_to_le_64(buf_dma_addr);
763 txd->read.cmd_type_len =
764 rte_cpu_to_le_32(cmd_type_len | slen);
765 txd->read.olinfo_status =
766 rte_cpu_to_le_32(olinfo_status);
767 txe->last_id = tx_last;
768 tx_id = txe->next_id;
771 } while (m_seg != NULL);
774 * The last packet data descriptor needs End Of Packet (EOP)
776 cmd_type_len |= IXGBE_TXD_CMD_EOP;
777 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
778 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
780 /* Set RS bit only on threshold packets' last descriptor */
781 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
782 PMD_TX_FREE_LOG(DEBUG,
783 "Setting RS bit on TXD id="
784 "%4u (port=%d queue=%d)",
785 tx_last, txq->port_id, txq->queue_id);
787 cmd_type_len |= IXGBE_TXD_CMD_RS;
789 /* Update txq RS bit counters */
792 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
798 * Set the Transmit Descriptor Tail (TDT)
800 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
801 (unsigned) txq->port_id, (unsigned) txq->queue_id,
802 (unsigned) tx_id, (unsigned) nb_tx);
803 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
804 txq->tx_tail = tx_id;
809 /*********************************************************************
813 **********************************************************************/
814 static inline uint64_t
815 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
819 static uint64_t ip_pkt_types_map[16] = {
820 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
821 PKT_RX_IPV6_HDR, 0, 0, 0,
822 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
823 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
826 static uint64_t ip_rss_types_map[16] = {
827 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
828 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
829 PKT_RX_RSS_HASH, 0, 0, 0,
830 0, 0, 0, PKT_RX_FDIR,
833 #ifdef RTE_LIBRTE_IEEE1588
834 static uint32_t ip_pkt_etqf_map[8] = {
835 0, 0, 0, PKT_RX_IEEE1588_PTP,
839 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
840 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
841 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
843 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
844 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
847 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
850 static inline uint64_t
851 rx_desc_status_to_pkt_flags(uint32_t rx_status)
856 * Check if VLAN present only.
857 * Do not check whether L3/L4 rx checksum done by NIC or not,
858 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
860 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
862 #ifdef RTE_LIBRTE_IEEE1588
863 if (rx_status & IXGBE_RXD_STAT_TMST)
864 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
869 static inline uint64_t
870 rx_desc_error_to_pkt_flags(uint32_t rx_status)
873 * Bit 31: IPE, IPv4 checksum error
874 * Bit 30: L4I, L4I integrity error
876 static uint64_t error_to_pkt_flags_map[4] = {
877 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
878 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
880 return error_to_pkt_flags_map[(rx_status >>
881 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
884 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
886 * LOOK_AHEAD defines how many desc statuses to check beyond the
887 * current descriptor.
888 * It must be a pound define for optimal performance.
889 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
890 * function only works with LOOK_AHEAD=8.
893 #if (LOOK_AHEAD != 8)
894 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
897 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
899 volatile union ixgbe_adv_rx_desc *rxdp;
900 struct igb_rx_entry *rxep;
903 int s[LOOK_AHEAD], nb_dd;
907 /* get references to current descriptor and S/W ring entry */
908 rxdp = &rxq->rx_ring[rxq->rx_tail];
909 rxep = &rxq->sw_ring[rxq->rx_tail];
911 /* check to make sure there is at least 1 packet to receive */
912 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
916 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
917 * reference packets that are ready to be received.
919 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
920 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
922 /* Read desc statuses backwards to avoid race condition */
923 for (j = LOOK_AHEAD-1; j >= 0; --j)
924 s[j] = rxdp[j].wb.upper.status_error;
926 /* Compute how many status bits were set */
928 for (j = 0; j < LOOK_AHEAD; ++j)
929 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
933 /* Translate descriptor info to mbuf format */
934 for (j = 0; j < nb_dd; ++j) {
936 pkt_len = (uint16_t)(rxdp[j].wb.upper.length -
938 mb->data_len = pkt_len;
939 mb->pkt_len = pkt_len;
940 mb->vlan_tci = rxdp[j].wb.upper.vlan;
941 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
943 /* convert descriptor fields to rte mbuf flags */
944 mb->ol_flags = rx_desc_hlen_type_rss_to_pkt_flags(
945 rxdp[j].wb.lower.lo_dword.data);
946 /* reuse status field from scan list */
947 mb->ol_flags = mb->ol_flags |
948 rx_desc_status_to_pkt_flags(s[j]);
949 mb->ol_flags = mb->ol_flags |
950 rx_desc_error_to_pkt_flags(s[j]);
953 /* Move mbuf pointers from the S/W ring to the stage */
954 for (j = 0; j < LOOK_AHEAD; ++j) {
955 rxq->rx_stage[i + j] = rxep[j].mbuf;
958 /* stop if all requested packets could not be received */
959 if (nb_dd != LOOK_AHEAD)
963 /* clear software ring entries so we can cleanup correctly */
964 for (i = 0; i < nb_rx; ++i) {
965 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
973 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
975 volatile union ixgbe_adv_rx_desc *rxdp;
976 struct igb_rx_entry *rxep;
982 /* allocate buffers in bulk directly into the S/W ring */
983 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
984 (rxq->rx_free_thresh - 1));
985 rxep = &rxq->sw_ring[alloc_idx];
986 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
987 rxq->rx_free_thresh);
988 if (unlikely(diag != 0))
991 rxdp = &rxq->rx_ring[alloc_idx];
992 for (i = 0; i < rxq->rx_free_thresh; ++i) {
993 /* populate the static rte mbuf fields */
995 rte_mbuf_refcnt_set(mb, 1);
997 mb->data_off = RTE_PKTMBUF_HEADROOM;
999 mb->port = rxq->port_id;
1001 /* populate the descriptors */
1002 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1003 rxdp[i].read.hdr_addr = dma_addr;
1004 rxdp[i].read.pkt_addr = dma_addr;
1007 /* update tail pointer */
1009 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1011 /* update state of internal queue structure */
1012 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1013 rxq->rx_free_thresh);
1014 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1015 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1021 static inline uint16_t
1022 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1025 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1028 /* how many packets are ready to return? */
1029 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1031 /* copy mbuf pointers to the application's packet list */
1032 for (i = 0; i < nb_pkts; ++i)
1033 rx_pkts[i] = stage[i];
1035 /* update internal queue state */
1036 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1037 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1042 static inline uint16_t
1043 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1046 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1049 /* Any previously recv'd pkts will be returned from the Rx stage */
1050 if (rxq->rx_nb_avail)
1051 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1053 /* Scan the H/W ring for packets to receive */
1054 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1056 /* update internal queue state */
1057 rxq->rx_next_avail = 0;
1058 rxq->rx_nb_avail = nb_rx;
1059 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1061 /* if required, allocate new buffers to replenish descriptors */
1062 if (rxq->rx_tail > rxq->rx_free_trigger) {
1063 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1065 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1066 "queue_id=%u\n", (unsigned) rxq->port_id,
1067 (unsigned) rxq->queue_id);
1069 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1070 rxq->rx_free_thresh;
1073 * Need to rewind any previous receives if we cannot
1074 * allocate new buffers to replenish the old ones.
1076 rxq->rx_nb_avail = 0;
1077 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1078 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1079 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1085 if (rxq->rx_tail >= rxq->nb_rx_desc)
1088 /* received any packets this loop? */
1089 if (rxq->rx_nb_avail)
1090 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1095 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1097 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1102 if (unlikely(nb_pkts == 0))
1105 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1106 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1108 /* request is relatively large, chunk it up */
1112 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1113 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1114 nb_rx = (uint16_t)(nb_rx + ret);
1115 nb_pkts = (uint16_t)(nb_pkts - ret);
1122 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1125 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1128 struct igb_rx_queue *rxq;
1129 volatile union ixgbe_adv_rx_desc *rx_ring;
1130 volatile union ixgbe_adv_rx_desc *rxdp;
1131 struct igb_rx_entry *sw_ring;
1132 struct igb_rx_entry *rxe;
1133 struct rte_mbuf *rxm;
1134 struct rte_mbuf *nmb;
1135 union ixgbe_adv_rx_desc rxd;
1138 uint32_t hlen_type_rss;
1148 rx_id = rxq->rx_tail;
1149 rx_ring = rxq->rx_ring;
1150 sw_ring = rxq->sw_ring;
1151 while (nb_rx < nb_pkts) {
1153 * The order of operations here is important as the DD status
1154 * bit must not be read after any other descriptor fields.
1155 * rx_ring and rxdp are pointing to volatile data so the order
1156 * of accesses cannot be reordered by the compiler. If they were
1157 * not volatile, they could be reordered which could lead to
1158 * using invalid descriptor fields when read from rxd.
1160 rxdp = &rx_ring[rx_id];
1161 staterr = rxdp->wb.upper.status_error;
1162 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1169 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1170 * is likely to be invalid and to be dropped by the various
1171 * validation checks performed by the network stack.
1173 * Allocate a new mbuf to replenish the RX ring descriptor.
1174 * If the allocation fails:
1175 * - arrange for that RX descriptor to be the first one
1176 * being parsed the next time the receive function is
1177 * invoked [on the same queue].
1179 * - Stop parsing the RX ring and return immediately.
1181 * This policy do not drop the packet received in the RX
1182 * descriptor for which the allocation of a new mbuf failed.
1183 * Thus, it allows that packet to be later retrieved if
1184 * mbuf have been freed in the mean time.
1185 * As a side effect, holding RX descriptors instead of
1186 * systematically giving them back to the NIC may lead to
1187 * RX ring exhaustion situations.
1188 * However, the NIC can gracefully prevent such situations
1189 * to happen by sending specific "back-pressure" flow control
1190 * frames to its peer(s).
1192 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1193 "ext_err_stat=0x%08x pkt_len=%u\n",
1194 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1195 (unsigned) rx_id, (unsigned) staterr,
1196 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1198 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1200 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1201 "queue_id=%u\n", (unsigned) rxq->port_id,
1202 (unsigned) rxq->queue_id);
1203 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1208 rxe = &sw_ring[rx_id];
1210 if (rx_id == rxq->nb_rx_desc)
1213 /* Prefetch next mbuf while processing current one. */
1214 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1217 * When next RX descriptor is on a cache-line boundary,
1218 * prefetch the next 4 RX descriptors and the next 8 pointers
1221 if ((rx_id & 0x3) == 0) {
1222 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1223 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1229 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1230 rxdp->read.hdr_addr = dma_addr;
1231 rxdp->read.pkt_addr = dma_addr;
1234 * Initialize the returned mbuf.
1235 * 1) setup generic mbuf fields:
1236 * - number of segments,
1239 * - RX port identifier.
1240 * 2) integrate hardware offload data, if any:
1241 * - RSS flag & hash,
1242 * - IP checksum flag,
1243 * - VLAN TCI, if any,
1246 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1248 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1249 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1252 rxm->pkt_len = pkt_len;
1253 rxm->data_len = pkt_len;
1254 rxm->port = rxq->port_id;
1256 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1257 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1258 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1260 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1261 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1262 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1263 rxm->ol_flags = pkt_flags;
1265 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1266 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1267 else if (pkt_flags & PKT_RX_FDIR) {
1268 rxm->hash.fdir.hash =
1269 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1270 & IXGBE_ATR_HASH_MASK);
1271 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1274 * Store the mbuf address into the next entry of the array
1275 * of returned packets.
1277 rx_pkts[nb_rx++] = rxm;
1279 rxq->rx_tail = rx_id;
1282 * If the number of free RX descriptors is greater than the RX free
1283 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1285 * Update the RDT with the value of the last processed RX descriptor
1286 * minus 1, to guarantee that the RDT register is never equal to the
1287 * RDH register, which creates a "full" ring situtation from the
1288 * hardware point of view...
1290 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1291 if (nb_hold > rxq->rx_free_thresh) {
1292 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1293 "nb_hold=%u nb_rx=%u\n",
1294 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1295 (unsigned) rx_id, (unsigned) nb_hold,
1297 rx_id = (uint16_t) ((rx_id == 0) ?
1298 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1299 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1302 rxq->nb_rx_hold = nb_hold;
1307 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1310 struct igb_rx_queue *rxq;
1311 volatile union ixgbe_adv_rx_desc *rx_ring;
1312 volatile union ixgbe_adv_rx_desc *rxdp;
1313 struct igb_rx_entry *sw_ring;
1314 struct igb_rx_entry *rxe;
1315 struct rte_mbuf *first_seg;
1316 struct rte_mbuf *last_seg;
1317 struct rte_mbuf *rxm;
1318 struct rte_mbuf *nmb;
1319 union ixgbe_adv_rx_desc rxd;
1320 uint64_t dma; /* Physical address of mbuf data buffer */
1322 uint32_t hlen_type_rss;
1332 rx_id = rxq->rx_tail;
1333 rx_ring = rxq->rx_ring;
1334 sw_ring = rxq->sw_ring;
1337 * Retrieve RX context of current packet, if any.
1339 first_seg = rxq->pkt_first_seg;
1340 last_seg = rxq->pkt_last_seg;
1342 while (nb_rx < nb_pkts) {
1345 * The order of operations here is important as the DD status
1346 * bit must not be read after any other descriptor fields.
1347 * rx_ring and rxdp are pointing to volatile data so the order
1348 * of accesses cannot be reordered by the compiler. If they were
1349 * not volatile, they could be reordered which could lead to
1350 * using invalid descriptor fields when read from rxd.
1352 rxdp = &rx_ring[rx_id];
1353 staterr = rxdp->wb.upper.status_error;
1354 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1361 * Allocate a new mbuf to replenish the RX ring descriptor.
1362 * If the allocation fails:
1363 * - arrange for that RX descriptor to be the first one
1364 * being parsed the next time the receive function is
1365 * invoked [on the same queue].
1367 * - Stop parsing the RX ring and return immediately.
1369 * This policy does not drop the packet received in the RX
1370 * descriptor for which the allocation of a new mbuf failed.
1371 * Thus, it allows that packet to be later retrieved if
1372 * mbuf have been freed in the mean time.
1373 * As a side effect, holding RX descriptors instead of
1374 * systematically giving them back to the NIC may lead to
1375 * RX ring exhaustion situations.
1376 * However, the NIC can gracefully prevent such situations
1377 * to happen by sending specific "back-pressure" flow control
1378 * frames to its peer(s).
1380 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
1381 "staterr=0x%x data_len=%u\n",
1382 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1383 (unsigned) rx_id, (unsigned) staterr,
1384 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1386 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1388 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1389 "queue_id=%u\n", (unsigned) rxq->port_id,
1390 (unsigned) rxq->queue_id);
1391 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1396 rxe = &sw_ring[rx_id];
1398 if (rx_id == rxq->nb_rx_desc)
1401 /* Prefetch next mbuf while processing current one. */
1402 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1405 * When next RX descriptor is on a cache-line boundary,
1406 * prefetch the next 4 RX descriptors and the next 8 pointers
1409 if ((rx_id & 0x3) == 0) {
1410 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1411 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1415 * Update RX descriptor with the physical address of the new
1416 * data buffer of the new allocated mbuf.
1420 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1421 rxdp->read.hdr_addr = dma;
1422 rxdp->read.pkt_addr = dma;
1425 * Set data length & data buffer address of mbuf.
1427 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1428 rxm->data_len = data_len;
1429 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1432 * If this is the first buffer of the received packet,
1433 * set the pointer to the first mbuf of the packet and
1434 * initialize its context.
1435 * Otherwise, update the total length and the number of segments
1436 * of the current scattered packet, and update the pointer to
1437 * the last mbuf of the current packet.
1439 if (first_seg == NULL) {
1441 first_seg->pkt_len = data_len;
1442 first_seg->nb_segs = 1;
1444 first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
1446 first_seg->nb_segs++;
1447 last_seg->next = rxm;
1451 * If this is not the last buffer of the received packet,
1452 * update the pointer to the last mbuf of the current scattered
1453 * packet and continue to parse the RX ring.
1455 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1461 * This is the last buffer of the received packet.
1462 * If the CRC is not stripped by the hardware:
1463 * - Subtract the CRC length from the total packet length.
1464 * - If the last buffer only contains the whole CRC or a part
1465 * of it, free the mbuf associated to the last buffer.
1466 * If part of the CRC is also contained in the previous
1467 * mbuf, subtract the length of that CRC part from the
1468 * data length of the previous mbuf.
1471 if (unlikely(rxq->crc_len > 0)) {
1472 first_seg->pkt_len -= ETHER_CRC_LEN;
1473 if (data_len <= ETHER_CRC_LEN) {
1474 rte_pktmbuf_free_seg(rxm);
1475 first_seg->nb_segs--;
1476 last_seg->data_len = (uint16_t)
1477 (last_seg->data_len -
1478 (ETHER_CRC_LEN - data_len));
1479 last_seg->next = NULL;
1482 (uint16_t) (data_len - ETHER_CRC_LEN);
1486 * Initialize the first mbuf of the returned packet:
1487 * - RX port identifier,
1488 * - hardware offload data, if any:
1489 * - RSS flag & hash,
1490 * - IP checksum flag,
1491 * - VLAN TCI, if any,
1494 first_seg->port = rxq->port_id;
1497 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1498 * set in the pkt_flags field.
1500 first_seg->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1501 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1502 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1503 pkt_flags = (uint16_t)(pkt_flags |
1504 rx_desc_status_to_pkt_flags(staterr));
1505 pkt_flags = (uint16_t)(pkt_flags |
1506 rx_desc_error_to_pkt_flags(staterr));
1507 first_seg->ol_flags = pkt_flags;
1509 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1510 first_seg->hash.rss = rxd.wb.lower.hi_dword.rss;
1511 else if (pkt_flags & PKT_RX_FDIR) {
1512 first_seg->hash.fdir.hash =
1513 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1514 & IXGBE_ATR_HASH_MASK);
1515 first_seg->hash.fdir.id =
1516 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1519 /* Prefetch data of first segment, if configured to do so. */
1520 rte_packet_prefetch((char *)first_seg->buf_addr +
1521 first_seg->data_off);
1524 * Store the mbuf address into the next entry of the array
1525 * of returned packets.
1527 rx_pkts[nb_rx++] = first_seg;
1530 * Setup receipt context for a new packet.
1536 * Record index of the next RX descriptor to probe.
1538 rxq->rx_tail = rx_id;
1541 * Save receive context.
1543 rxq->pkt_first_seg = first_seg;
1544 rxq->pkt_last_seg = last_seg;
1547 * If the number of free RX descriptors is greater than the RX free
1548 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1550 * Update the RDT with the value of the last processed RX descriptor
1551 * minus 1, to guarantee that the RDT register is never equal to the
1552 * RDH register, which creates a "full" ring situtation from the
1553 * hardware point of view...
1555 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1556 if (nb_hold > rxq->rx_free_thresh) {
1557 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1558 "nb_hold=%u nb_rx=%u\n",
1559 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1560 (unsigned) rx_id, (unsigned) nb_hold,
1562 rx_id = (uint16_t) ((rx_id == 0) ?
1563 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1564 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1567 rxq->nb_rx_hold = nb_hold;
1571 /*********************************************************************
1573 * Queue management functions
1575 **********************************************************************/
1578 * Rings setup and release.
1580 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1581 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1582 * also optimize cache line size effect. H/W supports up to cache line size 128.
1584 #define IXGBE_ALIGN 128
1587 * Maximum number of Ring Descriptors.
1589 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1590 * descriptors should meet the following condition:
1591 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1593 #define IXGBE_MIN_RING_DESC 32
1594 #define IXGBE_MAX_RING_DESC 4096
1597 * Create memzone for HW rings. malloc can't be used as the physical address is
1598 * needed. If the memzone is already created, then this function returns a ptr
1601 static const struct rte_memzone *
1602 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1603 uint16_t queue_id, uint32_t ring_size, int socket_id)
1605 char z_name[RTE_MEMZONE_NAMESIZE];
1606 const struct rte_memzone *mz;
1608 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1609 dev->driver->pci_drv.name, ring_name,
1610 dev->data->port_id, queue_id);
1612 mz = rte_memzone_lookup(z_name);
1616 #ifdef RTE_LIBRTE_XEN_DOM0
1617 return rte_memzone_reserve_bounded(z_name, ring_size,
1618 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1620 return rte_memzone_reserve_aligned(z_name, ring_size,
1621 socket_id, 0, IXGBE_ALIGN);
1626 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1630 if (txq->sw_ring != NULL) {
1631 for (i = 0; i < txq->nb_tx_desc; i++) {
1632 if (txq->sw_ring[i].mbuf != NULL) {
1633 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1634 txq->sw_ring[i].mbuf = NULL;
1641 ixgbe_tx_free_swring(struct igb_tx_queue *txq)
1644 txq->sw_ring != NULL)
1645 rte_free(txq->sw_ring);
1649 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1651 if (txq != NULL && txq->ops != NULL) {
1652 txq->ops->release_mbufs(txq);
1653 txq->ops->free_swring(txq);
1659 ixgbe_dev_tx_queue_release(void *txq)
1661 ixgbe_tx_queue_release(txq);
1664 /* (Re)set dynamic igb_tx_queue fields to defaults */
1666 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1668 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1670 struct igb_tx_entry *txe = txq->sw_ring;
1673 /* Zero out HW ring memory */
1674 for (i = 0; i < txq->nb_tx_desc; i++) {
1675 txq->tx_ring[i] = zeroed_desc;
1678 /* Initialize SW ring entries */
1679 prev = (uint16_t) (txq->nb_tx_desc - 1);
1680 for (i = 0; i < txq->nb_tx_desc; i++) {
1681 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1682 txd->wb.status = IXGBE_TXD_STAT_DD;
1685 txe[prev].next_id = i;
1689 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1690 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1693 txq->nb_tx_used = 0;
1695 * Always allow 1 descriptor to be un-allocated to avoid
1696 * a H/W race condition
1698 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1699 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1701 memset((void*)&txq->ctx_cache, 0,
1702 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1705 static struct ixgbe_txq_ops def_txq_ops = {
1706 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1707 .free_swring = ixgbe_tx_free_swring,
1708 .reset = ixgbe_reset_tx_queue,
1712 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1715 unsigned int socket_id,
1716 const struct rte_eth_txconf *tx_conf)
1718 const struct rte_memzone *tz;
1719 struct igb_tx_queue *txq;
1720 struct ixgbe_hw *hw;
1721 uint16_t tx_rs_thresh, tx_free_thresh;
1723 PMD_INIT_FUNC_TRACE();
1724 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1727 * Validate number of transmit descriptors.
1728 * It must not exceed hardware maximum, and must be multiple
1731 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1732 (nb_desc > IXGBE_MAX_RING_DESC) ||
1733 (nb_desc < IXGBE_MIN_RING_DESC)) {
1738 * The following two parameters control the setting of the RS bit on
1739 * transmit descriptors.
1740 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1741 * descriptors have been used.
1742 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1743 * descriptors are used or if the number of descriptors required
1744 * to transmit a packet is greater than the number of free TX
1746 * The following constraints must be satisfied:
1747 * tx_rs_thresh must be greater than 0.
1748 * tx_rs_thresh must be less than the size of the ring minus 2.
1749 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1750 * tx_rs_thresh must be a divisor of the ring size.
1751 * tx_free_thresh must be greater than 0.
1752 * tx_free_thresh must be less than the size of the ring minus 3.
1753 * One descriptor in the TX ring is used as a sentinel to avoid a
1754 * H/W race condition, hence the maximum threshold constraints.
1755 * When set to zero use default values.
1757 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1758 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1759 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1760 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1761 if (tx_rs_thresh >= (nb_desc - 2)) {
1762 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the number "
1763 "of TX descriptors minus 2. (tx_rs_thresh=%u port=%d "
1764 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1765 (int)dev->data->port_id, (int)queue_idx);
1768 if (tx_free_thresh >= (nb_desc - 3)) {
1769 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the "
1770 "tx_free_thresh must be less than the number of TX "
1771 "descriptors minus 3. (tx_free_thresh=%u port=%d "
1772 "queue=%d)\n", (unsigned int)tx_free_thresh,
1773 (int)dev->data->port_id, (int)queue_idx);
1776 if (tx_rs_thresh > tx_free_thresh) {
1777 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than or equal to "
1778 "tx_free_thresh. (tx_free_thresh=%u tx_rs_thresh=%u "
1779 "port=%d queue=%d)\n", (unsigned int)tx_free_thresh,
1780 (unsigned int)tx_rs_thresh, (int)dev->data->port_id,
1784 if ((nb_desc % tx_rs_thresh) != 0) {
1785 RTE_LOG(ERR, PMD, "tx_rs_thresh must be a divisor of the "
1786 "number of TX descriptors. (tx_rs_thresh=%u port=%d "
1787 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1788 (int)dev->data->port_id, (int)queue_idx);
1793 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1794 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1795 * by the NIC and all descriptors are written back after the NIC
1796 * accumulates WTHRESH descriptors.
1798 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1799 RTE_LOG(ERR, PMD, "TX WTHRESH must be set to 0 if "
1800 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1801 "port=%d queue=%d)\n", (unsigned int)tx_rs_thresh,
1802 (int)dev->data->port_id, (int)queue_idx);
1806 /* Free memory prior to re-allocation if needed... */
1807 if (dev->data->tx_queues[queue_idx] != NULL) {
1808 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1809 dev->data->tx_queues[queue_idx] = NULL;
1812 /* First allocate the tx queue data structure */
1813 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct igb_tx_queue),
1814 CACHE_LINE_SIZE, socket_id);
1819 * Allocate TX ring hardware descriptors. A memzone large enough to
1820 * handle the maximum ring size is allocated in order to allow for
1821 * resizing in later calls to the queue setup function.
1823 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1824 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1827 ixgbe_tx_queue_release(txq);
1831 txq->nb_tx_desc = nb_desc;
1832 txq->tx_rs_thresh = tx_rs_thresh;
1833 txq->tx_free_thresh = tx_free_thresh;
1834 txq->pthresh = tx_conf->tx_thresh.pthresh;
1835 txq->hthresh = tx_conf->tx_thresh.hthresh;
1836 txq->wthresh = tx_conf->tx_thresh.wthresh;
1837 txq->queue_id = queue_idx;
1838 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1839 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1840 txq->port_id = dev->data->port_id;
1841 txq->txq_flags = tx_conf->txq_flags;
1842 txq->ops = &def_txq_ops;
1843 txq->start_tx_per_q = tx_conf->start_tx_per_q;
1846 * Modification to set VFTDT for virtual function if vf is detected
1848 if (hw->mac.type == ixgbe_mac_82599_vf)
1849 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1851 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1852 #ifndef RTE_LIBRTE_XEN_DOM0
1853 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1855 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1857 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1859 /* Allocate software ring */
1860 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1861 sizeof(struct igb_tx_entry) * nb_desc,
1862 CACHE_LINE_SIZE, socket_id);
1863 if (txq->sw_ring == NULL) {
1864 ixgbe_tx_queue_release(txq);
1867 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1868 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1870 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1871 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
1872 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1873 PMD_INIT_LOG(INFO, "Using simple tx code path\n");
1874 #ifdef RTE_IXGBE_INC_VECTOR
1875 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1876 ixgbe_txq_vec_setup(txq) == 0) {
1877 PMD_INIT_LOG(INFO, "Vector tx enabled.\n");
1878 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1882 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1884 PMD_INIT_LOG(INFO, "Using full-featured tx code path\n");
1885 PMD_INIT_LOG(INFO, " - txq_flags = %lx [IXGBE_SIMPLE_FLAGS=%lx]\n", (long unsigned)txq->txq_flags, (long unsigned)IXGBE_SIMPLE_FLAGS);
1886 PMD_INIT_LOG(INFO, " - tx_rs_thresh = %lu [RTE_PMD_IXGBE_TX_MAX_BURST=%lu]\n", (long unsigned)txq->tx_rs_thresh, (long unsigned)RTE_PMD_IXGBE_TX_MAX_BURST);
1887 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1890 txq->ops->reset(txq);
1892 dev->data->tx_queues[queue_idx] = txq;
1899 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1903 if (rxq->sw_ring != NULL) {
1904 for (i = 0; i < rxq->nb_rx_desc; i++) {
1905 if (rxq->sw_ring[i].mbuf != NULL) {
1906 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1907 rxq->sw_ring[i].mbuf = NULL;
1910 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1911 if (rxq->rx_nb_avail) {
1912 for (i = 0; i < rxq->rx_nb_avail; ++i) {
1913 struct rte_mbuf *mb;
1914 mb = rxq->rx_stage[rxq->rx_next_avail + i];
1915 rte_pktmbuf_free_seg(mb);
1917 rxq->rx_nb_avail = 0;
1924 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
1927 ixgbe_rx_queue_release_mbufs(rxq);
1928 rte_free(rxq->sw_ring);
1934 ixgbe_dev_rx_queue_release(void *rxq)
1936 ixgbe_rx_queue_release(rxq);
1940 * Check if Rx Burst Bulk Alloc function can be used.
1942 * 0: the preconditions are satisfied and the bulk allocation function
1944 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
1945 * function must be used.
1948 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1949 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
1951 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct igb_rx_queue *rxq)
1957 * Make sure the following pre-conditions are satisfied:
1958 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
1959 * rxq->rx_free_thresh < rxq->nb_rx_desc
1960 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
1961 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
1962 * Scattered packets are not supported. This should be checked
1963 * outside of this function.
1965 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1966 if (! (rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST))
1968 else if (! (rxq->rx_free_thresh < rxq->nb_rx_desc))
1970 else if (! ((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0))
1972 else if (! (rxq->nb_rx_desc <
1973 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST)))
1982 /* Reset dynamic igb_rx_queue fields back to defaults */
1984 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
1986 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
1992 * By default, the Rx queue setup function allocates enough memory for
1993 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
1994 * extra memory at the end of the descriptor ring to be zero'd out. A
1995 * pre-condition for using the Rx burst bulk alloc function is that the
1996 * number of descriptors is less than or equal to
1997 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
1998 * constraints here to see if we need to zero out memory after the end
1999 * of the H/W descriptor ring.
2001 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2002 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2003 /* zero out extra memory */
2004 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2007 /* do not zero out extra memory */
2008 len = rxq->nb_rx_desc;
2011 * Zero out HW ring memory. Zero out extra memory at the end of
2012 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2013 * reads extra memory as zeros.
2015 for (i = 0; i < len; i++) {
2016 rxq->rx_ring[i] = zeroed_desc;
2019 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2021 * initialize extra software ring entries. Space for these extra
2022 * entries is always allocated
2024 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2025 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2026 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2029 rxq->rx_nb_avail = 0;
2030 rxq->rx_next_avail = 0;
2031 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2032 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2034 rxq->nb_rx_hold = 0;
2035 rxq->pkt_first_seg = NULL;
2036 rxq->pkt_last_seg = NULL;
2040 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2043 unsigned int socket_id,
2044 const struct rte_eth_rxconf *rx_conf,
2045 struct rte_mempool *mp)
2047 const struct rte_memzone *rz;
2048 struct igb_rx_queue *rxq;
2049 struct ixgbe_hw *hw;
2050 int use_def_burst_func = 1;
2053 PMD_INIT_FUNC_TRACE();
2054 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057 * Validate number of receive descriptors.
2058 * It must not exceed hardware maximum, and must be multiple
2061 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2062 (nb_desc > IXGBE_MAX_RING_DESC) ||
2063 (nb_desc < IXGBE_MIN_RING_DESC)) {
2067 /* Free memory prior to re-allocation if needed... */
2068 if (dev->data->rx_queues[queue_idx] != NULL) {
2069 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2070 dev->data->rx_queues[queue_idx] = NULL;
2073 /* First allocate the rx queue data structure */
2074 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct igb_rx_queue),
2075 CACHE_LINE_SIZE, socket_id);
2079 rxq->nb_rx_desc = nb_desc;
2080 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2081 rxq->queue_id = queue_idx;
2082 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2083 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2084 rxq->port_id = dev->data->port_id;
2085 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2087 rxq->drop_en = rx_conf->rx_drop_en;
2088 rxq->start_rx_per_q = rx_conf->start_rx_per_q;
2091 * Allocate RX ring hardware descriptors. A memzone large enough to
2092 * handle the maximum ring size is allocated in order to allow for
2093 * resizing in later calls to the queue setup function.
2095 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2096 RX_RING_SZ, socket_id);
2098 ixgbe_rx_queue_release(rxq);
2103 * Zero init all the descriptors in the ring.
2105 memset (rz->addr, 0, RX_RING_SZ);
2108 * Modified to setup VFRDT for Virtual Function
2110 if (hw->mac.type == ixgbe_mac_82599_vf) {
2112 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2114 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2118 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2120 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2122 #ifndef RTE_LIBRTE_XEN_DOM0
2123 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2125 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2127 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2130 * Allocate software ring. Allow for space at the end of the
2131 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2132 * function does not access an invalid memory region.
2134 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2135 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2139 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2140 sizeof(struct igb_rx_entry) * len,
2141 CACHE_LINE_SIZE, socket_id);
2142 if (rxq->sw_ring == NULL) {
2143 ixgbe_rx_queue_release(rxq);
2146 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
2147 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2150 * Certain constraints must be met in order to use the bulk buffer
2151 * allocation Rx burst function.
2153 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2155 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2156 if (!use_def_burst_func && !dev->data->scattered_rx) {
2157 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2158 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2159 "satisfied. Rx Burst Bulk Alloc function will be "
2160 "used on port=%d, queue=%d.\n",
2161 rxq->port_id, rxq->queue_id);
2162 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2163 #ifdef RTE_IXGBE_INC_VECTOR
2164 if (!ixgbe_rx_vec_condition_check(dev)) {
2165 PMD_INIT_LOG(INFO, "Vector rx enabled, please make "
2166 "sure RX burst size no less than 32.\n");
2167 ixgbe_rxq_vec_setup(rxq);
2168 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
2173 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2174 "are not satisfied, Scattered Rx is requested, "
2175 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2176 "enabled (port=%d, queue=%d).\n",
2177 rxq->port_id, rxq->queue_id);
2179 dev->data->rx_queues[queue_idx] = rxq;
2181 ixgbe_reset_rx_queue(rxq);
2187 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2189 #define IXGBE_RXQ_SCAN_INTERVAL 4
2190 volatile union ixgbe_adv_rx_desc *rxdp;
2191 struct igb_rx_queue *rxq;
2194 if (rx_queue_id >= dev->data->nb_rx_queues) {
2195 PMD_RX_LOG(ERR, "Invalid RX queue id=%d\n", rx_queue_id);
2199 rxq = dev->data->rx_queues[rx_queue_id];
2200 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2202 while ((desc < rxq->nb_rx_desc) &&
2203 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2204 desc += IXGBE_RXQ_SCAN_INTERVAL;
2205 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2206 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2207 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2208 desc - rxq->nb_rx_desc]);
2215 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2217 volatile union ixgbe_adv_rx_desc *rxdp;
2218 struct igb_rx_queue *rxq = rx_queue;
2221 if (unlikely(offset >= rxq->nb_rx_desc))
2223 desc = rxq->rx_tail + offset;
2224 if (desc >= rxq->nb_rx_desc)
2225 desc -= rxq->nb_rx_desc;
2227 rxdp = &rxq->rx_ring[desc];
2228 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2232 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2236 PMD_INIT_FUNC_TRACE();
2238 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2239 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2241 txq->ops->release_mbufs(txq);
2242 txq->ops->reset(txq);
2246 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2247 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2249 ixgbe_rx_queue_release_mbufs(rxq);
2250 ixgbe_reset_rx_queue(rxq);
2255 /*********************************************************************
2257 * Device RX/TX init functions
2259 **********************************************************************/
2262 * Receive Side Scaling (RSS)
2263 * See section 7.1.2.8 in the following document:
2264 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2267 * The source and destination IP addresses of the IP header and the source
2268 * and destination ports of TCP/UDP headers, if any, of received packets are
2269 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2270 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2271 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2272 * RSS output index which is used as the RX queue index where to store the
2274 * The following output is supplied in the RX write-back descriptor:
2275 * - 32-bit result of the Microsoft RSS hash function,
2276 * - 4-bit RSS type field.
2280 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2281 * Used as the default key.
2283 static uint8_t rss_intel_key[40] = {
2284 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2285 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2286 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2287 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2288 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2292 ixgbe_rss_disable(struct rte_eth_dev *dev)
2294 struct ixgbe_hw *hw;
2297 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2298 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2299 mrqc &= ~IXGBE_MRQC_RSSEN;
2300 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2304 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2312 hash_key = rss_conf->rss_key;
2313 if (hash_key != NULL) {
2314 /* Fill in RSS hash key */
2315 for (i = 0; i < 10; i++) {
2316 rss_key = hash_key[(i * 4)];
2317 rss_key |= hash_key[(i * 4) + 1] << 8;
2318 rss_key |= hash_key[(i * 4) + 2] << 16;
2319 rss_key |= hash_key[(i * 4) + 3] << 24;
2320 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2324 /* Set configured hashing protocols in MRQC register */
2325 rss_hf = rss_conf->rss_hf;
2326 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2327 if (rss_hf & ETH_RSS_IPV4)
2328 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2329 if (rss_hf & ETH_RSS_IPV4_TCP)
2330 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2331 if (rss_hf & ETH_RSS_IPV6)
2332 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2333 if (rss_hf & ETH_RSS_IPV6_EX)
2334 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2335 if (rss_hf & ETH_RSS_IPV6_TCP)
2336 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2337 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2338 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2339 if (rss_hf & ETH_RSS_IPV4_UDP)
2340 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2341 if (rss_hf & ETH_RSS_IPV6_UDP)
2342 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2343 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2344 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2345 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2349 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2350 struct rte_eth_rss_conf *rss_conf)
2352 struct ixgbe_hw *hw;
2356 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2359 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2360 * "RSS enabling cannot be done dynamically while it must be
2361 * preceded by a software reset"
2362 * Before changing anything, first check that the update RSS operation
2363 * does not attempt to disable RSS, if RSS was enabled at
2364 * initialization time, or does not attempt to enable RSS, if RSS was
2365 * disabled at initialization time.
2367 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2368 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2369 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2370 if (rss_hf != 0) /* Enable RSS */
2372 return 0; /* Nothing to do */
2375 if (rss_hf == 0) /* Disable RSS */
2377 ixgbe_hw_rss_hash_set(hw, rss_conf);
2382 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2383 struct rte_eth_rss_conf *rss_conf)
2385 struct ixgbe_hw *hw;
2392 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2393 hash_key = rss_conf->rss_key;
2394 if (hash_key != NULL) {
2395 /* Return RSS hash key */
2396 for (i = 0; i < 10; i++) {
2397 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2398 hash_key[(i * 4)] = rss_key & 0x000000FF;
2399 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2400 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2401 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2405 /* Get RSS functions configured in MRQC register */
2406 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2407 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2408 rss_conf->rss_hf = 0;
2412 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2413 rss_hf |= ETH_RSS_IPV4;
2414 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2415 rss_hf |= ETH_RSS_IPV4_TCP;
2416 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2417 rss_hf |= ETH_RSS_IPV6;
2418 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2419 rss_hf |= ETH_RSS_IPV6_EX;
2420 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2421 rss_hf |= ETH_RSS_IPV6_TCP;
2422 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2423 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2424 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2425 rss_hf |= ETH_RSS_IPV4_UDP;
2426 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2427 rss_hf |= ETH_RSS_IPV6_UDP;
2428 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2429 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2430 rss_conf->rss_hf = rss_hf;
2435 ixgbe_rss_configure(struct rte_eth_dev *dev)
2437 struct rte_eth_rss_conf rss_conf;
2438 struct ixgbe_hw *hw;
2443 PMD_INIT_FUNC_TRACE();
2444 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2447 * Fill in redirection table
2448 * The byte-swap is needed because NIC registers are in
2449 * little-endian order.
2452 for (i = 0, j = 0; i < 128; i++, j++) {
2453 if (j == dev->data->nb_rx_queues)
2455 reta = (reta << 8) | j;
2457 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2462 * Configure the RSS key and the RSS protocols used to compute
2463 * the RSS hash of input packets.
2465 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2466 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2467 ixgbe_rss_disable(dev);
2470 if (rss_conf.rss_key == NULL)
2471 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2472 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2475 #define NUM_VFTA_REGISTERS 128
2476 #define NIC_RX_BUFFER_SIZE 0x200
2479 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2481 struct rte_eth_vmdq_dcb_conf *cfg;
2482 struct ixgbe_hw *hw;
2483 enum rte_eth_nb_pools num_pools;
2484 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2486 uint8_t nb_tcs; /* number of traffic classes */
2489 PMD_INIT_FUNC_TRACE();
2490 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2491 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2492 num_pools = cfg->nb_queue_pools;
2493 /* Check we have a valid number of pools */
2494 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2495 ixgbe_rss_disable(dev);
2498 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2499 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2503 * split rx buffer up into sections, each for 1 traffic class
2505 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2506 for (i = 0 ; i < nb_tcs; i++) {
2507 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2508 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2509 /* clear 10 bits. */
2510 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2511 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2513 /* zero alloc all unused TCs */
2514 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2515 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2516 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2517 /* clear 10 bits. */
2518 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2521 /* MRQC: enable vmdq and dcb */
2522 mrqc = ((num_pools == ETH_16_POOLS) ? \
2523 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2524 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2526 /* PFVTCTL: turn on virtualisation and set the default pool */
2527 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2528 if (cfg->enable_default_pool) {
2529 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2531 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2534 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2536 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2538 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2540 * mapping is done with 3 bits per priority,
2541 * so shift by i*3 each time
2543 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2545 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2547 /* RTRPCS: DCB related */
2548 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2550 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2551 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2552 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2553 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2555 /* VFTA - enable all vlan filters */
2556 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2557 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2560 /* VFRE: pool enabling for receive - 16 or 32 */
2561 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2562 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2565 * MPSAR - allow pools to read specific mac addresses
2566 * In this case, all pools should be able to read from mac addr 0
2568 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2569 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2571 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2572 for (i = 0; i < cfg->nb_pool_maps; i++) {
2573 /* set vlan id in VF register and set the valid bit */
2574 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2575 (cfg->pool_map[i].vlan_id & 0xFFF)));
2577 * Put the allowed pools in VFB reg. As we only have 16 or 32
2578 * pools, we only need to use the first half of the register
2581 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2586 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2587 * @hw: pointer to hardware structure
2588 * @dcb_config: pointer to ixgbe_dcb_config structure
2591 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2592 struct ixgbe_dcb_config *dcb_config)
2597 PMD_INIT_FUNC_TRACE();
2598 if (hw->mac.type != ixgbe_mac_82598EB) {
2599 /* Disable the Tx desc arbiter so that MTQC can be changed */
2600 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2601 reg |= IXGBE_RTTDCS_ARBDIS;
2602 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2604 /* Enable DCB for Tx with 8 TCs */
2605 if (dcb_config->num_tcs.pg_tcs == 8) {
2606 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2609 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2611 if (dcb_config->vt_mode)
2612 reg |= IXGBE_MTQC_VT_ENA;
2613 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2615 /* Disable drop for all queues */
2616 for (q = 0; q < 128; q++)
2617 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2618 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2620 /* Enable the Tx desc arbiter */
2621 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2622 reg &= ~IXGBE_RTTDCS_ARBDIS;
2623 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2625 /* Enable Security TX Buffer IFG for DCB */
2626 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2627 reg |= IXGBE_SECTX_DCB;
2628 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2634 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2635 * @dev: pointer to rte_eth_dev structure
2636 * @dcb_config: pointer to ixgbe_dcb_config structure
2639 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2640 struct ixgbe_dcb_config *dcb_config)
2642 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2643 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2644 struct ixgbe_hw *hw =
2645 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647 PMD_INIT_FUNC_TRACE();
2648 if (hw->mac.type != ixgbe_mac_82598EB)
2649 /*PF VF Transmit Enable*/
2650 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2651 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2653 /*Configure general DCB TX parameters*/
2654 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2659 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2660 struct ixgbe_dcb_config *dcb_config)
2662 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2663 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2664 struct ixgbe_dcb_tc_config *tc;
2667 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2668 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2669 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2670 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2673 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2674 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2676 /* User Priority to Traffic Class mapping */
2677 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2678 j = vmdq_rx_conf->dcb_queue[i];
2679 tc = &dcb_config->tc_config[j];
2680 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2686 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2687 struct ixgbe_dcb_config *dcb_config)
2689 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2690 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2691 struct ixgbe_dcb_tc_config *tc;
2694 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2695 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2696 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2697 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2700 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2701 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2704 /* User Priority to Traffic Class mapping */
2705 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2706 j = vmdq_tx_conf->dcb_queue[i];
2707 tc = &dcb_config->tc_config[j];
2708 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2715 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2716 struct ixgbe_dcb_config *dcb_config)
2718 struct rte_eth_dcb_rx_conf *rx_conf =
2719 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2720 struct ixgbe_dcb_tc_config *tc;
2723 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2724 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2726 /* User Priority to Traffic Class mapping */
2727 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2728 j = rx_conf->dcb_queue[i];
2729 tc = &dcb_config->tc_config[j];
2730 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2736 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2737 struct ixgbe_dcb_config *dcb_config)
2739 struct rte_eth_dcb_tx_conf *tx_conf =
2740 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2741 struct ixgbe_dcb_tc_config *tc;
2744 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2745 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2747 /* User Priority to Traffic Class mapping */
2748 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2749 j = tx_conf->dcb_queue[i];
2750 tc = &dcb_config->tc_config[j];
2751 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2757 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2758 * @hw: pointer to hardware structure
2759 * @dcb_config: pointer to ixgbe_dcb_config structure
2762 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2763 struct ixgbe_dcb_config *dcb_config)
2769 PMD_INIT_FUNC_TRACE();
2771 * Disable the arbiter before changing parameters
2772 * (always enable recycle mode; WSP)
2774 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2775 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2777 if (hw->mac.type != ixgbe_mac_82598EB) {
2778 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2779 if (dcb_config->num_tcs.pg_tcs == 4) {
2780 if (dcb_config->vt_mode)
2781 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2782 IXGBE_MRQC_VMDQRT4TCEN;
2784 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2785 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2789 if (dcb_config->num_tcs.pg_tcs == 8) {
2790 if (dcb_config->vt_mode)
2791 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2792 IXGBE_MRQC_VMDQRT8TCEN;
2794 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2795 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2800 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2803 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2804 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2805 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2806 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2808 /* VFTA - enable all vlan filters */
2809 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2810 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2814 * Configure Rx packet plane (recycle mode; WSP) and
2817 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2818 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2824 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2825 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2827 switch (hw->mac.type) {
2828 case ixgbe_mac_82598EB:
2829 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2831 case ixgbe_mac_82599EB:
2832 case ixgbe_mac_X540:
2833 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2842 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2843 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2845 switch (hw->mac.type) {
2846 case ixgbe_mac_82598EB:
2847 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2848 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2850 case ixgbe_mac_82599EB:
2851 case ixgbe_mac_X540:
2852 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2853 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2860 #define DCB_RX_CONFIG 1
2861 #define DCB_TX_CONFIG 1
2862 #define DCB_TX_PB 1024
2864 * ixgbe_dcb_hw_configure - Enable DCB and configure
2865 * general DCB in VT mode and non-VT mode parameters
2866 * @dev: pointer to rte_eth_dev structure
2867 * @dcb_config: pointer to ixgbe_dcb_config structure
2870 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2871 struct ixgbe_dcb_config *dcb_config)
2874 uint8_t i,pfc_en,nb_tcs;
2876 uint8_t config_dcb_rx = 0;
2877 uint8_t config_dcb_tx = 0;
2878 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2879 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2880 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2881 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2882 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2883 struct ixgbe_dcb_tc_config *tc;
2884 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2885 struct ixgbe_hw *hw =
2886 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2888 switch(dev->data->dev_conf.rxmode.mq_mode){
2889 case ETH_MQ_RX_VMDQ_DCB:
2890 dcb_config->vt_mode = true;
2891 if (hw->mac.type != ixgbe_mac_82598EB) {
2892 config_dcb_rx = DCB_RX_CONFIG;
2894 *get dcb and VT rx configuration parameters
2897 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2898 /*Configure general VMDQ and DCB RX parameters*/
2899 ixgbe_vmdq_dcb_configure(dev);
2903 dcb_config->vt_mode = false;
2904 config_dcb_rx = DCB_RX_CONFIG;
2905 /* Get dcb TX configuration parameters from rte_eth_conf */
2906 ixgbe_dcb_rx_config(dev,dcb_config);
2907 /*Configure general DCB RX parameters*/
2908 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2911 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration\n");
2914 switch (dev->data->dev_conf.txmode.mq_mode) {
2915 case ETH_MQ_TX_VMDQ_DCB:
2916 dcb_config->vt_mode = true;
2917 config_dcb_tx = DCB_TX_CONFIG;
2918 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2919 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2920 /*Configure general VMDQ and DCB TX parameters*/
2921 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2925 dcb_config->vt_mode = false;
2926 config_dcb_tx = DCB_TX_CONFIG;
2927 /*get DCB TX configuration parameters from rte_eth_conf*/
2928 ixgbe_dcb_tx_config(dev,dcb_config);
2929 /*Configure general DCB TX parameters*/
2930 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2933 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration\n");
2937 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2939 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2940 if(nb_tcs == ETH_4_TCS) {
2941 /* Avoid un-configured priority mapping to TC0 */
2943 uint8_t mask = 0xFF;
2944 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
2945 mask = (uint8_t)(mask & (~ (1 << map[i])));
2946 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
2947 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
2951 /* Re-configure 4 TCs BW */
2952 for (i = 0; i < nb_tcs; i++) {
2953 tc = &dcb_config->tc_config[i];
2954 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
2955 (uint8_t)(100 / nb_tcs);
2956 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
2957 (uint8_t)(100 / nb_tcs);
2959 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2960 tc = &dcb_config->tc_config[i];
2961 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
2962 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
2967 /* Set RX buffer size */
2968 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2969 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
2970 for (i = 0 ; i < nb_tcs; i++) {
2971 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2973 /* zero alloc all unused TCs */
2974 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2975 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
2979 /* Only support an equally distributed Tx packet buffer strategy. */
2980 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
2981 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
2982 for (i = 0; i < nb_tcs; i++) {
2983 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
2984 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
2986 /* Clear unused TCs, if any, to zero buffer size*/
2987 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2988 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
2989 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
2993 /*Calculates traffic class credits*/
2994 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2995 IXGBE_DCB_TX_CONFIG);
2996 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2997 IXGBE_DCB_RX_CONFIG);
3000 /* Unpack CEE standard containers */
3001 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3002 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3003 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3004 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3005 /* Configure PG(ETS) RX */
3006 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3010 /* Unpack CEE standard containers */
3011 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3012 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3013 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3014 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3015 /* Configure PG(ETS) TX */
3016 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3019 /*Configure queue statistics registers*/
3020 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3022 /* Check if the PFC is supported */
3023 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3024 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3025 for (i = 0; i < nb_tcs; i++) {
3027 * If the TC count is 8,and the default high_water is 48,
3028 * the low_water is 16 as default.
3030 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3031 hw->fc.low_water[i] = pbsize / 4;
3032 /* Enable pfc for this TC */
3033 tc = &dcb_config->tc_config[i];
3034 tc->pfc = ixgbe_dcb_pfc_enabled;
3036 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3037 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3039 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3046 * ixgbe_configure_dcb - Configure DCB Hardware
3047 * @dev: pointer to rte_eth_dev
3049 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3051 struct ixgbe_dcb_config *dcb_cfg =
3052 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3053 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3055 PMD_INIT_FUNC_TRACE();
3057 /* check support mq_mode for DCB */
3058 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3059 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3062 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3065 /** Configure DCB hardware **/
3066 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3072 * VMDq only support for 10 GbE NIC.
3075 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3077 struct rte_eth_vmdq_rx_conf *cfg;
3078 struct ixgbe_hw *hw;
3079 enum rte_eth_nb_pools num_pools;
3080 uint32_t mrqc, vt_ctl, vlanctrl;
3083 PMD_INIT_FUNC_TRACE();
3084 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3085 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3086 num_pools = cfg->nb_queue_pools;
3088 ixgbe_rss_disable(dev);
3090 /* MRQC: enable vmdq */
3091 mrqc = IXGBE_MRQC_VMDQEN;
3092 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3094 /* PFVTCTL: turn on virtualisation and set the default pool */
3095 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3096 if (cfg->enable_default_pool)
3097 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3099 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3101 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3103 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3104 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3105 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3106 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3108 /* VFTA - enable all vlan filters */
3109 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3110 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3112 /* VFRE: pool enabling for receive - 64 */
3113 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3114 if (num_pools == ETH_64_POOLS)
3115 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3118 * MPSAR - allow pools to read specific mac addresses
3119 * In this case, all pools should be able to read from mac addr 0
3121 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3122 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3124 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3125 for (i = 0; i < cfg->nb_pool_maps; i++) {
3126 /* set vlan id in VF register and set the valid bit */
3127 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3128 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3130 * Put the allowed pools in VFB reg. As we only have 16 or 64
3131 * pools, we only need to use the first half of the register
3134 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3135 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3136 (cfg->pool_map[i].pools & UINT32_MAX));
3138 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3139 ((cfg->pool_map[i].pools >> 32) \
3144 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3145 if (cfg->enable_loop_back) {
3146 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3147 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3148 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3151 IXGBE_WRITE_FLUSH(hw);
3155 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3156 * @hw: pointer to hardware structure
3159 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3164 PMD_INIT_FUNC_TRACE();
3165 /*PF VF Transmit Enable*/
3166 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3167 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3169 /* Disable the Tx desc arbiter so that MTQC can be changed */
3170 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3171 reg |= IXGBE_RTTDCS_ARBDIS;
3172 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3174 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3175 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3177 /* Disable drop for all queues */
3178 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3179 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3180 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3182 /* Enable the Tx desc arbiter */
3183 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3184 reg &= ~IXGBE_RTTDCS_ARBDIS;
3185 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3187 IXGBE_WRITE_FLUSH(hw);
3193 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
3195 struct igb_rx_entry *rxe = rxq->sw_ring;
3199 /* Initialize software ring entries */
3200 for (i = 0; i < rxq->nb_rx_desc; i++) {
3201 volatile union ixgbe_adv_rx_desc *rxd;
3202 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3204 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u\n",
3205 (unsigned) rxq->queue_id);
3209 rte_mbuf_refcnt_set(mbuf, 1);
3211 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3213 mbuf->port = rxq->port_id;
3216 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3217 rxd = &rxq->rx_ring[i];
3218 rxd->read.hdr_addr = dma_addr;
3219 rxd->read.pkt_addr = dma_addr;
3227 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3229 struct ixgbe_hw *hw =
3230 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3232 if (hw->mac.type == ixgbe_mac_82598EB)
3235 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3237 * SRIOV inactive scheme
3238 * any DCB/RSS w/o VMDq multi-queue setting
3240 switch (dev->data->dev_conf.rxmode.mq_mode) {
3242 ixgbe_rss_configure(dev);
3245 case ETH_MQ_RX_VMDQ_DCB:
3246 ixgbe_vmdq_dcb_configure(dev);
3249 case ETH_MQ_RX_VMDQ_ONLY:
3250 ixgbe_vmdq_rx_hw_configure(dev);
3253 case ETH_MQ_RX_NONE:
3254 /* if mq_mode is none, disable rss mode.*/
3255 default: ixgbe_rss_disable(dev);
3258 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3260 * SRIOV active scheme
3261 * FIXME if support DCB/RSS together with VMDq & SRIOV
3264 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQEN);
3268 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT4TCEN);
3272 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT8TCEN);
3275 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3283 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3285 struct ixgbe_hw *hw =
3286 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3290 if (hw->mac.type == ixgbe_mac_82598EB)
3293 /* disable arbiter before setting MTQC */
3294 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3295 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3296 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3298 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3300 * SRIOV inactive scheme
3301 * any DCB w/o VMDq multi-queue setting
3303 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3304 ixgbe_vmdq_tx_hw_configure(hw);
3306 mtqc = IXGBE_MTQC_64Q_1PB;
3307 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3310 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3313 * SRIOV active scheme
3314 * FIXME if support DCB together with VMDq & SRIOV
3317 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3320 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3323 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3327 mtqc = IXGBE_MTQC_64Q_1PB;
3328 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3330 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3333 /* re-enable arbiter */
3334 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3335 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3341 * Initializes Receive Unit.
3344 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3346 struct ixgbe_hw *hw;
3347 struct igb_rx_queue *rxq;
3348 struct rte_pktmbuf_pool_private *mbp_priv;
3360 PMD_INIT_FUNC_TRACE();
3361 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3364 * Make sure receives are disabled while setting
3365 * up the RX context (registers, descriptor rings, etc.).
3367 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3368 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3370 /* Enable receipt of broadcasted frames */
3371 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3372 fctrl |= IXGBE_FCTRL_BAM;
3373 fctrl |= IXGBE_FCTRL_DPF;
3374 fctrl |= IXGBE_FCTRL_PMCF;
3375 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3378 * Configure CRC stripping, if any.
3380 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3381 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3382 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3384 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3387 * Configure jumbo frame support, if any.
3389 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3390 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3391 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3392 maxfrs &= 0x0000FFFF;
3393 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3394 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3396 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3399 * If loopback mode is configured for 82599, set LPBK bit.
3401 if (hw->mac.type == ixgbe_mac_82599EB &&
3402 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3403 hlreg0 |= IXGBE_HLREG0_LPBK;
3405 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3407 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3409 /* Setup RX queues */
3410 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3411 rxq = dev->data->rx_queues[i];
3414 * Reset crc_len in case it was changed after queue setup by a
3415 * call to configure.
3417 rxq->crc_len = (uint8_t)
3418 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3421 /* Setup the Base and Length of the Rx Descriptor Rings */
3422 bus_addr = rxq->rx_ring_phys_addr;
3423 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3424 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3425 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3426 (uint32_t)(bus_addr >> 32));
3427 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3428 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3429 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3430 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3432 /* Configure the SRRCTL register */
3433 #ifdef RTE_HEADER_SPLIT_ENABLE
3435 * Configure Header Split
3437 if (dev->data->dev_conf.rxmode.header_split) {
3438 if (hw->mac.type == ixgbe_mac_82599EB) {
3439 /* Must setup the PSRTYPE register */
3441 psrtype = IXGBE_PSRTYPE_TCPHDR |
3442 IXGBE_PSRTYPE_UDPHDR |
3443 IXGBE_PSRTYPE_IPV4HDR |
3444 IXGBE_PSRTYPE_IPV6HDR;
3445 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3447 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3448 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3449 IXGBE_SRRCTL_BSIZEHDR_MASK);
3450 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3453 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3455 /* Set if packets are dropped when no descriptors available */
3457 srrctl |= IXGBE_SRRCTL_DROP_EN;
3460 * Configure the RX buffer size in the BSIZEPACKET field of
3461 * the SRRCTL register of the queue.
3462 * The value is in 1 KB resolution. Valid values can be from
3465 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3466 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3467 RTE_PKTMBUF_HEADROOM);
3468 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3469 IXGBE_SRRCTL_BSIZEPKT_MASK);
3470 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3472 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3473 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3475 /* It adds dual VLAN length for supporting dual VLAN */
3476 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3477 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3478 dev->data->scattered_rx = 1;
3479 #ifdef RTE_IXGBE_INC_VECTOR
3480 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3482 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3487 if (dev->data->dev_conf.rxmode.enable_scatter) {
3488 #ifdef RTE_IXGBE_INC_VECTOR
3489 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3491 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3493 dev->data->scattered_rx = 1;
3497 * Device configured with multiple RX queues.
3499 ixgbe_dev_mq_rx_configure(dev);
3502 * Setup the Checksum Register.
3503 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3504 * Enable IP/L4 checkum computation by hardware if requested to do so.
3506 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3507 rxcsum |= IXGBE_RXCSUM_PCSD;
3508 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3509 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3511 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3513 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3515 if (hw->mac.type == ixgbe_mac_82599EB) {
3516 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3517 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3518 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3520 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3521 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3522 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3529 * Initializes Transmit Unit.
3532 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3534 struct ixgbe_hw *hw;
3535 struct igb_tx_queue *txq;
3541 PMD_INIT_FUNC_TRACE();
3542 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3544 /* Enable TX CRC (checksum offload requirement) */
3545 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3546 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
3547 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3549 /* Setup the Base and Length of the Tx Descriptor Rings */
3550 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3551 txq = dev->data->tx_queues[i];
3553 bus_addr = txq->tx_ring_phys_addr;
3554 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3555 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3556 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3557 (uint32_t)(bus_addr >> 32));
3558 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3559 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3560 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3561 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3562 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3565 * Disable Tx Head Writeback RO bit, since this hoses
3566 * bookkeeping if things aren't delivered in order.
3568 switch (hw->mac.type) {
3569 case ixgbe_mac_82598EB:
3570 txctrl = IXGBE_READ_REG(hw,
3571 IXGBE_DCA_TXCTRL(txq->reg_idx));
3572 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3573 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3577 case ixgbe_mac_82599EB:
3578 case ixgbe_mac_X540:
3580 txctrl = IXGBE_READ_REG(hw,
3581 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3582 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3583 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3589 /* Device configured with multiple TX queues. */
3590 ixgbe_dev_mq_tx_configure(dev);
3594 * Set up link for 82599 loopback mode Tx->Rx.
3597 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3599 DEBUGFUNC("ixgbe_setup_loopback_link_82599");
3601 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3602 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3604 PMD_INIT_LOG(ERR, "Could not enable loopback mode\n");
3613 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3614 ixgbe_reset_pipeline_82599(hw);
3616 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3622 * Start Transmit and Receive Units.
3625 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3627 struct ixgbe_hw *hw;
3628 struct igb_tx_queue *txq;
3629 struct igb_rx_queue *rxq;
3635 PMD_INIT_FUNC_TRACE();
3636 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3638 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3639 txq = dev->data->tx_queues[i];
3640 /* Setup Transmit Threshold Registers */
3641 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3642 txdctl |= txq->pthresh & 0x7F;
3643 txdctl |= ((txq->hthresh & 0x7F) << 8);
3644 txdctl |= ((txq->wthresh & 0x7F) << 16);
3645 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3648 if (hw->mac.type != ixgbe_mac_82598EB) {
3649 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3650 dmatxctl |= IXGBE_DMATXCTL_TE;
3651 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3654 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3655 txq = dev->data->tx_queues[i];
3656 if (!txq->start_tx_per_q)
3657 ixgbe_dev_tx_queue_start(dev, i);
3660 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3661 rxq = dev->data->rx_queues[i];
3662 if (!rxq->start_rx_per_q)
3663 ixgbe_dev_rx_queue_start(dev, i);
3666 /* Enable Receive engine */
3667 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3668 if (hw->mac.type == ixgbe_mac_82598EB)
3669 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3670 rxctrl |= IXGBE_RXCTRL_RXEN;
3671 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3673 /* If loopback mode is enabled for 82599, set up the link accordingly */
3674 if (hw->mac.type == ixgbe_mac_82599EB &&
3675 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3676 ixgbe_setup_loopback_link_82599(hw);
3681 * Start Receive Units for specified queue.
3684 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3686 struct ixgbe_hw *hw;
3687 struct igb_rx_queue *rxq;
3691 PMD_INIT_FUNC_TRACE();
3692 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3694 if (rx_queue_id < dev->data->nb_rx_queues) {
3695 rxq = dev->data->rx_queues[rx_queue_id];
3697 /* Allocate buffers for descriptor rings */
3698 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
3700 "Could not alloc mbuf for queue:%d\n",
3704 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3705 rxdctl |= IXGBE_RXDCTL_ENABLE;
3706 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3708 /* Wait until RX Enable ready */
3709 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3712 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3713 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3715 PMD_INIT_LOG(ERR, "Could not enable "
3716 "Rx Queue %d\n", rx_queue_id);
3718 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3719 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3727 * Stop Receive Units for specified queue.
3730 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3732 struct ixgbe_hw *hw;
3733 struct igb_rx_queue *rxq;
3737 PMD_INIT_FUNC_TRACE();
3738 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3740 if (rx_queue_id < dev->data->nb_rx_queues) {
3741 rxq = dev->data->rx_queues[rx_queue_id];
3743 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3744 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3745 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3747 /* Wait until RX Enable ready */
3748 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3751 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3752 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
3754 PMD_INIT_LOG(ERR, "Could not disable "
3755 "Rx Queue %d\n", rx_queue_id);
3757 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3759 ixgbe_rx_queue_release_mbufs(rxq);
3760 ixgbe_reset_rx_queue(rxq);
3769 * Start Transmit Units for specified queue.
3772 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3774 struct ixgbe_hw *hw;
3775 struct igb_tx_queue *txq;
3779 PMD_INIT_FUNC_TRACE();
3780 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3782 if (tx_queue_id < dev->data->nb_tx_queues) {
3783 txq = dev->data->tx_queues[tx_queue_id];
3784 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3785 txdctl |= IXGBE_TXDCTL_ENABLE;
3786 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3788 /* Wait until TX Enable ready */
3789 if (hw->mac.type == ixgbe_mac_82599EB) {
3790 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3793 txdctl = IXGBE_READ_REG(hw,
3794 IXGBE_TXDCTL(txq->reg_idx));
3795 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3797 PMD_INIT_LOG(ERR, "Could not enable "
3798 "Tx Queue %d\n", tx_queue_id);
3801 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3802 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3810 * Stop Transmit Units for specified queue.
3813 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3815 struct ixgbe_hw *hw;
3816 struct igb_tx_queue *txq;
3818 uint32_t txtdh, txtdt;
3821 PMD_INIT_FUNC_TRACE();
3822 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3824 if (tx_queue_id < dev->data->nb_tx_queues) {
3825 txq = dev->data->tx_queues[tx_queue_id];
3827 /* Wait until TX queue is empty */
3828 if (hw->mac.type == ixgbe_mac_82599EB) {
3829 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3831 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3832 txtdh = IXGBE_READ_REG(hw,
3833 IXGBE_TDH(txq->reg_idx));
3834 txtdt = IXGBE_READ_REG(hw,
3835 IXGBE_TDT(txq->reg_idx));
3836 } while (--poll_ms && (txtdh != txtdt));
3839 "Tx Queue %d is not empty when stopping.\n",
3843 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3844 txdctl &= ~IXGBE_TXDCTL_ENABLE;
3845 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3847 /* Wait until TX Enable ready */
3848 if (hw->mac.type == ixgbe_mac_82599EB) {
3849 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3852 txdctl = IXGBE_READ_REG(hw,
3853 IXGBE_TXDCTL(txq->reg_idx));
3854 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
3856 PMD_INIT_LOG(ERR, "Could not disable "
3857 "Tx Queue %d\n", tx_queue_id);
3860 if (txq->ops != NULL) {
3861 txq->ops->release_mbufs(txq);
3862 txq->ops->reset(txq);
3871 * [VF] Initializes Receive Unit.
3874 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3876 struct ixgbe_hw *hw;
3877 struct igb_rx_queue *rxq;
3878 struct rte_pktmbuf_pool_private *mbp_priv;
3885 PMD_INIT_FUNC_TRACE();
3886 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3889 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
3890 * disables the VF receipt of packets if the PF MTU is > 1500.
3891 * This is done to deal with 82599 limitations that imposes
3892 * the PF and all VFs to share the same MTU.
3893 * Then, the PF driver enables again the VF receipt of packet when
3894 * the VF driver issues a IXGBE_VF_SET_LPE request.
3895 * In the meantime, the VF device cannot be used, even if the VF driver
3896 * and the Guest VM network stack are ready to accept packets with a
3897 * size up to the PF MTU.
3898 * As a work-around to this PF behaviour, force the call to
3899 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
3900 * VF packets received can work in all cases.
3902 ixgbevf_rlpml_set_vf(hw,
3903 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
3905 /* Setup RX queues */
3906 dev->rx_pkt_burst = ixgbe_recv_pkts;
3907 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3908 rxq = dev->data->rx_queues[i];
3910 /* Allocate buffers for descriptor rings */
3911 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3915 /* Setup the Base and Length of the Rx Descriptor Rings */
3916 bus_addr = rxq->rx_ring_phys_addr;
3918 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3919 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3920 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3921 (uint32_t)(bus_addr >> 32));
3922 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3923 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3924 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3925 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3928 /* Configure the SRRCTL register */
3929 #ifdef RTE_HEADER_SPLIT_ENABLE
3931 * Configure Header Split
3933 if (dev->data->dev_conf.rxmode.header_split) {
3935 /* Must setup the PSRTYPE register */
3937 psrtype = IXGBE_PSRTYPE_TCPHDR |
3938 IXGBE_PSRTYPE_UDPHDR |
3939 IXGBE_PSRTYPE_IPV4HDR |
3940 IXGBE_PSRTYPE_IPV6HDR;
3942 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
3944 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3945 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3946 IXGBE_SRRCTL_BSIZEHDR_MASK);
3947 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3950 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3952 /* Set if packets are dropped when no descriptors available */
3954 srrctl |= IXGBE_SRRCTL_DROP_EN;
3957 * Configure the RX buffer size in the BSIZEPACKET field of
3958 * the SRRCTL register of the queue.
3959 * The value is in 1 KB resolution. Valid values can be from
3962 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3963 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3964 RTE_PKTMBUF_HEADROOM);
3965 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3966 IXGBE_SRRCTL_BSIZEPKT_MASK);
3969 * VF modification to write virtual function SRRCTL register
3971 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
3973 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3974 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3976 /* It adds dual VLAN length for supporting dual VLAN */
3977 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3978 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
3979 dev->data->scattered_rx = 1;
3980 #ifdef RTE_IXGBE_INC_VECTOR
3981 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3983 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3988 if (dev->data->dev_conf.rxmode.enable_scatter) {
3989 #ifdef RTE_IXGBE_INC_VECTOR
3990 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3992 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3994 dev->data->scattered_rx = 1;
4001 * [VF] Initializes Transmit Unit.
4004 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4006 struct ixgbe_hw *hw;
4007 struct igb_tx_queue *txq;
4012 PMD_INIT_FUNC_TRACE();
4013 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4015 /* Setup the Base and Length of the Tx Descriptor Rings */
4016 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4017 txq = dev->data->tx_queues[i];
4018 bus_addr = txq->tx_ring_phys_addr;
4019 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4020 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4021 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4022 (uint32_t)(bus_addr >> 32));
4023 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4024 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4025 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4026 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4027 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4030 * Disable Tx Head Writeback RO bit, since this hoses
4031 * bookkeeping if things aren't delivered in order.
4033 txctrl = IXGBE_READ_REG(hw,
4034 IXGBE_VFDCA_TXCTRL(i));
4035 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4036 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4042 * [VF] Start Transmit and Receive Units.
4045 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4047 struct ixgbe_hw *hw;
4048 struct igb_tx_queue *txq;
4049 struct igb_rx_queue *rxq;
4055 PMD_INIT_FUNC_TRACE();
4056 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4058 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4059 txq = dev->data->tx_queues[i];
4060 /* Setup Transmit Threshold Registers */
4061 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4062 txdctl |= txq->pthresh & 0x7F;
4063 txdctl |= ((txq->hthresh & 0x7F) << 8);
4064 txdctl |= ((txq->wthresh & 0x7F) << 16);
4065 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4068 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4070 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4071 txdctl |= IXGBE_TXDCTL_ENABLE;
4072 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4075 /* Wait until TX Enable ready */
4078 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4079 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4081 PMD_INIT_LOG(ERR, "Could not enable "
4082 "Tx Queue %d\n", i);
4084 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4086 rxq = dev->data->rx_queues[i];
4088 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4089 rxdctl |= IXGBE_RXDCTL_ENABLE;
4090 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4092 /* Wait until RX Enable ready */
4096 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4097 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4099 PMD_INIT_LOG(ERR, "Could not enable "
4100 "Rx Queue %d\n", i);
4102 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);