4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
47 #include <rte_cycles.h>
49 #include <rte_debug.h>
50 #include <rte_interrupts.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_launch.h>
55 #include <rte_tailq.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
80 #include "ixgbe_rxtx.h"
82 #define IXGBE_RSS_OFFLOAD_ALL ( \
88 ETH_RSS_IPV6_TCP_EX | \
93 static inline struct rte_mbuf *
94 rte_rxmbuf_alloc(struct rte_mempool *mp)
98 m = __rte_mbuf_raw_alloc(mp);
99 __rte_mbuf_sanity_check_raw(m, 0);
105 #define RTE_PMD_USE_PREFETCH
108 #ifdef RTE_PMD_USE_PREFETCH
110 * Prefetch a cache line into all cache levels.
112 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
114 #define rte_ixgbe_prefetch(p) do {} while(0)
117 /*********************************************************************
121 **********************************************************************/
124 * Check for descriptors with their DD bit set and free mbufs.
125 * Return the total number of buffers freed.
127 static inline int __attribute__((always_inline))
128 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
130 struct igb_tx_entry *txep;
134 /* check DD bit on threshold descriptor */
135 status = txq->tx_ring[txq->tx_next_dd].wb.status;
136 if (! (status & IXGBE_ADVTXD_STAT_DD))
140 * first buffer to free from S/W ring is at index
141 * tx_next_dd - (tx_rs_thresh-1)
143 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
145 /* prefetch the mbufs that are about to be freed */
146 for (i = 0; i < txq->tx_rs_thresh; ++i)
147 rte_prefetch0((txep + i)->mbuf);
149 /* free buffers one at a time */
150 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
151 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
152 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
156 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
157 rte_pktmbuf_free_seg(txep->mbuf);
162 /* buffers were freed, update counters */
163 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
164 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
165 if (txq->tx_next_dd >= txq->nb_tx_desc)
166 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
168 return txq->tx_rs_thresh;
171 /* Populate 4 descriptors with data from 4 mbufs */
173 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
175 uint64_t buf_dma_addr;
179 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
180 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
181 pkt_len = (*pkts)->data_len;
183 /* write data to descriptor */
184 txdp->read.buffer_addr = buf_dma_addr;
185 txdp->read.cmd_type_len =
186 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
187 txdp->read.olinfo_status =
188 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
192 /* Populate 1 descriptor with data from 1 mbuf */
194 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
196 uint64_t buf_dma_addr;
199 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
200 pkt_len = (*pkts)->data_len;
202 /* write data to descriptor */
203 txdp->read.buffer_addr = buf_dma_addr;
204 txdp->read.cmd_type_len =
205 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
206 txdp->read.olinfo_status =
207 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
211 * Fill H/W descriptor ring with mbuf data.
212 * Copy mbuf pointers to the S/W ring.
215 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
218 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
219 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
220 const int N_PER_LOOP = 4;
221 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
222 int mainpart, leftover;
226 * Process most of the packets in chunks of N pkts. Any
227 * leftover packets will get processed one at a time.
229 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
230 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
231 for (i = 0; i < mainpart; i += N_PER_LOOP) {
232 /* Copy N mbuf pointers to the S/W ring */
233 for (j = 0; j < N_PER_LOOP; ++j) {
234 (txep + i + j)->mbuf = *(pkts + i + j);
236 tx4(txdp + i, pkts + i);
239 if (unlikely(leftover > 0)) {
240 for (i = 0; i < leftover; ++i) {
241 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
242 tx1(txdp + mainpart + i, pkts + mainpart + i);
247 static inline uint16_t
248 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
251 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
252 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
256 * Begin scanning the H/W ring for done descriptors when the
257 * number of available descriptors drops below tx_free_thresh. For
258 * each done descriptor, free the associated buffer.
260 if (txq->nb_tx_free < txq->tx_free_thresh)
261 ixgbe_tx_free_bufs(txq);
263 /* Only use descriptors that are available */
264 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
265 if (unlikely(nb_pkts == 0))
268 /* Use exactly nb_pkts descriptors */
269 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
272 * At this point, we know there are enough descriptors in the
273 * ring to transmit all the packets. This assumes that each
274 * mbuf contains a single segment, and that no new offloads
275 * are expected, which would require a new context descriptor.
279 * See if we're going to wrap-around. If so, handle the top
280 * of the descriptor ring first, then do the bottom. If not,
281 * the processing looks just like the "bottom" part anyway...
283 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
284 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
285 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
288 * We know that the last descriptor in the ring will need to
289 * have its RS bit set because tx_rs_thresh has to be
290 * a divisor of the ring size
292 tx_r[txq->tx_next_rs].read.cmd_type_len |=
293 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
294 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
299 /* Fill H/W descriptor ring with mbuf data */
300 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
301 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
304 * Determine if RS bit should be set
305 * This is what we actually want:
306 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
307 * but instead of subtracting 1 and doing >=, we can just do
308 * greater than without subtracting.
310 if (txq->tx_tail > txq->tx_next_rs) {
311 tx_r[txq->tx_next_rs].read.cmd_type_len |=
312 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
313 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
315 if (txq->tx_next_rs >= txq->nb_tx_desc)
316 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
320 * Check for wrap-around. This would only happen if we used
321 * up to the last descriptor in the ring, no more, no less.
323 if (txq->tx_tail >= txq->nb_tx_desc)
326 /* update tail pointer */
328 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
334 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
339 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
340 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
341 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
343 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
347 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
348 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
349 nb_tx = (uint16_t)(nb_tx + ret);
350 nb_pkts = (uint16_t)(nb_pkts - ret);
359 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
360 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
361 uint16_t ol_flags, uint32_t vlan_macip_lens)
363 uint32_t type_tucmd_mlhl;
364 uint32_t mss_l4len_idx;
368 ctx_idx = txq->ctx_curr;
372 if (ol_flags & PKT_TX_VLAN_PKT) {
373 cmp_mask |= TX_VLAN_CMP_MASK;
376 if (ol_flags & PKT_TX_IP_CKSUM) {
377 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
378 cmp_mask |= TX_MAC_LEN_CMP_MASK;
381 /* Specify which HW CTX to upload. */
382 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
383 switch (ol_flags & PKT_TX_L4_MASK) {
384 case PKT_TX_UDP_CKSUM:
385 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
386 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
387 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
388 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
390 case PKT_TX_TCP_CKSUM:
391 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
392 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
393 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
394 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
396 case PKT_TX_SCTP_CKSUM:
397 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
398 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
399 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
400 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
403 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
404 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
408 txq->ctx_cache[ctx_idx].flags = ol_flags;
409 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
410 txq->ctx_cache[ctx_idx].vlan_macip_lens.data =
411 vlan_macip_lens & cmp_mask;
413 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
414 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
415 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
416 ctx_txd->seqnum_seed = 0;
420 * Check which hardware context can be used. Use the existing match
421 * or create a new context descriptor.
423 static inline uint32_t
424 what_advctx_update(struct igb_tx_queue *txq, uint16_t flags,
425 uint32_t vlan_macip_lens)
427 /* If match with the current used context */
428 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
429 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
430 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
431 return txq->ctx_curr;
434 /* What if match with the next context */
436 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
437 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
438 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
439 return txq->ctx_curr;
442 /* Mismatch, use the previous context */
443 return (IXGBE_CTX_NUM);
446 static inline uint32_t
447 tx_desc_cksum_flags_to_olinfo(uint16_t ol_flags)
449 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
450 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
453 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
454 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
458 static inline uint32_t
459 tx_desc_vlan_flags_to_cmdtype(uint16_t ol_flags)
461 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
462 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
465 /* Default RS bit threshold values */
466 #ifndef DEFAULT_TX_RS_THRESH
467 #define DEFAULT_TX_RS_THRESH 32
469 #ifndef DEFAULT_TX_FREE_THRESH
470 #define DEFAULT_TX_FREE_THRESH 32
473 /* Reset transmit descriptors after they have been used */
475 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
477 struct igb_tx_entry *sw_ring = txq->sw_ring;
478 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
479 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
480 uint16_t nb_tx_desc = txq->nb_tx_desc;
481 uint16_t desc_to_clean_to;
482 uint16_t nb_tx_to_clean;
484 /* Determine the last descriptor needing to be cleaned */
485 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
486 if (desc_to_clean_to >= nb_tx_desc)
487 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
489 /* Check to make sure the last descriptor to clean is done */
490 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
491 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
493 PMD_TX_FREE_LOG(DEBUG,
494 "TX descriptor %4u is not done"
495 "(port=%d queue=%d)",
497 txq->port_id, txq->queue_id);
498 /* Failed to clean any descriptors, better luck next time */
502 /* Figure out how many descriptors will be cleaned */
503 if (last_desc_cleaned > desc_to_clean_to)
504 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
507 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
510 PMD_TX_FREE_LOG(DEBUG,
511 "Cleaning %4u TX descriptors: %4u to %4u "
512 "(port=%d queue=%d)",
513 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
514 txq->port_id, txq->queue_id);
517 * The last descriptor to clean is done, so that means all the
518 * descriptors from the last descriptor that was cleaned
519 * up to the last descriptor with the RS bit set
520 * are done. Only reset the threshold descriptor.
522 txr[desc_to_clean_to].wb.status = 0;
524 /* Update the txq to reflect the last descriptor that was cleaned */
525 txq->last_desc_cleaned = desc_to_clean_to;
526 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
533 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
536 struct igb_tx_queue *txq;
537 struct igb_tx_entry *sw_ring;
538 struct igb_tx_entry *txe, *txn;
539 volatile union ixgbe_adv_tx_desc *txr;
540 volatile union ixgbe_adv_tx_desc *txd;
541 struct rte_mbuf *tx_pkt;
542 struct rte_mbuf *m_seg;
543 uint64_t buf_dma_addr;
544 uint32_t olinfo_status;
545 uint32_t cmd_type_len;
554 uint32_t vlan_macip_lens;
559 sw_ring = txq->sw_ring;
561 tx_id = txq->tx_tail;
562 txe = &sw_ring[tx_id];
564 /* Determine if the descriptor ring needs to be cleaned. */
565 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
566 ixgbe_xmit_cleanup(txq);
570 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
573 pkt_len = tx_pkt->pkt_len;
575 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
578 * Determine how many (if any) context descriptors
579 * are needed for offload functionality.
581 ol_flags = tx_pkt->ol_flags;
582 vlan_macip_lens = tx_pkt->vlan_macip.data;
584 /* If hardware offload required */
585 tx_ol_req = (uint16_t)(ol_flags & PKT_TX_OFFLOAD_MASK);
587 /* If new context need be built or reuse the exist ctx. */
588 ctx = what_advctx_update(txq, tx_ol_req,
590 /* Only allocate context descriptor if required*/
591 new_ctx = (ctx == IXGBE_CTX_NUM);
596 * Keep track of how many descriptors are used this loop
597 * This will always be the number of segments + the number of
598 * Context descriptors required to transmit the packet
600 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
603 * The number of descriptors that must be allocated for a
604 * packet is the number of segments of that packet, plus 1
605 * Context Descriptor for the hardware offload, if any.
606 * Determine the last TX descriptor to allocate in the TX ring
607 * for the packet, starting from the current position (tx_id)
610 tx_last = (uint16_t) (tx_id + nb_used - 1);
613 if (tx_last >= txq->nb_tx_desc)
614 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
616 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
617 " tx_first=%u tx_last=%u\n",
618 (unsigned) txq->port_id,
619 (unsigned) txq->queue_id,
625 * Make sure there are enough TX descriptors available to
626 * transmit the entire packet.
627 * nb_used better be less than or equal to txq->tx_rs_thresh
629 if (nb_used > txq->nb_tx_free) {
630 PMD_TX_FREE_LOG(DEBUG,
631 "Not enough free TX descriptors "
632 "nb_used=%4u nb_free=%4u "
633 "(port=%d queue=%d)",
634 nb_used, txq->nb_tx_free,
635 txq->port_id, txq->queue_id);
637 if (ixgbe_xmit_cleanup(txq) != 0) {
638 /* Could not clean any descriptors */
644 /* nb_used better be <= txq->tx_rs_thresh */
645 if (unlikely(nb_used > txq->tx_rs_thresh)) {
646 PMD_TX_FREE_LOG(DEBUG,
647 "The number of descriptors needed to "
648 "transmit the packet exceeds the "
649 "RS bit threshold. This will impact "
651 "nb_used=%4u nb_free=%4u "
653 "(port=%d queue=%d)",
654 nb_used, txq->nb_tx_free,
656 txq->port_id, txq->queue_id);
658 * Loop here until there are enough TX
659 * descriptors or until the ring cannot be
662 while (nb_used > txq->nb_tx_free) {
663 if (ixgbe_xmit_cleanup(txq) != 0) {
665 * Could not clean any
677 * By now there are enough free TX descriptors to transmit
682 * Set common flags of all TX Data Descriptors.
684 * The following bits must be set in all Data Descriptors:
685 * - IXGBE_ADVTXD_DTYP_DATA
686 * - IXGBE_ADVTXD_DCMD_DEXT
688 * The following bits must be set in the first Data Descriptor
689 * and are ignored in the other ones:
690 * - IXGBE_ADVTXD_DCMD_IFCS
691 * - IXGBE_ADVTXD_MAC_1588
692 * - IXGBE_ADVTXD_DCMD_VLE
694 * The following bits must only be set in the last Data
696 * - IXGBE_TXD_CMD_EOP
698 * The following bits can be set in any Data Descriptor, but
699 * are only set in the last Data Descriptor:
702 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
703 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
704 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
705 #ifdef RTE_LIBRTE_IEEE1588
706 if (ol_flags & PKT_TX_IEEE1588_TMST)
707 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
712 * Setup the TX Advanced Context Descriptor if required
715 volatile struct ixgbe_adv_tx_context_desc *
718 ctx_txd = (volatile struct
719 ixgbe_adv_tx_context_desc *)
722 txn = &sw_ring[txe->next_id];
723 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
725 if (txe->mbuf != NULL) {
726 rte_pktmbuf_free_seg(txe->mbuf);
730 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
733 txe->last_id = tx_last;
734 tx_id = txe->next_id;
739 * Setup the TX Advanced Data Descriptor,
740 * This path will go through
741 * whatever new/reuse the context descriptor
743 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
744 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
745 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
751 txn = &sw_ring[txe->next_id];
753 if (txe->mbuf != NULL)
754 rte_pktmbuf_free_seg(txe->mbuf);
758 * Set up Transmit Data Descriptor.
760 slen = m_seg->data_len;
761 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
762 txd->read.buffer_addr =
763 rte_cpu_to_le_64(buf_dma_addr);
764 txd->read.cmd_type_len =
765 rte_cpu_to_le_32(cmd_type_len | slen);
766 txd->read.olinfo_status =
767 rte_cpu_to_le_32(olinfo_status);
768 txe->last_id = tx_last;
769 tx_id = txe->next_id;
772 } while (m_seg != NULL);
775 * The last packet data descriptor needs End Of Packet (EOP)
777 cmd_type_len |= IXGBE_TXD_CMD_EOP;
778 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
779 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
781 /* Set RS bit only on threshold packets' last descriptor */
782 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
783 PMD_TX_FREE_LOG(DEBUG,
784 "Setting RS bit on TXD id="
785 "%4u (port=%d queue=%d)",
786 tx_last, txq->port_id, txq->queue_id);
788 cmd_type_len |= IXGBE_TXD_CMD_RS;
790 /* Update txq RS bit counters */
793 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
799 * Set the Transmit Descriptor Tail (TDT)
801 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
802 (unsigned) txq->port_id, (unsigned) txq->queue_id,
803 (unsigned) tx_id, (unsigned) nb_tx);
804 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
805 txq->tx_tail = tx_id;
810 /*********************************************************************
814 **********************************************************************/
815 static inline uint16_t
816 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
820 static uint16_t ip_pkt_types_map[16] = {
821 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
822 PKT_RX_IPV6_HDR, 0, 0, 0,
823 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
824 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
827 static uint16_t ip_rss_types_map[16] = {
828 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
829 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
830 PKT_RX_RSS_HASH, 0, 0, 0,
831 0, 0, 0, PKT_RX_FDIR,
834 #ifdef RTE_LIBRTE_IEEE1588
835 static uint32_t ip_pkt_etqf_map[8] = {
836 0, 0, 0, PKT_RX_IEEE1588_PTP,
840 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
841 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
842 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
844 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
845 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
848 return (uint16_t)(pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF]);
851 static inline uint16_t
852 rx_desc_status_to_pkt_flags(uint32_t rx_status)
857 * Check if VLAN present only.
858 * Do not check whether L3/L4 rx checksum done by NIC or not,
859 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
861 pkt_flags = (uint16_t)((rx_status & IXGBE_RXD_STAT_VP) ?
862 PKT_RX_VLAN_PKT : 0);
864 #ifdef RTE_LIBRTE_IEEE1588
865 if (rx_status & IXGBE_RXD_STAT_TMST)
866 pkt_flags = (uint16_t)(pkt_flags | PKT_RX_IEEE1588_TMST);
871 static inline uint16_t
872 rx_desc_error_to_pkt_flags(uint32_t rx_status)
875 * Bit 31: IPE, IPv4 checksum error
876 * Bit 30: L4I, L4I integrity error
878 static uint16_t error_to_pkt_flags_map[4] = {
879 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
880 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
882 return error_to_pkt_flags_map[(rx_status >>
883 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
886 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
888 * LOOK_AHEAD defines how many desc statuses to check beyond the
889 * current descriptor.
890 * It must be a pound define for optimal performance.
891 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
892 * function only works with LOOK_AHEAD=8.
895 #if (LOOK_AHEAD != 8)
896 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
899 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
901 volatile union ixgbe_adv_rx_desc *rxdp;
902 struct igb_rx_entry *rxep;
905 int s[LOOK_AHEAD], nb_dd;
909 /* get references to current descriptor and S/W ring entry */
910 rxdp = &rxq->rx_ring[rxq->rx_tail];
911 rxep = &rxq->sw_ring[rxq->rx_tail];
913 /* check to make sure there is at least 1 packet to receive */
914 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
918 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
919 * reference packets that are ready to be received.
921 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
922 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
924 /* Read desc statuses backwards to avoid race condition */
925 for (j = LOOK_AHEAD-1; j >= 0; --j)
926 s[j] = rxdp[j].wb.upper.status_error;
928 /* Compute how many status bits were set */
930 for (j = 0; j < LOOK_AHEAD; ++j)
931 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
935 /* Translate descriptor info to mbuf format */
936 for (j = 0; j < nb_dd; ++j) {
938 pkt_len = (uint16_t)(rxdp[j].wb.upper.length -
940 mb->data_len = pkt_len;
941 mb->pkt_len = pkt_len;
942 mb->vlan_macip.f.vlan_tci = rxdp[j].wb.upper.vlan;
943 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
945 /* convert descriptor fields to rte mbuf flags */
946 mb->ol_flags = rx_desc_hlen_type_rss_to_pkt_flags(
947 rxdp[j].wb.lower.lo_dword.data);
948 /* reuse status field from scan list */
949 mb->ol_flags = (uint16_t)(mb->ol_flags |
950 rx_desc_status_to_pkt_flags(s[j]));
951 mb->ol_flags = (uint16_t)(mb->ol_flags |
952 rx_desc_error_to_pkt_flags(s[j]));
955 /* Move mbuf pointers from the S/W ring to the stage */
956 for (j = 0; j < LOOK_AHEAD; ++j) {
957 rxq->rx_stage[i + j] = rxep[j].mbuf;
960 /* stop if all requested packets could not be received */
961 if (nb_dd != LOOK_AHEAD)
965 /* clear software ring entries so we can cleanup correctly */
966 for (i = 0; i < nb_rx; ++i) {
967 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
975 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
977 volatile union ixgbe_adv_rx_desc *rxdp;
978 struct igb_rx_entry *rxep;
984 /* allocate buffers in bulk directly into the S/W ring */
985 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
986 (rxq->rx_free_thresh - 1));
987 rxep = &rxq->sw_ring[alloc_idx];
988 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
989 rxq->rx_free_thresh);
990 if (unlikely(diag != 0))
993 rxdp = &rxq->rx_ring[alloc_idx];
994 for (i = 0; i < rxq->rx_free_thresh; ++i) {
995 /* populate the static rte mbuf fields */
997 rte_mbuf_refcnt_set(mb, 1);
999 mb->data = (char *)mb->buf_addr + RTE_PKTMBUF_HEADROOM;
1001 mb->in_port = rxq->port_id;
1003 /* populate the descriptors */
1004 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1005 rxdp[i].read.hdr_addr = dma_addr;
1006 rxdp[i].read.pkt_addr = dma_addr;
1009 /* update tail pointer */
1011 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1013 /* update state of internal queue structure */
1014 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1015 rxq->rx_free_thresh);
1016 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1017 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1023 static inline uint16_t
1024 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1027 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1030 /* how many packets are ready to return? */
1031 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1033 /* copy mbuf pointers to the application's packet list */
1034 for (i = 0; i < nb_pkts; ++i)
1035 rx_pkts[i] = stage[i];
1037 /* update internal queue state */
1038 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1039 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1044 static inline uint16_t
1045 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1048 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1051 /* Any previously recv'd pkts will be returned from the Rx stage */
1052 if (rxq->rx_nb_avail)
1053 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1055 /* Scan the H/W ring for packets to receive */
1056 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1058 /* update internal queue state */
1059 rxq->rx_next_avail = 0;
1060 rxq->rx_nb_avail = nb_rx;
1061 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1063 /* if required, allocate new buffers to replenish descriptors */
1064 if (rxq->rx_tail > rxq->rx_free_trigger) {
1065 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1067 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1068 "queue_id=%u\n", (unsigned) rxq->port_id,
1069 (unsigned) rxq->queue_id);
1071 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1072 rxq->rx_free_thresh;
1075 * Need to rewind any previous receives if we cannot
1076 * allocate new buffers to replenish the old ones.
1078 rxq->rx_nb_avail = 0;
1079 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1080 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1081 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1087 if (rxq->rx_tail >= rxq->nb_rx_desc)
1090 /* received any packets this loop? */
1091 if (rxq->rx_nb_avail)
1092 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1097 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1099 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1104 if (unlikely(nb_pkts == 0))
1107 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1108 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1110 /* request is relatively large, chunk it up */
1114 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1115 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1116 nb_rx = (uint16_t)(nb_rx + ret);
1117 nb_pkts = (uint16_t)(nb_pkts - ret);
1124 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1127 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1130 struct igb_rx_queue *rxq;
1131 volatile union ixgbe_adv_rx_desc *rx_ring;
1132 volatile union ixgbe_adv_rx_desc *rxdp;
1133 struct igb_rx_entry *sw_ring;
1134 struct igb_rx_entry *rxe;
1135 struct rte_mbuf *rxm;
1136 struct rte_mbuf *nmb;
1137 union ixgbe_adv_rx_desc rxd;
1140 uint32_t hlen_type_rss;
1150 rx_id = rxq->rx_tail;
1151 rx_ring = rxq->rx_ring;
1152 sw_ring = rxq->sw_ring;
1153 while (nb_rx < nb_pkts) {
1155 * The order of operations here is important as the DD status
1156 * bit must not be read after any other descriptor fields.
1157 * rx_ring and rxdp are pointing to volatile data so the order
1158 * of accesses cannot be reordered by the compiler. If they were
1159 * not volatile, they could be reordered which could lead to
1160 * using invalid descriptor fields when read from rxd.
1162 rxdp = &rx_ring[rx_id];
1163 staterr = rxdp->wb.upper.status_error;
1164 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1171 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1172 * is likely to be invalid and to be dropped by the various
1173 * validation checks performed by the network stack.
1175 * Allocate a new mbuf to replenish the RX ring descriptor.
1176 * If the allocation fails:
1177 * - arrange for that RX descriptor to be the first one
1178 * being parsed the next time the receive function is
1179 * invoked [on the same queue].
1181 * - Stop parsing the RX ring and return immediately.
1183 * This policy do not drop the packet received in the RX
1184 * descriptor for which the allocation of a new mbuf failed.
1185 * Thus, it allows that packet to be later retrieved if
1186 * mbuf have been freed in the mean time.
1187 * As a side effect, holding RX descriptors instead of
1188 * systematically giving them back to the NIC may lead to
1189 * RX ring exhaustion situations.
1190 * However, the NIC can gracefully prevent such situations
1191 * to happen by sending specific "back-pressure" flow control
1192 * frames to its peer(s).
1194 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1195 "ext_err_stat=0x%08x pkt_len=%u\n",
1196 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1197 (unsigned) rx_id, (unsigned) staterr,
1198 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1200 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1202 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1203 "queue_id=%u\n", (unsigned) rxq->port_id,
1204 (unsigned) rxq->queue_id);
1205 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1210 rxe = &sw_ring[rx_id];
1212 if (rx_id == rxq->nb_rx_desc)
1215 /* Prefetch next mbuf while processing current one. */
1216 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1219 * When next RX descriptor is on a cache-line boundary,
1220 * prefetch the next 4 RX descriptors and the next 8 pointers
1223 if ((rx_id & 0x3) == 0) {
1224 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1225 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1231 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1232 rxdp->read.hdr_addr = dma_addr;
1233 rxdp->read.pkt_addr = dma_addr;
1236 * Initialize the returned mbuf.
1237 * 1) setup generic mbuf fields:
1238 * - number of segments,
1241 * - RX port identifier.
1242 * 2) integrate hardware offload data, if any:
1243 * - RSS flag & hash,
1244 * - IP checksum flag,
1245 * - VLAN TCI, if any,
1248 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1250 rxm->data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1251 rte_packet_prefetch(rxm->data);
1254 rxm->pkt_len = pkt_len;
1255 rxm->data_len = pkt_len;
1256 rxm->in_port = rxq->port_id;
1258 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1259 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1260 rxm->vlan_macip.f.vlan_tci =
1261 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1263 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1264 pkt_flags = (uint16_t)(pkt_flags |
1265 rx_desc_status_to_pkt_flags(staterr));
1266 pkt_flags = (uint16_t)(pkt_flags |
1267 rx_desc_error_to_pkt_flags(staterr));
1268 rxm->ol_flags = pkt_flags;
1270 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1271 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1272 else if (pkt_flags & PKT_RX_FDIR) {
1273 rxm->hash.fdir.hash =
1274 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1275 & IXGBE_ATR_HASH_MASK);
1276 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1279 * Store the mbuf address into the next entry of the array
1280 * of returned packets.
1282 rx_pkts[nb_rx++] = rxm;
1284 rxq->rx_tail = rx_id;
1287 * If the number of free RX descriptors is greater than the RX free
1288 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1290 * Update the RDT with the value of the last processed RX descriptor
1291 * minus 1, to guarantee that the RDT register is never equal to the
1292 * RDH register, which creates a "full" ring situtation from the
1293 * hardware point of view...
1295 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1296 if (nb_hold > rxq->rx_free_thresh) {
1297 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1298 "nb_hold=%u nb_rx=%u\n",
1299 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1300 (unsigned) rx_id, (unsigned) nb_hold,
1302 rx_id = (uint16_t) ((rx_id == 0) ?
1303 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1304 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1307 rxq->nb_rx_hold = nb_hold;
1312 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1315 struct igb_rx_queue *rxq;
1316 volatile union ixgbe_adv_rx_desc *rx_ring;
1317 volatile union ixgbe_adv_rx_desc *rxdp;
1318 struct igb_rx_entry *sw_ring;
1319 struct igb_rx_entry *rxe;
1320 struct rte_mbuf *first_seg;
1321 struct rte_mbuf *last_seg;
1322 struct rte_mbuf *rxm;
1323 struct rte_mbuf *nmb;
1324 union ixgbe_adv_rx_desc rxd;
1325 uint64_t dma; /* Physical address of mbuf data buffer */
1327 uint32_t hlen_type_rss;
1337 rx_id = rxq->rx_tail;
1338 rx_ring = rxq->rx_ring;
1339 sw_ring = rxq->sw_ring;
1342 * Retrieve RX context of current packet, if any.
1344 first_seg = rxq->pkt_first_seg;
1345 last_seg = rxq->pkt_last_seg;
1347 while (nb_rx < nb_pkts) {
1350 * The order of operations here is important as the DD status
1351 * bit must not be read after any other descriptor fields.
1352 * rx_ring and rxdp are pointing to volatile data so the order
1353 * of accesses cannot be reordered by the compiler. If they were
1354 * not volatile, they could be reordered which could lead to
1355 * using invalid descriptor fields when read from rxd.
1357 rxdp = &rx_ring[rx_id];
1358 staterr = rxdp->wb.upper.status_error;
1359 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1366 * Allocate a new mbuf to replenish the RX ring descriptor.
1367 * If the allocation fails:
1368 * - arrange for that RX descriptor to be the first one
1369 * being parsed the next time the receive function is
1370 * invoked [on the same queue].
1372 * - Stop parsing the RX ring and return immediately.
1374 * This policy does not drop the packet received in the RX
1375 * descriptor for which the allocation of a new mbuf failed.
1376 * Thus, it allows that packet to be later retrieved if
1377 * mbuf have been freed in the mean time.
1378 * As a side effect, holding RX descriptors instead of
1379 * systematically giving them back to the NIC may lead to
1380 * RX ring exhaustion situations.
1381 * However, the NIC can gracefully prevent such situations
1382 * to happen by sending specific "back-pressure" flow control
1383 * frames to its peer(s).
1385 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
1386 "staterr=0x%x data_len=%u\n",
1387 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1388 (unsigned) rx_id, (unsigned) staterr,
1389 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1391 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1393 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1394 "queue_id=%u\n", (unsigned) rxq->port_id,
1395 (unsigned) rxq->queue_id);
1396 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1401 rxe = &sw_ring[rx_id];
1403 if (rx_id == rxq->nb_rx_desc)
1406 /* Prefetch next mbuf while processing current one. */
1407 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1410 * When next RX descriptor is on a cache-line boundary,
1411 * prefetch the next 4 RX descriptors and the next 8 pointers
1414 if ((rx_id & 0x3) == 0) {
1415 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1416 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1420 * Update RX descriptor with the physical address of the new
1421 * data buffer of the new allocated mbuf.
1425 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1426 rxdp->read.hdr_addr = dma;
1427 rxdp->read.pkt_addr = dma;
1430 * Set data length & data buffer address of mbuf.
1432 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1433 rxm->data_len = data_len;
1434 rxm->data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1437 * If this is the first buffer of the received packet,
1438 * set the pointer to the first mbuf of the packet and
1439 * initialize its context.
1440 * Otherwise, update the total length and the number of segments
1441 * of the current scattered packet, and update the pointer to
1442 * the last mbuf of the current packet.
1444 if (first_seg == NULL) {
1446 first_seg->pkt_len = data_len;
1447 first_seg->nb_segs = 1;
1449 first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
1451 first_seg->nb_segs++;
1452 last_seg->next = rxm;
1456 * If this is not the last buffer of the received packet,
1457 * update the pointer to the last mbuf of the current scattered
1458 * packet and continue to parse the RX ring.
1460 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1466 * This is the last buffer of the received packet.
1467 * If the CRC is not stripped by the hardware:
1468 * - Subtract the CRC length from the total packet length.
1469 * - If the last buffer only contains the whole CRC or a part
1470 * of it, free the mbuf associated to the last buffer.
1471 * If part of the CRC is also contained in the previous
1472 * mbuf, subtract the length of that CRC part from the
1473 * data length of the previous mbuf.
1476 if (unlikely(rxq->crc_len > 0)) {
1477 first_seg->pkt_len -= ETHER_CRC_LEN;
1478 if (data_len <= ETHER_CRC_LEN) {
1479 rte_pktmbuf_free_seg(rxm);
1480 first_seg->nb_segs--;
1481 last_seg->data_len = (uint16_t)
1482 (last_seg->data_len -
1483 (ETHER_CRC_LEN - data_len));
1484 last_seg->next = NULL;
1487 (uint16_t) (data_len - ETHER_CRC_LEN);
1491 * Initialize the first mbuf of the returned packet:
1492 * - RX port identifier,
1493 * - hardware offload data, if any:
1494 * - RSS flag & hash,
1495 * - IP checksum flag,
1496 * - VLAN TCI, if any,
1499 first_seg->in_port = rxq->port_id;
1502 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1503 * set in the pkt_flags field.
1505 first_seg->vlan_macip.f.vlan_tci =
1506 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1507 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1508 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1509 pkt_flags = (uint16_t)(pkt_flags |
1510 rx_desc_status_to_pkt_flags(staterr));
1511 pkt_flags = (uint16_t)(pkt_flags |
1512 rx_desc_error_to_pkt_flags(staterr));
1513 first_seg->ol_flags = pkt_flags;
1515 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1516 first_seg->hash.rss = rxd.wb.lower.hi_dword.rss;
1517 else if (pkt_flags & PKT_RX_FDIR) {
1518 first_seg->hash.fdir.hash =
1519 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1520 & IXGBE_ATR_HASH_MASK);
1521 first_seg->hash.fdir.id =
1522 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1525 /* Prefetch data of first segment, if configured to do so. */
1526 rte_packet_prefetch(first_seg->data);
1529 * Store the mbuf address into the next entry of the array
1530 * of returned packets.
1532 rx_pkts[nb_rx++] = first_seg;
1535 * Setup receipt context for a new packet.
1541 * Record index of the next RX descriptor to probe.
1543 rxq->rx_tail = rx_id;
1546 * Save receive context.
1548 rxq->pkt_first_seg = first_seg;
1549 rxq->pkt_last_seg = last_seg;
1552 * If the number of free RX descriptors is greater than the RX free
1553 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1555 * Update the RDT with the value of the last processed RX descriptor
1556 * minus 1, to guarantee that the RDT register is never equal to the
1557 * RDH register, which creates a "full" ring situtation from the
1558 * hardware point of view...
1560 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1561 if (nb_hold > rxq->rx_free_thresh) {
1562 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1563 "nb_hold=%u nb_rx=%u\n",
1564 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1565 (unsigned) rx_id, (unsigned) nb_hold,
1567 rx_id = (uint16_t) ((rx_id == 0) ?
1568 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1569 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1572 rxq->nb_rx_hold = nb_hold;
1576 /*********************************************************************
1578 * Queue management functions
1580 **********************************************************************/
1583 * Rings setup and release.
1585 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1586 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1587 * also optimize cache line size effect. H/W supports up to cache line size 128.
1589 #define IXGBE_ALIGN 128
1592 * Maximum number of Ring Descriptors.
1594 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1595 * descriptors should meet the following condition:
1596 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1598 #define IXGBE_MIN_RING_DESC 32
1599 #define IXGBE_MAX_RING_DESC 4096
1602 * Create memzone for HW rings. malloc can't be used as the physical address is
1603 * needed. If the memzone is already created, then this function returns a ptr
1606 static const struct rte_memzone *
1607 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1608 uint16_t queue_id, uint32_t ring_size, int socket_id)
1610 char z_name[RTE_MEMZONE_NAMESIZE];
1611 const struct rte_memzone *mz;
1613 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1614 dev->driver->pci_drv.name, ring_name,
1615 dev->data->port_id, queue_id);
1617 mz = rte_memzone_lookup(z_name);
1621 #ifdef RTE_LIBRTE_XEN_DOM0
1622 return rte_memzone_reserve_bounded(z_name, ring_size,
1623 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1625 return rte_memzone_reserve_aligned(z_name, ring_size,
1626 socket_id, 0, IXGBE_ALIGN);
1631 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1635 if (txq->sw_ring != NULL) {
1636 for (i = 0; i < txq->nb_tx_desc; i++) {
1637 if (txq->sw_ring[i].mbuf != NULL) {
1638 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1639 txq->sw_ring[i].mbuf = NULL;
1646 ixgbe_tx_free_swring(struct igb_tx_queue *txq)
1649 txq->sw_ring != NULL)
1650 rte_free(txq->sw_ring);
1654 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1656 if (txq != NULL && txq->ops != NULL) {
1657 txq->ops->release_mbufs(txq);
1658 txq->ops->free_swring(txq);
1664 ixgbe_dev_tx_queue_release(void *txq)
1666 ixgbe_tx_queue_release(txq);
1669 /* (Re)set dynamic igb_tx_queue fields to defaults */
1671 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1673 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1675 struct igb_tx_entry *txe = txq->sw_ring;
1678 /* Zero out HW ring memory */
1679 for (i = 0; i < txq->nb_tx_desc; i++) {
1680 txq->tx_ring[i] = zeroed_desc;
1683 /* Initialize SW ring entries */
1684 prev = (uint16_t) (txq->nb_tx_desc - 1);
1685 for (i = 0; i < txq->nb_tx_desc; i++) {
1686 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1687 txd->wb.status = IXGBE_TXD_STAT_DD;
1690 txe[prev].next_id = i;
1694 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1695 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1698 txq->nb_tx_used = 0;
1700 * Always allow 1 descriptor to be un-allocated to avoid
1701 * a H/W race condition
1703 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1704 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1706 memset((void*)&txq->ctx_cache, 0,
1707 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1710 static struct ixgbe_txq_ops def_txq_ops = {
1711 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1712 .free_swring = ixgbe_tx_free_swring,
1713 .reset = ixgbe_reset_tx_queue,
1717 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1720 unsigned int socket_id,
1721 const struct rte_eth_txconf *tx_conf)
1723 const struct rte_memzone *tz;
1724 struct igb_tx_queue *txq;
1725 struct ixgbe_hw *hw;
1726 uint16_t tx_rs_thresh, tx_free_thresh;
1728 PMD_INIT_FUNC_TRACE();
1729 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1732 * Validate number of transmit descriptors.
1733 * It must not exceed hardware maximum, and must be multiple
1736 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1737 (nb_desc > IXGBE_MAX_RING_DESC) ||
1738 (nb_desc < IXGBE_MIN_RING_DESC)) {
1743 * The following two parameters control the setting of the RS bit on
1744 * transmit descriptors.
1745 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1746 * descriptors have been used.
1747 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1748 * descriptors are used or if the number of descriptors required
1749 * to transmit a packet is greater than the number of free TX
1751 * The following constraints must be satisfied:
1752 * tx_rs_thresh must be greater than 0.
1753 * tx_rs_thresh must be less than the size of the ring minus 2.
1754 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1755 * tx_rs_thresh must be a divisor of the ring size.
1756 * tx_free_thresh must be greater than 0.
1757 * tx_free_thresh must be less than the size of the ring minus 3.
1758 * One descriptor in the TX ring is used as a sentinel to avoid a
1759 * H/W race condition, hence the maximum threshold constraints.
1760 * When set to zero use default values.
1762 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1763 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1764 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1765 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1766 if (tx_rs_thresh >= (nb_desc - 2)) {
1767 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the number "
1768 "of TX descriptors minus 2. (tx_rs_thresh=%u port=%d "
1769 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1770 (int)dev->data->port_id, (int)queue_idx);
1773 if (tx_free_thresh >= (nb_desc - 3)) {
1774 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the "
1775 "tx_free_thresh must be less than the number of TX "
1776 "descriptors minus 3. (tx_free_thresh=%u port=%d "
1777 "queue=%d)\n", (unsigned int)tx_free_thresh,
1778 (int)dev->data->port_id, (int)queue_idx);
1781 if (tx_rs_thresh > tx_free_thresh) {
1782 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than or equal to "
1783 "tx_free_thresh. (tx_free_thresh=%u tx_rs_thresh=%u "
1784 "port=%d queue=%d)\n", (unsigned int)tx_free_thresh,
1785 (unsigned int)tx_rs_thresh, (int)dev->data->port_id,
1789 if ((nb_desc % tx_rs_thresh) != 0) {
1790 RTE_LOG(ERR, PMD, "tx_rs_thresh must be a divisor of the "
1791 "number of TX descriptors. (tx_rs_thresh=%u port=%d "
1792 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1793 (int)dev->data->port_id, (int)queue_idx);
1798 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1799 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1800 * by the NIC and all descriptors are written back after the NIC
1801 * accumulates WTHRESH descriptors.
1803 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1804 RTE_LOG(ERR, PMD, "TX WTHRESH must be set to 0 if "
1805 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1806 "port=%d queue=%d)\n", (unsigned int)tx_rs_thresh,
1807 (int)dev->data->port_id, (int)queue_idx);
1811 /* Free memory prior to re-allocation if needed... */
1812 if (dev->data->tx_queues[queue_idx] != NULL) {
1813 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1814 dev->data->tx_queues[queue_idx] = NULL;
1817 /* First allocate the tx queue data structure */
1818 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct igb_tx_queue),
1819 CACHE_LINE_SIZE, socket_id);
1824 * Allocate TX ring hardware descriptors. A memzone large enough to
1825 * handle the maximum ring size is allocated in order to allow for
1826 * resizing in later calls to the queue setup function.
1828 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1829 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1832 ixgbe_tx_queue_release(txq);
1836 txq->nb_tx_desc = nb_desc;
1837 txq->tx_rs_thresh = tx_rs_thresh;
1838 txq->tx_free_thresh = tx_free_thresh;
1839 txq->pthresh = tx_conf->tx_thresh.pthresh;
1840 txq->hthresh = tx_conf->tx_thresh.hthresh;
1841 txq->wthresh = tx_conf->tx_thresh.wthresh;
1842 txq->queue_id = queue_idx;
1843 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1844 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1845 txq->port_id = dev->data->port_id;
1846 txq->txq_flags = tx_conf->txq_flags;
1847 txq->ops = &def_txq_ops;
1848 txq->start_tx_per_q = tx_conf->start_tx_per_q;
1851 * Modification to set VFTDT for virtual function if vf is detected
1853 if (hw->mac.type == ixgbe_mac_82599_vf)
1854 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1856 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1857 #ifndef RTE_LIBRTE_XEN_DOM0
1858 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1860 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1862 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1864 /* Allocate software ring */
1865 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1866 sizeof(struct igb_tx_entry) * nb_desc,
1867 CACHE_LINE_SIZE, socket_id);
1868 if (txq->sw_ring == NULL) {
1869 ixgbe_tx_queue_release(txq);
1872 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1873 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1875 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1876 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
1877 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1878 PMD_INIT_LOG(INFO, "Using simple tx code path\n");
1879 #ifdef RTE_IXGBE_INC_VECTOR
1880 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1881 ixgbe_txq_vec_setup(txq, socket_id) == 0) {
1882 PMD_INIT_LOG(INFO, "Vector tx enabled.\n");
1883 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1887 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1889 PMD_INIT_LOG(INFO, "Using full-featured tx code path\n");
1890 PMD_INIT_LOG(INFO, " - txq_flags = %lx [IXGBE_SIMPLE_FLAGS=%lx]\n", (long unsigned)txq->txq_flags, (long unsigned)IXGBE_SIMPLE_FLAGS);
1891 PMD_INIT_LOG(INFO, " - tx_rs_thresh = %lu [RTE_PMD_IXGBE_TX_MAX_BURST=%lu]\n", (long unsigned)txq->tx_rs_thresh, (long unsigned)RTE_PMD_IXGBE_TX_MAX_BURST);
1892 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1895 txq->ops->reset(txq);
1897 dev->data->tx_queues[queue_idx] = txq;
1904 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1908 if (rxq->sw_ring != NULL) {
1909 for (i = 0; i < rxq->nb_rx_desc; i++) {
1910 if (rxq->sw_ring[i].mbuf != NULL) {
1911 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1912 rxq->sw_ring[i].mbuf = NULL;
1915 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1916 if (rxq->rx_nb_avail) {
1917 for (i = 0; i < rxq->rx_nb_avail; ++i) {
1918 struct rte_mbuf *mb;
1919 mb = rxq->rx_stage[rxq->rx_next_avail + i];
1920 rte_pktmbuf_free_seg(mb);
1922 rxq->rx_nb_avail = 0;
1929 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
1932 ixgbe_rx_queue_release_mbufs(rxq);
1933 rte_free(rxq->sw_ring);
1939 ixgbe_dev_rx_queue_release(void *rxq)
1941 ixgbe_rx_queue_release(rxq);
1945 * Check if Rx Burst Bulk Alloc function can be used.
1947 * 0: the preconditions are satisfied and the bulk allocation function
1949 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
1950 * function must be used.
1953 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1954 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
1956 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct igb_rx_queue *rxq)
1962 * Make sure the following pre-conditions are satisfied:
1963 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
1964 * rxq->rx_free_thresh < rxq->nb_rx_desc
1965 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
1966 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
1967 * Scattered packets are not supported. This should be checked
1968 * outside of this function.
1970 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1971 if (! (rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST))
1973 else if (! (rxq->rx_free_thresh < rxq->nb_rx_desc))
1975 else if (! ((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0))
1977 else if (! (rxq->nb_rx_desc <
1978 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST)))
1987 /* Reset dynamic igb_rx_queue fields back to defaults */
1989 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
1991 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
1997 * By default, the Rx queue setup function allocates enough memory for
1998 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
1999 * extra memory at the end of the descriptor ring to be zero'd out. A
2000 * pre-condition for using the Rx burst bulk alloc function is that the
2001 * number of descriptors is less than or equal to
2002 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2003 * constraints here to see if we need to zero out memory after the end
2004 * of the H/W descriptor ring.
2006 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2007 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2008 /* zero out extra memory */
2009 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2012 /* do not zero out extra memory */
2013 len = rxq->nb_rx_desc;
2016 * Zero out HW ring memory. Zero out extra memory at the end of
2017 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2018 * reads extra memory as zeros.
2020 for (i = 0; i < len; i++) {
2021 rxq->rx_ring[i] = zeroed_desc;
2024 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2026 * initialize extra software ring entries. Space for these extra
2027 * entries is always allocated
2029 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2030 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2031 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2034 rxq->rx_nb_avail = 0;
2035 rxq->rx_next_avail = 0;
2036 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2037 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2039 rxq->nb_rx_hold = 0;
2040 rxq->pkt_first_seg = NULL;
2041 rxq->pkt_last_seg = NULL;
2045 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2048 unsigned int socket_id,
2049 const struct rte_eth_rxconf *rx_conf,
2050 struct rte_mempool *mp)
2052 const struct rte_memzone *rz;
2053 struct igb_rx_queue *rxq;
2054 struct ixgbe_hw *hw;
2055 int use_def_burst_func = 1;
2058 PMD_INIT_FUNC_TRACE();
2059 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2062 * Validate number of receive descriptors.
2063 * It must not exceed hardware maximum, and must be multiple
2066 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2067 (nb_desc > IXGBE_MAX_RING_DESC) ||
2068 (nb_desc < IXGBE_MIN_RING_DESC)) {
2072 /* Free memory prior to re-allocation if needed... */
2073 if (dev->data->rx_queues[queue_idx] != NULL) {
2074 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2075 dev->data->rx_queues[queue_idx] = NULL;
2078 /* First allocate the rx queue data structure */
2079 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct igb_rx_queue),
2080 CACHE_LINE_SIZE, socket_id);
2084 rxq->nb_rx_desc = nb_desc;
2085 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2086 rxq->queue_id = queue_idx;
2087 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2088 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2089 rxq->port_id = dev->data->port_id;
2090 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2092 rxq->drop_en = rx_conf->rx_drop_en;
2093 rxq->start_rx_per_q = rx_conf->start_rx_per_q;
2096 * Allocate RX ring hardware descriptors. A memzone large enough to
2097 * handle the maximum ring size is allocated in order to allow for
2098 * resizing in later calls to the queue setup function.
2100 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2101 RX_RING_SZ, socket_id);
2103 ixgbe_rx_queue_release(rxq);
2108 * Zero init all the descriptors in the ring.
2110 memset (rz->addr, 0, RX_RING_SZ);
2113 * Modified to setup VFRDT for Virtual Function
2115 if (hw->mac.type == ixgbe_mac_82599_vf) {
2117 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2119 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2123 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2125 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2127 #ifndef RTE_LIBRTE_XEN_DOM0
2128 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2130 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2132 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2135 * Allocate software ring. Allow for space at the end of the
2136 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2137 * function does not access an invalid memory region.
2139 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2140 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2144 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2145 sizeof(struct igb_rx_entry) * len,
2146 CACHE_LINE_SIZE, socket_id);
2147 if (rxq->sw_ring == NULL) {
2148 ixgbe_rx_queue_release(rxq);
2151 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
2152 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2155 * Certain constraints must be met in order to use the bulk buffer
2156 * allocation Rx burst function.
2158 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2160 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2161 if (!use_def_burst_func && !dev->data->scattered_rx) {
2162 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2163 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2164 "satisfied. Rx Burst Bulk Alloc function will be "
2165 "used on port=%d, queue=%d.\n",
2166 rxq->port_id, rxq->queue_id);
2167 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2168 #ifdef RTE_IXGBE_INC_VECTOR
2169 if (!ixgbe_rx_vec_condition_check(dev)) {
2170 PMD_INIT_LOG(INFO, "Vector rx enabled, please make "
2171 "sure RX burst size no less than 32.\n");
2172 ixgbe_rxq_vec_setup(rxq, socket_id);
2173 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
2178 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2179 "are not satisfied, Scattered Rx is requested, "
2180 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2181 "enabled (port=%d, queue=%d).\n",
2182 rxq->port_id, rxq->queue_id);
2184 dev->data->rx_queues[queue_idx] = rxq;
2186 ixgbe_reset_rx_queue(rxq);
2192 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2194 #define IXGBE_RXQ_SCAN_INTERVAL 4
2195 volatile union ixgbe_adv_rx_desc *rxdp;
2196 struct igb_rx_queue *rxq;
2199 if (rx_queue_id >= dev->data->nb_rx_queues) {
2200 PMD_RX_LOG(ERR, "Invalid RX queue id=%d\n", rx_queue_id);
2204 rxq = dev->data->rx_queues[rx_queue_id];
2205 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2207 while ((desc < rxq->nb_rx_desc) &&
2208 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2209 desc += IXGBE_RXQ_SCAN_INTERVAL;
2210 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2211 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2212 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2213 desc - rxq->nb_rx_desc]);
2220 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2222 volatile union ixgbe_adv_rx_desc *rxdp;
2223 struct igb_rx_queue *rxq = rx_queue;
2226 if (unlikely(offset >= rxq->nb_rx_desc))
2228 desc = rxq->rx_tail + offset;
2229 if (desc >= rxq->nb_rx_desc)
2230 desc -= rxq->nb_rx_desc;
2232 rxdp = &rxq->rx_ring[desc];
2233 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2237 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2241 PMD_INIT_FUNC_TRACE();
2243 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2244 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2246 txq->ops->release_mbufs(txq);
2247 txq->ops->reset(txq);
2251 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2252 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2254 ixgbe_rx_queue_release_mbufs(rxq);
2255 ixgbe_reset_rx_queue(rxq);
2260 /*********************************************************************
2262 * Device RX/TX init functions
2264 **********************************************************************/
2267 * Receive Side Scaling (RSS)
2268 * See section 7.1.2.8 in the following document:
2269 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2272 * The source and destination IP addresses of the IP header and the source
2273 * and destination ports of TCP/UDP headers, if any, of received packets are
2274 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2275 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2276 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2277 * RSS output index which is used as the RX queue index where to store the
2279 * The following output is supplied in the RX write-back descriptor:
2280 * - 32-bit result of the Microsoft RSS hash function,
2281 * - 4-bit RSS type field.
2285 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2286 * Used as the default key.
2288 static uint8_t rss_intel_key[40] = {
2289 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2290 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2291 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2292 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2293 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2297 ixgbe_rss_disable(struct rte_eth_dev *dev)
2299 struct ixgbe_hw *hw;
2302 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2303 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2304 mrqc &= ~IXGBE_MRQC_RSSEN;
2305 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2309 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2317 hash_key = rss_conf->rss_key;
2318 if (hash_key != NULL) {
2319 /* Fill in RSS hash key */
2320 for (i = 0; i < 10; i++) {
2321 rss_key = hash_key[(i * 4)];
2322 rss_key |= hash_key[(i * 4) + 1] << 8;
2323 rss_key |= hash_key[(i * 4) + 2] << 16;
2324 rss_key |= hash_key[(i * 4) + 3] << 24;
2325 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2329 /* Set configured hashing protocols in MRQC register */
2330 rss_hf = rss_conf->rss_hf;
2331 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2332 if (rss_hf & ETH_RSS_IPV4)
2333 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2334 if (rss_hf & ETH_RSS_IPV4_TCP)
2335 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2336 if (rss_hf & ETH_RSS_IPV6)
2337 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2338 if (rss_hf & ETH_RSS_IPV6_EX)
2339 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2340 if (rss_hf & ETH_RSS_IPV6_TCP)
2341 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2342 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2343 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2344 if (rss_hf & ETH_RSS_IPV4_UDP)
2345 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2346 if (rss_hf & ETH_RSS_IPV6_UDP)
2347 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2348 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2349 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2350 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2354 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2355 struct rte_eth_rss_conf *rss_conf)
2357 struct ixgbe_hw *hw;
2361 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2364 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2365 * "RSS enabling cannot be done dynamically while it must be
2366 * preceded by a software reset"
2367 * Before changing anything, first check that the update RSS operation
2368 * does not attempt to disable RSS, if RSS was enabled at
2369 * initialization time, or does not attempt to enable RSS, if RSS was
2370 * disabled at initialization time.
2372 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2373 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2374 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2375 if (rss_hf != 0) /* Enable RSS */
2377 return 0; /* Nothing to do */
2380 if (rss_hf == 0) /* Disable RSS */
2382 ixgbe_hw_rss_hash_set(hw, rss_conf);
2387 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2388 struct rte_eth_rss_conf *rss_conf)
2390 struct ixgbe_hw *hw;
2397 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2398 hash_key = rss_conf->rss_key;
2399 if (hash_key != NULL) {
2400 /* Return RSS hash key */
2401 for (i = 0; i < 10; i++) {
2402 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2403 hash_key[(i * 4)] = rss_key & 0x000000FF;
2404 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2405 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2406 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2410 /* Get RSS functions configured in MRQC register */
2411 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2412 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2413 rss_conf->rss_hf = 0;
2417 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2418 rss_hf |= ETH_RSS_IPV4;
2419 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2420 rss_hf |= ETH_RSS_IPV4_TCP;
2421 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2422 rss_hf |= ETH_RSS_IPV6;
2423 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2424 rss_hf |= ETH_RSS_IPV6_EX;
2425 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2426 rss_hf |= ETH_RSS_IPV6_TCP;
2427 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2428 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2429 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2430 rss_hf |= ETH_RSS_IPV4_UDP;
2431 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2432 rss_hf |= ETH_RSS_IPV6_UDP;
2433 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2434 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2435 rss_conf->rss_hf = rss_hf;
2440 ixgbe_rss_configure(struct rte_eth_dev *dev)
2442 struct rte_eth_rss_conf rss_conf;
2443 struct ixgbe_hw *hw;
2448 PMD_INIT_FUNC_TRACE();
2449 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2452 * Fill in redirection table
2453 * The byte-swap is needed because NIC registers are in
2454 * little-endian order.
2457 for (i = 0, j = 0; i < 128; i++, j++) {
2458 if (j == dev->data->nb_rx_queues)
2460 reta = (reta << 8) | j;
2462 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2467 * Configure the RSS key and the RSS protocols used to compute
2468 * the RSS hash of input packets.
2470 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2471 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2472 ixgbe_rss_disable(dev);
2475 if (rss_conf.rss_key == NULL)
2476 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2477 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2480 #define NUM_VFTA_REGISTERS 128
2481 #define NIC_RX_BUFFER_SIZE 0x200
2484 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2486 struct rte_eth_vmdq_dcb_conf *cfg;
2487 struct ixgbe_hw *hw;
2488 enum rte_eth_nb_pools num_pools;
2489 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2491 uint8_t nb_tcs; /* number of traffic classes */
2494 PMD_INIT_FUNC_TRACE();
2495 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2496 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2497 num_pools = cfg->nb_queue_pools;
2498 /* Check we have a valid number of pools */
2499 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2500 ixgbe_rss_disable(dev);
2503 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2504 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2508 * split rx buffer up into sections, each for 1 traffic class
2510 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2511 for (i = 0 ; i < nb_tcs; i++) {
2512 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2513 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2514 /* clear 10 bits. */
2515 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2516 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2518 /* zero alloc all unused TCs */
2519 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2520 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2521 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2522 /* clear 10 bits. */
2523 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2526 /* MRQC: enable vmdq and dcb */
2527 mrqc = ((num_pools == ETH_16_POOLS) ? \
2528 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2529 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2531 /* PFVTCTL: turn on virtualisation and set the default pool */
2532 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2533 if (cfg->enable_default_pool) {
2534 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2536 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2539 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2541 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2543 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2545 * mapping is done with 3 bits per priority,
2546 * so shift by i*3 each time
2548 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2550 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2552 /* RTRPCS: DCB related */
2553 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2555 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2556 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2557 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2558 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2560 /* VFTA - enable all vlan filters */
2561 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2562 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2565 /* VFRE: pool enabling for receive - 16 or 32 */
2566 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2567 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2570 * MPSAR - allow pools to read specific mac addresses
2571 * In this case, all pools should be able to read from mac addr 0
2573 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2574 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2576 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2577 for (i = 0; i < cfg->nb_pool_maps; i++) {
2578 /* set vlan id in VF register and set the valid bit */
2579 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2580 (cfg->pool_map[i].vlan_id & 0xFFF)));
2582 * Put the allowed pools in VFB reg. As we only have 16 or 32
2583 * pools, we only need to use the first half of the register
2586 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2591 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2592 * @hw: pointer to hardware structure
2593 * @dcb_config: pointer to ixgbe_dcb_config structure
2596 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2597 struct ixgbe_dcb_config *dcb_config)
2602 PMD_INIT_FUNC_TRACE();
2603 if (hw->mac.type != ixgbe_mac_82598EB) {
2604 /* Disable the Tx desc arbiter so that MTQC can be changed */
2605 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2606 reg |= IXGBE_RTTDCS_ARBDIS;
2607 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2609 /* Enable DCB for Tx with 8 TCs */
2610 if (dcb_config->num_tcs.pg_tcs == 8) {
2611 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2614 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2616 if (dcb_config->vt_mode)
2617 reg |= IXGBE_MTQC_VT_ENA;
2618 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2620 /* Disable drop for all queues */
2621 for (q = 0; q < 128; q++)
2622 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2623 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2625 /* Enable the Tx desc arbiter */
2626 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2627 reg &= ~IXGBE_RTTDCS_ARBDIS;
2628 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2630 /* Enable Security TX Buffer IFG for DCB */
2631 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2632 reg |= IXGBE_SECTX_DCB;
2633 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2639 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2640 * @dev: pointer to rte_eth_dev structure
2641 * @dcb_config: pointer to ixgbe_dcb_config structure
2644 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2645 struct ixgbe_dcb_config *dcb_config)
2647 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2648 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2649 struct ixgbe_hw *hw =
2650 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2652 PMD_INIT_FUNC_TRACE();
2653 if (hw->mac.type != ixgbe_mac_82598EB)
2654 /*PF VF Transmit Enable*/
2655 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2656 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2658 /*Configure general DCB TX parameters*/
2659 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2664 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2665 struct ixgbe_dcb_config *dcb_config)
2667 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2668 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2669 struct ixgbe_dcb_tc_config *tc;
2672 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2673 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2674 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2675 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2678 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2679 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2681 /* User Priority to Traffic Class mapping */
2682 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2683 j = vmdq_rx_conf->dcb_queue[i];
2684 tc = &dcb_config->tc_config[j];
2685 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2691 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2692 struct ixgbe_dcb_config *dcb_config)
2694 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2695 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2696 struct ixgbe_dcb_tc_config *tc;
2699 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2700 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2701 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2702 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2705 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2706 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2709 /* User Priority to Traffic Class mapping */
2710 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2711 j = vmdq_tx_conf->dcb_queue[i];
2712 tc = &dcb_config->tc_config[j];
2713 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2720 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2721 struct ixgbe_dcb_config *dcb_config)
2723 struct rte_eth_dcb_rx_conf *rx_conf =
2724 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2725 struct ixgbe_dcb_tc_config *tc;
2728 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2729 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2731 /* User Priority to Traffic Class mapping */
2732 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2733 j = rx_conf->dcb_queue[i];
2734 tc = &dcb_config->tc_config[j];
2735 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2741 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2742 struct ixgbe_dcb_config *dcb_config)
2744 struct rte_eth_dcb_tx_conf *tx_conf =
2745 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2746 struct ixgbe_dcb_tc_config *tc;
2749 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2750 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2752 /* User Priority to Traffic Class mapping */
2753 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2754 j = tx_conf->dcb_queue[i];
2755 tc = &dcb_config->tc_config[j];
2756 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2762 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2763 * @hw: pointer to hardware structure
2764 * @dcb_config: pointer to ixgbe_dcb_config structure
2767 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2768 struct ixgbe_dcb_config *dcb_config)
2774 PMD_INIT_FUNC_TRACE();
2776 * Disable the arbiter before changing parameters
2777 * (always enable recycle mode; WSP)
2779 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2780 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2782 if (hw->mac.type != ixgbe_mac_82598EB) {
2783 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2784 if (dcb_config->num_tcs.pg_tcs == 4) {
2785 if (dcb_config->vt_mode)
2786 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2787 IXGBE_MRQC_VMDQRT4TCEN;
2789 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2790 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2794 if (dcb_config->num_tcs.pg_tcs == 8) {
2795 if (dcb_config->vt_mode)
2796 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2797 IXGBE_MRQC_VMDQRT8TCEN;
2799 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2800 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2805 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2808 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2809 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2810 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2811 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2813 /* VFTA - enable all vlan filters */
2814 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2815 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2819 * Configure Rx packet plane (recycle mode; WSP) and
2822 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2823 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2829 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2830 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2832 switch (hw->mac.type) {
2833 case ixgbe_mac_82598EB:
2834 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2836 case ixgbe_mac_82599EB:
2837 case ixgbe_mac_X540:
2838 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2847 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2848 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2850 switch (hw->mac.type) {
2851 case ixgbe_mac_82598EB:
2852 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2853 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2855 case ixgbe_mac_82599EB:
2856 case ixgbe_mac_X540:
2857 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2858 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2865 #define DCB_RX_CONFIG 1
2866 #define DCB_TX_CONFIG 1
2867 #define DCB_TX_PB 1024
2869 * ixgbe_dcb_hw_configure - Enable DCB and configure
2870 * general DCB in VT mode and non-VT mode parameters
2871 * @dev: pointer to rte_eth_dev structure
2872 * @dcb_config: pointer to ixgbe_dcb_config structure
2875 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2876 struct ixgbe_dcb_config *dcb_config)
2879 uint8_t i,pfc_en,nb_tcs;
2881 uint8_t config_dcb_rx = 0;
2882 uint8_t config_dcb_tx = 0;
2883 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2884 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2885 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2886 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2887 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2888 struct ixgbe_dcb_tc_config *tc;
2889 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2890 struct ixgbe_hw *hw =
2891 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2893 switch(dev->data->dev_conf.rxmode.mq_mode){
2894 case ETH_MQ_RX_VMDQ_DCB:
2895 dcb_config->vt_mode = true;
2896 if (hw->mac.type != ixgbe_mac_82598EB) {
2897 config_dcb_rx = DCB_RX_CONFIG;
2899 *get dcb and VT rx configuration parameters
2902 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2903 /*Configure general VMDQ and DCB RX parameters*/
2904 ixgbe_vmdq_dcb_configure(dev);
2908 dcb_config->vt_mode = false;
2909 config_dcb_rx = DCB_RX_CONFIG;
2910 /* Get dcb TX configuration parameters from rte_eth_conf */
2911 ixgbe_dcb_rx_config(dev,dcb_config);
2912 /*Configure general DCB RX parameters*/
2913 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2916 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration\n");
2919 switch (dev->data->dev_conf.txmode.mq_mode) {
2920 case ETH_MQ_TX_VMDQ_DCB:
2921 dcb_config->vt_mode = true;
2922 config_dcb_tx = DCB_TX_CONFIG;
2923 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2924 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2925 /*Configure general VMDQ and DCB TX parameters*/
2926 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2930 dcb_config->vt_mode = false;
2931 config_dcb_tx = DCB_TX_CONFIG;
2932 /*get DCB TX configuration parameters from rte_eth_conf*/
2933 ixgbe_dcb_tx_config(dev,dcb_config);
2934 /*Configure general DCB TX parameters*/
2935 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2938 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration\n");
2942 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2944 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2945 if(nb_tcs == ETH_4_TCS) {
2946 /* Avoid un-configured priority mapping to TC0 */
2948 uint8_t mask = 0xFF;
2949 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
2950 mask = (uint8_t)(mask & (~ (1 << map[i])));
2951 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
2952 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
2956 /* Re-configure 4 TCs BW */
2957 for (i = 0; i < nb_tcs; i++) {
2958 tc = &dcb_config->tc_config[i];
2959 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
2960 (uint8_t)(100 / nb_tcs);
2961 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
2962 (uint8_t)(100 / nb_tcs);
2964 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2965 tc = &dcb_config->tc_config[i];
2966 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
2967 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
2972 /* Set RX buffer size */
2973 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2974 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
2975 for (i = 0 ; i < nb_tcs; i++) {
2976 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2978 /* zero alloc all unused TCs */
2979 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2980 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
2984 /* Only support an equally distributed Tx packet buffer strategy. */
2985 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
2986 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
2987 for (i = 0; i < nb_tcs; i++) {
2988 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
2989 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
2991 /* Clear unused TCs, if any, to zero buffer size*/
2992 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2993 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
2994 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
2998 /*Calculates traffic class credits*/
2999 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3000 IXGBE_DCB_TX_CONFIG);
3001 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3002 IXGBE_DCB_RX_CONFIG);
3005 /* Unpack CEE standard containers */
3006 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3007 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3008 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3009 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3010 /* Configure PG(ETS) RX */
3011 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3015 /* Unpack CEE standard containers */
3016 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3017 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3018 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3019 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3020 /* Configure PG(ETS) TX */
3021 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3024 /*Configure queue statistics registers*/
3025 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3027 /* Check if the PFC is supported */
3028 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3029 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3030 for (i = 0; i < nb_tcs; i++) {
3032 * If the TC count is 8,and the default high_water is 48,
3033 * the low_water is 16 as default.
3035 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3036 hw->fc.low_water[i] = pbsize / 4;
3037 /* Enable pfc for this TC */
3038 tc = &dcb_config->tc_config[i];
3039 tc->pfc = ixgbe_dcb_pfc_enabled;
3041 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3042 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3044 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3051 * ixgbe_configure_dcb - Configure DCB Hardware
3052 * @dev: pointer to rte_eth_dev
3054 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3056 struct ixgbe_dcb_config *dcb_cfg =
3057 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3058 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3060 PMD_INIT_FUNC_TRACE();
3062 /* check support mq_mode for DCB */
3063 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3064 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3067 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3070 /** Configure DCB hardware **/
3071 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3077 * VMDq only support for 10 GbE NIC.
3080 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3082 struct rte_eth_vmdq_rx_conf *cfg;
3083 struct ixgbe_hw *hw;
3084 enum rte_eth_nb_pools num_pools;
3085 uint32_t mrqc, vt_ctl, vlanctrl;
3088 PMD_INIT_FUNC_TRACE();
3089 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3090 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3091 num_pools = cfg->nb_queue_pools;
3093 ixgbe_rss_disable(dev);
3095 /* MRQC: enable vmdq */
3096 mrqc = IXGBE_MRQC_VMDQEN;
3097 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3099 /* PFVTCTL: turn on virtualisation and set the default pool */
3100 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3101 if (cfg->enable_default_pool)
3102 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3104 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3106 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3108 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3109 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3110 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3111 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3113 /* VFTA - enable all vlan filters */
3114 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3115 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3117 /* VFRE: pool enabling for receive - 64 */
3118 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3119 if (num_pools == ETH_64_POOLS)
3120 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3123 * MPSAR - allow pools to read specific mac addresses
3124 * In this case, all pools should be able to read from mac addr 0
3126 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3127 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3129 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3130 for (i = 0; i < cfg->nb_pool_maps; i++) {
3131 /* set vlan id in VF register and set the valid bit */
3132 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3133 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3135 * Put the allowed pools in VFB reg. As we only have 16 or 64
3136 * pools, we only need to use the first half of the register
3139 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3140 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3141 (cfg->pool_map[i].pools & UINT32_MAX));
3143 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3144 ((cfg->pool_map[i].pools >> 32) \
3149 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3150 if (cfg->enable_loop_back) {
3151 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3152 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3153 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3156 IXGBE_WRITE_FLUSH(hw);
3160 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3161 * @hw: pointer to hardware structure
3164 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3169 PMD_INIT_FUNC_TRACE();
3170 /*PF VF Transmit Enable*/
3171 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3172 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3174 /* Disable the Tx desc arbiter so that MTQC can be changed */
3175 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3176 reg |= IXGBE_RTTDCS_ARBDIS;
3177 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3179 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3180 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3182 /* Disable drop for all queues */
3183 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3184 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3185 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3187 /* Enable the Tx desc arbiter */
3188 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3189 reg &= ~IXGBE_RTTDCS_ARBDIS;
3190 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3192 IXGBE_WRITE_FLUSH(hw);
3198 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
3200 struct igb_rx_entry *rxe = rxq->sw_ring;
3204 /* Initialize software ring entries */
3205 for (i = 0; i < rxq->nb_rx_desc; i++) {
3206 volatile union ixgbe_adv_rx_desc *rxd;
3207 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3209 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u\n",
3210 (unsigned) rxq->queue_id);
3214 rte_mbuf_refcnt_set(mbuf, 1);
3216 mbuf->data = (char *)mbuf->buf_addr + RTE_PKTMBUF_HEADROOM;
3218 mbuf->in_port = rxq->port_id;
3221 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3222 rxd = &rxq->rx_ring[i];
3223 rxd->read.hdr_addr = dma_addr;
3224 rxd->read.pkt_addr = dma_addr;
3232 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3234 struct ixgbe_hw *hw =
3235 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3237 if (hw->mac.type == ixgbe_mac_82598EB)
3240 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3242 * SRIOV inactive scheme
3243 * any DCB/RSS w/o VMDq multi-queue setting
3245 switch (dev->data->dev_conf.rxmode.mq_mode) {
3247 ixgbe_rss_configure(dev);
3250 case ETH_MQ_RX_VMDQ_DCB:
3251 ixgbe_vmdq_dcb_configure(dev);
3254 case ETH_MQ_RX_VMDQ_ONLY:
3255 ixgbe_vmdq_rx_hw_configure(dev);
3258 case ETH_MQ_RX_NONE:
3259 /* if mq_mode is none, disable rss mode.*/
3260 default: ixgbe_rss_disable(dev);
3263 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3265 * SRIOV active scheme
3266 * FIXME if support DCB/RSS together with VMDq & SRIOV
3269 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQEN);
3273 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT4TCEN);
3277 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT8TCEN);
3280 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3288 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3290 struct ixgbe_hw *hw =
3291 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3295 if (hw->mac.type == ixgbe_mac_82598EB)
3298 /* disable arbiter before setting MTQC */
3299 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3300 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3301 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3303 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3305 * SRIOV inactive scheme
3306 * any DCB w/o VMDq multi-queue setting
3308 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3309 ixgbe_vmdq_tx_hw_configure(hw);
3311 mtqc = IXGBE_MTQC_64Q_1PB;
3312 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3315 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3318 * SRIOV active scheme
3319 * FIXME if support DCB together with VMDq & SRIOV
3322 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3325 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3328 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3332 mtqc = IXGBE_MTQC_64Q_1PB;
3333 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3335 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3338 /* re-enable arbiter */
3339 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3340 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3346 * Initializes Receive Unit.
3349 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3351 struct ixgbe_hw *hw;
3352 struct igb_rx_queue *rxq;
3353 struct rte_pktmbuf_pool_private *mbp_priv;
3365 PMD_INIT_FUNC_TRACE();
3366 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3369 * Make sure receives are disabled while setting
3370 * up the RX context (registers, descriptor rings, etc.).
3372 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3373 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3375 /* Enable receipt of broadcasted frames */
3376 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3377 fctrl |= IXGBE_FCTRL_BAM;
3378 fctrl |= IXGBE_FCTRL_DPF;
3379 fctrl |= IXGBE_FCTRL_PMCF;
3380 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3383 * Configure CRC stripping, if any.
3385 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3386 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3387 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3389 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3392 * Configure jumbo frame support, if any.
3394 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3395 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3396 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3397 maxfrs &= 0x0000FFFF;
3398 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3399 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3401 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3404 * If loopback mode is configured for 82599, set LPBK bit.
3406 if (hw->mac.type == ixgbe_mac_82599EB &&
3407 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3408 hlreg0 |= IXGBE_HLREG0_LPBK;
3410 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3412 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3414 /* Setup RX queues */
3415 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3416 rxq = dev->data->rx_queues[i];
3419 * Reset crc_len in case it was changed after queue setup by a
3420 * call to configure.
3422 rxq->crc_len = (uint8_t)
3423 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3426 /* Setup the Base and Length of the Rx Descriptor Rings */
3427 bus_addr = rxq->rx_ring_phys_addr;
3428 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3429 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3430 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3431 (uint32_t)(bus_addr >> 32));
3432 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3433 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3434 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3435 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3437 /* Configure the SRRCTL register */
3438 #ifdef RTE_HEADER_SPLIT_ENABLE
3440 * Configure Header Split
3442 if (dev->data->dev_conf.rxmode.header_split) {
3443 if (hw->mac.type == ixgbe_mac_82599EB) {
3444 /* Must setup the PSRTYPE register */
3446 psrtype = IXGBE_PSRTYPE_TCPHDR |
3447 IXGBE_PSRTYPE_UDPHDR |
3448 IXGBE_PSRTYPE_IPV4HDR |
3449 IXGBE_PSRTYPE_IPV6HDR;
3450 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3452 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3453 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3454 IXGBE_SRRCTL_BSIZEHDR_MASK);
3455 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3458 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3460 /* Set if packets are dropped when no descriptors available */
3462 srrctl |= IXGBE_SRRCTL_DROP_EN;
3465 * Configure the RX buffer size in the BSIZEPACKET field of
3466 * the SRRCTL register of the queue.
3467 * The value is in 1 KB resolution. Valid values can be from
3470 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3471 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3472 RTE_PKTMBUF_HEADROOM);
3473 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3474 IXGBE_SRRCTL_BSIZEPKT_MASK);
3475 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3477 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3478 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3480 /* It adds dual VLAN length for supporting dual VLAN */
3481 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3482 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3483 dev->data->scattered_rx = 1;
3484 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3488 if (dev->data->dev_conf.rxmode.enable_scatter) {
3489 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3490 dev->data->scattered_rx = 1;
3494 * Device configured with multiple RX queues.
3496 ixgbe_dev_mq_rx_configure(dev);
3499 * Setup the Checksum Register.
3500 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3501 * Enable IP/L4 checkum computation by hardware if requested to do so.
3503 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3504 rxcsum |= IXGBE_RXCSUM_PCSD;
3505 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3506 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3508 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3510 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3512 if (hw->mac.type == ixgbe_mac_82599EB) {
3513 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3514 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3515 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3517 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3518 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3519 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3526 * Initializes Transmit Unit.
3529 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3531 struct ixgbe_hw *hw;
3532 struct igb_tx_queue *txq;
3538 PMD_INIT_FUNC_TRACE();
3539 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3541 /* Enable TX CRC (checksum offload requirement) */
3542 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3543 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
3544 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3546 /* Setup the Base and Length of the Tx Descriptor Rings */
3547 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3548 txq = dev->data->tx_queues[i];
3550 bus_addr = txq->tx_ring_phys_addr;
3551 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3552 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3553 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3554 (uint32_t)(bus_addr >> 32));
3555 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3556 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3557 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3558 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3559 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3562 * Disable Tx Head Writeback RO bit, since this hoses
3563 * bookkeeping if things aren't delivered in order.
3565 switch (hw->mac.type) {
3566 case ixgbe_mac_82598EB:
3567 txctrl = IXGBE_READ_REG(hw,
3568 IXGBE_DCA_TXCTRL(txq->reg_idx));
3569 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3570 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3574 case ixgbe_mac_82599EB:
3575 case ixgbe_mac_X540:
3577 txctrl = IXGBE_READ_REG(hw,
3578 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3579 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3580 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3586 /* Device configured with multiple TX queues. */
3587 ixgbe_dev_mq_tx_configure(dev);
3591 * Set up link for 82599 loopback mode Tx->Rx.
3594 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3596 DEBUGFUNC("ixgbe_setup_loopback_link_82599");
3598 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3599 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3601 PMD_INIT_LOG(ERR, "Could not enable loopback mode\n");
3610 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3611 ixgbe_reset_pipeline_82599(hw);
3613 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3619 * Start Transmit and Receive Units.
3622 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3624 struct ixgbe_hw *hw;
3625 struct igb_tx_queue *txq;
3626 struct igb_rx_queue *rxq;
3632 PMD_INIT_FUNC_TRACE();
3633 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3635 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3636 txq = dev->data->tx_queues[i];
3637 /* Setup Transmit Threshold Registers */
3638 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3639 txdctl |= txq->pthresh & 0x7F;
3640 txdctl |= ((txq->hthresh & 0x7F) << 8);
3641 txdctl |= ((txq->wthresh & 0x7F) << 16);
3642 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3645 if (hw->mac.type != ixgbe_mac_82598EB) {
3646 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3647 dmatxctl |= IXGBE_DMATXCTL_TE;
3648 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3651 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3652 txq = dev->data->tx_queues[i];
3653 if (!txq->start_tx_per_q)
3654 ixgbe_dev_tx_queue_start(dev, i);
3657 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3658 rxq = dev->data->rx_queues[i];
3659 if (!rxq->start_rx_per_q)
3660 ixgbe_dev_rx_queue_start(dev, i);
3663 /* Enable Receive engine */
3664 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3665 if (hw->mac.type == ixgbe_mac_82598EB)
3666 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3667 rxctrl |= IXGBE_RXCTRL_RXEN;
3668 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3670 /* If loopback mode is enabled for 82599, set up the link accordingly */
3671 if (hw->mac.type == ixgbe_mac_82599EB &&
3672 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3673 ixgbe_setup_loopback_link_82599(hw);
3678 * Start Receive Units for specified queue.
3681 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3683 struct ixgbe_hw *hw;
3684 struct igb_rx_queue *rxq;
3688 PMD_INIT_FUNC_TRACE();
3689 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3691 if (rx_queue_id < dev->data->nb_rx_queues) {
3692 rxq = dev->data->rx_queues[rx_queue_id];
3694 /* Allocate buffers for descriptor rings */
3695 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
3697 "Could not alloc mbuf for queue:%d\n",
3701 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3702 rxdctl |= IXGBE_RXDCTL_ENABLE;
3703 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3705 /* Wait until RX Enable ready */
3706 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3709 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3710 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3712 PMD_INIT_LOG(ERR, "Could not enable "
3713 "Rx Queue %d\n", rx_queue_id);
3715 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3716 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3724 * Stop Receive Units for specified queue.
3727 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3729 struct ixgbe_hw *hw;
3730 struct igb_rx_queue *rxq;
3734 PMD_INIT_FUNC_TRACE();
3735 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3737 if (rx_queue_id < dev->data->nb_rx_queues) {
3738 rxq = dev->data->rx_queues[rx_queue_id];
3740 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3741 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3742 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3744 /* Wait until RX Enable ready */
3745 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3748 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3749 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
3751 PMD_INIT_LOG(ERR, "Could not disable "
3752 "Rx Queue %d\n", rx_queue_id);
3754 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3756 ixgbe_rx_queue_release_mbufs(rxq);
3757 ixgbe_reset_rx_queue(rxq);
3766 * Start Transmit Units for specified queue.
3769 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3771 struct ixgbe_hw *hw;
3772 struct igb_tx_queue *txq;
3776 PMD_INIT_FUNC_TRACE();
3777 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3779 if (tx_queue_id < dev->data->nb_tx_queues) {
3780 txq = dev->data->tx_queues[tx_queue_id];
3781 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3782 txdctl |= IXGBE_TXDCTL_ENABLE;
3783 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3785 /* Wait until TX Enable ready */
3786 if (hw->mac.type == ixgbe_mac_82599EB) {
3787 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3790 txdctl = IXGBE_READ_REG(hw,
3791 IXGBE_TXDCTL(txq->reg_idx));
3792 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3794 PMD_INIT_LOG(ERR, "Could not enable "
3795 "Tx Queue %d\n", tx_queue_id);
3798 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3799 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3807 * Stop Transmit Units for specified queue.
3810 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3812 struct ixgbe_hw *hw;
3813 struct igb_tx_queue *txq;
3815 uint32_t txtdh, txtdt;
3818 PMD_INIT_FUNC_TRACE();
3819 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3821 if (tx_queue_id < dev->data->nb_tx_queues) {
3822 txq = dev->data->tx_queues[tx_queue_id];
3824 /* Wait until TX queue is empty */
3825 if (hw->mac.type == ixgbe_mac_82599EB) {
3826 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3828 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3829 txtdh = IXGBE_READ_REG(hw,
3830 IXGBE_TDH(txq->reg_idx));
3831 txtdt = IXGBE_READ_REG(hw,
3832 IXGBE_TDT(txq->reg_idx));
3833 } while (--poll_ms && (txtdh != txtdt));
3836 "Tx Queue %d is not empty when stopping.\n",
3840 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3841 txdctl &= ~IXGBE_TXDCTL_ENABLE;
3842 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3844 /* Wait until TX Enable ready */
3845 if (hw->mac.type == ixgbe_mac_82599EB) {
3846 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3849 txdctl = IXGBE_READ_REG(hw,
3850 IXGBE_TXDCTL(txq->reg_idx));
3851 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
3853 PMD_INIT_LOG(ERR, "Could not disable "
3854 "Tx Queue %d\n", tx_queue_id);
3857 if (txq->ops != NULL) {
3858 txq->ops->release_mbufs(txq);
3859 txq->ops->reset(txq);
3868 * [VF] Initializes Receive Unit.
3871 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3873 struct ixgbe_hw *hw;
3874 struct igb_rx_queue *rxq;
3875 struct rte_pktmbuf_pool_private *mbp_priv;
3882 PMD_INIT_FUNC_TRACE();
3883 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3886 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
3887 * disables the VF receipt of packets if the PF MTU is > 1500.
3888 * This is done to deal with 82599 limitations that imposes
3889 * the PF and all VFs to share the same MTU.
3890 * Then, the PF driver enables again the VF receipt of packet when
3891 * the VF driver issues a IXGBE_VF_SET_LPE request.
3892 * In the meantime, the VF device cannot be used, even if the VF driver
3893 * and the Guest VM network stack are ready to accept packets with a
3894 * size up to the PF MTU.
3895 * As a work-around to this PF behaviour, force the call to
3896 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
3897 * VF packets received can work in all cases.
3899 ixgbevf_rlpml_set_vf(hw,
3900 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
3902 /* Setup RX queues */
3903 dev->rx_pkt_burst = ixgbe_recv_pkts;
3904 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3905 rxq = dev->data->rx_queues[i];
3907 /* Allocate buffers for descriptor rings */
3908 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3912 /* Setup the Base and Length of the Rx Descriptor Rings */
3913 bus_addr = rxq->rx_ring_phys_addr;
3915 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3916 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3917 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3918 (uint32_t)(bus_addr >> 32));
3919 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3920 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3921 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3922 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3925 /* Configure the SRRCTL register */
3926 #ifdef RTE_HEADER_SPLIT_ENABLE
3928 * Configure Header Split
3930 if (dev->data->dev_conf.rxmode.header_split) {
3932 /* Must setup the PSRTYPE register */
3934 psrtype = IXGBE_PSRTYPE_TCPHDR |
3935 IXGBE_PSRTYPE_UDPHDR |
3936 IXGBE_PSRTYPE_IPV4HDR |
3937 IXGBE_PSRTYPE_IPV6HDR;
3939 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
3941 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3942 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3943 IXGBE_SRRCTL_BSIZEHDR_MASK);
3944 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3947 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3949 /* Set if packets are dropped when no descriptors available */
3951 srrctl |= IXGBE_SRRCTL_DROP_EN;
3954 * Configure the RX buffer size in the BSIZEPACKET field of
3955 * the SRRCTL register of the queue.
3956 * The value is in 1 KB resolution. Valid values can be from
3959 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3960 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3961 RTE_PKTMBUF_HEADROOM);
3962 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3963 IXGBE_SRRCTL_BSIZEPKT_MASK);
3966 * VF modification to write virtual function SRRCTL register
3968 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
3970 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3971 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3973 /* It adds dual VLAN length for supporting dual VLAN */
3974 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3975 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
3976 dev->data->scattered_rx = 1;
3977 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3981 if (dev->data->dev_conf.rxmode.enable_scatter) {
3982 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3983 dev->data->scattered_rx = 1;
3990 * [VF] Initializes Transmit Unit.
3993 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
3995 struct ixgbe_hw *hw;
3996 struct igb_tx_queue *txq;
4001 PMD_INIT_FUNC_TRACE();
4002 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4004 /* Setup the Base and Length of the Tx Descriptor Rings */
4005 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4006 txq = dev->data->tx_queues[i];
4007 bus_addr = txq->tx_ring_phys_addr;
4008 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4009 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4010 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4011 (uint32_t)(bus_addr >> 32));
4012 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4013 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4014 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4015 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4016 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4019 * Disable Tx Head Writeback RO bit, since this hoses
4020 * bookkeeping if things aren't delivered in order.
4022 txctrl = IXGBE_READ_REG(hw,
4023 IXGBE_VFDCA_TXCTRL(i));
4024 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4025 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4031 * [VF] Start Transmit and Receive Units.
4034 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4036 struct ixgbe_hw *hw;
4037 struct igb_tx_queue *txq;
4038 struct igb_rx_queue *rxq;
4044 PMD_INIT_FUNC_TRACE();
4045 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4047 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4048 txq = dev->data->tx_queues[i];
4049 /* Setup Transmit Threshold Registers */
4050 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4051 txdctl |= txq->pthresh & 0x7F;
4052 txdctl |= ((txq->hthresh & 0x7F) << 8);
4053 txdctl |= ((txq->wthresh & 0x7F) << 16);
4054 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4057 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4059 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4060 txdctl |= IXGBE_TXDCTL_ENABLE;
4061 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4064 /* Wait until TX Enable ready */
4067 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4068 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4070 PMD_INIT_LOG(ERR, "Could not enable "
4071 "Tx Queue %d\n", i);
4073 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4075 rxq = dev->data->rx_queues[i];
4077 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4078 rxdctl |= IXGBE_RXDCTL_ENABLE;
4079 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4081 /* Wait until RX Enable ready */
4085 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4086 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4088 PMD_INIT_LOG(ERR, "Could not enable "
4089 "Rx Queue %d\n", i);
4091 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);