4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
47 #include <rte_cycles.h>
49 #include <rte_debug.h>
50 #include <rte_interrupts.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_launch.h>
55 #include <rte_tailq.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
80 #include "ixgbe_rxtx.h"
82 #define IXGBE_RSS_OFFLOAD_ALL ( \
88 ETH_RSS_IPV6_TCP_EX | \
93 static inline struct rte_mbuf *
94 rte_rxmbuf_alloc(struct rte_mempool *mp)
98 m = __rte_mbuf_raw_alloc(mp);
99 __rte_mbuf_sanity_check_raw(m, 0);
105 #define RTE_PMD_USE_PREFETCH
108 #ifdef RTE_PMD_USE_PREFETCH
110 * Prefetch a cache line into all cache levels.
112 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
114 #define rte_ixgbe_prefetch(p) do {} while(0)
117 /*********************************************************************
121 **********************************************************************/
124 * Check for descriptors with their DD bit set and free mbufs.
125 * Return the total number of buffers freed.
127 static inline int __attribute__((always_inline))
128 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
130 struct igb_tx_entry *txep;
134 /* check DD bit on threshold descriptor */
135 status = txq->tx_ring[txq->tx_next_dd].wb.status;
136 if (! (status & IXGBE_ADVTXD_STAT_DD))
140 * first buffer to free from S/W ring is at index
141 * tx_next_dd - (tx_rs_thresh-1)
143 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
145 /* free buffers one at a time */
146 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
147 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
148 txep->mbuf->next = NULL;
149 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
153 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
154 rte_pktmbuf_free_seg(txep->mbuf);
159 /* buffers were freed, update counters */
160 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
161 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
162 if (txq->tx_next_dd >= txq->nb_tx_desc)
163 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
165 return txq->tx_rs_thresh;
168 /* Populate 4 descriptors with data from 4 mbufs */
170 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
172 uint64_t buf_dma_addr;
176 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
177 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
178 pkt_len = (*pkts)->data_len;
180 /* write data to descriptor */
181 txdp->read.buffer_addr = buf_dma_addr;
182 txdp->read.cmd_type_len =
183 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
184 txdp->read.olinfo_status =
185 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
186 rte_prefetch0(&(*pkts)->pool);
190 /* Populate 1 descriptor with data from 1 mbuf */
192 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
194 uint64_t buf_dma_addr;
197 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
198 pkt_len = (*pkts)->data_len;
200 /* write data to descriptor */
201 txdp->read.buffer_addr = buf_dma_addr;
202 txdp->read.cmd_type_len =
203 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
204 txdp->read.olinfo_status =
205 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
206 rte_prefetch0(&(*pkts)->pool);
210 * Fill H/W descriptor ring with mbuf data.
211 * Copy mbuf pointers to the S/W ring.
214 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
217 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
218 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
219 const int N_PER_LOOP = 4;
220 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
221 int mainpart, leftover;
225 * Process most of the packets in chunks of N pkts. Any
226 * leftover packets will get processed one at a time.
228 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
229 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
230 for (i = 0; i < mainpart; i += N_PER_LOOP) {
231 /* Copy N mbuf pointers to the S/W ring */
232 for (j = 0; j < N_PER_LOOP; ++j) {
233 (txep + i + j)->mbuf = *(pkts + i + j);
235 tx4(txdp + i, pkts + i);
238 if (unlikely(leftover > 0)) {
239 for (i = 0; i < leftover; ++i) {
240 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
241 tx1(txdp + mainpart + i, pkts + mainpart + i);
246 static inline uint16_t
247 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
250 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
251 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
255 * Begin scanning the H/W ring for done descriptors when the
256 * number of available descriptors drops below tx_free_thresh. For
257 * each done descriptor, free the associated buffer.
259 if (txq->nb_tx_free < txq->tx_free_thresh)
260 ixgbe_tx_free_bufs(txq);
262 /* Only use descriptors that are available */
263 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
264 if (unlikely(nb_pkts == 0))
267 /* Use exactly nb_pkts descriptors */
268 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
271 * At this point, we know there are enough descriptors in the
272 * ring to transmit all the packets. This assumes that each
273 * mbuf contains a single segment, and that no new offloads
274 * are expected, which would require a new context descriptor.
278 * See if we're going to wrap-around. If so, handle the top
279 * of the descriptor ring first, then do the bottom. If not,
280 * the processing looks just like the "bottom" part anyway...
282 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
283 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
284 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
287 * We know that the last descriptor in the ring will need to
288 * have its RS bit set because tx_rs_thresh has to be
289 * a divisor of the ring size
291 tx_r[txq->tx_next_rs].read.cmd_type_len |=
292 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
293 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
298 /* Fill H/W descriptor ring with mbuf data */
299 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
300 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
303 * Determine if RS bit should be set
304 * This is what we actually want:
305 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
306 * but instead of subtracting 1 and doing >=, we can just do
307 * greater than without subtracting.
309 if (txq->tx_tail > txq->tx_next_rs) {
310 tx_r[txq->tx_next_rs].read.cmd_type_len |=
311 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
312 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
314 if (txq->tx_next_rs >= txq->nb_tx_desc)
315 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
319 * Check for wrap-around. This would only happen if we used
320 * up to the last descriptor in the ring, no more, no less.
322 if (txq->tx_tail >= txq->nb_tx_desc)
325 /* update tail pointer */
327 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
333 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
338 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
339 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
340 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
342 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
346 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
347 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
348 nb_tx = (uint16_t)(nb_tx + ret);
349 nb_pkts = (uint16_t)(nb_pkts - ret);
358 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
359 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
360 uint64_t ol_flags, uint32_t vlan_macip_lens)
362 uint32_t type_tucmd_mlhl;
363 uint32_t mss_l4len_idx;
367 ctx_idx = txq->ctx_curr;
371 if (ol_flags & PKT_TX_VLAN_PKT) {
372 cmp_mask |= TX_VLAN_CMP_MASK;
375 if (ol_flags & PKT_TX_IP_CKSUM) {
376 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
377 cmp_mask |= TX_MAC_LEN_CMP_MASK;
380 /* Specify which HW CTX to upload. */
381 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
382 switch (ol_flags & PKT_TX_L4_MASK) {
383 case PKT_TX_UDP_CKSUM:
384 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
385 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
386 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
387 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
389 case PKT_TX_TCP_CKSUM:
390 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
391 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
392 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
393 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
395 case PKT_TX_SCTP_CKSUM:
396 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
397 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
398 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
399 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
402 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
403 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
407 txq->ctx_cache[ctx_idx].flags = ol_flags;
408 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
409 txq->ctx_cache[ctx_idx].vlan_macip_lens.data =
410 vlan_macip_lens & cmp_mask;
412 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
413 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
414 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
415 ctx_txd->seqnum_seed = 0;
419 * Check which hardware context can be used. Use the existing match
420 * or create a new context descriptor.
422 static inline uint32_t
423 what_advctx_update(struct igb_tx_queue *txq, uint64_t flags,
424 uint32_t vlan_macip_lens)
426 /* If match with the current used context */
427 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
428 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
429 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
430 return txq->ctx_curr;
433 /* What if match with the next context */
435 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
436 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
437 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
438 return txq->ctx_curr;
441 /* Mismatch, use the previous context */
442 return (IXGBE_CTX_NUM);
445 static inline uint32_t
446 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
448 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
449 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
452 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
453 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
457 static inline uint32_t
458 tx_desc_vlan_flags_to_cmdtype(uint64_t ol_flags)
460 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
461 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
464 /* Default RS bit threshold values */
465 #ifndef DEFAULT_TX_RS_THRESH
466 #define DEFAULT_TX_RS_THRESH 32
468 #ifndef DEFAULT_TX_FREE_THRESH
469 #define DEFAULT_TX_FREE_THRESH 32
472 /* Reset transmit descriptors after they have been used */
474 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
476 struct igb_tx_entry *sw_ring = txq->sw_ring;
477 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
478 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
479 uint16_t nb_tx_desc = txq->nb_tx_desc;
480 uint16_t desc_to_clean_to;
481 uint16_t nb_tx_to_clean;
483 /* Determine the last descriptor needing to be cleaned */
484 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
485 if (desc_to_clean_to >= nb_tx_desc)
486 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
488 /* Check to make sure the last descriptor to clean is done */
489 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
490 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
492 PMD_TX_FREE_LOG(DEBUG,
493 "TX descriptor %4u is not done"
494 "(port=%d queue=%d)",
496 txq->port_id, txq->queue_id);
497 /* Failed to clean any descriptors, better luck next time */
501 /* Figure out how many descriptors will be cleaned */
502 if (last_desc_cleaned > desc_to_clean_to)
503 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
506 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
509 PMD_TX_FREE_LOG(DEBUG,
510 "Cleaning %4u TX descriptors: %4u to %4u "
511 "(port=%d queue=%d)",
512 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
513 txq->port_id, txq->queue_id);
516 * The last descriptor to clean is done, so that means all the
517 * descriptors from the last descriptor that was cleaned
518 * up to the last descriptor with the RS bit set
519 * are done. Only reset the threshold descriptor.
521 txr[desc_to_clean_to].wb.status = 0;
523 /* Update the txq to reflect the last descriptor that was cleaned */
524 txq->last_desc_cleaned = desc_to_clean_to;
525 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
532 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
535 struct igb_tx_queue *txq;
536 struct igb_tx_entry *sw_ring;
537 struct igb_tx_entry *txe, *txn;
538 volatile union ixgbe_adv_tx_desc *txr;
539 volatile union ixgbe_adv_tx_desc *txd;
540 struct rte_mbuf *tx_pkt;
541 struct rte_mbuf *m_seg;
542 union ixgbe_vlan_macip vlan_macip_lens;
543 uint64_t buf_dma_addr;
544 uint32_t olinfo_status;
545 uint32_t cmd_type_len;
558 sw_ring = txq->sw_ring;
560 tx_id = txq->tx_tail;
561 txe = &sw_ring[tx_id];
563 /* Determine if the descriptor ring needs to be cleaned. */
564 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
565 ixgbe_xmit_cleanup(txq);
569 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
572 pkt_len = tx_pkt->pkt_len;
574 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
577 * Determine how many (if any) context descriptors
578 * are needed for offload functionality.
580 ol_flags = tx_pkt->ol_flags;
581 vlan_macip_lens.f.vlan_tci = tx_pkt->vlan_tci;
582 vlan_macip_lens.f.l2_l3_len = tx_pkt->l2_l3_len;
584 /* If hardware offload required */
585 tx_ol_req = ol_flags & PKT_TX_OFFLOAD_MASK;
587 /* If new context need be built or reuse the exist ctx. */
588 ctx = what_advctx_update(txq, tx_ol_req,
589 vlan_macip_lens.data);
590 /* Only allocate context descriptor if required*/
591 new_ctx = (ctx == IXGBE_CTX_NUM);
596 * Keep track of how many descriptors are used this loop
597 * This will always be the number of segments + the number of
598 * Context descriptors required to transmit the packet
600 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
603 * The number of descriptors that must be allocated for a
604 * packet is the number of segments of that packet, plus 1
605 * Context Descriptor for the hardware offload, if any.
606 * Determine the last TX descriptor to allocate in the TX ring
607 * for the packet, starting from the current position (tx_id)
610 tx_last = (uint16_t) (tx_id + nb_used - 1);
613 if (tx_last >= txq->nb_tx_desc)
614 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
616 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
617 " tx_first=%u tx_last=%u",
618 (unsigned) txq->port_id,
619 (unsigned) txq->queue_id,
625 * Make sure there are enough TX descriptors available to
626 * transmit the entire packet.
627 * nb_used better be less than or equal to txq->tx_rs_thresh
629 if (nb_used > txq->nb_tx_free) {
630 PMD_TX_FREE_LOG(DEBUG,
631 "Not enough free TX descriptors "
632 "nb_used=%4u nb_free=%4u "
633 "(port=%d queue=%d)",
634 nb_used, txq->nb_tx_free,
635 txq->port_id, txq->queue_id);
637 if (ixgbe_xmit_cleanup(txq) != 0) {
638 /* Could not clean any descriptors */
644 /* nb_used better be <= txq->tx_rs_thresh */
645 if (unlikely(nb_used > txq->tx_rs_thresh)) {
646 PMD_TX_FREE_LOG(DEBUG,
647 "The number of descriptors needed to "
648 "transmit the packet exceeds the "
649 "RS bit threshold. This will impact "
651 "nb_used=%4u nb_free=%4u "
653 "(port=%d queue=%d)",
654 nb_used, txq->nb_tx_free,
656 txq->port_id, txq->queue_id);
658 * Loop here until there are enough TX
659 * descriptors or until the ring cannot be
662 while (nb_used > txq->nb_tx_free) {
663 if (ixgbe_xmit_cleanup(txq) != 0) {
665 * Could not clean any
677 * By now there are enough free TX descriptors to transmit
682 * Set common flags of all TX Data Descriptors.
684 * The following bits must be set in all Data Descriptors:
685 * - IXGBE_ADVTXD_DTYP_DATA
686 * - IXGBE_ADVTXD_DCMD_DEXT
688 * The following bits must be set in the first Data Descriptor
689 * and are ignored in the other ones:
690 * - IXGBE_ADVTXD_DCMD_IFCS
691 * - IXGBE_ADVTXD_MAC_1588
692 * - IXGBE_ADVTXD_DCMD_VLE
694 * The following bits must only be set in the last Data
696 * - IXGBE_TXD_CMD_EOP
698 * The following bits can be set in any Data Descriptor, but
699 * are only set in the last Data Descriptor:
702 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
703 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
704 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
705 #ifdef RTE_LIBRTE_IEEE1588
706 if (ol_flags & PKT_TX_IEEE1588_TMST)
707 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
712 * Setup the TX Advanced Context Descriptor if required
715 volatile struct ixgbe_adv_tx_context_desc *
718 ctx_txd = (volatile struct
719 ixgbe_adv_tx_context_desc *)
722 txn = &sw_ring[txe->next_id];
723 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
725 if (txe->mbuf != NULL) {
726 rte_pktmbuf_free_seg(txe->mbuf);
730 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
731 vlan_macip_lens.data);
733 txe->last_id = tx_last;
734 tx_id = txe->next_id;
739 * Setup the TX Advanced Data Descriptor,
740 * This path will go through
741 * whatever new/reuse the context descriptor
743 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
744 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
745 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
751 txn = &sw_ring[txe->next_id];
753 if (txe->mbuf != NULL)
754 rte_pktmbuf_free_seg(txe->mbuf);
758 * Set up Transmit Data Descriptor.
760 slen = m_seg->data_len;
761 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
762 txd->read.buffer_addr =
763 rte_cpu_to_le_64(buf_dma_addr);
764 txd->read.cmd_type_len =
765 rte_cpu_to_le_32(cmd_type_len | slen);
766 txd->read.olinfo_status =
767 rte_cpu_to_le_32(olinfo_status);
768 txe->last_id = tx_last;
769 tx_id = txe->next_id;
772 } while (m_seg != NULL);
775 * The last packet data descriptor needs End Of Packet (EOP)
777 cmd_type_len |= IXGBE_TXD_CMD_EOP;
778 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
779 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
781 /* Set RS bit only on threshold packets' last descriptor */
782 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
783 PMD_TX_FREE_LOG(DEBUG,
784 "Setting RS bit on TXD id="
785 "%4u (port=%d queue=%d)",
786 tx_last, txq->port_id, txq->queue_id);
788 cmd_type_len |= IXGBE_TXD_CMD_RS;
790 /* Update txq RS bit counters */
793 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
799 * Set the Transmit Descriptor Tail (TDT)
801 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
802 (unsigned) txq->port_id, (unsigned) txq->queue_id,
803 (unsigned) tx_id, (unsigned) nb_tx);
804 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
805 txq->tx_tail = tx_id;
810 /*********************************************************************
814 **********************************************************************/
815 static inline uint64_t
816 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
820 static uint64_t ip_pkt_types_map[16] = {
821 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
822 PKT_RX_IPV6_HDR, 0, 0, 0,
823 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
824 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
827 static uint64_t ip_rss_types_map[16] = {
828 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
829 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
830 PKT_RX_RSS_HASH, 0, 0, 0,
831 0, 0, 0, PKT_RX_FDIR,
834 #ifdef RTE_LIBRTE_IEEE1588
835 static uint32_t ip_pkt_etqf_map[8] = {
836 0, 0, 0, PKT_RX_IEEE1588_PTP,
840 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
841 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
842 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
844 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
845 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
848 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
851 static inline uint64_t
852 rx_desc_status_to_pkt_flags(uint32_t rx_status)
857 * Check if VLAN present only.
858 * Do not check whether L3/L4 rx checksum done by NIC or not,
859 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
861 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
863 #ifdef RTE_LIBRTE_IEEE1588
864 if (rx_status & IXGBE_RXD_STAT_TMST)
865 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
870 static inline uint64_t
871 rx_desc_error_to_pkt_flags(uint32_t rx_status)
874 * Bit 31: IPE, IPv4 checksum error
875 * Bit 30: L4I, L4I integrity error
877 static uint64_t error_to_pkt_flags_map[4] = {
878 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
879 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
881 return error_to_pkt_flags_map[(rx_status >>
882 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
885 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
887 * LOOK_AHEAD defines how many desc statuses to check beyond the
888 * current descriptor.
889 * It must be a pound define for optimal performance.
890 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
891 * function only works with LOOK_AHEAD=8.
894 #if (LOOK_AHEAD != 8)
895 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
898 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
900 volatile union ixgbe_adv_rx_desc *rxdp;
901 struct igb_rx_entry *rxep;
905 int s[LOOK_AHEAD], nb_dd;
909 /* get references to current descriptor and S/W ring entry */
910 rxdp = &rxq->rx_ring[rxq->rx_tail];
911 rxep = &rxq->sw_ring[rxq->rx_tail];
913 /* check to make sure there is at least 1 packet to receive */
914 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
918 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
919 * reference packets that are ready to be received.
921 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
922 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
924 /* Read desc statuses backwards to avoid race condition */
925 for (j = LOOK_AHEAD-1; j >= 0; --j)
926 s[j] = rxdp[j].wb.upper.status_error;
928 /* Compute how many status bits were set */
930 for (j = 0; j < LOOK_AHEAD; ++j)
931 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
935 /* Translate descriptor info to mbuf format */
936 for (j = 0; j < nb_dd; ++j) {
938 pkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len);
939 mb->data_len = pkt_len;
940 mb->pkt_len = pkt_len;
941 mb->vlan_tci = rxdp[j].wb.upper.vlan;
942 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
944 /* convert descriptor fields to rte mbuf flags */
945 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(
946 rxdp[j].wb.lower.lo_dword.data);
947 /* reuse status field from scan list */
948 pkt_flags |= rx_desc_status_to_pkt_flags(s[j]);
949 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
950 mb->ol_flags = pkt_flags;
952 if (likely(pkt_flags & PKT_RX_RSS_HASH))
953 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
954 else if (pkt_flags & PKT_RX_FDIR) {
956 (uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum)
957 & IXGBE_ATR_HASH_MASK);
958 mb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id;
962 /* Move mbuf pointers from the S/W ring to the stage */
963 for (j = 0; j < LOOK_AHEAD; ++j) {
964 rxq->rx_stage[i + j] = rxep[j].mbuf;
967 /* stop if all requested packets could not be received */
968 if (nb_dd != LOOK_AHEAD)
972 /* clear software ring entries so we can cleanup correctly */
973 for (i = 0; i < nb_rx; ++i) {
974 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
982 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
984 volatile union ixgbe_adv_rx_desc *rxdp;
985 struct igb_rx_entry *rxep;
991 /* allocate buffers in bulk directly into the S/W ring */
992 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
993 (rxq->rx_free_thresh - 1));
994 rxep = &rxq->sw_ring[alloc_idx];
995 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
996 rxq->rx_free_thresh);
997 if (unlikely(diag != 0))
1000 rxdp = &rxq->rx_ring[alloc_idx];
1001 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1002 /* populate the static rte mbuf fields */
1004 rte_mbuf_refcnt_set(mb, 1);
1006 mb->data_off = RTE_PKTMBUF_HEADROOM;
1008 mb->port = rxq->port_id;
1010 /* populate the descriptors */
1011 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1012 rxdp[i].read.hdr_addr = dma_addr;
1013 rxdp[i].read.pkt_addr = dma_addr;
1016 /* update tail pointer */
1018 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1020 /* update state of internal queue structure */
1021 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1022 rxq->rx_free_thresh);
1023 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1024 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1030 static inline uint16_t
1031 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1034 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1037 /* how many packets are ready to return? */
1038 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1040 /* copy mbuf pointers to the application's packet list */
1041 for (i = 0; i < nb_pkts; ++i)
1042 rx_pkts[i] = stage[i];
1044 /* update internal queue state */
1045 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1046 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1051 static inline uint16_t
1052 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1055 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1058 /* Any previously recv'd pkts will be returned from the Rx stage */
1059 if (rxq->rx_nb_avail)
1060 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1062 /* Scan the H/W ring for packets to receive */
1063 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1065 /* update internal queue state */
1066 rxq->rx_next_avail = 0;
1067 rxq->rx_nb_avail = nb_rx;
1068 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1070 /* if required, allocate new buffers to replenish descriptors */
1071 if (rxq->rx_tail > rxq->rx_free_trigger) {
1072 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1074 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1075 "queue_id=%u", (unsigned) rxq->port_id,
1076 (unsigned) rxq->queue_id);
1078 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1079 rxq->rx_free_thresh;
1082 * Need to rewind any previous receives if we cannot
1083 * allocate new buffers to replenish the old ones.
1085 rxq->rx_nb_avail = 0;
1086 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1087 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1088 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1094 if (rxq->rx_tail >= rxq->nb_rx_desc)
1097 /* received any packets this loop? */
1098 if (rxq->rx_nb_avail)
1099 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1104 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1106 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1111 if (unlikely(nb_pkts == 0))
1114 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1115 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1117 /* request is relatively large, chunk it up */
1121 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1122 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1123 nb_rx = (uint16_t)(nb_rx + ret);
1124 nb_pkts = (uint16_t)(nb_pkts - ret);
1131 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1134 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1137 struct igb_rx_queue *rxq;
1138 volatile union ixgbe_adv_rx_desc *rx_ring;
1139 volatile union ixgbe_adv_rx_desc *rxdp;
1140 struct igb_rx_entry *sw_ring;
1141 struct igb_rx_entry *rxe;
1142 struct rte_mbuf *rxm;
1143 struct rte_mbuf *nmb;
1144 union ixgbe_adv_rx_desc rxd;
1147 uint32_t hlen_type_rss;
1157 rx_id = rxq->rx_tail;
1158 rx_ring = rxq->rx_ring;
1159 sw_ring = rxq->sw_ring;
1160 while (nb_rx < nb_pkts) {
1162 * The order of operations here is important as the DD status
1163 * bit must not be read after any other descriptor fields.
1164 * rx_ring and rxdp are pointing to volatile data so the order
1165 * of accesses cannot be reordered by the compiler. If they were
1166 * not volatile, they could be reordered which could lead to
1167 * using invalid descriptor fields when read from rxd.
1169 rxdp = &rx_ring[rx_id];
1170 staterr = rxdp->wb.upper.status_error;
1171 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1178 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1179 * is likely to be invalid and to be dropped by the various
1180 * validation checks performed by the network stack.
1182 * Allocate a new mbuf to replenish the RX ring descriptor.
1183 * If the allocation fails:
1184 * - arrange for that RX descriptor to be the first one
1185 * being parsed the next time the receive function is
1186 * invoked [on the same queue].
1188 * - Stop parsing the RX ring and return immediately.
1190 * This policy do not drop the packet received in the RX
1191 * descriptor for which the allocation of a new mbuf failed.
1192 * Thus, it allows that packet to be later retrieved if
1193 * mbuf have been freed in the mean time.
1194 * As a side effect, holding RX descriptors instead of
1195 * systematically giving them back to the NIC may lead to
1196 * RX ring exhaustion situations.
1197 * However, the NIC can gracefully prevent such situations
1198 * to happen by sending specific "back-pressure" flow control
1199 * frames to its peer(s).
1201 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1202 "ext_err_stat=0x%08x pkt_len=%u",
1203 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1204 (unsigned) rx_id, (unsigned) staterr,
1205 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1207 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1209 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1210 "queue_id=%u", (unsigned) rxq->port_id,
1211 (unsigned) rxq->queue_id);
1212 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1217 rxe = &sw_ring[rx_id];
1219 if (rx_id == rxq->nb_rx_desc)
1222 /* Prefetch next mbuf while processing current one. */
1223 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1226 * When next RX descriptor is on a cache-line boundary,
1227 * prefetch the next 4 RX descriptors and the next 8 pointers
1230 if ((rx_id & 0x3) == 0) {
1231 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1232 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1238 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1239 rxdp->read.hdr_addr = dma_addr;
1240 rxdp->read.pkt_addr = dma_addr;
1243 * Initialize the returned mbuf.
1244 * 1) setup generic mbuf fields:
1245 * - number of segments,
1248 * - RX port identifier.
1249 * 2) integrate hardware offload data, if any:
1250 * - RSS flag & hash,
1251 * - IP checksum flag,
1252 * - VLAN TCI, if any,
1255 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1257 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1258 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1261 rxm->pkt_len = pkt_len;
1262 rxm->data_len = pkt_len;
1263 rxm->port = rxq->port_id;
1265 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1266 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1267 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1269 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1270 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1271 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1272 rxm->ol_flags = pkt_flags;
1274 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1275 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1276 else if (pkt_flags & PKT_RX_FDIR) {
1277 rxm->hash.fdir.hash =
1278 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1279 & IXGBE_ATR_HASH_MASK);
1280 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1283 * Store the mbuf address into the next entry of the array
1284 * of returned packets.
1286 rx_pkts[nb_rx++] = rxm;
1288 rxq->rx_tail = rx_id;
1291 * If the number of free RX descriptors is greater than the RX free
1292 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1294 * Update the RDT with the value of the last processed RX descriptor
1295 * minus 1, to guarantee that the RDT register is never equal to the
1296 * RDH register, which creates a "full" ring situtation from the
1297 * hardware point of view...
1299 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1300 if (nb_hold > rxq->rx_free_thresh) {
1301 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1302 "nb_hold=%u nb_rx=%u",
1303 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1304 (unsigned) rx_id, (unsigned) nb_hold,
1306 rx_id = (uint16_t) ((rx_id == 0) ?
1307 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1308 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1311 rxq->nb_rx_hold = nb_hold;
1316 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1319 struct igb_rx_queue *rxq;
1320 volatile union ixgbe_adv_rx_desc *rx_ring;
1321 volatile union ixgbe_adv_rx_desc *rxdp;
1322 struct igb_rx_entry *sw_ring;
1323 struct igb_rx_entry *rxe;
1324 struct rte_mbuf *first_seg;
1325 struct rte_mbuf *last_seg;
1326 struct rte_mbuf *rxm;
1327 struct rte_mbuf *nmb;
1328 union ixgbe_adv_rx_desc rxd;
1329 uint64_t dma; /* Physical address of mbuf data buffer */
1331 uint32_t hlen_type_rss;
1341 rx_id = rxq->rx_tail;
1342 rx_ring = rxq->rx_ring;
1343 sw_ring = rxq->sw_ring;
1346 * Retrieve RX context of current packet, if any.
1348 first_seg = rxq->pkt_first_seg;
1349 last_seg = rxq->pkt_last_seg;
1351 while (nb_rx < nb_pkts) {
1354 * The order of operations here is important as the DD status
1355 * bit must not be read after any other descriptor fields.
1356 * rx_ring and rxdp are pointing to volatile data so the order
1357 * of accesses cannot be reordered by the compiler. If they were
1358 * not volatile, they could be reordered which could lead to
1359 * using invalid descriptor fields when read from rxd.
1361 rxdp = &rx_ring[rx_id];
1362 staterr = rxdp->wb.upper.status_error;
1363 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1370 * Allocate a new mbuf to replenish the RX ring descriptor.
1371 * If the allocation fails:
1372 * - arrange for that RX descriptor to be the first one
1373 * being parsed the next time the receive function is
1374 * invoked [on the same queue].
1376 * - Stop parsing the RX ring and return immediately.
1378 * This policy does not drop the packet received in the RX
1379 * descriptor for which the allocation of a new mbuf failed.
1380 * Thus, it allows that packet to be later retrieved if
1381 * mbuf have been freed in the mean time.
1382 * As a side effect, holding RX descriptors instead of
1383 * systematically giving them back to the NIC may lead to
1384 * RX ring exhaustion situations.
1385 * However, the NIC can gracefully prevent such situations
1386 * to happen by sending specific "back-pressure" flow control
1387 * frames to its peer(s).
1389 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1390 "staterr=0x%x data_len=%u",
1391 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1392 (unsigned) rx_id, (unsigned) staterr,
1393 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1395 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1397 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1398 "queue_id=%u", (unsigned) rxq->port_id,
1399 (unsigned) rxq->queue_id);
1400 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1405 rxe = &sw_ring[rx_id];
1407 if (rx_id == rxq->nb_rx_desc)
1410 /* Prefetch next mbuf while processing current one. */
1411 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1414 * When next RX descriptor is on a cache-line boundary,
1415 * prefetch the next 4 RX descriptors and the next 8 pointers
1418 if ((rx_id & 0x3) == 0) {
1419 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1420 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1424 * Update RX descriptor with the physical address of the new
1425 * data buffer of the new allocated mbuf.
1429 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1430 rxdp->read.hdr_addr = dma;
1431 rxdp->read.pkt_addr = dma;
1434 * Set data length & data buffer address of mbuf.
1436 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1437 rxm->data_len = data_len;
1438 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1441 * If this is the first buffer of the received packet,
1442 * set the pointer to the first mbuf of the packet and
1443 * initialize its context.
1444 * Otherwise, update the total length and the number of segments
1445 * of the current scattered packet, and update the pointer to
1446 * the last mbuf of the current packet.
1448 if (first_seg == NULL) {
1450 first_seg->pkt_len = data_len;
1451 first_seg->nb_segs = 1;
1453 first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
1455 first_seg->nb_segs++;
1456 last_seg->next = rxm;
1460 * If this is not the last buffer of the received packet,
1461 * update the pointer to the last mbuf of the current scattered
1462 * packet and continue to parse the RX ring.
1464 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1470 * This is the last buffer of the received packet.
1471 * If the CRC is not stripped by the hardware:
1472 * - Subtract the CRC length from the total packet length.
1473 * - If the last buffer only contains the whole CRC or a part
1474 * of it, free the mbuf associated to the last buffer.
1475 * If part of the CRC is also contained in the previous
1476 * mbuf, subtract the length of that CRC part from the
1477 * data length of the previous mbuf.
1480 if (unlikely(rxq->crc_len > 0)) {
1481 first_seg->pkt_len -= ETHER_CRC_LEN;
1482 if (data_len <= ETHER_CRC_LEN) {
1483 rte_pktmbuf_free_seg(rxm);
1484 first_seg->nb_segs--;
1485 last_seg->data_len = (uint16_t)
1486 (last_seg->data_len -
1487 (ETHER_CRC_LEN - data_len));
1488 last_seg->next = NULL;
1491 (uint16_t) (data_len - ETHER_CRC_LEN);
1495 * Initialize the first mbuf of the returned packet:
1496 * - RX port identifier,
1497 * - hardware offload data, if any:
1498 * - RSS flag & hash,
1499 * - IP checksum flag,
1500 * - VLAN TCI, if any,
1503 first_seg->port = rxq->port_id;
1506 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1507 * set in the pkt_flags field.
1509 first_seg->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1510 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1511 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1512 pkt_flags = (uint16_t)(pkt_flags |
1513 rx_desc_status_to_pkt_flags(staterr));
1514 pkt_flags = (uint16_t)(pkt_flags |
1515 rx_desc_error_to_pkt_flags(staterr));
1516 first_seg->ol_flags = pkt_flags;
1518 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1519 first_seg->hash.rss = rxd.wb.lower.hi_dword.rss;
1520 else if (pkt_flags & PKT_RX_FDIR) {
1521 first_seg->hash.fdir.hash =
1522 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1523 & IXGBE_ATR_HASH_MASK);
1524 first_seg->hash.fdir.id =
1525 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1528 /* Prefetch data of first segment, if configured to do so. */
1529 rte_packet_prefetch((char *)first_seg->buf_addr +
1530 first_seg->data_off);
1533 * Store the mbuf address into the next entry of the array
1534 * of returned packets.
1536 rx_pkts[nb_rx++] = first_seg;
1539 * Setup receipt context for a new packet.
1545 * Record index of the next RX descriptor to probe.
1547 rxq->rx_tail = rx_id;
1550 * Save receive context.
1552 rxq->pkt_first_seg = first_seg;
1553 rxq->pkt_last_seg = last_seg;
1556 * If the number of free RX descriptors is greater than the RX free
1557 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1559 * Update the RDT with the value of the last processed RX descriptor
1560 * minus 1, to guarantee that the RDT register is never equal to the
1561 * RDH register, which creates a "full" ring situtation from the
1562 * hardware point of view...
1564 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1565 if (nb_hold > rxq->rx_free_thresh) {
1566 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1567 "nb_hold=%u nb_rx=%u",
1568 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1569 (unsigned) rx_id, (unsigned) nb_hold,
1571 rx_id = (uint16_t) ((rx_id == 0) ?
1572 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1573 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1576 rxq->nb_rx_hold = nb_hold;
1580 /*********************************************************************
1582 * Queue management functions
1584 **********************************************************************/
1587 * Rings setup and release.
1589 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1590 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1591 * also optimize cache line size effect. H/W supports up to cache line size 128.
1593 #define IXGBE_ALIGN 128
1596 * Maximum number of Ring Descriptors.
1598 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1599 * descriptors should meet the following condition:
1600 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1602 #define IXGBE_MIN_RING_DESC 32
1603 #define IXGBE_MAX_RING_DESC 4096
1606 * Create memzone for HW rings. malloc can't be used as the physical address is
1607 * needed. If the memzone is already created, then this function returns a ptr
1610 static const struct rte_memzone *
1611 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1612 uint16_t queue_id, uint32_t ring_size, int socket_id)
1614 char z_name[RTE_MEMZONE_NAMESIZE];
1615 const struct rte_memzone *mz;
1617 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1618 dev->driver->pci_drv.name, ring_name,
1619 dev->data->port_id, queue_id);
1621 mz = rte_memzone_lookup(z_name);
1625 #ifdef RTE_LIBRTE_XEN_DOM0
1626 return rte_memzone_reserve_bounded(z_name, ring_size,
1627 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1629 return rte_memzone_reserve_aligned(z_name, ring_size,
1630 socket_id, 0, IXGBE_ALIGN);
1635 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1639 if (txq->sw_ring != NULL) {
1640 for (i = 0; i < txq->nb_tx_desc; i++) {
1641 if (txq->sw_ring[i].mbuf != NULL) {
1642 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1643 txq->sw_ring[i].mbuf = NULL;
1650 ixgbe_tx_free_swring(struct igb_tx_queue *txq)
1653 txq->sw_ring != NULL)
1654 rte_free(txq->sw_ring);
1658 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1660 if (txq != NULL && txq->ops != NULL) {
1661 txq->ops->release_mbufs(txq);
1662 txq->ops->free_swring(txq);
1668 ixgbe_dev_tx_queue_release(void *txq)
1670 ixgbe_tx_queue_release(txq);
1673 /* (Re)set dynamic igb_tx_queue fields to defaults */
1675 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1677 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1679 struct igb_tx_entry *txe = txq->sw_ring;
1682 /* Zero out HW ring memory */
1683 for (i = 0; i < txq->nb_tx_desc; i++) {
1684 txq->tx_ring[i] = zeroed_desc;
1687 /* Initialize SW ring entries */
1688 prev = (uint16_t) (txq->nb_tx_desc - 1);
1689 for (i = 0; i < txq->nb_tx_desc; i++) {
1690 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1691 txd->wb.status = IXGBE_TXD_STAT_DD;
1694 txe[prev].next_id = i;
1698 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1699 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1702 txq->nb_tx_used = 0;
1704 * Always allow 1 descriptor to be un-allocated to avoid
1705 * a H/W race condition
1707 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1708 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1710 memset((void*)&txq->ctx_cache, 0,
1711 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1714 static struct ixgbe_txq_ops def_txq_ops = {
1715 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1716 .free_swring = ixgbe_tx_free_swring,
1717 .reset = ixgbe_reset_tx_queue,
1721 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1724 unsigned int socket_id,
1725 const struct rte_eth_txconf *tx_conf)
1727 const struct rte_memzone *tz;
1728 struct igb_tx_queue *txq;
1729 struct ixgbe_hw *hw;
1730 uint16_t tx_rs_thresh, tx_free_thresh;
1732 PMD_INIT_FUNC_TRACE();
1733 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1736 * Validate number of transmit descriptors.
1737 * It must not exceed hardware maximum, and must be multiple
1740 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1741 (nb_desc > IXGBE_MAX_RING_DESC) ||
1742 (nb_desc < IXGBE_MIN_RING_DESC)) {
1747 * The following two parameters control the setting of the RS bit on
1748 * transmit descriptors.
1749 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1750 * descriptors have been used.
1751 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1752 * descriptors are used or if the number of descriptors required
1753 * to transmit a packet is greater than the number of free TX
1755 * The following constraints must be satisfied:
1756 * tx_rs_thresh must be greater than 0.
1757 * tx_rs_thresh must be less than the size of the ring minus 2.
1758 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1759 * tx_rs_thresh must be a divisor of the ring size.
1760 * tx_free_thresh must be greater than 0.
1761 * tx_free_thresh must be less than the size of the ring minus 3.
1762 * One descriptor in the TX ring is used as a sentinel to avoid a
1763 * H/W race condition, hence the maximum threshold constraints.
1764 * When set to zero use default values.
1766 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1767 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1768 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1769 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1770 if (tx_rs_thresh >= (nb_desc - 2)) {
1771 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
1772 "of TX descriptors minus 2. (tx_rs_thresh=%u "
1773 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1774 (int)dev->data->port_id, (int)queue_idx);
1777 if (tx_free_thresh >= (nb_desc - 3)) {
1778 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1779 "tx_free_thresh must be less than the number of "
1780 "TX descriptors minus 3. (tx_free_thresh=%u "
1781 "port=%d queue=%d)",
1782 (unsigned int)tx_free_thresh,
1783 (int)dev->data->port_id, (int)queue_idx);
1786 if (tx_rs_thresh > tx_free_thresh) {
1787 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
1788 "tx_free_thresh. (tx_free_thresh=%u "
1789 "tx_rs_thresh=%u port=%d queue=%d)",
1790 (unsigned int)tx_free_thresh,
1791 (unsigned int)tx_rs_thresh,
1792 (int)dev->data->port_id,
1796 if ((nb_desc % tx_rs_thresh) != 0) {
1797 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1798 "number of TX descriptors. (tx_rs_thresh=%u "
1799 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1800 (int)dev->data->port_id, (int)queue_idx);
1805 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1806 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1807 * by the NIC and all descriptors are written back after the NIC
1808 * accumulates WTHRESH descriptors.
1810 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1811 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1812 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1813 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1814 (int)dev->data->port_id, (int)queue_idx);
1818 /* Free memory prior to re-allocation if needed... */
1819 if (dev->data->tx_queues[queue_idx] != NULL) {
1820 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1821 dev->data->tx_queues[queue_idx] = NULL;
1824 /* First allocate the tx queue data structure */
1825 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct igb_tx_queue),
1826 CACHE_LINE_SIZE, socket_id);
1831 * Allocate TX ring hardware descriptors. A memzone large enough to
1832 * handle the maximum ring size is allocated in order to allow for
1833 * resizing in later calls to the queue setup function.
1835 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1836 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1839 ixgbe_tx_queue_release(txq);
1843 txq->nb_tx_desc = nb_desc;
1844 txq->tx_rs_thresh = tx_rs_thresh;
1845 txq->tx_free_thresh = tx_free_thresh;
1846 txq->pthresh = tx_conf->tx_thresh.pthresh;
1847 txq->hthresh = tx_conf->tx_thresh.hthresh;
1848 txq->wthresh = tx_conf->tx_thresh.wthresh;
1849 txq->queue_id = queue_idx;
1850 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1851 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1852 txq->port_id = dev->data->port_id;
1853 txq->txq_flags = tx_conf->txq_flags;
1854 txq->ops = &def_txq_ops;
1855 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1858 * Modification to set VFTDT for virtual function if vf is detected
1860 if (hw->mac.type == ixgbe_mac_82599_vf)
1861 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1863 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1864 #ifndef RTE_LIBRTE_XEN_DOM0
1865 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1867 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1869 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1871 /* Allocate software ring */
1872 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1873 sizeof(struct igb_tx_entry) * nb_desc,
1874 CACHE_LINE_SIZE, socket_id);
1875 if (txq->sw_ring == NULL) {
1876 ixgbe_tx_queue_release(txq);
1879 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1880 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1882 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1883 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
1884 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1885 PMD_INIT_LOG(INFO, "Using simple tx code path");
1886 #ifdef RTE_IXGBE_INC_VECTOR
1887 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1888 ixgbe_txq_vec_setup(txq) == 0) {
1889 PMD_INIT_LOG(INFO, "Vector tx enabled.");
1890 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1894 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1896 PMD_INIT_LOG(INFO, "Using full-featured tx code path");
1897 PMD_INIT_LOG(INFO, " - txq_flags = %lx "
1898 "[IXGBE_SIMPLE_FLAGS=%lx]",
1899 (long unsigned)txq->txq_flags,
1900 (long unsigned)IXGBE_SIMPLE_FLAGS);
1901 PMD_INIT_LOG(INFO, " - tx_rs_thresh = %lu "
1902 "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
1903 (long unsigned)txq->tx_rs_thresh,
1904 (long unsigned)RTE_PMD_IXGBE_TX_MAX_BURST);
1905 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1908 txq->ops->reset(txq);
1910 dev->data->tx_queues[queue_idx] = txq;
1917 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1921 if (rxq->sw_ring != NULL) {
1922 for (i = 0; i < rxq->nb_rx_desc; i++) {
1923 if (rxq->sw_ring[i].mbuf != NULL) {
1924 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1925 rxq->sw_ring[i].mbuf = NULL;
1928 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1929 if (rxq->rx_nb_avail) {
1930 for (i = 0; i < rxq->rx_nb_avail; ++i) {
1931 struct rte_mbuf *mb;
1932 mb = rxq->rx_stage[rxq->rx_next_avail + i];
1933 rte_pktmbuf_free_seg(mb);
1935 rxq->rx_nb_avail = 0;
1942 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
1945 ixgbe_rx_queue_release_mbufs(rxq);
1946 rte_free(rxq->sw_ring);
1952 ixgbe_dev_rx_queue_release(void *rxq)
1954 ixgbe_rx_queue_release(rxq);
1958 * Check if Rx Burst Bulk Alloc function can be used.
1960 * 0: the preconditions are satisfied and the bulk allocation function
1962 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
1963 * function must be used.
1966 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1967 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
1969 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct igb_rx_queue *rxq)
1975 * Make sure the following pre-conditions are satisfied:
1976 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
1977 * rxq->rx_free_thresh < rxq->nb_rx_desc
1978 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
1979 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
1980 * Scattered packets are not supported. This should be checked
1981 * outside of this function.
1983 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1984 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
1985 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
1986 "rxq->rx_free_thresh=%d, "
1987 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
1988 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
1990 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
1991 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
1992 "rxq->rx_free_thresh=%d, "
1993 "rxq->nb_rx_desc=%d",
1994 rxq->rx_free_thresh, rxq->nb_rx_desc);
1996 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
1997 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
1998 "rxq->nb_rx_desc=%d, "
1999 "rxq->rx_free_thresh=%d",
2000 rxq->nb_rx_desc, rxq->rx_free_thresh);
2002 } else if (!(rxq->nb_rx_desc <
2003 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2004 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2005 "rxq->nb_rx_desc=%d, "
2006 "IXGBE_MAX_RING_DESC=%d, "
2007 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2008 rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2009 RTE_PMD_IXGBE_RX_MAX_BURST);
2019 /* Reset dynamic igb_rx_queue fields back to defaults */
2021 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
2023 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
2029 * By default, the Rx queue setup function allocates enough memory for
2030 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2031 * extra memory at the end of the descriptor ring to be zero'd out. A
2032 * pre-condition for using the Rx burst bulk alloc function is that the
2033 * number of descriptors is less than or equal to
2034 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2035 * constraints here to see if we need to zero out memory after the end
2036 * of the H/W descriptor ring.
2038 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2039 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2040 /* zero out extra memory */
2041 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2044 /* do not zero out extra memory */
2045 len = rxq->nb_rx_desc;
2048 * Zero out HW ring memory. Zero out extra memory at the end of
2049 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2050 * reads extra memory as zeros.
2052 for (i = 0; i < len; i++) {
2053 rxq->rx_ring[i] = zeroed_desc;
2056 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2058 * initialize extra software ring entries. Space for these extra
2059 * entries is always allocated
2061 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2062 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2063 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2066 rxq->rx_nb_avail = 0;
2067 rxq->rx_next_avail = 0;
2068 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2069 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2071 rxq->nb_rx_hold = 0;
2072 rxq->pkt_first_seg = NULL;
2073 rxq->pkt_last_seg = NULL;
2077 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2080 unsigned int socket_id,
2081 const struct rte_eth_rxconf *rx_conf,
2082 struct rte_mempool *mp)
2084 const struct rte_memzone *rz;
2085 struct igb_rx_queue *rxq;
2086 struct ixgbe_hw *hw;
2087 int use_def_burst_func = 1;
2090 PMD_INIT_FUNC_TRACE();
2091 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2094 * Validate number of receive descriptors.
2095 * It must not exceed hardware maximum, and must be multiple
2098 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2099 (nb_desc > IXGBE_MAX_RING_DESC) ||
2100 (nb_desc < IXGBE_MIN_RING_DESC)) {
2104 /* Free memory prior to re-allocation if needed... */
2105 if (dev->data->rx_queues[queue_idx] != NULL) {
2106 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2107 dev->data->rx_queues[queue_idx] = NULL;
2110 /* First allocate the rx queue data structure */
2111 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct igb_rx_queue),
2112 CACHE_LINE_SIZE, socket_id);
2116 rxq->nb_rx_desc = nb_desc;
2117 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2118 rxq->queue_id = queue_idx;
2119 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2120 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2121 rxq->port_id = dev->data->port_id;
2122 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2124 rxq->drop_en = rx_conf->rx_drop_en;
2125 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2128 * Allocate RX ring hardware descriptors. A memzone large enough to
2129 * handle the maximum ring size is allocated in order to allow for
2130 * resizing in later calls to the queue setup function.
2132 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2133 RX_RING_SZ, socket_id);
2135 ixgbe_rx_queue_release(rxq);
2140 * Zero init all the descriptors in the ring.
2142 memset (rz->addr, 0, RX_RING_SZ);
2145 * Modified to setup VFRDT for Virtual Function
2147 if (hw->mac.type == ixgbe_mac_82599_vf) {
2149 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2151 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2155 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2157 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2159 #ifndef RTE_LIBRTE_XEN_DOM0
2160 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2162 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2164 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2167 * Allocate software ring. Allow for space at the end of the
2168 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2169 * function does not access an invalid memory region.
2171 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2172 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2176 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2177 sizeof(struct igb_rx_entry) * len,
2178 CACHE_LINE_SIZE, socket_id);
2179 if (rxq->sw_ring == NULL) {
2180 ixgbe_rx_queue_release(rxq);
2183 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2184 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2187 * Certain constraints must be met in order to use the bulk buffer
2188 * allocation Rx burst function.
2190 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2192 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2193 if (!use_def_burst_func && !dev->data->scattered_rx) {
2194 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2195 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2196 "satisfied. Rx Burst Bulk Alloc function will be "
2197 "used on port=%d, queue=%d.",
2198 rxq->port_id, rxq->queue_id);
2199 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2200 #ifdef RTE_IXGBE_INC_VECTOR
2201 if (!ixgbe_rx_vec_condition_check(dev)) {
2202 PMD_INIT_LOG(INFO, "Vector rx enabled, please make "
2203 "sure RX burst size no less than 32.");
2204 ixgbe_rxq_vec_setup(rxq);
2205 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
2210 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2211 "are not satisfied, Scattered Rx is requested, "
2212 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2213 "enabled (port=%d, queue=%d).",
2214 rxq->port_id, rxq->queue_id);
2216 dev->data->rx_queues[queue_idx] = rxq;
2218 ixgbe_reset_rx_queue(rxq);
2224 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2226 #define IXGBE_RXQ_SCAN_INTERVAL 4
2227 volatile union ixgbe_adv_rx_desc *rxdp;
2228 struct igb_rx_queue *rxq;
2231 if (rx_queue_id >= dev->data->nb_rx_queues) {
2232 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2236 rxq = dev->data->rx_queues[rx_queue_id];
2237 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2239 while ((desc < rxq->nb_rx_desc) &&
2240 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2241 desc += IXGBE_RXQ_SCAN_INTERVAL;
2242 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2243 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2244 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2245 desc - rxq->nb_rx_desc]);
2252 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2254 volatile union ixgbe_adv_rx_desc *rxdp;
2255 struct igb_rx_queue *rxq = rx_queue;
2258 if (unlikely(offset >= rxq->nb_rx_desc))
2260 desc = rxq->rx_tail + offset;
2261 if (desc >= rxq->nb_rx_desc)
2262 desc -= rxq->nb_rx_desc;
2264 rxdp = &rxq->rx_ring[desc];
2265 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2269 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2273 PMD_INIT_FUNC_TRACE();
2275 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2276 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2278 txq->ops->release_mbufs(txq);
2279 txq->ops->reset(txq);
2283 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2284 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2286 ixgbe_rx_queue_release_mbufs(rxq);
2287 ixgbe_reset_rx_queue(rxq);
2292 /*********************************************************************
2294 * Device RX/TX init functions
2296 **********************************************************************/
2299 * Receive Side Scaling (RSS)
2300 * See section 7.1.2.8 in the following document:
2301 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2304 * The source and destination IP addresses of the IP header and the source
2305 * and destination ports of TCP/UDP headers, if any, of received packets are
2306 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2307 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2308 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2309 * RSS output index which is used as the RX queue index where to store the
2311 * The following output is supplied in the RX write-back descriptor:
2312 * - 32-bit result of the Microsoft RSS hash function,
2313 * - 4-bit RSS type field.
2317 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2318 * Used as the default key.
2320 static uint8_t rss_intel_key[40] = {
2321 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2322 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2323 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2324 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2325 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2329 ixgbe_rss_disable(struct rte_eth_dev *dev)
2331 struct ixgbe_hw *hw;
2334 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2335 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2336 mrqc &= ~IXGBE_MRQC_RSSEN;
2337 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2341 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2349 hash_key = rss_conf->rss_key;
2350 if (hash_key != NULL) {
2351 /* Fill in RSS hash key */
2352 for (i = 0; i < 10; i++) {
2353 rss_key = hash_key[(i * 4)];
2354 rss_key |= hash_key[(i * 4) + 1] << 8;
2355 rss_key |= hash_key[(i * 4) + 2] << 16;
2356 rss_key |= hash_key[(i * 4) + 3] << 24;
2357 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2361 /* Set configured hashing protocols in MRQC register */
2362 rss_hf = rss_conf->rss_hf;
2363 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2364 if (rss_hf & ETH_RSS_IPV4)
2365 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2366 if (rss_hf & ETH_RSS_IPV4_TCP)
2367 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2368 if (rss_hf & ETH_RSS_IPV6)
2369 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2370 if (rss_hf & ETH_RSS_IPV6_EX)
2371 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2372 if (rss_hf & ETH_RSS_IPV6_TCP)
2373 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2374 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2375 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2376 if (rss_hf & ETH_RSS_IPV4_UDP)
2377 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2378 if (rss_hf & ETH_RSS_IPV6_UDP)
2379 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2380 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2381 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2382 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2386 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2387 struct rte_eth_rss_conf *rss_conf)
2389 struct ixgbe_hw *hw;
2393 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2396 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2397 * "RSS enabling cannot be done dynamically while it must be
2398 * preceded by a software reset"
2399 * Before changing anything, first check that the update RSS operation
2400 * does not attempt to disable RSS, if RSS was enabled at
2401 * initialization time, or does not attempt to enable RSS, if RSS was
2402 * disabled at initialization time.
2404 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2405 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2406 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2407 if (rss_hf != 0) /* Enable RSS */
2409 return 0; /* Nothing to do */
2412 if (rss_hf == 0) /* Disable RSS */
2414 ixgbe_hw_rss_hash_set(hw, rss_conf);
2419 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2420 struct rte_eth_rss_conf *rss_conf)
2422 struct ixgbe_hw *hw;
2429 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2430 hash_key = rss_conf->rss_key;
2431 if (hash_key != NULL) {
2432 /* Return RSS hash key */
2433 for (i = 0; i < 10; i++) {
2434 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2435 hash_key[(i * 4)] = rss_key & 0x000000FF;
2436 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2437 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2438 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2442 /* Get RSS functions configured in MRQC register */
2443 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2444 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2445 rss_conf->rss_hf = 0;
2449 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2450 rss_hf |= ETH_RSS_IPV4;
2451 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2452 rss_hf |= ETH_RSS_IPV4_TCP;
2453 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2454 rss_hf |= ETH_RSS_IPV6;
2455 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2456 rss_hf |= ETH_RSS_IPV6_EX;
2457 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2458 rss_hf |= ETH_RSS_IPV6_TCP;
2459 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2460 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2461 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2462 rss_hf |= ETH_RSS_IPV4_UDP;
2463 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2464 rss_hf |= ETH_RSS_IPV6_UDP;
2465 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2466 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2467 rss_conf->rss_hf = rss_hf;
2472 ixgbe_rss_configure(struct rte_eth_dev *dev)
2474 struct rte_eth_rss_conf rss_conf;
2475 struct ixgbe_hw *hw;
2480 PMD_INIT_FUNC_TRACE();
2481 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2484 * Fill in redirection table
2485 * The byte-swap is needed because NIC registers are in
2486 * little-endian order.
2489 for (i = 0, j = 0; i < 128; i++, j++) {
2490 if (j == dev->data->nb_rx_queues)
2492 reta = (reta << 8) | j;
2494 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2499 * Configure the RSS key and the RSS protocols used to compute
2500 * the RSS hash of input packets.
2502 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2503 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2504 ixgbe_rss_disable(dev);
2507 if (rss_conf.rss_key == NULL)
2508 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2509 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2512 #define NUM_VFTA_REGISTERS 128
2513 #define NIC_RX_BUFFER_SIZE 0x200
2516 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2518 struct rte_eth_vmdq_dcb_conf *cfg;
2519 struct ixgbe_hw *hw;
2520 enum rte_eth_nb_pools num_pools;
2521 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2523 uint8_t nb_tcs; /* number of traffic classes */
2526 PMD_INIT_FUNC_TRACE();
2527 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2528 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2529 num_pools = cfg->nb_queue_pools;
2530 /* Check we have a valid number of pools */
2531 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2532 ixgbe_rss_disable(dev);
2535 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2536 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2540 * split rx buffer up into sections, each for 1 traffic class
2542 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2543 for (i = 0 ; i < nb_tcs; i++) {
2544 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2545 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2546 /* clear 10 bits. */
2547 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2548 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2550 /* zero alloc all unused TCs */
2551 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2552 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2553 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2554 /* clear 10 bits. */
2555 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2558 /* MRQC: enable vmdq and dcb */
2559 mrqc = ((num_pools == ETH_16_POOLS) ? \
2560 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2561 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2563 /* PFVTCTL: turn on virtualisation and set the default pool */
2564 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2565 if (cfg->enable_default_pool) {
2566 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2568 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2571 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2573 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2575 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2577 * mapping is done with 3 bits per priority,
2578 * so shift by i*3 each time
2580 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2582 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2584 /* RTRPCS: DCB related */
2585 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2587 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2588 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2589 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2590 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2592 /* VFTA - enable all vlan filters */
2593 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2594 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2597 /* VFRE: pool enabling for receive - 16 or 32 */
2598 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2599 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2602 * MPSAR - allow pools to read specific mac addresses
2603 * In this case, all pools should be able to read from mac addr 0
2605 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2606 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2608 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2609 for (i = 0; i < cfg->nb_pool_maps; i++) {
2610 /* set vlan id in VF register and set the valid bit */
2611 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2612 (cfg->pool_map[i].vlan_id & 0xFFF)));
2614 * Put the allowed pools in VFB reg. As we only have 16 or 32
2615 * pools, we only need to use the first half of the register
2618 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2623 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2624 * @hw: pointer to hardware structure
2625 * @dcb_config: pointer to ixgbe_dcb_config structure
2628 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2629 struct ixgbe_dcb_config *dcb_config)
2634 PMD_INIT_FUNC_TRACE();
2635 if (hw->mac.type != ixgbe_mac_82598EB) {
2636 /* Disable the Tx desc arbiter so that MTQC can be changed */
2637 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2638 reg |= IXGBE_RTTDCS_ARBDIS;
2639 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2641 /* Enable DCB for Tx with 8 TCs */
2642 if (dcb_config->num_tcs.pg_tcs == 8) {
2643 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2646 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2648 if (dcb_config->vt_mode)
2649 reg |= IXGBE_MTQC_VT_ENA;
2650 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2652 /* Disable drop for all queues */
2653 for (q = 0; q < 128; q++)
2654 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2655 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2657 /* Enable the Tx desc arbiter */
2658 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2659 reg &= ~IXGBE_RTTDCS_ARBDIS;
2660 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2662 /* Enable Security TX Buffer IFG for DCB */
2663 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2664 reg |= IXGBE_SECTX_DCB;
2665 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2671 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2672 * @dev: pointer to rte_eth_dev structure
2673 * @dcb_config: pointer to ixgbe_dcb_config structure
2676 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2677 struct ixgbe_dcb_config *dcb_config)
2679 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2680 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2681 struct ixgbe_hw *hw =
2682 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2684 PMD_INIT_FUNC_TRACE();
2685 if (hw->mac.type != ixgbe_mac_82598EB)
2686 /*PF VF Transmit Enable*/
2687 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2688 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2690 /*Configure general DCB TX parameters*/
2691 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2696 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2697 struct ixgbe_dcb_config *dcb_config)
2699 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2700 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2701 struct ixgbe_dcb_tc_config *tc;
2704 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2705 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2706 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2707 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2710 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2711 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2713 /* User Priority to Traffic Class mapping */
2714 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2715 j = vmdq_rx_conf->dcb_queue[i];
2716 tc = &dcb_config->tc_config[j];
2717 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2723 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2724 struct ixgbe_dcb_config *dcb_config)
2726 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2727 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2728 struct ixgbe_dcb_tc_config *tc;
2731 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2732 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2733 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2734 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2737 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2738 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2741 /* User Priority to Traffic Class mapping */
2742 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2743 j = vmdq_tx_conf->dcb_queue[i];
2744 tc = &dcb_config->tc_config[j];
2745 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2752 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2753 struct ixgbe_dcb_config *dcb_config)
2755 struct rte_eth_dcb_rx_conf *rx_conf =
2756 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2757 struct ixgbe_dcb_tc_config *tc;
2760 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2761 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2763 /* User Priority to Traffic Class mapping */
2764 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2765 j = rx_conf->dcb_queue[i];
2766 tc = &dcb_config->tc_config[j];
2767 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2773 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2774 struct ixgbe_dcb_config *dcb_config)
2776 struct rte_eth_dcb_tx_conf *tx_conf =
2777 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2778 struct ixgbe_dcb_tc_config *tc;
2781 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2782 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2784 /* User Priority to Traffic Class mapping */
2785 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2786 j = tx_conf->dcb_queue[i];
2787 tc = &dcb_config->tc_config[j];
2788 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2794 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2795 * @hw: pointer to hardware structure
2796 * @dcb_config: pointer to ixgbe_dcb_config structure
2799 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2800 struct ixgbe_dcb_config *dcb_config)
2806 PMD_INIT_FUNC_TRACE();
2808 * Disable the arbiter before changing parameters
2809 * (always enable recycle mode; WSP)
2811 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2812 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2814 if (hw->mac.type != ixgbe_mac_82598EB) {
2815 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2816 if (dcb_config->num_tcs.pg_tcs == 4) {
2817 if (dcb_config->vt_mode)
2818 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2819 IXGBE_MRQC_VMDQRT4TCEN;
2821 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2822 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2826 if (dcb_config->num_tcs.pg_tcs == 8) {
2827 if (dcb_config->vt_mode)
2828 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2829 IXGBE_MRQC_VMDQRT8TCEN;
2831 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2832 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2837 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2840 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2841 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2842 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2843 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2845 /* VFTA - enable all vlan filters */
2846 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2847 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2851 * Configure Rx packet plane (recycle mode; WSP) and
2854 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2855 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2861 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2862 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2864 switch (hw->mac.type) {
2865 case ixgbe_mac_82598EB:
2866 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2868 case ixgbe_mac_82599EB:
2869 case ixgbe_mac_X540:
2870 case ixgbe_mac_X550:
2871 case ixgbe_mac_X550EM_x:
2872 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2881 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2882 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2884 switch (hw->mac.type) {
2885 case ixgbe_mac_82598EB:
2886 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2887 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2889 case ixgbe_mac_82599EB:
2890 case ixgbe_mac_X540:
2891 case ixgbe_mac_X550:
2892 case ixgbe_mac_X550EM_x:
2893 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2894 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2901 #define DCB_RX_CONFIG 1
2902 #define DCB_TX_CONFIG 1
2903 #define DCB_TX_PB 1024
2905 * ixgbe_dcb_hw_configure - Enable DCB and configure
2906 * general DCB in VT mode and non-VT mode parameters
2907 * @dev: pointer to rte_eth_dev structure
2908 * @dcb_config: pointer to ixgbe_dcb_config structure
2911 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2912 struct ixgbe_dcb_config *dcb_config)
2915 uint8_t i,pfc_en,nb_tcs;
2917 uint8_t config_dcb_rx = 0;
2918 uint8_t config_dcb_tx = 0;
2919 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2920 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2921 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2922 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2923 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2924 struct ixgbe_dcb_tc_config *tc;
2925 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2926 struct ixgbe_hw *hw =
2927 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2929 switch(dev->data->dev_conf.rxmode.mq_mode){
2930 case ETH_MQ_RX_VMDQ_DCB:
2931 dcb_config->vt_mode = true;
2932 if (hw->mac.type != ixgbe_mac_82598EB) {
2933 config_dcb_rx = DCB_RX_CONFIG;
2935 *get dcb and VT rx configuration parameters
2938 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2939 /*Configure general VMDQ and DCB RX parameters*/
2940 ixgbe_vmdq_dcb_configure(dev);
2944 dcb_config->vt_mode = false;
2945 config_dcb_rx = DCB_RX_CONFIG;
2946 /* Get dcb TX configuration parameters from rte_eth_conf */
2947 ixgbe_dcb_rx_config(dev,dcb_config);
2948 /*Configure general DCB RX parameters*/
2949 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2952 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
2955 switch (dev->data->dev_conf.txmode.mq_mode) {
2956 case ETH_MQ_TX_VMDQ_DCB:
2957 dcb_config->vt_mode = true;
2958 config_dcb_tx = DCB_TX_CONFIG;
2959 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2960 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2961 /*Configure general VMDQ and DCB TX parameters*/
2962 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2966 dcb_config->vt_mode = false;
2967 config_dcb_tx = DCB_TX_CONFIG;
2968 /*get DCB TX configuration parameters from rte_eth_conf*/
2969 ixgbe_dcb_tx_config(dev,dcb_config);
2970 /*Configure general DCB TX parameters*/
2971 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2974 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
2978 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2980 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2981 if(nb_tcs == ETH_4_TCS) {
2982 /* Avoid un-configured priority mapping to TC0 */
2984 uint8_t mask = 0xFF;
2985 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
2986 mask = (uint8_t)(mask & (~ (1 << map[i])));
2987 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
2988 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
2992 /* Re-configure 4 TCs BW */
2993 for (i = 0; i < nb_tcs; i++) {
2994 tc = &dcb_config->tc_config[i];
2995 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
2996 (uint8_t)(100 / nb_tcs);
2997 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
2998 (uint8_t)(100 / nb_tcs);
3000 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3001 tc = &dcb_config->tc_config[i];
3002 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3003 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3008 /* Set RX buffer size */
3009 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3010 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3011 for (i = 0 ; i < nb_tcs; i++) {
3012 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3014 /* zero alloc all unused TCs */
3015 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3016 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3020 /* Only support an equally distributed Tx packet buffer strategy. */
3021 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3022 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3023 for (i = 0; i < nb_tcs; i++) {
3024 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3025 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3027 /* Clear unused TCs, if any, to zero buffer size*/
3028 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3029 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3030 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3034 /*Calculates traffic class credits*/
3035 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3036 IXGBE_DCB_TX_CONFIG);
3037 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3038 IXGBE_DCB_RX_CONFIG);
3041 /* Unpack CEE standard containers */
3042 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3043 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3044 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3045 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3046 /* Configure PG(ETS) RX */
3047 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3051 /* Unpack CEE standard containers */
3052 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3053 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3054 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3055 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3056 /* Configure PG(ETS) TX */
3057 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3060 /*Configure queue statistics registers*/
3061 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3063 /* Check if the PFC is supported */
3064 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3065 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3066 for (i = 0; i < nb_tcs; i++) {
3068 * If the TC count is 8,and the default high_water is 48,
3069 * the low_water is 16 as default.
3071 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3072 hw->fc.low_water[i] = pbsize / 4;
3073 /* Enable pfc for this TC */
3074 tc = &dcb_config->tc_config[i];
3075 tc->pfc = ixgbe_dcb_pfc_enabled;
3077 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3078 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3080 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3087 * ixgbe_configure_dcb - Configure DCB Hardware
3088 * @dev: pointer to rte_eth_dev
3090 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3092 struct ixgbe_dcb_config *dcb_cfg =
3093 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3094 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3096 PMD_INIT_FUNC_TRACE();
3098 /* check support mq_mode for DCB */
3099 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3100 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3103 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3106 /** Configure DCB hardware **/
3107 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3113 * VMDq only support for 10 GbE NIC.
3116 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3118 struct rte_eth_vmdq_rx_conf *cfg;
3119 struct ixgbe_hw *hw;
3120 enum rte_eth_nb_pools num_pools;
3121 uint32_t mrqc, vt_ctl, vlanctrl;
3124 PMD_INIT_FUNC_TRACE();
3125 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3126 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3127 num_pools = cfg->nb_queue_pools;
3129 ixgbe_rss_disable(dev);
3131 /* MRQC: enable vmdq */
3132 mrqc = IXGBE_MRQC_VMDQEN;
3133 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3135 /* PFVTCTL: turn on virtualisation and set the default pool */
3136 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3137 if (cfg->enable_default_pool)
3138 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3140 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3142 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3144 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3145 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3146 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3147 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3149 /* VFTA - enable all vlan filters */
3150 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3151 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3153 /* VFRE: pool enabling for receive - 64 */
3154 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3155 if (num_pools == ETH_64_POOLS)
3156 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3159 * MPSAR - allow pools to read specific mac addresses
3160 * In this case, all pools should be able to read from mac addr 0
3162 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3163 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3165 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3166 for (i = 0; i < cfg->nb_pool_maps; i++) {
3167 /* set vlan id in VF register and set the valid bit */
3168 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3169 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3171 * Put the allowed pools in VFB reg. As we only have 16 or 64
3172 * pools, we only need to use the first half of the register
3175 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3176 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3177 (cfg->pool_map[i].pools & UINT32_MAX));
3179 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3180 ((cfg->pool_map[i].pools >> 32) \
3185 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3186 if (cfg->enable_loop_back) {
3187 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3188 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3189 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3192 IXGBE_WRITE_FLUSH(hw);
3196 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3197 * @hw: pointer to hardware structure
3200 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3205 PMD_INIT_FUNC_TRACE();
3206 /*PF VF Transmit Enable*/
3207 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3208 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3210 /* Disable the Tx desc arbiter so that MTQC can be changed */
3211 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3212 reg |= IXGBE_RTTDCS_ARBDIS;
3213 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3215 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3216 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3218 /* Disable drop for all queues */
3219 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3220 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3221 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3223 /* Enable the Tx desc arbiter */
3224 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3225 reg &= ~IXGBE_RTTDCS_ARBDIS;
3226 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3228 IXGBE_WRITE_FLUSH(hw);
3234 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
3236 struct igb_rx_entry *rxe = rxq->sw_ring;
3240 /* Initialize software ring entries */
3241 for (i = 0; i < rxq->nb_rx_desc; i++) {
3242 volatile union ixgbe_adv_rx_desc *rxd;
3243 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3245 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3246 (unsigned) rxq->queue_id);
3250 rte_mbuf_refcnt_set(mbuf, 1);
3252 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3254 mbuf->port = rxq->port_id;
3257 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3258 rxd = &rxq->rx_ring[i];
3259 rxd->read.hdr_addr = dma_addr;
3260 rxd->read.pkt_addr = dma_addr;
3268 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3270 struct ixgbe_hw *hw =
3271 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3273 if (hw->mac.type == ixgbe_mac_82598EB)
3276 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3278 * SRIOV inactive scheme
3279 * any DCB/RSS w/o VMDq multi-queue setting
3281 switch (dev->data->dev_conf.rxmode.mq_mode) {
3283 ixgbe_rss_configure(dev);
3286 case ETH_MQ_RX_VMDQ_DCB:
3287 ixgbe_vmdq_dcb_configure(dev);
3290 case ETH_MQ_RX_VMDQ_ONLY:
3291 ixgbe_vmdq_rx_hw_configure(dev);
3294 case ETH_MQ_RX_NONE:
3295 /* if mq_mode is none, disable rss mode.*/
3296 default: ixgbe_rss_disable(dev);
3299 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3301 * SRIOV active scheme
3302 * FIXME if support DCB/RSS together with VMDq & SRIOV
3305 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQEN);
3309 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT4TCEN);
3313 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT8TCEN);
3316 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3324 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3326 struct ixgbe_hw *hw =
3327 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3331 if (hw->mac.type == ixgbe_mac_82598EB)
3334 /* disable arbiter before setting MTQC */
3335 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3336 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3337 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3339 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3341 * SRIOV inactive scheme
3342 * any DCB w/o VMDq multi-queue setting
3344 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3345 ixgbe_vmdq_tx_hw_configure(hw);
3347 mtqc = IXGBE_MTQC_64Q_1PB;
3348 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3351 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3354 * SRIOV active scheme
3355 * FIXME if support DCB together with VMDq & SRIOV
3358 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3361 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3364 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3368 mtqc = IXGBE_MTQC_64Q_1PB;
3369 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3371 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3374 /* re-enable arbiter */
3375 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3376 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3382 * Initializes Receive Unit.
3385 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3387 struct ixgbe_hw *hw;
3388 struct igb_rx_queue *rxq;
3389 struct rte_pktmbuf_pool_private *mbp_priv;
3401 PMD_INIT_FUNC_TRACE();
3402 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3405 * Make sure receives are disabled while setting
3406 * up the RX context (registers, descriptor rings, etc.).
3408 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3409 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3411 /* Enable receipt of broadcasted frames */
3412 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3413 fctrl |= IXGBE_FCTRL_BAM;
3414 fctrl |= IXGBE_FCTRL_DPF;
3415 fctrl |= IXGBE_FCTRL_PMCF;
3416 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3419 * Configure CRC stripping, if any.
3421 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3422 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3423 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3425 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3428 * Configure jumbo frame support, if any.
3430 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3431 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3432 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3433 maxfrs &= 0x0000FFFF;
3434 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3435 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3437 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3440 * If loopback mode is configured for 82599, set LPBK bit.
3442 if (hw->mac.type == ixgbe_mac_82599EB &&
3443 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3444 hlreg0 |= IXGBE_HLREG0_LPBK;
3446 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3448 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3450 /* Setup RX queues */
3451 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3452 rxq = dev->data->rx_queues[i];
3455 * Reset crc_len in case it was changed after queue setup by a
3456 * call to configure.
3458 rxq->crc_len = (uint8_t)
3459 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3462 /* Setup the Base and Length of the Rx Descriptor Rings */
3463 bus_addr = rxq->rx_ring_phys_addr;
3464 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3465 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3466 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3467 (uint32_t)(bus_addr >> 32));
3468 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3469 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3470 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3471 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3473 /* Configure the SRRCTL register */
3474 #ifdef RTE_HEADER_SPLIT_ENABLE
3476 * Configure Header Split
3478 if (dev->data->dev_conf.rxmode.header_split) {
3479 if (hw->mac.type == ixgbe_mac_82599EB) {
3480 /* Must setup the PSRTYPE register */
3482 psrtype = IXGBE_PSRTYPE_TCPHDR |
3483 IXGBE_PSRTYPE_UDPHDR |
3484 IXGBE_PSRTYPE_IPV4HDR |
3485 IXGBE_PSRTYPE_IPV6HDR;
3486 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3488 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3489 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3490 IXGBE_SRRCTL_BSIZEHDR_MASK);
3491 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3494 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3496 /* Set if packets are dropped when no descriptors available */
3498 srrctl |= IXGBE_SRRCTL_DROP_EN;
3501 * Configure the RX buffer size in the BSIZEPACKET field of
3502 * the SRRCTL register of the queue.
3503 * The value is in 1 KB resolution. Valid values can be from
3506 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3507 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3508 RTE_PKTMBUF_HEADROOM);
3509 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3510 IXGBE_SRRCTL_BSIZEPKT_MASK);
3511 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3513 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3514 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3516 /* It adds dual VLAN length for supporting dual VLAN */
3517 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3518 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3519 if (!dev->data->scattered_rx)
3520 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
3521 dev->data->scattered_rx = 1;
3522 #ifdef RTE_IXGBE_INC_VECTOR
3523 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3525 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3530 if (dev->data->dev_conf.rxmode.enable_scatter) {
3531 if (!dev->data->scattered_rx)
3532 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
3533 #ifdef RTE_IXGBE_INC_VECTOR
3534 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3536 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3538 dev->data->scattered_rx = 1;
3542 * Device configured with multiple RX queues.
3544 ixgbe_dev_mq_rx_configure(dev);
3547 * Setup the Checksum Register.
3548 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3549 * Enable IP/L4 checkum computation by hardware if requested to do so.
3551 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3552 rxcsum |= IXGBE_RXCSUM_PCSD;
3553 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3554 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3556 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3558 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3560 if (hw->mac.type == ixgbe_mac_82599EB) {
3561 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3562 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3563 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3565 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3566 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3567 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3574 * Initializes Transmit Unit.
3577 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3579 struct ixgbe_hw *hw;
3580 struct igb_tx_queue *txq;
3586 PMD_INIT_FUNC_TRACE();
3587 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3589 /* Enable TX CRC (checksum offload requirement) */
3590 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3591 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
3592 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3594 /* Setup the Base and Length of the Tx Descriptor Rings */
3595 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3596 txq = dev->data->tx_queues[i];
3598 bus_addr = txq->tx_ring_phys_addr;
3599 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3600 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3601 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3602 (uint32_t)(bus_addr >> 32));
3603 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3604 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3605 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3606 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3607 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3610 * Disable Tx Head Writeback RO bit, since this hoses
3611 * bookkeeping if things aren't delivered in order.
3613 switch (hw->mac.type) {
3614 case ixgbe_mac_82598EB:
3615 txctrl = IXGBE_READ_REG(hw,
3616 IXGBE_DCA_TXCTRL(txq->reg_idx));
3617 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3618 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3622 case ixgbe_mac_82599EB:
3623 case ixgbe_mac_X540:
3624 case ixgbe_mac_X550:
3625 case ixgbe_mac_X550EM_x:
3627 txctrl = IXGBE_READ_REG(hw,
3628 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3629 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3630 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3636 /* Device configured with multiple TX queues. */
3637 ixgbe_dev_mq_tx_configure(dev);
3641 * Set up link for 82599 loopback mode Tx->Rx.
3644 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3646 PMD_INIT_FUNC_TRACE();
3648 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3649 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3651 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
3660 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3661 ixgbe_reset_pipeline_82599(hw);
3663 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3669 * Start Transmit and Receive Units.
3672 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3674 struct ixgbe_hw *hw;
3675 struct igb_tx_queue *txq;
3676 struct igb_rx_queue *rxq;
3682 PMD_INIT_FUNC_TRACE();
3683 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3685 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3686 txq = dev->data->tx_queues[i];
3687 /* Setup Transmit Threshold Registers */
3688 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3689 txdctl |= txq->pthresh & 0x7F;
3690 txdctl |= ((txq->hthresh & 0x7F) << 8);
3691 txdctl |= ((txq->wthresh & 0x7F) << 16);
3692 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3695 if (hw->mac.type != ixgbe_mac_82598EB) {
3696 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3697 dmatxctl |= IXGBE_DMATXCTL_TE;
3698 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3701 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3702 txq = dev->data->tx_queues[i];
3703 if (!txq->tx_deferred_start)
3704 ixgbe_dev_tx_queue_start(dev, i);
3707 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3708 rxq = dev->data->rx_queues[i];
3709 if (!rxq->rx_deferred_start)
3710 ixgbe_dev_rx_queue_start(dev, i);
3713 /* Enable Receive engine */
3714 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3715 if (hw->mac.type == ixgbe_mac_82598EB)
3716 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3717 rxctrl |= IXGBE_RXCTRL_RXEN;
3718 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3720 /* If loopback mode is enabled for 82599, set up the link accordingly */
3721 if (hw->mac.type == ixgbe_mac_82599EB &&
3722 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3723 ixgbe_setup_loopback_link_82599(hw);
3728 * Start Receive Units for specified queue.
3731 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3733 struct ixgbe_hw *hw;
3734 struct igb_rx_queue *rxq;
3738 PMD_INIT_FUNC_TRACE();
3739 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3741 if (rx_queue_id < dev->data->nb_rx_queues) {
3742 rxq = dev->data->rx_queues[rx_queue_id];
3744 /* Allocate buffers for descriptor rings */
3745 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
3746 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
3750 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3751 rxdctl |= IXGBE_RXDCTL_ENABLE;
3752 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3754 /* Wait until RX Enable ready */
3755 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3758 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3759 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3761 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
3764 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3765 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3773 * Stop Receive Units for specified queue.
3776 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3778 struct ixgbe_hw *hw;
3779 struct igb_rx_queue *rxq;
3783 PMD_INIT_FUNC_TRACE();
3784 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3786 if (rx_queue_id < dev->data->nb_rx_queues) {
3787 rxq = dev->data->rx_queues[rx_queue_id];
3789 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3790 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3791 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3793 /* Wait until RX Enable ready */
3794 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3797 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3798 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
3800 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
3803 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3805 ixgbe_rx_queue_release_mbufs(rxq);
3806 ixgbe_reset_rx_queue(rxq);
3815 * Start Transmit Units for specified queue.
3818 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3820 struct ixgbe_hw *hw;
3821 struct igb_tx_queue *txq;
3825 PMD_INIT_FUNC_TRACE();
3826 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3828 if (tx_queue_id < dev->data->nb_tx_queues) {
3829 txq = dev->data->tx_queues[tx_queue_id];
3830 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3831 txdctl |= IXGBE_TXDCTL_ENABLE;
3832 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3834 /* Wait until TX Enable ready */
3835 if (hw->mac.type == ixgbe_mac_82599EB) {
3836 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3839 txdctl = IXGBE_READ_REG(hw,
3840 IXGBE_TXDCTL(txq->reg_idx));
3841 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3843 PMD_INIT_LOG(ERR, "Could not enable "
3844 "Tx Queue %d", tx_queue_id);
3847 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3848 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3856 * Stop Transmit Units for specified queue.
3859 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3861 struct ixgbe_hw *hw;
3862 struct igb_tx_queue *txq;
3864 uint32_t txtdh, txtdt;
3867 PMD_INIT_FUNC_TRACE();
3868 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3870 if (tx_queue_id < dev->data->nb_tx_queues) {
3871 txq = dev->data->tx_queues[tx_queue_id];
3873 /* Wait until TX queue is empty */
3874 if (hw->mac.type == ixgbe_mac_82599EB) {
3875 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3877 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3878 txtdh = IXGBE_READ_REG(hw,
3879 IXGBE_TDH(txq->reg_idx));
3880 txtdt = IXGBE_READ_REG(hw,
3881 IXGBE_TDT(txq->reg_idx));
3882 } while (--poll_ms && (txtdh != txtdt));
3884 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
3885 "when stopping.", tx_queue_id);
3888 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3889 txdctl &= ~IXGBE_TXDCTL_ENABLE;
3890 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3892 /* Wait until TX Enable ready */
3893 if (hw->mac.type == ixgbe_mac_82599EB) {
3894 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3897 txdctl = IXGBE_READ_REG(hw,
3898 IXGBE_TXDCTL(txq->reg_idx));
3899 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
3901 PMD_INIT_LOG(ERR, "Could not disable "
3902 "Tx Queue %d", tx_queue_id);
3905 if (txq->ops != NULL) {
3906 txq->ops->release_mbufs(txq);
3907 txq->ops->reset(txq);
3916 * [VF] Initializes Receive Unit.
3919 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3921 struct ixgbe_hw *hw;
3922 struct igb_rx_queue *rxq;
3923 struct rte_pktmbuf_pool_private *mbp_priv;
3930 PMD_INIT_FUNC_TRACE();
3931 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3934 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
3935 * disables the VF receipt of packets if the PF MTU is > 1500.
3936 * This is done to deal with 82599 limitations that imposes
3937 * the PF and all VFs to share the same MTU.
3938 * Then, the PF driver enables again the VF receipt of packet when
3939 * the VF driver issues a IXGBE_VF_SET_LPE request.
3940 * In the meantime, the VF device cannot be used, even if the VF driver
3941 * and the Guest VM network stack are ready to accept packets with a
3942 * size up to the PF MTU.
3943 * As a work-around to this PF behaviour, force the call to
3944 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
3945 * VF packets received can work in all cases.
3947 ixgbevf_rlpml_set_vf(hw,
3948 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
3950 /* Setup RX queues */
3951 dev->rx_pkt_burst = ixgbe_recv_pkts;
3952 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3953 rxq = dev->data->rx_queues[i];
3955 /* Allocate buffers for descriptor rings */
3956 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3960 /* Setup the Base and Length of the Rx Descriptor Rings */
3961 bus_addr = rxq->rx_ring_phys_addr;
3963 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3964 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3965 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3966 (uint32_t)(bus_addr >> 32));
3967 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3968 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3969 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3970 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3973 /* Configure the SRRCTL register */
3974 #ifdef RTE_HEADER_SPLIT_ENABLE
3976 * Configure Header Split
3978 if (dev->data->dev_conf.rxmode.header_split) {
3980 /* Must setup the PSRTYPE register */
3982 psrtype = IXGBE_PSRTYPE_TCPHDR |
3983 IXGBE_PSRTYPE_UDPHDR |
3984 IXGBE_PSRTYPE_IPV4HDR |
3985 IXGBE_PSRTYPE_IPV6HDR;
3987 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
3989 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3990 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3991 IXGBE_SRRCTL_BSIZEHDR_MASK);
3992 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3995 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3997 /* Set if packets are dropped when no descriptors available */
3999 srrctl |= IXGBE_SRRCTL_DROP_EN;
4002 * Configure the RX buffer size in the BSIZEPACKET field of
4003 * the SRRCTL register of the queue.
4004 * The value is in 1 KB resolution. Valid values can be from
4007 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
4008 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
4009 RTE_PKTMBUF_HEADROOM);
4010 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4011 IXGBE_SRRCTL_BSIZEPKT_MASK);
4014 * VF modification to write virtual function SRRCTL register
4016 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
4018 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4019 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4021 /* It adds dual VLAN length for supporting dual VLAN */
4022 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
4023 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
4024 if (!dev->data->scattered_rx)
4025 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4026 dev->data->scattered_rx = 1;
4027 #ifdef RTE_IXGBE_INC_VECTOR
4028 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4030 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
4035 if (dev->data->dev_conf.rxmode.enable_scatter) {
4036 if (!dev->data->scattered_rx)
4037 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4038 #ifdef RTE_IXGBE_INC_VECTOR
4039 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4041 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
4043 dev->data->scattered_rx = 1;
4050 * [VF] Initializes Transmit Unit.
4053 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4055 struct ixgbe_hw *hw;
4056 struct igb_tx_queue *txq;
4061 PMD_INIT_FUNC_TRACE();
4062 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4064 /* Setup the Base and Length of the Tx Descriptor Rings */
4065 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4066 txq = dev->data->tx_queues[i];
4067 bus_addr = txq->tx_ring_phys_addr;
4068 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4069 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4070 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4071 (uint32_t)(bus_addr >> 32));
4072 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4073 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4074 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4075 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4076 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4079 * Disable Tx Head Writeback RO bit, since this hoses
4080 * bookkeeping if things aren't delivered in order.
4082 txctrl = IXGBE_READ_REG(hw,
4083 IXGBE_VFDCA_TXCTRL(i));
4084 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4085 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4091 * [VF] Start Transmit and Receive Units.
4094 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4096 struct ixgbe_hw *hw;
4097 struct igb_tx_queue *txq;
4098 struct igb_rx_queue *rxq;
4104 PMD_INIT_FUNC_TRACE();
4105 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4107 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4108 txq = dev->data->tx_queues[i];
4109 /* Setup Transmit Threshold Registers */
4110 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4111 txdctl |= txq->pthresh & 0x7F;
4112 txdctl |= ((txq->hthresh & 0x7F) << 8);
4113 txdctl |= ((txq->wthresh & 0x7F) << 16);
4114 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4117 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4119 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4120 txdctl |= IXGBE_TXDCTL_ENABLE;
4121 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4124 /* Wait until TX Enable ready */
4127 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4128 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4130 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
4132 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4134 rxq = dev->data->rx_queues[i];
4136 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4137 rxdctl |= IXGBE_RXDCTL_ENABLE;
4138 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4140 /* Wait until RX Enable ready */
4144 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4145 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4147 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
4149 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);