4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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34 #include <sys/queue.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
47 #include <rte_cycles.h>
49 #include <rte_debug.h>
50 #include <rte_interrupts.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_launch.h>
55 #include <rte_tailq.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
82 #define RTE_PMD_IXGBE_TX_MAX_BURST 32
84 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
85 #define RTE_PMD_IXGBE_RX_MAX_BURST 32
88 static inline struct rte_mbuf *
89 rte_rxmbuf_alloc(struct rte_mempool *mp)
93 m = __rte_mbuf_raw_alloc(mp);
94 __rte_mbuf_sanity_check_raw(m, RTE_MBUF_PKT, 0);
98 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
99 (uint64_t) ((mb)->buf_physaddr + (uint64_t)((char *)((mb)->pkt.data) - \
100 (char *)(mb)->buf_addr))
102 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
103 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
106 * Structure associated with each descriptor of the RX ring of a RX queue.
108 struct igb_rx_entry {
109 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
113 * Structure associated with each descriptor of the TX ring of a TX queue.
115 struct igb_tx_entry {
116 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
117 uint16_t next_id; /**< Index of next descriptor in ring. */
118 uint16_t last_id; /**< Index of last scattered descriptor. */
122 * Structure associated with each RX queue.
124 struct igb_rx_queue {
125 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
126 volatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
127 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
128 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
129 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
130 struct igb_rx_entry *sw_ring; /**< address of RX software ring. */
131 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
132 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
133 uint16_t nb_rx_desc; /**< number of RX descriptors. */
134 uint16_t rx_tail; /**< current value of RDT register. */
135 uint16_t nb_rx_hold; /**< number of held free RX desc. */
136 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
137 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
138 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
139 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
141 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
142 uint16_t queue_id; /**< RX queue index. */
143 uint16_t reg_idx; /**< RX queue register index. */
144 uint8_t port_id; /**< Device port identifier. */
145 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
146 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
147 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
148 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */
149 struct rte_mbuf fake_mbuf;
150 /** hold packets to return to application */
151 struct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2];
156 * IXGBE CTX Constants
158 enum ixgbe_advctx_num {
159 IXGBE_CTX_0 = 0, /**< CTX0 */
160 IXGBE_CTX_1 = 1, /**< CTX1 */
161 IXGBE_CTX_NUM = 2, /**< CTX NUMBER */
165 * Structure to check if new context need be built
168 struct ixgbe_advctx_info {
169 uint16_t flags; /**< ol_flags for context build. */
170 uint32_t cmp_mask; /**< compare mask for vlan_macip_lens */
171 union rte_vlan_macip vlan_macip_lens; /**< vlan, mac ip length. */
175 * Structure associated with each TX queue.
177 struct igb_tx_queue {
178 /** TX ring virtual address. */
179 volatile union ixgbe_adv_tx_desc *tx_ring;
180 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
181 struct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */
182 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
183 uint16_t nb_tx_desc; /**< number of TX descriptors. */
184 uint16_t tx_tail; /**< current value of TDT reg. */
185 uint16_t tx_free_thresh;/**< minimum TX before freeing. */
186 /** Number of TX descriptors to use before RS bit is set. */
187 uint16_t tx_rs_thresh;
188 /** Number of TX descriptors used since RS bit was set. */
190 /** Index to last TX descriptor to have been cleaned. */
191 uint16_t last_desc_cleaned;
192 /** Total number of TX descriptors ready to be allocated. */
194 uint16_t tx_next_dd; /**< next desc to scan for DD bit */
195 uint16_t tx_next_rs; /**< next desc to set RS bit */
196 uint16_t queue_id; /**< TX queue index. */
197 uint16_t reg_idx; /**< TX queue register index. */
198 uint8_t port_id; /**< Device port identifier. */
199 uint8_t pthresh; /**< Prefetch threshold register. */
200 uint8_t hthresh; /**< Host threshold register. */
201 uint8_t wthresh; /**< Write-back threshold reg. */
202 uint32_t txq_flags; /**< Holds flags for this TXq */
203 uint32_t ctx_curr; /**< Hardware context states. */
204 /** Hardware context0 history. */
205 struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM];
210 #define RTE_PMD_USE_PREFETCH
213 #ifdef RTE_PMD_USE_PREFETCH
215 * Prefetch a cache line into all cache levels.
217 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
219 #define rte_ixgbe_prefetch(p) do {} while(0)
222 #ifdef RTE_PMD_PACKET_PREFETCH
223 #define rte_packet_prefetch(p) rte_prefetch1(p)
225 #define rte_packet_prefetch(p) do {} while(0)
228 /*********************************************************************
232 **********************************************************************/
235 * The "simple" TX queue functions require that the following
236 * flags are set when the TX queue is configured:
237 * - ETH_TXQ_FLAGS_NOMULTSEGS
238 * - ETH_TXQ_FLAGS_NOVLANOFFL
239 * - ETH_TXQ_FLAGS_NOXSUMSCTP
240 * - ETH_TXQ_FLAGS_NOXSUMUDP
241 * - ETH_TXQ_FLAGS_NOXSUMTCP
242 * and that the RS bit threshold (tx_rs_thresh) is at least equal to
243 * RTE_PMD_IXGBE_TX_MAX_BURST.
245 #define IXGBE_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
246 ETH_TXQ_FLAGS_NOOFFLOADS)
249 * Check for descriptors with their DD bit set and free mbufs.
250 * Return the total number of buffers freed.
252 static inline int __attribute__((always_inline))
253 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
255 struct igb_tx_entry *txep;
259 /* check DD bit on threshold descriptor */
260 status = txq->tx_ring[txq->tx_next_dd].wb.status;
261 if (! (status & IXGBE_ADVTXD_STAT_DD))
265 * first buffer to free from S/W ring is at index
266 * tx_next_dd - (tx_rs_thresh-1)
268 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
270 /* prefetch the mbufs that are about to be freed */
271 for (i = 0; i < txq->tx_rs_thresh; ++i)
272 rte_prefetch0((txep + i)->mbuf);
274 /* free buffers one at a time */
275 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
276 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
277 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
281 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
282 rte_pktmbuf_free_seg(txep->mbuf);
287 /* buffers were freed, update counters */
288 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
289 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
290 if (txq->tx_next_dd >= txq->nb_tx_desc)
291 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
293 return txq->tx_rs_thresh;
297 * Populate descriptors with the following info:
298 * 1.) buffer_addr = phys_addr + headroom
299 * 2.) cmd_type_len = DCMD_DTYP_FLAGS | pkt_len
300 * 3.) olinfo_status = pkt_len << PAYLEN_SHIFT
303 /* Defines for Tx descriptor */
304 #define DCMD_DTYP_FLAGS (IXGBE_ADVTXD_DTYP_DATA |\
305 IXGBE_ADVTXD_DCMD_IFCS |\
306 IXGBE_ADVTXD_DCMD_DEXT |\
307 IXGBE_ADVTXD_DCMD_EOP)
309 /* Populate 4 descriptors with data from 4 mbufs */
311 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
313 uint64_t buf_dma_addr;
317 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
318 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
319 pkt_len = (*pkts)->pkt.data_len;
321 /* write data to descriptor */
322 txdp->read.buffer_addr = buf_dma_addr;
323 txdp->read.cmd_type_len =
324 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
325 txdp->read.olinfo_status =
326 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
330 /* Populate 1 descriptor with data from 1 mbuf */
332 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
334 uint64_t buf_dma_addr;
337 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
338 pkt_len = (*pkts)->pkt.data_len;
340 /* write data to descriptor */
341 txdp->read.buffer_addr = buf_dma_addr;
342 txdp->read.cmd_type_len =
343 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
344 txdp->read.olinfo_status =
345 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
349 * Fill H/W descriptor ring with mbuf data.
350 * Copy mbuf pointers to the S/W ring.
353 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
356 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
357 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
358 const int N_PER_LOOP = 4;
359 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
360 int mainpart, leftover;
364 * Process most of the packets in chunks of N pkts. Any
365 * leftover packets will get processed one at a time.
367 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
368 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
369 for (i = 0; i < mainpart; i += N_PER_LOOP) {
370 /* Copy N mbuf pointers to the S/W ring */
371 for (j = 0; j < N_PER_LOOP; ++j) {
372 (txep + i + j)->mbuf = *(pkts + i + j);
374 tx4(txdp + i, pkts + i);
377 if (unlikely(leftover > 0)) {
378 for (i = 0; i < leftover; ++i) {
379 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
380 tx1(txdp + mainpart + i, pkts + mainpart + i);
385 static inline uint16_t
386 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
389 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
390 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
394 * Begin scanning the H/W ring for done descriptors when the
395 * number of available descriptors drops below tx_free_thresh. For
396 * each done descriptor, free the associated buffer.
398 if (txq->nb_tx_free < txq->tx_free_thresh)
399 ixgbe_tx_free_bufs(txq);
401 /* Only use descriptors that are available */
402 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
403 if (unlikely(nb_pkts == 0))
406 /* Use exactly nb_pkts descriptors */
407 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
410 * At this point, we know there are enough descriptors in the
411 * ring to transmit all the packets. This assumes that each
412 * mbuf contains a single segment, and that no new offloads
413 * are expected, which would require a new context descriptor.
417 * See if we're going to wrap-around. If so, handle the top
418 * of the descriptor ring first, then do the bottom. If not,
419 * the processing looks just like the "bottom" part anyway...
421 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
422 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
423 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
426 * We know that the last descriptor in the ring will need to
427 * have its RS bit set because tx_rs_thresh has to be
428 * a divisor of the ring size
430 tx_r[txq->tx_next_rs].read.cmd_type_len |=
431 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
432 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
437 /* Fill H/W descriptor ring with mbuf data */
438 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
439 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
442 * Determine if RS bit should be set
443 * This is what we actually want:
444 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
445 * but instead of subtracting 1 and doing >=, we can just do
446 * greater than without subtracting.
448 if (txq->tx_tail > txq->tx_next_rs) {
449 tx_r[txq->tx_next_rs].read.cmd_type_len |=
450 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
451 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
453 if (txq->tx_next_rs >= txq->nb_tx_desc)
454 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
458 * Check for wrap-around. This would only happen if we used
459 * up to the last descriptor in the ring, no more, no less.
461 if (txq->tx_tail >= txq->nb_tx_desc)
464 /* update tail pointer */
466 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
472 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
477 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
478 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
479 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
481 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
485 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
486 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
487 nb_tx = (uint16_t)(nb_tx + ret);
488 nb_pkts = (uint16_t)(nb_pkts - ret);
497 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
498 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
499 uint16_t ol_flags, uint32_t vlan_macip_lens)
501 uint32_t type_tucmd_mlhl;
502 uint32_t mss_l4len_idx;
506 ctx_idx = txq->ctx_curr;
510 if (ol_flags & PKT_TX_VLAN_PKT) {
511 cmp_mask |= TX_VLAN_CMP_MASK;
514 if (ol_flags & PKT_TX_IP_CKSUM) {
515 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
516 cmp_mask |= TX_MAC_LEN_CMP_MASK;
519 /* Specify which HW CTX to upload. */
520 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
521 switch (ol_flags & PKT_TX_L4_MASK) {
522 case PKT_TX_UDP_CKSUM:
523 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
524 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
525 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
526 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
528 case PKT_TX_TCP_CKSUM:
529 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
530 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
531 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
532 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
534 case PKT_TX_SCTP_CKSUM:
535 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
536 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
537 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
538 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
541 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
542 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
546 txq->ctx_cache[ctx_idx].flags = ol_flags;
547 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
548 txq->ctx_cache[ctx_idx].vlan_macip_lens.data =
549 vlan_macip_lens & cmp_mask;
551 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
552 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
553 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
554 ctx_txd->seqnum_seed = 0;
558 * Check which hardware context can be used. Use the existing match
559 * or create a new context descriptor.
561 static inline uint32_t
562 what_advctx_update(struct igb_tx_queue *txq, uint16_t flags,
563 uint32_t vlan_macip_lens)
565 /* If match with the current used context */
566 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
567 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
568 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
569 return txq->ctx_curr;
572 /* What if match with the next context */
574 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
575 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
576 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
577 return txq->ctx_curr;
580 /* Mismatch, use the previous context */
581 return (IXGBE_CTX_NUM);
584 static inline uint32_t
585 tx_desc_cksum_flags_to_olinfo(uint16_t ol_flags)
587 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
588 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
591 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
592 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
596 static inline uint32_t
597 tx_desc_vlan_flags_to_cmdtype(uint16_t ol_flags)
599 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
600 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
603 /* Default RS bit threshold values */
604 #ifndef DEFAULT_TX_RS_THRESH
605 #define DEFAULT_TX_RS_THRESH 32
607 #ifndef DEFAULT_TX_FREE_THRESH
608 #define DEFAULT_TX_FREE_THRESH 32
611 /* Reset transmit descriptors after they have been used */
613 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
615 struct igb_tx_entry *sw_ring = txq->sw_ring;
616 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
617 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
618 uint16_t nb_tx_desc = txq->nb_tx_desc;
619 uint16_t desc_to_clean_to;
620 uint16_t nb_tx_to_clean;
622 /* Determine the last descriptor needing to be cleaned */
623 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
624 if (desc_to_clean_to >= nb_tx_desc)
625 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
627 /* Check to make sure the last descriptor to clean is done */
628 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
629 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
631 PMD_TX_FREE_LOG(DEBUG,
632 "TX descriptor %4u is not done"
633 "(port=%d queue=%d)",
635 txq->port_id, txq->queue_id);
636 /* Failed to clean any descriptors, better luck next time */
640 /* Figure out how many descriptors will be cleaned */
641 if (last_desc_cleaned > desc_to_clean_to)
642 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
645 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
648 PMD_TX_FREE_LOG(DEBUG,
649 "Cleaning %4u TX descriptors: %4u to %4u "
650 "(port=%d queue=%d)",
651 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
652 txq->port_id, txq->queue_id);
655 * The last descriptor to clean is done, so that means all the
656 * descriptors from the last descriptor that was cleaned
657 * up to the last descriptor with the RS bit set
658 * are done. Only reset the threshold descriptor.
660 txr[desc_to_clean_to].wb.status = 0;
662 /* Update the txq to reflect the last descriptor that was cleaned */
663 txq->last_desc_cleaned = desc_to_clean_to;
664 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
671 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
674 struct igb_tx_queue *txq;
675 struct igb_tx_entry *sw_ring;
676 struct igb_tx_entry *txe, *txn;
677 volatile union ixgbe_adv_tx_desc *txr;
678 volatile union ixgbe_adv_tx_desc *txd;
679 struct rte_mbuf *tx_pkt;
680 struct rte_mbuf *m_seg;
681 uint64_t buf_dma_addr;
682 uint32_t olinfo_status;
683 uint32_t cmd_type_len;
692 uint32_t vlan_macip_lens;
697 sw_ring = txq->sw_ring;
699 tx_id = txq->tx_tail;
700 txe = &sw_ring[tx_id];
702 /* Determine if the descriptor ring needs to be cleaned. */
703 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
704 ixgbe_xmit_cleanup(txq);
708 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
711 pkt_len = tx_pkt->pkt.pkt_len;
713 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
716 * Determine how many (if any) context descriptors
717 * are needed for offload functionality.
719 ol_flags = tx_pkt->ol_flags;
720 vlan_macip_lens = tx_pkt->pkt.vlan_macip.data;
722 /* If hardware offload required */
723 tx_ol_req = (uint16_t)(ol_flags & PKT_TX_OFFLOAD_MASK);
725 /* If new context need be built or reuse the exist ctx. */
726 ctx = what_advctx_update(txq, tx_ol_req,
728 /* Only allocate context descriptor if required*/
729 new_ctx = (ctx == IXGBE_CTX_NUM);
734 * Keep track of how many descriptors are used this loop
735 * This will always be the number of segments + the number of
736 * Context descriptors required to transmit the packet
738 nb_used = (uint16_t)(tx_pkt->pkt.nb_segs + new_ctx);
741 * The number of descriptors that must be allocated for a
742 * packet is the number of segments of that packet, plus 1
743 * Context Descriptor for the hardware offload, if any.
744 * Determine the last TX descriptor to allocate in the TX ring
745 * for the packet, starting from the current position (tx_id)
748 tx_last = (uint16_t) (tx_id + nb_used - 1);
751 if (tx_last >= txq->nb_tx_desc)
752 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
754 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
755 " tx_first=%u tx_last=%u\n",
756 (unsigned) txq->port_id,
757 (unsigned) txq->queue_id,
763 * Make sure there are enough TX descriptors available to
764 * transmit the entire packet.
765 * nb_used better be less than or equal to txq->tx_rs_thresh
767 if (nb_used > txq->nb_tx_free) {
768 PMD_TX_FREE_LOG(DEBUG,
769 "Not enough free TX descriptors "
770 "nb_used=%4u nb_free=%4u "
771 "(port=%d queue=%d)",
772 nb_used, txq->nb_tx_free,
773 txq->port_id, txq->queue_id);
775 if (ixgbe_xmit_cleanup(txq) != 0) {
776 /* Could not clean any descriptors */
782 /* nb_used better be <= txq->tx_rs_thresh */
783 if (unlikely(nb_used > txq->tx_rs_thresh)) {
784 PMD_TX_FREE_LOG(DEBUG,
785 "The number of descriptors needed to "
786 "transmit the packet exceeds the "
787 "RS bit threshold. This will impact "
789 "nb_used=%4u nb_free=%4u "
791 "(port=%d queue=%d)",
792 nb_used, txq->nb_tx_free,
794 txq->port_id, txq->queue_id);
796 * Loop here until there are enough TX
797 * descriptors or until the ring cannot be
800 while (nb_used > txq->nb_tx_free) {
801 if (ixgbe_xmit_cleanup(txq) != 0) {
803 * Could not clean any
815 * By now there are enough free TX descriptors to transmit
820 * Set common flags of all TX Data Descriptors.
822 * The following bits must be set in all Data Descriptors:
823 * - IXGBE_ADVTXD_DTYP_DATA
824 * - IXGBE_ADVTXD_DCMD_DEXT
826 * The following bits must be set in the first Data Descriptor
827 * and are ignored in the other ones:
828 * - IXGBE_ADVTXD_DCMD_IFCS
829 * - IXGBE_ADVTXD_MAC_1588
830 * - IXGBE_ADVTXD_DCMD_VLE
832 * The following bits must only be set in the last Data
834 * - IXGBE_TXD_CMD_EOP
836 * The following bits can be set in any Data Descriptor, but
837 * are only set in the last Data Descriptor:
840 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
841 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
842 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
843 #ifdef RTE_LIBRTE_IEEE1588
844 if (ol_flags & PKT_TX_IEEE1588_TMST)
845 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
850 * Setup the TX Advanced Context Descriptor if required
853 volatile struct ixgbe_adv_tx_context_desc *
856 ctx_txd = (volatile struct
857 ixgbe_adv_tx_context_desc *)
860 txn = &sw_ring[txe->next_id];
861 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
863 if (txe->mbuf != NULL) {
864 rte_pktmbuf_free_seg(txe->mbuf);
868 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
871 txe->last_id = tx_last;
872 tx_id = txe->next_id;
877 * Setup the TX Advanced Data Descriptor,
878 * This path will go through
879 * whatever new/reuse the context descriptor
881 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
882 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
883 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
889 txn = &sw_ring[txe->next_id];
891 if (txe->mbuf != NULL)
892 rte_pktmbuf_free_seg(txe->mbuf);
896 * Set up Transmit Data Descriptor.
898 slen = m_seg->pkt.data_len;
899 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
900 txd->read.buffer_addr =
901 rte_cpu_to_le_64(buf_dma_addr);
902 txd->read.cmd_type_len =
903 rte_cpu_to_le_32(cmd_type_len | slen);
904 txd->read.olinfo_status =
905 rte_cpu_to_le_32(olinfo_status);
906 txe->last_id = tx_last;
907 tx_id = txe->next_id;
909 m_seg = m_seg->pkt.next;
910 } while (m_seg != NULL);
913 * The last packet data descriptor needs End Of Packet (EOP)
915 cmd_type_len |= IXGBE_TXD_CMD_EOP;
916 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
917 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
919 /* Set RS bit only on threshold packets' last descriptor */
920 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
921 PMD_TX_FREE_LOG(DEBUG,
922 "Setting RS bit on TXD id="
923 "%4u (port=%d queue=%d)",
924 tx_last, txq->port_id, txq->queue_id);
926 cmd_type_len |= IXGBE_TXD_CMD_RS;
928 /* Update txq RS bit counters */
931 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
937 * Set the Transmit Descriptor Tail (TDT)
939 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
940 (unsigned) txq->port_id, (unsigned) txq->queue_id,
941 (unsigned) tx_id, (unsigned) nb_tx);
942 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
943 txq->tx_tail = tx_id;
948 /*********************************************************************
952 **********************************************************************/
953 static inline uint16_t
954 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
958 static uint16_t ip_pkt_types_map[16] = {
959 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
960 PKT_RX_IPV6_HDR, 0, 0, 0,
961 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
962 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
965 static uint16_t ip_rss_types_map[16] = {
966 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
967 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
968 PKT_RX_RSS_HASH, 0, 0, 0,
969 0, 0, 0, PKT_RX_FDIR,
972 #ifdef RTE_LIBRTE_IEEE1588
973 static uint32_t ip_pkt_etqf_map[8] = {
974 0, 0, 0, PKT_RX_IEEE1588_PTP,
978 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
979 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
980 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
982 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
983 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
986 return (uint16_t)(pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF]);
989 static inline uint16_t
990 rx_desc_status_to_pkt_flags(uint32_t rx_status)
995 * Check if VLAN present only.
996 * Do not check whether L3/L4 rx checksum done by NIC or not,
997 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
999 pkt_flags = (uint16_t)((rx_status & IXGBE_RXD_STAT_VP) ?
1000 PKT_RX_VLAN_PKT : 0);
1002 #ifdef RTE_LIBRTE_IEEE1588
1003 if (rx_status & IXGBE_RXD_STAT_TMST)
1004 pkt_flags = (uint16_t)(pkt_flags | PKT_RX_IEEE1588_TMST);
1009 static inline uint16_t
1010 rx_desc_error_to_pkt_flags(uint32_t rx_status)
1013 * Bit 31: IPE, IPv4 checksum error
1014 * Bit 30: L4I, L4I integrity error
1016 static uint16_t error_to_pkt_flags_map[4] = {
1017 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
1018 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1020 return error_to_pkt_flags_map[(rx_status >>
1021 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1024 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1026 * LOOK_AHEAD defines how many desc statuses to check beyond the
1027 * current descriptor.
1028 * It must be a pound define for optimal performance.
1029 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1030 * function only works with LOOK_AHEAD=8.
1032 #define LOOK_AHEAD 8
1033 #if (LOOK_AHEAD != 8)
1034 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1037 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
1039 volatile union ixgbe_adv_rx_desc *rxdp;
1040 struct igb_rx_entry *rxep;
1041 struct rte_mbuf *mb;
1043 int s[LOOK_AHEAD], nb_dd;
1044 int i, j, nb_rx = 0;
1047 /* get references to current descriptor and S/W ring entry */
1048 rxdp = &rxq->rx_ring[rxq->rx_tail];
1049 rxep = &rxq->sw_ring[rxq->rx_tail];
1051 /* check to make sure there is at least 1 packet to receive */
1052 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
1056 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1057 * reference packets that are ready to be received.
1059 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1060 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
1062 /* Read desc statuses backwards to avoid race condition */
1063 for (j = LOOK_AHEAD-1; j >= 0; --j)
1064 s[j] = rxdp[j].wb.upper.status_error;
1066 /* Clear everything but the status bits (LSB) */
1067 for (j = 0; j < LOOK_AHEAD; ++j)
1068 s[j] &= IXGBE_RXDADV_STAT_DD;
1070 /* Compute how many status bits were set */
1071 nb_dd = s[0]+s[1]+s[2]+s[3]+s[4]+s[5]+s[6]+s[7];
1074 /* Translate descriptor info to mbuf format */
1075 for (j = 0; j < nb_dd; ++j) {
1077 pkt_len = (uint16_t)(rxdp[j].wb.upper.length -
1079 mb->pkt.data_len = pkt_len;
1080 mb->pkt.pkt_len = pkt_len;
1081 mb->pkt.vlan_macip.f.vlan_tci = rxdp[j].wb.upper.vlan;
1082 mb->pkt.hash.rss = rxdp[j].wb.lower.hi_dword.rss;
1084 /* convert descriptor fields to rte mbuf flags */
1085 mb->ol_flags = rx_desc_hlen_type_rss_to_pkt_flags(
1086 rxdp[j].wb.lower.lo_dword.data);
1087 /* reuse status field from scan list */
1088 mb->ol_flags = (uint16_t)(mb->ol_flags |
1089 rx_desc_status_to_pkt_flags(s[j]));
1090 mb->ol_flags = (uint16_t)(mb->ol_flags |
1091 rx_desc_error_to_pkt_flags(s[j]));
1094 /* Move mbuf pointers from the S/W ring to the stage */
1095 for (j = 0; j < LOOK_AHEAD; ++j) {
1096 rxq->rx_stage[i + j] = rxep[j].mbuf;
1099 /* stop if all requested packets could not be received */
1100 if (nb_dd != LOOK_AHEAD)
1104 /* clear software ring entries so we can cleanup correctly */
1105 for (i = 0; i < nb_rx; ++i) {
1106 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1114 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
1116 volatile union ixgbe_adv_rx_desc *rxdp;
1117 struct igb_rx_entry *rxep;
1118 struct rte_mbuf *mb;
1123 /* allocate buffers in bulk directly into the S/W ring */
1124 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1125 (rxq->rx_free_thresh - 1));
1126 rxep = &rxq->sw_ring[alloc_idx];
1127 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1128 rxq->rx_free_thresh);
1129 if (unlikely(diag != 0))
1132 rxdp = &rxq->rx_ring[alloc_idx];
1133 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1134 /* populate the static rte mbuf fields */
1136 rte_mbuf_refcnt_set(mb, 1);
1137 mb->type = RTE_MBUF_PKT;
1138 mb->pkt.next = NULL;
1139 mb->pkt.data = (char *)mb->buf_addr + RTE_PKTMBUF_HEADROOM;
1140 mb->pkt.nb_segs = 1;
1141 mb->pkt.in_port = rxq->port_id;
1143 /* populate the descriptors */
1144 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1145 rxdp[i].read.hdr_addr = dma_addr;
1146 rxdp[i].read.pkt_addr = dma_addr;
1149 /* update tail pointer */
1151 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1153 /* update state of internal queue structure */
1154 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1155 rxq->rx_free_thresh);
1156 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1157 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1163 static inline uint16_t
1164 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1167 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1170 /* how many packets are ready to return? */
1171 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1173 /* copy mbuf pointers to the application's packet list */
1174 for (i = 0; i < nb_pkts; ++i)
1175 rx_pkts[i] = stage[i];
1177 /* update internal queue state */
1178 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1179 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1184 static inline uint16_t
1185 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1188 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1191 /* Any previously recv'd pkts will be returned from the Rx stage */
1192 if (rxq->rx_nb_avail)
1193 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1195 /* Scan the H/W ring for packets to receive */
1196 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1198 /* update internal queue state */
1199 rxq->rx_next_avail = 0;
1200 rxq->rx_nb_avail = nb_rx;
1201 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1203 /* if required, allocate new buffers to replenish descriptors */
1204 if (rxq->rx_tail > rxq->rx_free_trigger) {
1205 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1207 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1208 "queue_id=%u\n", (unsigned) rxq->port_id,
1209 (unsigned) rxq->queue_id);
1211 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1212 rxq->rx_free_thresh;
1215 * Need to rewind any previous receives if we cannot
1216 * allocate new buffers to replenish the old ones.
1218 rxq->rx_nb_avail = 0;
1219 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1220 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1221 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1227 if (rxq->rx_tail >= rxq->nb_rx_desc)
1230 /* received any packets this loop? */
1231 if (rxq->rx_nb_avail)
1232 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1237 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1239 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1244 if (unlikely(nb_pkts == 0))
1247 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1248 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1250 /* request is relatively large, chunk it up */
1254 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1255 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1256 nb_rx = (uint16_t)(nb_rx + ret);
1257 nb_pkts = (uint16_t)(nb_pkts - ret);
1264 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1267 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1270 struct igb_rx_queue *rxq;
1271 volatile union ixgbe_adv_rx_desc *rx_ring;
1272 volatile union ixgbe_adv_rx_desc *rxdp;
1273 struct igb_rx_entry *sw_ring;
1274 struct igb_rx_entry *rxe;
1275 struct rte_mbuf *rxm;
1276 struct rte_mbuf *nmb;
1277 union ixgbe_adv_rx_desc rxd;
1280 uint32_t hlen_type_rss;
1290 rx_id = rxq->rx_tail;
1291 rx_ring = rxq->rx_ring;
1292 sw_ring = rxq->sw_ring;
1293 while (nb_rx < nb_pkts) {
1295 * The order of operations here is important as the DD status
1296 * bit must not be read after any other descriptor fields.
1297 * rx_ring and rxdp are pointing to volatile data so the order
1298 * of accesses cannot be reordered by the compiler. If they were
1299 * not volatile, they could be reordered which could lead to
1300 * using invalid descriptor fields when read from rxd.
1302 rxdp = &rx_ring[rx_id];
1303 staterr = rxdp->wb.upper.status_error;
1304 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1311 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1312 * is likely to be invalid and to be dropped by the various
1313 * validation checks performed by the network stack.
1315 * Allocate a new mbuf to replenish the RX ring descriptor.
1316 * If the allocation fails:
1317 * - arrange for that RX descriptor to be the first one
1318 * being parsed the next time the receive function is
1319 * invoked [on the same queue].
1321 * - Stop parsing the RX ring and return immediately.
1323 * This policy do not drop the packet received in the RX
1324 * descriptor for which the allocation of a new mbuf failed.
1325 * Thus, it allows that packet to be later retrieved if
1326 * mbuf have been freed in the mean time.
1327 * As a side effect, holding RX descriptors instead of
1328 * systematically giving them back to the NIC may lead to
1329 * RX ring exhaustion situations.
1330 * However, the NIC can gracefully prevent such situations
1331 * to happen by sending specific "back-pressure" flow control
1332 * frames to its peer(s).
1334 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1335 "ext_err_stat=0x%08x pkt_len=%u\n",
1336 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1337 (unsigned) rx_id, (unsigned) staterr,
1338 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1340 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1342 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1343 "queue_id=%u\n", (unsigned) rxq->port_id,
1344 (unsigned) rxq->queue_id);
1345 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1350 rxe = &sw_ring[rx_id];
1352 if (rx_id == rxq->nb_rx_desc)
1355 /* Prefetch next mbuf while processing current one. */
1356 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1359 * When next RX descriptor is on a cache-line boundary,
1360 * prefetch the next 4 RX descriptors and the next 8 pointers
1363 if ((rx_id & 0x3) == 0) {
1364 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1365 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1371 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1372 rxdp->read.hdr_addr = dma_addr;
1373 rxdp->read.pkt_addr = dma_addr;
1376 * Initialize the returned mbuf.
1377 * 1) setup generic mbuf fields:
1378 * - number of segments,
1381 * - RX port identifier.
1382 * 2) integrate hardware offload data, if any:
1383 * - RSS flag & hash,
1384 * - IP checksum flag,
1385 * - VLAN TCI, if any,
1388 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1390 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1391 rte_packet_prefetch(rxm->pkt.data);
1392 rxm->pkt.nb_segs = 1;
1393 rxm->pkt.next = NULL;
1394 rxm->pkt.pkt_len = pkt_len;
1395 rxm->pkt.data_len = pkt_len;
1396 rxm->pkt.in_port = rxq->port_id;
1398 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1399 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1400 rxm->pkt.vlan_macip.f.vlan_tci =
1401 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1403 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1404 pkt_flags = (uint16_t)(pkt_flags |
1405 rx_desc_status_to_pkt_flags(staterr));
1406 pkt_flags = (uint16_t)(pkt_flags |
1407 rx_desc_error_to_pkt_flags(staterr));
1408 rxm->ol_flags = pkt_flags;
1410 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1411 rxm->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1412 else if (pkt_flags & PKT_RX_FDIR) {
1413 rxm->pkt.hash.fdir.hash =
1414 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1415 & IXGBE_ATR_HASH_MASK);
1416 rxm->pkt.hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1419 * Store the mbuf address into the next entry of the array
1420 * of returned packets.
1422 rx_pkts[nb_rx++] = rxm;
1424 rxq->rx_tail = rx_id;
1427 * If the number of free RX descriptors is greater than the RX free
1428 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1430 * Update the RDT with the value of the last processed RX descriptor
1431 * minus 1, to guarantee that the RDT register is never equal to the
1432 * RDH register, which creates a "full" ring situtation from the
1433 * hardware point of view...
1435 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1436 if (nb_hold > rxq->rx_free_thresh) {
1437 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1438 "nb_hold=%u nb_rx=%u\n",
1439 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1440 (unsigned) rx_id, (unsigned) nb_hold,
1442 rx_id = (uint16_t) ((rx_id == 0) ?
1443 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1444 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1447 rxq->nb_rx_hold = nb_hold;
1452 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1455 struct igb_rx_queue *rxq;
1456 volatile union ixgbe_adv_rx_desc *rx_ring;
1457 volatile union ixgbe_adv_rx_desc *rxdp;
1458 struct igb_rx_entry *sw_ring;
1459 struct igb_rx_entry *rxe;
1460 struct rte_mbuf *first_seg;
1461 struct rte_mbuf *last_seg;
1462 struct rte_mbuf *rxm;
1463 struct rte_mbuf *nmb;
1464 union ixgbe_adv_rx_desc rxd;
1465 uint64_t dma; /* Physical address of mbuf data buffer */
1467 uint32_t hlen_type_rss;
1477 rx_id = rxq->rx_tail;
1478 rx_ring = rxq->rx_ring;
1479 sw_ring = rxq->sw_ring;
1482 * Retrieve RX context of current packet, if any.
1484 first_seg = rxq->pkt_first_seg;
1485 last_seg = rxq->pkt_last_seg;
1487 while (nb_rx < nb_pkts) {
1490 * The order of operations here is important as the DD status
1491 * bit must not be read after any other descriptor fields.
1492 * rx_ring and rxdp are pointing to volatile data so the order
1493 * of accesses cannot be reordered by the compiler. If they were
1494 * not volatile, they could be reordered which could lead to
1495 * using invalid descriptor fields when read from rxd.
1497 rxdp = &rx_ring[rx_id];
1498 staterr = rxdp->wb.upper.status_error;
1499 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1506 * Allocate a new mbuf to replenish the RX ring descriptor.
1507 * If the allocation fails:
1508 * - arrange for that RX descriptor to be the first one
1509 * being parsed the next time the receive function is
1510 * invoked [on the same queue].
1512 * - Stop parsing the RX ring and return immediately.
1514 * This policy does not drop the packet received in the RX
1515 * descriptor for which the allocation of a new mbuf failed.
1516 * Thus, it allows that packet to be later retrieved if
1517 * mbuf have been freed in the mean time.
1518 * As a side effect, holding RX descriptors instead of
1519 * systematically giving them back to the NIC may lead to
1520 * RX ring exhaustion situations.
1521 * However, the NIC can gracefully prevent such situations
1522 * to happen by sending specific "back-pressure" flow control
1523 * frames to its peer(s).
1525 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
1526 "staterr=0x%x data_len=%u\n",
1527 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1528 (unsigned) rx_id, (unsigned) staterr,
1529 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1531 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1533 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1534 "queue_id=%u\n", (unsigned) rxq->port_id,
1535 (unsigned) rxq->queue_id);
1536 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1541 rxe = &sw_ring[rx_id];
1543 if (rx_id == rxq->nb_rx_desc)
1546 /* Prefetch next mbuf while processing current one. */
1547 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1550 * When next RX descriptor is on a cache-line boundary,
1551 * prefetch the next 4 RX descriptors and the next 8 pointers
1554 if ((rx_id & 0x3) == 0) {
1555 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1556 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1560 * Update RX descriptor with the physical address of the new
1561 * data buffer of the new allocated mbuf.
1565 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1566 rxdp->read.hdr_addr = dma;
1567 rxdp->read.pkt_addr = dma;
1570 * Set data length & data buffer address of mbuf.
1572 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1573 rxm->pkt.data_len = data_len;
1574 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1577 * If this is the first buffer of the received packet,
1578 * set the pointer to the first mbuf of the packet and
1579 * initialize its context.
1580 * Otherwise, update the total length and the number of segments
1581 * of the current scattered packet, and update the pointer to
1582 * the last mbuf of the current packet.
1584 if (first_seg == NULL) {
1586 first_seg->pkt.pkt_len = data_len;
1587 first_seg->pkt.nb_segs = 1;
1589 first_seg->pkt.pkt_len = (uint16_t)(first_seg->pkt.pkt_len
1591 first_seg->pkt.nb_segs++;
1592 last_seg->pkt.next = rxm;
1596 * If this is not the last buffer of the received packet,
1597 * update the pointer to the last mbuf of the current scattered
1598 * packet and continue to parse the RX ring.
1600 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1606 * This is the last buffer of the received packet.
1607 * If the CRC is not stripped by the hardware:
1608 * - Subtract the CRC length from the total packet length.
1609 * - If the last buffer only contains the whole CRC or a part
1610 * of it, free the mbuf associated to the last buffer.
1611 * If part of the CRC is also contained in the previous
1612 * mbuf, subtract the length of that CRC part from the
1613 * data length of the previous mbuf.
1615 rxm->pkt.next = NULL;
1616 if (unlikely(rxq->crc_len > 0)) {
1617 first_seg->pkt.pkt_len -= ETHER_CRC_LEN;
1618 if (data_len <= ETHER_CRC_LEN) {
1619 rte_pktmbuf_free_seg(rxm);
1620 first_seg->pkt.nb_segs--;
1621 last_seg->pkt.data_len = (uint16_t)
1622 (last_seg->pkt.data_len -
1623 (ETHER_CRC_LEN - data_len));
1624 last_seg->pkt.next = NULL;
1627 (uint16_t) (data_len - ETHER_CRC_LEN);
1631 * Initialize the first mbuf of the returned packet:
1632 * - RX port identifier,
1633 * - hardware offload data, if any:
1634 * - RSS flag & hash,
1635 * - IP checksum flag,
1636 * - VLAN TCI, if any,
1639 first_seg->pkt.in_port = rxq->port_id;
1642 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1643 * set in the pkt_flags field.
1645 first_seg->pkt.vlan_macip.f.vlan_tci =
1646 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1647 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1648 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1649 pkt_flags = (uint16_t)(pkt_flags |
1650 rx_desc_status_to_pkt_flags(staterr));
1651 pkt_flags = (uint16_t)(pkt_flags |
1652 rx_desc_error_to_pkt_flags(staterr));
1653 first_seg->ol_flags = pkt_flags;
1655 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1656 first_seg->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1657 else if (pkt_flags & PKT_RX_FDIR) {
1658 first_seg->pkt.hash.fdir.hash =
1659 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1660 & IXGBE_ATR_HASH_MASK);
1661 first_seg->pkt.hash.fdir.id =
1662 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1665 /* Prefetch data of first segment, if configured to do so. */
1666 rte_packet_prefetch(first_seg->pkt.data);
1669 * Store the mbuf address into the next entry of the array
1670 * of returned packets.
1672 rx_pkts[nb_rx++] = first_seg;
1675 * Setup receipt context for a new packet.
1681 * Record index of the next RX descriptor to probe.
1683 rxq->rx_tail = rx_id;
1686 * Save receive context.
1688 rxq->pkt_first_seg = first_seg;
1689 rxq->pkt_last_seg = last_seg;
1692 * If the number of free RX descriptors is greater than the RX free
1693 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1695 * Update the RDT with the value of the last processed RX descriptor
1696 * minus 1, to guarantee that the RDT register is never equal to the
1697 * RDH register, which creates a "full" ring situtation from the
1698 * hardware point of view...
1700 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1701 if (nb_hold > rxq->rx_free_thresh) {
1702 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1703 "nb_hold=%u nb_rx=%u\n",
1704 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1705 (unsigned) rx_id, (unsigned) nb_hold,
1707 rx_id = (uint16_t) ((rx_id == 0) ?
1708 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1709 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1712 rxq->nb_rx_hold = nb_hold;
1716 /*********************************************************************
1718 * Queue management functions
1720 **********************************************************************/
1723 * Rings setup and release.
1725 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1726 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1727 * also optimize cache line size effect. H/W supports up to cache line size 128.
1729 #define IXGBE_ALIGN 128
1732 * Maximum number of Ring Descriptors.
1734 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1735 * descriptors should meet the following condition:
1736 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1738 #define IXGBE_MIN_RING_DESC 64
1739 #define IXGBE_MAX_RING_DESC 4096
1742 * Create memzone for HW rings. malloc can't be used as the physical address is
1743 * needed. If the memzone is already created, then this function returns a ptr
1746 static const struct rte_memzone *
1747 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1748 uint16_t queue_id, uint32_t ring_size, int socket_id)
1750 char z_name[RTE_MEMZONE_NAMESIZE];
1751 const struct rte_memzone *mz;
1753 rte_snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1754 dev->driver->pci_drv.name, ring_name,
1755 dev->data->port_id, queue_id);
1757 mz = rte_memzone_lookup(z_name);
1761 #ifdef RTE_LIBRTE_XEN_DOM0
1762 return rte_memzone_reserve_bounded(z_name, ring_size,
1763 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1765 return rte_memzone_reserve_aligned(z_name, ring_size,
1766 socket_id, 0, IXGBE_ALIGN);
1771 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1775 if (txq->sw_ring != NULL) {
1776 for (i = 0; i < txq->nb_tx_desc; i++) {
1777 if (txq->sw_ring[i].mbuf != NULL) {
1778 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1779 txq->sw_ring[i].mbuf = NULL;
1786 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1789 ixgbe_tx_queue_release_mbufs(txq);
1790 rte_free(txq->sw_ring);
1796 ixgbe_dev_tx_queue_release(void *txq)
1798 ixgbe_tx_queue_release(txq);
1801 /* (Re)set dynamic igb_tx_queue fields to defaults */
1803 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1805 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1807 struct igb_tx_entry *txe = txq->sw_ring;
1810 /* Zero out HW ring memory */
1811 for (i = 0; i < txq->nb_tx_desc; i++) {
1812 txq->tx_ring[i] = zeroed_desc;
1815 /* Initialize SW ring entries */
1816 prev = (uint16_t) (txq->nb_tx_desc - 1);
1817 for (i = 0; i < txq->nb_tx_desc; i++) {
1818 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1819 txd->wb.status = IXGBE_TXD_STAT_DD;
1821 txe[i].last_id = (uint16_t)i;
1822 txe[prev].next_id = (uint16_t)i;
1826 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1827 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1830 txq->nb_tx_used = 0;
1832 * Always allow 1 descriptor to be un-allocated to avoid
1833 * a H/W race condition
1835 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1836 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1838 memset((void*)&txq->ctx_cache, 0,
1839 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1843 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1846 unsigned int socket_id,
1847 const struct rte_eth_txconf *tx_conf)
1849 const struct rte_memzone *tz;
1850 struct igb_tx_queue *txq;
1851 struct ixgbe_hw *hw;
1852 uint16_t tx_rs_thresh, tx_free_thresh;
1854 PMD_INIT_FUNC_TRACE();
1855 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858 * Validate number of transmit descriptors.
1859 * It must not exceed hardware maximum, and must be multiple
1862 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1863 (nb_desc > IXGBE_MAX_RING_DESC) ||
1864 (nb_desc < IXGBE_MIN_RING_DESC)) {
1869 * The following two parameters control the setting of the RS bit on
1870 * transmit descriptors.
1871 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1872 * descriptors have been used.
1873 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1874 * descriptors are used or if the number of descriptors required
1875 * to transmit a packet is greater than the number of free TX
1877 * The following constraints must be satisfied:
1878 * tx_rs_thresh must be greater than 0.
1879 * tx_rs_thresh must be less than the size of the ring minus 2.
1880 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1881 * tx_rs_thresh must be a divisor of the ring size.
1882 * tx_free_thresh must be greater than 0.
1883 * tx_free_thresh must be less than the size of the ring minus 3.
1884 * One descriptor in the TX ring is used as a sentinel to avoid a
1885 * H/W race condition, hence the maximum threshold constraints.
1886 * When set to zero use default values.
1888 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1889 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1890 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1891 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1892 if (tx_rs_thresh >= (nb_desc - 2)) {
1893 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the number "
1894 "of TX descriptors minus 2. (tx_rs_thresh=%u port=%d "
1895 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1896 (int)dev->data->port_id, (int)queue_idx);
1899 if (tx_free_thresh >= (nb_desc - 3)) {
1900 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the "
1901 "tx_free_thresh must be less than the number of TX "
1902 "descriptors minus 3. (tx_free_thresh=%u port=%d "
1903 "queue=%d)\n", (unsigned int)tx_free_thresh,
1904 (int)dev->data->port_id, (int)queue_idx);
1907 if (tx_rs_thresh > tx_free_thresh) {
1908 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than or equal to "
1909 "tx_free_thresh. (tx_free_thresh=%u tx_rs_thresh=%u "
1910 "port=%d queue=%d)\n", (unsigned int)tx_free_thresh,
1911 (unsigned int)tx_rs_thresh, (int)dev->data->port_id,
1915 if ((nb_desc % tx_rs_thresh) != 0) {
1916 RTE_LOG(ERR, PMD, "tx_rs_thresh must be a divisor of the "
1917 "number of TX descriptors. (tx_rs_thresh=%u port=%d "
1918 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1919 (int)dev->data->port_id, (int)queue_idx);
1924 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1925 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1926 * by the NIC and all descriptors are written back after the NIC
1927 * accumulates WTHRESH descriptors.
1929 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1930 RTE_LOG(ERR, PMD, "TX WTHRESH must be set to 0 if "
1931 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1932 "port=%d queue=%d)\n", (unsigned int)tx_rs_thresh,
1933 (int)dev->data->port_id, (int)queue_idx);
1937 /* Free memory prior to re-allocation if needed... */
1938 if (dev->data->tx_queues[queue_idx] != NULL)
1939 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1941 /* First allocate the tx queue data structure */
1942 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct igb_tx_queue),
1943 CACHE_LINE_SIZE, socket_id);
1948 * Allocate TX ring hardware descriptors. A memzone large enough to
1949 * handle the maximum ring size is allocated in order to allow for
1950 * resizing in later calls to the queue setup function.
1952 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1953 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1956 ixgbe_tx_queue_release(txq);
1960 txq->nb_tx_desc = nb_desc;
1961 txq->tx_rs_thresh = tx_rs_thresh;
1962 txq->tx_free_thresh = tx_free_thresh;
1963 txq->pthresh = tx_conf->tx_thresh.pthresh;
1964 txq->hthresh = tx_conf->tx_thresh.hthresh;
1965 txq->wthresh = tx_conf->tx_thresh.wthresh;
1966 txq->queue_id = queue_idx;
1967 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1968 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1969 txq->port_id = dev->data->port_id;
1970 txq->txq_flags = tx_conf->txq_flags;
1973 * Modification to set VFTDT for virtual function if vf is detected
1975 if (hw->mac.type == ixgbe_mac_82599_vf)
1976 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1978 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1979 #ifndef RTE_LIBRTE_XEN_DOM0
1980 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1982 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1984 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1986 /* Allocate software ring */
1987 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1988 sizeof(struct igb_tx_entry) * nb_desc,
1989 CACHE_LINE_SIZE, socket_id);
1990 if (txq->sw_ring == NULL) {
1991 ixgbe_tx_queue_release(txq);
1994 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1995 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1997 ixgbe_reset_tx_queue(txq);
1999 dev->data->tx_queues[queue_idx] = txq;
2001 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2002 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
2003 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
2004 PMD_INIT_LOG(INFO, "Using simple tx code path\n");
2005 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
2007 PMD_INIT_LOG(INFO, "Using full-featured tx code path\n");
2008 PMD_INIT_LOG(INFO, " - txq_flags = %lx [IXGBE_SIMPLE_FLAGS=%lx]\n", (long unsigned)txq->txq_flags, (long unsigned)IXGBE_SIMPLE_FLAGS);
2009 PMD_INIT_LOG(INFO, " - tx_rs_thresh = %lu [RTE_PMD_IXGBE_TX_MAX_BURST=%lu]\n", (long unsigned)txq->tx_rs_thresh, (long unsigned)RTE_PMD_IXGBE_TX_MAX_BURST);
2010 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2017 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
2021 if (rxq->sw_ring != NULL) {
2022 for (i = 0; i < rxq->nb_rx_desc; i++) {
2023 if (rxq->sw_ring[i].mbuf != NULL) {
2024 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2025 rxq->sw_ring[i].mbuf = NULL;
2028 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2029 if (rxq->rx_nb_avail) {
2030 for (i = 0; i < rxq->rx_nb_avail; ++i) {
2031 struct rte_mbuf *mb;
2032 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2033 rte_pktmbuf_free_seg(mb);
2035 rxq->rx_nb_avail = 0;
2042 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
2045 ixgbe_rx_queue_release_mbufs(rxq);
2046 rte_free(rxq->sw_ring);
2052 ixgbe_dev_rx_queue_release(void *rxq)
2054 ixgbe_rx_queue_release(rxq);
2058 * Check if Rx Burst Bulk Alloc function can be used.
2060 * 0: the preconditions are satisfied and the bulk allocation function
2062 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2063 * function must be used.
2066 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2067 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
2069 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct igb_rx_queue *rxq)
2075 * Make sure the following pre-conditions are satisfied:
2076 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2077 * rxq->rx_free_thresh < rxq->nb_rx_desc
2078 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2079 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2080 * Scattered packets are not supported. This should be checked
2081 * outside of this function.
2083 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2084 if (! (rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST))
2086 else if (! (rxq->rx_free_thresh < rxq->nb_rx_desc))
2088 else if (! ((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0))
2090 else if (! (rxq->nb_rx_desc <
2091 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST)))
2100 /* Reset dynamic igb_rx_queue fields back to defaults */
2102 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
2104 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
2110 * By default, the Rx queue setup function allocates enough memory for
2111 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2112 * extra memory at the end of the descriptor ring to be zero'd out. A
2113 * pre-condition for using the Rx burst bulk alloc function is that the
2114 * number of descriptors is less than or equal to
2115 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2116 * constraints here to see if we need to zero out memory after the end
2117 * of the H/W descriptor ring.
2119 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2120 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2121 /* zero out extra memory */
2122 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2125 /* do not zero out extra memory */
2126 len = rxq->nb_rx_desc;
2129 * Zero out HW ring memory. Zero out extra memory at the end of
2130 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2131 * reads extra memory as zeros.
2133 for (i = 0; i < len; i++) {
2134 rxq->rx_ring[i] = zeroed_desc;
2137 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2139 * initialize extra software ring entries. Space for these extra
2140 * entries is always allocated
2142 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2143 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2144 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2147 rxq->rx_nb_avail = 0;
2148 rxq->rx_next_avail = 0;
2149 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2150 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2152 rxq->nb_rx_hold = 0;
2153 rxq->pkt_first_seg = NULL;
2154 rxq->pkt_last_seg = NULL;
2158 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2161 unsigned int socket_id,
2162 const struct rte_eth_rxconf *rx_conf,
2163 struct rte_mempool *mp)
2165 const struct rte_memzone *rz;
2166 struct igb_rx_queue *rxq;
2167 struct ixgbe_hw *hw;
2168 int use_def_burst_func = 1;
2171 PMD_INIT_FUNC_TRACE();
2172 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2175 * Validate number of receive descriptors.
2176 * It must not exceed hardware maximum, and must be multiple
2179 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2180 (nb_desc > IXGBE_MAX_RING_DESC) ||
2181 (nb_desc < IXGBE_MIN_RING_DESC)) {
2185 /* Free memory prior to re-allocation if needed... */
2186 if (dev->data->rx_queues[queue_idx] != NULL)
2187 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2189 /* First allocate the rx queue data structure */
2190 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct igb_rx_queue),
2191 CACHE_LINE_SIZE, socket_id);
2195 rxq->nb_rx_desc = nb_desc;
2196 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2197 rxq->queue_id = queue_idx;
2198 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2199 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2200 rxq->port_id = dev->data->port_id;
2201 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2203 rxq->drop_en = rx_conf->rx_drop_en;
2206 * Allocate RX ring hardware descriptors. A memzone large enough to
2207 * handle the maximum ring size is allocated in order to allow for
2208 * resizing in later calls to the queue setup function.
2210 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2211 IXGBE_MAX_RING_DESC * sizeof(union ixgbe_adv_rx_desc),
2214 ixgbe_rx_queue_release(rxq);
2218 * Modified to setup VFRDT for Virtual Function
2220 if (hw->mac.type == ixgbe_mac_82599_vf) {
2222 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2224 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2228 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2230 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2232 #ifndef RTE_LIBRTE_XEN_DOM0
2233 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2235 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2237 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2240 * Allocate software ring. Allow for space at the end of the
2241 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2242 * function does not access an invalid memory region.
2244 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2245 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2249 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2250 sizeof(struct igb_rx_entry) * len,
2251 CACHE_LINE_SIZE, socket_id);
2252 if (rxq->sw_ring == NULL) {
2253 ixgbe_rx_queue_release(rxq);
2256 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
2257 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2260 * Certain constaints must be met in order to use the bulk buffer
2261 * allocation Rx burst function.
2263 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2265 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2266 if (!use_def_burst_func && !dev->data->scattered_rx) {
2267 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2268 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2269 "satisfied. Rx Burst Bulk Alloc function will be "
2270 "used on port=%d, queue=%d.\n",
2271 rxq->port_id, rxq->queue_id);
2272 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2275 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2276 "are not satisfied, Scattered Rx is requested, "
2277 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2278 "enabled (port=%d, queue=%d).\n",
2279 rxq->port_id, rxq->queue_id);
2281 dev->data->rx_queues[queue_idx] = rxq;
2283 ixgbe_reset_rx_queue(rxq);
2289 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2291 #define IXGBE_RXQ_SCAN_INTERVAL 4
2292 volatile union ixgbe_adv_rx_desc *rxdp;
2293 struct igb_rx_queue *rxq;
2296 if (rx_queue_id >= dev->data->nb_rx_queues) {
2297 PMD_RX_LOG(ERR, "Invalid RX queue id=%d\n", rx_queue_id);
2301 rxq = dev->data->rx_queues[rx_queue_id];
2302 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2304 while ((desc < rxq->nb_rx_desc) &&
2305 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2306 desc += IXGBE_RXQ_SCAN_INTERVAL;
2307 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2308 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2309 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2310 desc - rxq->nb_rx_desc]);
2317 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2319 volatile union ixgbe_adv_rx_desc *rxdp;
2320 struct igb_rx_queue *rxq = rx_queue;
2323 if (unlikely(offset >= rxq->nb_rx_desc))
2325 desc = rxq->rx_tail + offset;
2326 if (desc >= rxq->nb_rx_desc)
2327 desc -= rxq->nb_rx_desc;
2329 rxdp = &rxq->rx_ring[desc];
2330 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2334 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2338 PMD_INIT_FUNC_TRACE();
2340 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2341 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2343 ixgbe_tx_queue_release_mbufs(txq);
2344 ixgbe_reset_tx_queue(txq);
2348 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2349 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2351 ixgbe_rx_queue_release_mbufs(rxq);
2352 ixgbe_reset_rx_queue(rxq);
2357 /*********************************************************************
2359 * Device RX/TX init functions
2361 **********************************************************************/
2364 * Receive Side Scaling (RSS)
2365 * See section 7.1.2.8 in the following document:
2366 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2369 * The source and destination IP addresses of the IP header and the source
2370 * and destination ports of TCP/UDP headers, if any, of received packets are
2371 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2372 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2373 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2374 * RSS output index which is used as the RX queue index where to store the
2376 * The following output is supplied in the RX write-back descriptor:
2377 * - 32-bit result of the Microsoft RSS hash function,
2378 * - 4-bit RSS type field.
2382 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2383 * Used as the default key.
2385 static uint8_t rss_intel_key[40] = {
2386 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2387 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2388 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2389 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2390 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2394 ixgbe_rss_disable(struct rte_eth_dev *dev)
2396 struct ixgbe_hw *hw;
2399 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2400 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2401 mrqc &= ~IXGBE_MRQC_RSSEN;
2402 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2406 ixgbe_rss_configure(struct rte_eth_dev *dev)
2408 struct ixgbe_hw *hw;
2417 PMD_INIT_FUNC_TRACE();
2418 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2420 rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
2421 if (rss_hf == 0) { /* Disable RSS */
2422 ixgbe_rss_disable(dev);
2425 hash_key = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key;
2426 if (hash_key == NULL)
2427 hash_key = rss_intel_key; /* Default hash key */
2429 /* Fill in RSS hash key */
2430 for (i = 0; i < 10; i++) {
2431 rss_key = hash_key[(i * 4)];
2432 rss_key |= hash_key[(i * 4) + 1] << 8;
2433 rss_key |= hash_key[(i * 4) + 2] << 16;
2434 rss_key |= hash_key[(i * 4) + 3] << 24;
2435 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2438 /* Fill in redirection table */
2440 for (i = 0, j = 0; i < 128; i++, j++) {
2441 if (j == dev->data->nb_rx_queues) j = 0;
2442 reta = (reta << 8) | j;
2444 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), rte_bswap32(reta));
2447 /* Set configured hashing functions in MRQC register */
2448 mrqc = IXGBE_MRQC_RSSEN; /* RSS enable */
2449 if (rss_hf & ETH_RSS_IPV4)
2450 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2451 if (rss_hf & ETH_RSS_IPV4_TCP)
2452 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2453 if (rss_hf & ETH_RSS_IPV6)
2454 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2455 if (rss_hf & ETH_RSS_IPV6_EX)
2456 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2457 if (rss_hf & ETH_RSS_IPV6_TCP)
2458 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2459 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2460 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2461 if (rss_hf & ETH_RSS_IPV4_UDP)
2462 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2463 if (rss_hf & ETH_RSS_IPV6_UDP)
2464 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2465 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2466 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2467 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2470 #define NUM_VFTA_REGISTERS 128
2471 #define NIC_RX_BUFFER_SIZE 0x200
2474 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2476 struct rte_eth_vmdq_dcb_conf *cfg;
2477 struct ixgbe_hw *hw;
2478 enum rte_eth_nb_pools num_pools;
2479 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2481 uint8_t nb_tcs; /* number of traffic classes */
2484 PMD_INIT_FUNC_TRACE();
2485 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2487 num_pools = cfg->nb_queue_pools;
2488 /* Check we have a valid number of pools */
2489 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2490 ixgbe_rss_disable(dev);
2493 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2494 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2498 * split rx buffer up into sections, each for 1 traffic class
2500 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2501 for (i = 0 ; i < nb_tcs; i++) {
2502 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2503 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2504 /* clear 10 bits. */
2505 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2506 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2508 /* zero alloc all unused TCs */
2509 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2510 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2511 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2512 /* clear 10 bits. */
2513 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2516 /* MRQC: enable vmdq and dcb */
2517 mrqc = ((num_pools == ETH_16_POOLS) ? \
2518 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2519 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2521 /* PFVTCTL: turn on virtualisation and set the default pool */
2522 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2523 if (cfg->enable_default_pool) {
2524 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2526 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2529 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2531 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2533 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2535 * mapping is done with 3 bits per priority,
2536 * so shift by i*3 each time
2538 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2540 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2542 /* RTRPCS: DCB related */
2543 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2545 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2546 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2547 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2548 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2550 /* VFTA - enable all vlan filters */
2551 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2552 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2555 /* VFRE: pool enabling for receive - 16 or 32 */
2556 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2557 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2560 * MPSAR - allow pools to read specific mac addresses
2561 * In this case, all pools should be able to read from mac addr 0
2563 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2564 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2566 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2567 for (i = 0; i < cfg->nb_pool_maps; i++) {
2568 /* set vlan id in VF register and set the valid bit */
2569 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2570 (cfg->pool_map[i].vlan_id & 0xFFF)));
2572 * Put the allowed pools in VFB reg. As we only have 16 or 32
2573 * pools, we only need to use the first half of the register
2576 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2581 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2582 * @hw: pointer to hardware structure
2583 * @dcb_config: pointer to ixgbe_dcb_config structure
2586 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2587 struct ixgbe_dcb_config *dcb_config)
2592 PMD_INIT_FUNC_TRACE();
2593 if (hw->mac.type != ixgbe_mac_82598EB) {
2594 /* Disable the Tx desc arbiter so that MTQC can be changed */
2595 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2596 reg |= IXGBE_RTTDCS_ARBDIS;
2597 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2599 /* Enable DCB for Tx with 8 TCs */
2600 if (dcb_config->num_tcs.pg_tcs == 8) {
2601 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2604 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2606 if (dcb_config->vt_mode)
2607 reg |= IXGBE_MTQC_VT_ENA;
2608 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2610 /* Disable drop for all queues */
2611 for (q = 0; q < 128; q++)
2612 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2613 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2615 /* Enable the Tx desc arbiter */
2616 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2617 reg &= ~IXGBE_RTTDCS_ARBDIS;
2618 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2620 /* Enable Security TX Buffer IFG for DCB */
2621 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2622 reg |= IXGBE_SECTX_DCB;
2623 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2629 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2630 * @dev: pointer to rte_eth_dev structure
2631 * @dcb_config: pointer to ixgbe_dcb_config structure
2634 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2635 struct ixgbe_dcb_config *dcb_config)
2637 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2638 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2639 struct ixgbe_hw *hw =
2640 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2642 PMD_INIT_FUNC_TRACE();
2643 if (hw->mac.type != ixgbe_mac_82598EB)
2644 /*PF VF Transmit Enable*/
2645 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2646 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2648 /*Configure general DCB TX parameters*/
2649 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2654 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2655 struct ixgbe_dcb_config *dcb_config)
2657 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2658 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2659 struct ixgbe_dcb_tc_config *tc;
2662 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2663 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2664 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2665 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2668 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2669 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2671 /* User Priority to Traffic Class mapping */
2672 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2673 j = vmdq_rx_conf->dcb_queue[i];
2674 tc = &dcb_config->tc_config[j];
2675 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2681 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2682 struct ixgbe_dcb_config *dcb_config)
2684 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2685 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2686 struct ixgbe_dcb_tc_config *tc;
2689 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2690 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2691 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2692 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2695 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2696 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2699 /* User Priority to Traffic Class mapping */
2700 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2701 j = vmdq_tx_conf->dcb_queue[i];
2702 tc = &dcb_config->tc_config[j];
2703 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2710 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2711 struct ixgbe_dcb_config *dcb_config)
2713 struct rte_eth_dcb_rx_conf *rx_conf =
2714 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2715 struct ixgbe_dcb_tc_config *tc;
2718 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2719 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2721 /* User Priority to Traffic Class mapping */
2722 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2723 j = rx_conf->dcb_queue[i];
2724 tc = &dcb_config->tc_config[j];
2725 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2731 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2732 struct ixgbe_dcb_config *dcb_config)
2734 struct rte_eth_dcb_tx_conf *tx_conf =
2735 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2736 struct ixgbe_dcb_tc_config *tc;
2739 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2740 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2742 /* User Priority to Traffic Class mapping */
2743 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2744 j = tx_conf->dcb_queue[i];
2745 tc = &dcb_config->tc_config[j];
2746 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2752 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2753 * @hw: pointer to hardware structure
2754 * @dcb_config: pointer to ixgbe_dcb_config structure
2757 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2758 struct ixgbe_dcb_config *dcb_config)
2764 PMD_INIT_FUNC_TRACE();
2766 * Disable the arbiter before changing parameters
2767 * (always enable recycle mode; WSP)
2769 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2770 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2772 if (hw->mac.type != ixgbe_mac_82598EB) {
2773 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2774 if (dcb_config->num_tcs.pg_tcs == 4) {
2775 if (dcb_config->vt_mode)
2776 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2777 IXGBE_MRQC_VMDQRT4TCEN;
2779 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2780 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2784 if (dcb_config->num_tcs.pg_tcs == 8) {
2785 if (dcb_config->vt_mode)
2786 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2787 IXGBE_MRQC_VMDQRT8TCEN;
2789 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2790 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2795 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2798 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2799 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2800 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2801 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2803 /* VFTA - enable all vlan filters */
2804 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2805 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2809 * Configure Rx packet plane (recycle mode; WSP) and
2812 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2813 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2819 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2820 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2822 switch (hw->mac.type) {
2823 case ixgbe_mac_82598EB:
2824 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2826 case ixgbe_mac_82599EB:
2827 case ixgbe_mac_X540:
2828 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2837 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2838 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2840 switch (hw->mac.type) {
2841 case ixgbe_mac_82598EB:
2842 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2843 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2845 case ixgbe_mac_82599EB:
2846 case ixgbe_mac_X540:
2847 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2848 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2855 #define DCB_RX_CONFIG 1
2856 #define DCB_TX_CONFIG 1
2857 #define DCB_TX_PB 1024
2859 * ixgbe_dcb_hw_configure - Enable DCB and configure
2860 * general DCB in VT mode and non-VT mode parameters
2861 * @dev: pointer to rte_eth_dev structure
2862 * @dcb_config: pointer to ixgbe_dcb_config structure
2865 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2866 struct ixgbe_dcb_config *dcb_config)
2869 uint8_t i,pfc_en,nb_tcs;
2871 uint8_t config_dcb_rx = 0;
2872 uint8_t config_dcb_tx = 0;
2873 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2874 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2875 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2876 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2877 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2878 struct ixgbe_dcb_tc_config *tc;
2879 uint32_t max_frame = dev->data->max_frame_size;
2880 struct ixgbe_hw *hw =
2881 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2883 switch(dev->data->dev_conf.rxmode.mq_mode){
2884 case ETH_MQ_RX_VMDQ_DCB:
2885 dcb_config->vt_mode = true;
2886 if (hw->mac.type != ixgbe_mac_82598EB) {
2887 config_dcb_rx = DCB_RX_CONFIG;
2889 *get dcb and VT rx configuration parameters
2892 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2893 /*Configure general VMDQ and DCB RX parameters*/
2894 ixgbe_vmdq_dcb_configure(dev);
2898 dcb_config->vt_mode = false;
2899 config_dcb_rx = DCB_RX_CONFIG;
2900 /* Get dcb TX configuration parameters from rte_eth_conf */
2901 ixgbe_dcb_rx_config(dev,dcb_config);
2902 /*Configure general DCB RX parameters*/
2903 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2906 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration\n");
2909 switch (dev->data->dev_conf.txmode.mq_mode) {
2910 case ETH_MQ_TX_VMDQ_DCB:
2911 dcb_config->vt_mode = true;
2912 config_dcb_tx = DCB_TX_CONFIG;
2913 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2914 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2915 /*Configure general VMDQ and DCB TX parameters*/
2916 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2920 dcb_config->vt_mode = false;
2921 config_dcb_tx = DCB_TX_CONFIG;
2922 /*get DCB TX configuration parameters from rte_eth_conf*/
2923 ixgbe_dcb_tx_config(dev,dcb_config);
2924 /*Configure general DCB TX parameters*/
2925 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2928 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration\n");
2932 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2934 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2935 if(nb_tcs == ETH_4_TCS) {
2936 /* Avoid un-configured priority mapping to TC0 */
2938 uint8_t mask = 0xFF;
2939 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
2940 mask = (uint8_t)(mask & (~ (1 << map[i])));
2941 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
2942 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
2946 /* Re-configure 4 TCs BW */
2947 for (i = 0; i < nb_tcs; i++) {
2948 tc = &dcb_config->tc_config[i];
2949 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
2950 (uint8_t)(100 / nb_tcs);
2951 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
2952 (uint8_t)(100 / nb_tcs);
2954 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2955 tc = &dcb_config->tc_config[i];
2956 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
2957 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
2962 /* Set RX buffer size */
2963 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2964 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
2965 for (i = 0 ; i < nb_tcs; i++) {
2966 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2968 /* zero alloc all unused TCs */
2969 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2970 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
2974 /* Only support an equally distributed Tx packet buffer strategy. */
2975 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
2976 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
2977 for (i = 0; i < nb_tcs; i++) {
2978 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
2979 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
2981 /* Clear unused TCs, if any, to zero buffer size*/
2982 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2983 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
2984 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
2988 /*Calculates traffic class credits*/
2989 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2990 IXGBE_DCB_TX_CONFIG);
2991 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2992 IXGBE_DCB_RX_CONFIG);
2995 /* Unpack CEE standard containers */
2996 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
2997 ixgbe_dcb_unpack_max_cee(dcb_config, max);
2998 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
2999 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3000 /* Configure PG(ETS) RX */
3001 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3005 /* Unpack CEE standard containers */
3006 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3007 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3008 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3009 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3010 /* Configure PG(ETS) TX */
3011 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3014 /*Configure queue statistics registers*/
3015 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3017 /* Check if the PFC is supported */
3018 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3019 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3020 for (i = 0; i < nb_tcs; i++) {
3022 * If the TC count is 8,and the default high_water is 48,
3023 * the low_water is 16 as default.
3025 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3026 hw->fc.low_water[i] = pbsize / 4;
3027 /* Enable pfc for this TC */
3028 tc = &dcb_config->tc_config[i];
3029 tc->pfc = ixgbe_dcb_pfc_enabled;
3031 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3032 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3034 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3041 * ixgbe_configure_dcb - Configure DCB Hardware
3042 * @dev: pointer to rte_eth_dev
3044 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3046 struct ixgbe_dcb_config *dcb_cfg =
3047 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3048 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3050 PMD_INIT_FUNC_TRACE();
3052 /* check support mq_mode for DCB */
3053 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3054 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3057 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3060 /** Configure DCB hardware **/
3061 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3067 * VMDq only support for 10 GbE NIC.
3070 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3072 struct rte_eth_vmdq_rx_conf *cfg;
3073 struct ixgbe_hw *hw;
3074 enum rte_eth_nb_pools num_pools;
3075 uint32_t mrqc, vt_ctl, vlanctrl;
3078 PMD_INIT_FUNC_TRACE();
3079 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3080 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3081 num_pools = cfg->nb_queue_pools;
3083 ixgbe_rss_disable(dev);
3085 /* MRQC: enable vmdq */
3086 mrqc = IXGBE_MRQC_VMDQEN;
3087 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3089 /* PFVTCTL: turn on virtualisation and set the default pool */
3090 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3091 if (cfg->enable_default_pool)
3092 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3094 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3096 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3098 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3099 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3100 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3101 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3103 /* VFTA - enable all vlan filters */
3104 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3105 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3107 /* VFRE: pool enabling for receive - 64 */
3108 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3109 if (num_pools == ETH_64_POOLS)
3110 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3113 * MPSAR - allow pools to read specific mac addresses
3114 * In this case, all pools should be able to read from mac addr 0
3116 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3117 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3119 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3120 for (i = 0; i < cfg->nb_pool_maps; i++) {
3121 /* set vlan id in VF register and set the valid bit */
3122 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3123 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3125 * Put the allowed pools in VFB reg. As we only have 16 or 64
3126 * pools, we only need to use the first half of the register
3129 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3130 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3131 (cfg->pool_map[i].pools & UINT32_MAX));
3133 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3134 ((cfg->pool_map[i].pools >> 32) \
3139 IXGBE_WRITE_FLUSH(hw);
3143 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3144 * @hw: pointer to hardware structure
3147 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3152 PMD_INIT_FUNC_TRACE();
3153 /*PF VF Transmit Enable*/
3154 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3155 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3157 /* Disable the Tx desc arbiter so that MTQC can be changed */
3158 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3159 reg |= IXGBE_RTTDCS_ARBDIS;
3160 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3162 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3163 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3165 /* Disable drop for all queues */
3166 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3167 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3168 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3170 /* Enable the Tx desc arbiter */
3171 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3172 reg &= ~IXGBE_RTTDCS_ARBDIS;
3173 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3175 IXGBE_WRITE_FLUSH(hw);
3181 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
3183 struct igb_rx_entry *rxe = rxq->sw_ring;
3187 /* Initialize software ring entries */
3188 for (i = 0; i < rxq->nb_rx_desc; i++) {
3189 volatile union ixgbe_adv_rx_desc *rxd;
3190 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3192 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u\n",
3193 (unsigned) rxq->queue_id);
3197 rte_mbuf_refcnt_set(mbuf, 1);
3198 mbuf->type = RTE_MBUF_PKT;
3199 mbuf->pkt.next = NULL;
3200 mbuf->pkt.data = (char *)mbuf->buf_addr + RTE_PKTMBUF_HEADROOM;
3201 mbuf->pkt.nb_segs = 1;
3202 mbuf->pkt.in_port = rxq->port_id;
3205 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3206 rxd = &rxq->rx_ring[i];
3207 rxd->read.hdr_addr = dma_addr;
3208 rxd->read.pkt_addr = dma_addr;
3216 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3218 struct ixgbe_hw *hw =
3219 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3221 if (hw->mac.type == ixgbe_mac_82598EB)
3224 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3226 * SRIOV inactive scheme
3227 * any DCB/RSS w/o VMDq multi-queue setting
3229 switch (dev->data->dev_conf.rxmode.mq_mode) {
3231 ixgbe_rss_configure(dev);
3234 case ETH_MQ_RX_VMDQ_DCB:
3235 ixgbe_vmdq_dcb_configure(dev);
3238 case ETH_MQ_RX_VMDQ_ONLY:
3239 ixgbe_vmdq_rx_hw_configure(dev);
3242 case ETH_MQ_RX_NONE:
3243 /* if mq_mode is none, disable rss mode.*/
3244 default: ixgbe_rss_disable(dev);
3247 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3249 * SRIOV active scheme
3250 * FIXME if support DCB/RSS together with VMDq & SRIOV
3253 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQEN);
3257 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT4TCEN);
3261 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT8TCEN);
3264 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3272 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3274 struct ixgbe_hw *hw =
3275 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3279 if (hw->mac.type == ixgbe_mac_82598EB)
3282 /* disable arbiter before setting MTQC */
3283 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3284 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3285 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3287 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3289 * SRIOV inactive scheme
3290 * any DCB w/o VMDq multi-queue setting
3292 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3293 ixgbe_vmdq_tx_hw_configure(hw);
3295 mtqc = IXGBE_MTQC_64Q_1PB;
3296 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3299 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3302 * SRIOV active scheme
3303 * FIXME if support DCB together with VMDq & SRIOV
3306 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3309 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3312 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3316 mtqc = IXGBE_MTQC_64Q_1PB;
3317 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3319 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3322 /* re-enable arbiter */
3323 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3324 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3330 * Initializes Receive Unit.
3333 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3335 struct ixgbe_hw *hw;
3336 struct igb_rx_queue *rxq;
3337 struct rte_pktmbuf_pool_private *mbp_priv;
3350 PMD_INIT_FUNC_TRACE();
3351 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3354 * Make sure receives are disabled while setting
3355 * up the RX context (registers, descriptor rings, etc.).
3357 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3358 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3360 /* Enable receipt of broadcasted frames */
3361 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3362 fctrl |= IXGBE_FCTRL_BAM;
3363 fctrl |= IXGBE_FCTRL_DPF;
3364 fctrl |= IXGBE_FCTRL_PMCF;
3365 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3368 * Configure CRC stripping, if any.
3370 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3371 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3372 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3374 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3377 * Configure jumbo frame support, if any.
3379 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3380 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3381 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3382 maxfrs &= 0x0000FFFF;
3383 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3384 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3386 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3389 * If loopback mode is configured for 82599, set LPBK bit.
3391 if (hw->mac.type == ixgbe_mac_82599EB &&
3392 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3393 hlreg0 |= IXGBE_HLREG0_LPBK;
3395 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3397 /* Setup RX queues */
3398 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3399 rxq = dev->data->rx_queues[i];
3401 /* Allocate buffers for descriptor rings */
3402 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3407 * Reset crc_len in case it was changed after queue setup by a
3408 * call to configure.
3410 rxq->crc_len = (uint8_t)
3411 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3414 /* Setup the Base and Length of the Rx Descriptor Rings */
3415 bus_addr = rxq->rx_ring_phys_addr;
3416 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3417 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3418 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3419 (uint32_t)(bus_addr >> 32));
3420 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3421 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3422 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3423 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3425 /* Configure the SRRCTL register */
3426 #ifdef RTE_HEADER_SPLIT_ENABLE
3428 * Configure Header Split
3430 if (dev->data->dev_conf.rxmode.header_split) {
3431 if (hw->mac.type == ixgbe_mac_82599EB) {
3432 /* Must setup the PSRTYPE register */
3434 psrtype = IXGBE_PSRTYPE_TCPHDR |
3435 IXGBE_PSRTYPE_UDPHDR |
3436 IXGBE_PSRTYPE_IPV4HDR |
3437 IXGBE_PSRTYPE_IPV6HDR;
3438 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3440 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3441 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3442 IXGBE_SRRCTL_BSIZEHDR_MASK);
3443 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3446 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3448 /* Set if packets are dropped when no descriptors available */
3450 srrctl |= IXGBE_SRRCTL_DROP_EN;
3453 * Configure the RX buffer size in the BSIZEPACKET field of
3454 * the SRRCTL register of the queue.
3455 * The value is in 1 KB resolution. Valid values can be from
3458 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3459 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3460 RTE_PKTMBUF_HEADROOM);
3461 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3462 IXGBE_SRRCTL_BSIZEPKT_MASK);
3463 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3465 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3466 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3468 /* It adds dual VLAN length for supporting dual VLAN */
3469 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3470 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3471 dev->data->scattered_rx = 1;
3472 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3477 * Device configured with multiple RX queues.
3479 ixgbe_dev_mq_rx_configure(dev);
3482 * Setup the Checksum Register.
3483 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3484 * Enable IP/L4 checkum computation by hardware if requested to do so.
3486 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3487 rxcsum |= IXGBE_RXCSUM_PCSD;
3488 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3489 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3491 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3493 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3495 if (hw->mac.type == ixgbe_mac_82599EB) {
3496 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3497 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3498 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3500 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3501 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3502 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3509 * Initializes Transmit Unit.
3512 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3514 struct ixgbe_hw *hw;
3515 struct igb_tx_queue *txq;
3521 PMD_INIT_FUNC_TRACE();
3522 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3524 /* Enable TX CRC (checksum offload requirement) */
3525 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3526 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
3527 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3529 /* Setup the Base and Length of the Tx Descriptor Rings */
3530 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3531 txq = dev->data->tx_queues[i];
3533 bus_addr = txq->tx_ring_phys_addr;
3534 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3535 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3536 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3537 (uint32_t)(bus_addr >> 32));
3538 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3539 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3540 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3541 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3542 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3545 * Disable Tx Head Writeback RO bit, since this hoses
3546 * bookkeeping if things aren't delivered in order.
3548 switch (hw->mac.type) {
3549 case ixgbe_mac_82598EB:
3550 txctrl = IXGBE_READ_REG(hw,
3551 IXGBE_DCA_TXCTRL(txq->reg_idx));
3552 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3553 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3557 case ixgbe_mac_82599EB:
3558 case ixgbe_mac_X540:
3560 txctrl = IXGBE_READ_REG(hw,
3561 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3562 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3563 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3569 /* Device configured with multiple TX queues. */
3570 ixgbe_dev_mq_tx_configure(dev);
3574 * Set up link for 82599 loopback mode Tx->Rx.
3577 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3579 DEBUGFUNC("ixgbe_setup_loopback_link_82599");
3581 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3582 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3584 PMD_INIT_LOG(ERR, "Could not enable loopback mode\n");
3593 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3594 ixgbe_reset_pipeline_82599(hw);
3596 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3602 * Start Transmit and Receive Units.
3605 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3607 struct ixgbe_hw *hw;
3608 struct igb_tx_queue *txq;
3609 struct igb_rx_queue *rxq;
3617 PMD_INIT_FUNC_TRACE();
3618 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3620 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3621 txq = dev->data->tx_queues[i];
3622 /* Setup Transmit Threshold Registers */
3623 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3624 txdctl |= txq->pthresh & 0x7F;
3625 txdctl |= ((txq->hthresh & 0x7F) << 8);
3626 txdctl |= ((txq->wthresh & 0x7F) << 16);
3627 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3630 if (hw->mac.type != ixgbe_mac_82598EB) {
3631 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3632 dmatxctl |= IXGBE_DMATXCTL_TE;
3633 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3636 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3637 txq = dev->data->tx_queues[i];
3638 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3639 txdctl |= IXGBE_TXDCTL_ENABLE;
3640 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3642 /* Wait until TX Enable ready */
3643 if (hw->mac.type == ixgbe_mac_82599EB) {
3647 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3648 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3650 PMD_INIT_LOG(ERR, "Could not enable "
3651 "Tx Queue %d\n", i);
3654 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3655 rxq = dev->data->rx_queues[i];
3656 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3657 rxdctl |= IXGBE_RXDCTL_ENABLE;
3658 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3660 /* Wait until RX Enable ready */
3664 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3665 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3667 PMD_INIT_LOG(ERR, "Could not enable "
3668 "Rx Queue %d\n", i);
3670 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3673 /* Enable Receive engine */
3674 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3675 if (hw->mac.type == ixgbe_mac_82598EB)
3676 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3677 rxctrl |= IXGBE_RXCTRL_RXEN;
3678 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3680 /* If loopback mode is enabled for 82599, set up the link accordingly */
3681 if (hw->mac.type == ixgbe_mac_82599EB &&
3682 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3683 ixgbe_setup_loopback_link_82599(hw);
3689 * [VF] Initializes Receive Unit.
3692 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3694 struct ixgbe_hw *hw;
3695 struct igb_rx_queue *rxq;
3696 struct rte_pktmbuf_pool_private *mbp_priv;
3703 PMD_INIT_FUNC_TRACE();
3704 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3706 /* Setup RX queues */
3707 dev->rx_pkt_burst = ixgbe_recv_pkts;
3708 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3709 rxq = dev->data->rx_queues[i];
3711 /* Allocate buffers for descriptor rings */
3712 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3716 /* Setup the Base and Length of the Rx Descriptor Rings */
3717 bus_addr = rxq->rx_ring_phys_addr;
3719 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3720 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3721 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3722 (uint32_t)(bus_addr >> 32));
3723 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3724 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3725 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3726 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3729 /* Configure the SRRCTL register */
3730 #ifdef RTE_HEADER_SPLIT_ENABLE
3732 * Configure Header Split
3734 if (dev->data->dev_conf.rxmode.header_split) {
3736 /* Must setup the PSRTYPE register */
3738 psrtype = IXGBE_PSRTYPE_TCPHDR |
3739 IXGBE_PSRTYPE_UDPHDR |
3740 IXGBE_PSRTYPE_IPV4HDR |
3741 IXGBE_PSRTYPE_IPV6HDR;
3743 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
3745 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3746 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3747 IXGBE_SRRCTL_BSIZEHDR_MASK);
3748 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3751 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3753 /* Set if packets are dropped when no descriptors available */
3755 srrctl |= IXGBE_SRRCTL_DROP_EN;
3758 * Configure the RX buffer size in the BSIZEPACKET field of
3759 * the SRRCTL register of the queue.
3760 * The value is in 1 KB resolution. Valid values can be from
3763 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3764 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3765 RTE_PKTMBUF_HEADROOM);
3766 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3767 IXGBE_SRRCTL_BSIZEPKT_MASK);
3770 * VF modification to write virtual function SRRCTL register
3772 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
3774 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3775 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3777 /* It adds dual VLAN length for supporting dual VLAN */
3778 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3779 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
3780 dev->data->scattered_rx = 1;
3781 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3789 * [VF] Initializes Transmit Unit.
3792 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
3794 struct ixgbe_hw *hw;
3795 struct igb_tx_queue *txq;
3800 PMD_INIT_FUNC_TRACE();
3801 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3803 /* Setup the Base and Length of the Tx Descriptor Rings */
3804 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3805 txq = dev->data->tx_queues[i];
3806 bus_addr = txq->tx_ring_phys_addr;
3807 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
3808 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3809 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
3810 (uint32_t)(bus_addr >> 32));
3811 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
3812 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3813 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3814 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
3815 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
3818 * Disable Tx Head Writeback RO bit, since this hoses
3819 * bookkeeping if things aren't delivered in order.
3821 txctrl = IXGBE_READ_REG(hw,
3822 IXGBE_VFDCA_TXCTRL(i));
3823 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3824 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
3830 * [VF] Start Transmit and Receive Units.
3833 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
3835 struct ixgbe_hw *hw;
3836 struct igb_tx_queue *txq;
3837 struct igb_rx_queue *rxq;
3843 PMD_INIT_FUNC_TRACE();
3844 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3846 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3847 txq = dev->data->tx_queues[i];
3848 /* Setup Transmit Threshold Registers */
3849 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3850 txdctl |= txq->pthresh & 0x7F;
3851 txdctl |= ((txq->hthresh & 0x7F) << 8);
3852 txdctl |= ((txq->wthresh & 0x7F) << 16);
3853 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
3856 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3858 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3859 txdctl |= IXGBE_TXDCTL_ENABLE;
3860 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
3863 /* Wait until TX Enable ready */
3866 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3867 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3869 PMD_INIT_LOG(ERR, "Could not enable "
3870 "Tx Queue %d\n", i);
3872 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3874 rxq = dev->data->rx_queues[i];
3876 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
3877 rxdctl |= IXGBE_RXDCTL_ENABLE;
3878 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
3880 /* Wait until RX Enable ready */
3884 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
3885 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3887 PMD_INIT_LOG(ERR, "Could not enable "
3888 "Rx Queue %d\n", i);
3890 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);