4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
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13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
47 #include <rte_cycles.h>
49 #include <rte_debug.h>
50 #include <rte_interrupts.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_launch.h>
55 #include <rte_tailq.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
80 #include "ixgbe_rxtx.h"
82 #define IXGBE_RSS_OFFLOAD_ALL ( \
88 ETH_RSS_IPV6_TCP_EX | \
93 static inline struct rte_mbuf *
94 rte_rxmbuf_alloc(struct rte_mempool *mp)
98 m = __rte_mbuf_raw_alloc(mp);
99 __rte_mbuf_sanity_check_raw(m, 0);
105 #define RTE_PMD_USE_PREFETCH
108 #ifdef RTE_PMD_USE_PREFETCH
110 * Prefetch a cache line into all cache levels.
112 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
114 #define rte_ixgbe_prefetch(p) do {} while(0)
117 /*********************************************************************
121 **********************************************************************/
124 * Check for descriptors with their DD bit set and free mbufs.
125 * Return the total number of buffers freed.
127 static inline int __attribute__((always_inline))
128 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
130 struct igb_tx_entry *txep;
134 /* check DD bit on threshold descriptor */
135 status = txq->tx_ring[txq->tx_next_dd].wb.status;
136 if (! (status & IXGBE_ADVTXD_STAT_DD))
140 * first buffer to free from S/W ring is at index
141 * tx_next_dd - (tx_rs_thresh-1)
143 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
145 /* free buffers one at a time */
146 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
147 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
148 txep->mbuf->next = NULL;
149 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
153 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
154 rte_pktmbuf_free_seg(txep->mbuf);
159 /* buffers were freed, update counters */
160 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
161 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
162 if (txq->tx_next_dd >= txq->nb_tx_desc)
163 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
165 return txq->tx_rs_thresh;
168 /* Populate 4 descriptors with data from 4 mbufs */
170 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
172 uint64_t buf_dma_addr;
176 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
177 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
178 pkt_len = (*pkts)->data_len;
180 /* write data to descriptor */
181 txdp->read.buffer_addr = buf_dma_addr;
182 txdp->read.cmd_type_len =
183 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
184 txdp->read.olinfo_status =
185 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
186 rte_prefetch0(&(*pkts)->pool);
190 /* Populate 1 descriptor with data from 1 mbuf */
192 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
194 uint64_t buf_dma_addr;
197 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
198 pkt_len = (*pkts)->data_len;
200 /* write data to descriptor */
201 txdp->read.buffer_addr = buf_dma_addr;
202 txdp->read.cmd_type_len =
203 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
204 txdp->read.olinfo_status =
205 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
206 rte_prefetch0(&(*pkts)->pool);
210 * Fill H/W descriptor ring with mbuf data.
211 * Copy mbuf pointers to the S/W ring.
214 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
217 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
218 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
219 const int N_PER_LOOP = 4;
220 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
221 int mainpart, leftover;
225 * Process most of the packets in chunks of N pkts. Any
226 * leftover packets will get processed one at a time.
228 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
229 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
230 for (i = 0; i < mainpart; i += N_PER_LOOP) {
231 /* Copy N mbuf pointers to the S/W ring */
232 for (j = 0; j < N_PER_LOOP; ++j) {
233 (txep + i + j)->mbuf = *(pkts + i + j);
235 tx4(txdp + i, pkts + i);
238 if (unlikely(leftover > 0)) {
239 for (i = 0; i < leftover; ++i) {
240 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
241 tx1(txdp + mainpart + i, pkts + mainpart + i);
246 static inline uint16_t
247 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
250 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
251 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
255 * Begin scanning the H/W ring for done descriptors when the
256 * number of available descriptors drops below tx_free_thresh. For
257 * each done descriptor, free the associated buffer.
259 if (txq->nb_tx_free < txq->tx_free_thresh)
260 ixgbe_tx_free_bufs(txq);
262 /* Only use descriptors that are available */
263 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
264 if (unlikely(nb_pkts == 0))
267 /* Use exactly nb_pkts descriptors */
268 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
271 * At this point, we know there are enough descriptors in the
272 * ring to transmit all the packets. This assumes that each
273 * mbuf contains a single segment, and that no new offloads
274 * are expected, which would require a new context descriptor.
278 * See if we're going to wrap-around. If so, handle the top
279 * of the descriptor ring first, then do the bottom. If not,
280 * the processing looks just like the "bottom" part anyway...
282 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
283 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
284 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
287 * We know that the last descriptor in the ring will need to
288 * have its RS bit set because tx_rs_thresh has to be
289 * a divisor of the ring size
291 tx_r[txq->tx_next_rs].read.cmd_type_len |=
292 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
293 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
298 /* Fill H/W descriptor ring with mbuf data */
299 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
300 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
303 * Determine if RS bit should be set
304 * This is what we actually want:
305 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
306 * but instead of subtracting 1 and doing >=, we can just do
307 * greater than without subtracting.
309 if (txq->tx_tail > txq->tx_next_rs) {
310 tx_r[txq->tx_next_rs].read.cmd_type_len |=
311 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
312 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
314 if (txq->tx_next_rs >= txq->nb_tx_desc)
315 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
319 * Check for wrap-around. This would only happen if we used
320 * up to the last descriptor in the ring, no more, no less.
322 if (txq->tx_tail >= txq->nb_tx_desc)
325 /* update tail pointer */
327 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
333 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
338 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
339 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
340 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
342 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
346 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
347 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
348 nb_tx = (uint16_t)(nb_tx + ret);
349 nb_pkts = (uint16_t)(nb_pkts - ret);
358 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
359 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
360 uint64_t ol_flags, uint32_t vlan_macip_lens)
362 uint32_t type_tucmd_mlhl;
363 uint32_t mss_l4len_idx;
367 ctx_idx = txq->ctx_curr;
371 if (ol_flags & PKT_TX_VLAN_PKT) {
372 cmp_mask |= TX_VLAN_CMP_MASK;
375 if (ol_flags & PKT_TX_IP_CKSUM) {
376 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
377 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
380 /* Specify which HW CTX to upload. */
381 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
382 switch (ol_flags & PKT_TX_L4_MASK) {
383 case PKT_TX_UDP_CKSUM:
384 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
385 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
386 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
387 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
389 case PKT_TX_TCP_CKSUM:
390 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
391 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
392 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
393 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
395 case PKT_TX_SCTP_CKSUM:
396 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
397 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
398 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
399 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
402 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
403 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
407 txq->ctx_cache[ctx_idx].flags = ol_flags;
408 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
409 txq->ctx_cache[ctx_idx].vlan_macip_lens.data =
410 vlan_macip_lens & cmp_mask;
412 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
413 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
414 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
415 ctx_txd->seqnum_seed = 0;
419 * Check which hardware context can be used. Use the existing match
420 * or create a new context descriptor.
422 static inline uint32_t
423 what_advctx_update(struct igb_tx_queue *txq, uint64_t flags,
424 uint32_t vlan_macip_lens)
426 /* If match with the current used context */
427 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
428 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
429 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
430 return txq->ctx_curr;
433 /* What if match with the next context */
435 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
436 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
437 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
438 return txq->ctx_curr;
441 /* Mismatch, use the previous context */
442 return (IXGBE_CTX_NUM);
445 static inline uint32_t
446 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
448 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
449 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
452 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
453 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
457 static inline uint32_t
458 tx_desc_vlan_flags_to_cmdtype(uint64_t ol_flags)
460 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
461 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
464 /* Default RS bit threshold values */
465 #ifndef DEFAULT_TX_RS_THRESH
466 #define DEFAULT_TX_RS_THRESH 32
468 #ifndef DEFAULT_TX_FREE_THRESH
469 #define DEFAULT_TX_FREE_THRESH 32
472 /* Reset transmit descriptors after they have been used */
474 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
476 struct igb_tx_entry *sw_ring = txq->sw_ring;
477 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
478 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
479 uint16_t nb_tx_desc = txq->nb_tx_desc;
480 uint16_t desc_to_clean_to;
481 uint16_t nb_tx_to_clean;
483 /* Determine the last descriptor needing to be cleaned */
484 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
485 if (desc_to_clean_to >= nb_tx_desc)
486 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
488 /* Check to make sure the last descriptor to clean is done */
489 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
490 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
492 PMD_TX_FREE_LOG(DEBUG,
493 "TX descriptor %4u is not done"
494 "(port=%d queue=%d)",
496 txq->port_id, txq->queue_id);
497 /* Failed to clean any descriptors, better luck next time */
501 /* Figure out how many descriptors will be cleaned */
502 if (last_desc_cleaned > desc_to_clean_to)
503 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
506 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
509 PMD_TX_FREE_LOG(DEBUG,
510 "Cleaning %4u TX descriptors: %4u to %4u "
511 "(port=%d queue=%d)",
512 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
513 txq->port_id, txq->queue_id);
516 * The last descriptor to clean is done, so that means all the
517 * descriptors from the last descriptor that was cleaned
518 * up to the last descriptor with the RS bit set
519 * are done. Only reset the threshold descriptor.
521 txr[desc_to_clean_to].wb.status = 0;
523 /* Update the txq to reflect the last descriptor that was cleaned */
524 txq->last_desc_cleaned = desc_to_clean_to;
525 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
532 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
535 struct igb_tx_queue *txq;
536 struct igb_tx_entry *sw_ring;
537 struct igb_tx_entry *txe, *txn;
538 volatile union ixgbe_adv_tx_desc *txr;
539 volatile union ixgbe_adv_tx_desc *txd;
540 struct rte_mbuf *tx_pkt;
541 struct rte_mbuf *m_seg;
542 union ixgbe_vlan_macip vlan_macip_lens;
543 uint64_t buf_dma_addr;
544 uint32_t olinfo_status;
545 uint32_t cmd_type_len;
558 sw_ring = txq->sw_ring;
560 tx_id = txq->tx_tail;
561 txe = &sw_ring[tx_id];
563 /* Determine if the descriptor ring needs to be cleaned. */
564 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
565 ixgbe_xmit_cleanup(txq);
568 rte_prefetch0(&txe->mbuf->pool);
571 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
574 pkt_len = tx_pkt->pkt_len;
577 * Determine how many (if any) context descriptors
578 * are needed for offload functionality.
580 ol_flags = tx_pkt->ol_flags;
582 /* If hardware offload required */
583 tx_ol_req = ol_flags & PKT_TX_OFFLOAD_MASK;
585 vlan_macip_lens.f.vlan_tci = tx_pkt->vlan_tci;
586 vlan_macip_lens.f.l2_l3_len = tx_pkt->l2_l3_len;
588 /* If new context need be built or reuse the exist ctx. */
589 ctx = what_advctx_update(txq, tx_ol_req,
590 vlan_macip_lens.data);
591 /* Only allocate context descriptor if required*/
592 new_ctx = (ctx == IXGBE_CTX_NUM);
597 * Keep track of how many descriptors are used this loop
598 * This will always be the number of segments + the number of
599 * Context descriptors required to transmit the packet
601 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
604 * The number of descriptors that must be allocated for a
605 * packet is the number of segments of that packet, plus 1
606 * Context Descriptor for the hardware offload, if any.
607 * Determine the last TX descriptor to allocate in the TX ring
608 * for the packet, starting from the current position (tx_id)
611 tx_last = (uint16_t) (tx_id + nb_used - 1);
614 if (tx_last >= txq->nb_tx_desc)
615 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
617 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
618 " tx_first=%u tx_last=%u",
619 (unsigned) txq->port_id,
620 (unsigned) txq->queue_id,
626 * Make sure there are enough TX descriptors available to
627 * transmit the entire packet.
628 * nb_used better be less than or equal to txq->tx_rs_thresh
630 if (nb_used > txq->nb_tx_free) {
631 PMD_TX_FREE_LOG(DEBUG,
632 "Not enough free TX descriptors "
633 "nb_used=%4u nb_free=%4u "
634 "(port=%d queue=%d)",
635 nb_used, txq->nb_tx_free,
636 txq->port_id, txq->queue_id);
638 if (ixgbe_xmit_cleanup(txq) != 0) {
639 /* Could not clean any descriptors */
645 /* nb_used better be <= txq->tx_rs_thresh */
646 if (unlikely(nb_used > txq->tx_rs_thresh)) {
647 PMD_TX_FREE_LOG(DEBUG,
648 "The number of descriptors needed to "
649 "transmit the packet exceeds the "
650 "RS bit threshold. This will impact "
652 "nb_used=%4u nb_free=%4u "
654 "(port=%d queue=%d)",
655 nb_used, txq->nb_tx_free,
657 txq->port_id, txq->queue_id);
659 * Loop here until there are enough TX
660 * descriptors or until the ring cannot be
663 while (nb_used > txq->nb_tx_free) {
664 if (ixgbe_xmit_cleanup(txq) != 0) {
666 * Could not clean any
678 * By now there are enough free TX descriptors to transmit
683 * Set common flags of all TX Data Descriptors.
685 * The following bits must be set in all Data Descriptors:
686 * - IXGBE_ADVTXD_DTYP_DATA
687 * - IXGBE_ADVTXD_DCMD_DEXT
689 * The following bits must be set in the first Data Descriptor
690 * and are ignored in the other ones:
691 * - IXGBE_ADVTXD_DCMD_IFCS
692 * - IXGBE_ADVTXD_MAC_1588
693 * - IXGBE_ADVTXD_DCMD_VLE
695 * The following bits must only be set in the last Data
697 * - IXGBE_TXD_CMD_EOP
699 * The following bits can be set in any Data Descriptor, but
700 * are only set in the last Data Descriptor:
703 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
704 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
705 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
706 #ifdef RTE_LIBRTE_IEEE1588
707 if (ol_flags & PKT_TX_IEEE1588_TMST)
708 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
713 * Setup the TX Advanced Context Descriptor if required
716 volatile struct ixgbe_adv_tx_context_desc *
719 ctx_txd = (volatile struct
720 ixgbe_adv_tx_context_desc *)
723 txn = &sw_ring[txe->next_id];
724 rte_prefetch0(&txn->mbuf->pool);
726 if (txe->mbuf != NULL) {
727 rte_pktmbuf_free_seg(txe->mbuf);
731 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
732 vlan_macip_lens.data);
734 txe->last_id = tx_last;
735 tx_id = txe->next_id;
740 * Setup the TX Advanced Data Descriptor,
741 * This path will go through
742 * whatever new/reuse the context descriptor
744 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
745 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
746 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
752 txn = &sw_ring[txe->next_id];
753 rte_prefetch0(&txn->mbuf->pool);
755 if (txe->mbuf != NULL)
756 rte_pktmbuf_free_seg(txe->mbuf);
760 * Set up Transmit Data Descriptor.
762 slen = m_seg->data_len;
763 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
764 txd->read.buffer_addr =
765 rte_cpu_to_le_64(buf_dma_addr);
766 txd->read.cmd_type_len =
767 rte_cpu_to_le_32(cmd_type_len | slen);
768 txd->read.olinfo_status =
769 rte_cpu_to_le_32(olinfo_status);
770 txe->last_id = tx_last;
771 tx_id = txe->next_id;
774 } while (m_seg != NULL);
777 * The last packet data descriptor needs End Of Packet (EOP)
779 cmd_type_len |= IXGBE_TXD_CMD_EOP;
780 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
781 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
783 /* Set RS bit only on threshold packets' last descriptor */
784 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
785 PMD_TX_FREE_LOG(DEBUG,
786 "Setting RS bit on TXD id="
787 "%4u (port=%d queue=%d)",
788 tx_last, txq->port_id, txq->queue_id);
790 cmd_type_len |= IXGBE_TXD_CMD_RS;
792 /* Update txq RS bit counters */
795 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
801 * Set the Transmit Descriptor Tail (TDT)
803 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
804 (unsigned) txq->port_id, (unsigned) txq->queue_id,
805 (unsigned) tx_id, (unsigned) nb_tx);
806 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
807 txq->tx_tail = tx_id;
812 /*********************************************************************
816 **********************************************************************/
817 static inline uint64_t
818 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
822 static uint64_t ip_pkt_types_map[16] = {
823 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
824 PKT_RX_IPV6_HDR, 0, 0, 0,
825 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
826 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
829 static uint64_t ip_rss_types_map[16] = {
830 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
831 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
832 PKT_RX_RSS_HASH, 0, 0, 0,
833 0, 0, 0, PKT_RX_FDIR,
836 #ifdef RTE_LIBRTE_IEEE1588
837 static uint32_t ip_pkt_etqf_map[8] = {
838 0, 0, 0, PKT_RX_IEEE1588_PTP,
842 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
843 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
844 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
846 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
847 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
850 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
853 static inline uint64_t
854 rx_desc_status_to_pkt_flags(uint32_t rx_status)
859 * Check if VLAN present only.
860 * Do not check whether L3/L4 rx checksum done by NIC or not,
861 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
863 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
865 #ifdef RTE_LIBRTE_IEEE1588
866 if (rx_status & IXGBE_RXD_STAT_TMST)
867 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
872 static inline uint64_t
873 rx_desc_error_to_pkt_flags(uint32_t rx_status)
876 * Bit 31: IPE, IPv4 checksum error
877 * Bit 30: L4I, L4I integrity error
879 static uint64_t error_to_pkt_flags_map[4] = {
880 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
881 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
883 return error_to_pkt_flags_map[(rx_status >>
884 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
887 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
889 * LOOK_AHEAD defines how many desc statuses to check beyond the
890 * current descriptor.
891 * It must be a pound define for optimal performance.
892 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
893 * function only works with LOOK_AHEAD=8.
896 #if (LOOK_AHEAD != 8)
897 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
900 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
902 volatile union ixgbe_adv_rx_desc *rxdp;
903 struct igb_rx_entry *rxep;
907 int s[LOOK_AHEAD], nb_dd;
911 /* get references to current descriptor and S/W ring entry */
912 rxdp = &rxq->rx_ring[rxq->rx_tail];
913 rxep = &rxq->sw_ring[rxq->rx_tail];
915 /* check to make sure there is at least 1 packet to receive */
916 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
920 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
921 * reference packets that are ready to be received.
923 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
924 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
926 /* Read desc statuses backwards to avoid race condition */
927 for (j = LOOK_AHEAD-1; j >= 0; --j)
928 s[j] = rxdp[j].wb.upper.status_error;
930 /* Compute how many status bits were set */
932 for (j = 0; j < LOOK_AHEAD; ++j)
933 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
937 /* Translate descriptor info to mbuf format */
938 for (j = 0; j < nb_dd; ++j) {
940 pkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len);
941 mb->data_len = pkt_len;
942 mb->pkt_len = pkt_len;
943 mb->vlan_tci = rxdp[j].wb.upper.vlan;
944 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
946 /* convert descriptor fields to rte mbuf flags */
947 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(
948 rxdp[j].wb.lower.lo_dword.data);
949 /* reuse status field from scan list */
950 pkt_flags |= rx_desc_status_to_pkt_flags(s[j]);
951 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
952 mb->ol_flags = pkt_flags;
954 if (likely(pkt_flags & PKT_RX_RSS_HASH))
955 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
956 else if (pkt_flags & PKT_RX_FDIR) {
958 (uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum)
959 & IXGBE_ATR_HASH_MASK);
960 mb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id;
964 /* Move mbuf pointers from the S/W ring to the stage */
965 for (j = 0; j < LOOK_AHEAD; ++j) {
966 rxq->rx_stage[i + j] = rxep[j].mbuf;
969 /* stop if all requested packets could not be received */
970 if (nb_dd != LOOK_AHEAD)
974 /* clear software ring entries so we can cleanup correctly */
975 for (i = 0; i < nb_rx; ++i) {
976 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
984 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
986 volatile union ixgbe_adv_rx_desc *rxdp;
987 struct igb_rx_entry *rxep;
993 /* allocate buffers in bulk directly into the S/W ring */
994 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
995 (rxq->rx_free_thresh - 1));
996 rxep = &rxq->sw_ring[alloc_idx];
997 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
998 rxq->rx_free_thresh);
999 if (unlikely(diag != 0))
1002 rxdp = &rxq->rx_ring[alloc_idx];
1003 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1004 /* populate the static rte mbuf fields */
1006 rte_mbuf_refcnt_set(mb, 1);
1008 mb->data_off = RTE_PKTMBUF_HEADROOM;
1010 mb->port = rxq->port_id;
1012 /* populate the descriptors */
1013 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1014 rxdp[i].read.hdr_addr = dma_addr;
1015 rxdp[i].read.pkt_addr = dma_addr;
1018 /* update tail pointer */
1020 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1022 /* update state of internal queue structure */
1023 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1024 rxq->rx_free_thresh);
1025 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1026 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1032 static inline uint16_t
1033 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1036 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1039 /* how many packets are ready to return? */
1040 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1042 /* copy mbuf pointers to the application's packet list */
1043 for (i = 0; i < nb_pkts; ++i)
1044 rx_pkts[i] = stage[i];
1046 /* update internal queue state */
1047 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1048 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1053 static inline uint16_t
1054 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1057 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1060 /* Any previously recv'd pkts will be returned from the Rx stage */
1061 if (rxq->rx_nb_avail)
1062 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1064 /* Scan the H/W ring for packets to receive */
1065 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1067 /* update internal queue state */
1068 rxq->rx_next_avail = 0;
1069 rxq->rx_nb_avail = nb_rx;
1070 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1072 /* if required, allocate new buffers to replenish descriptors */
1073 if (rxq->rx_tail > rxq->rx_free_trigger) {
1074 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1076 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1077 "queue_id=%u", (unsigned) rxq->port_id,
1078 (unsigned) rxq->queue_id);
1080 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1081 rxq->rx_free_thresh;
1084 * Need to rewind any previous receives if we cannot
1085 * allocate new buffers to replenish the old ones.
1087 rxq->rx_nb_avail = 0;
1088 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1089 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1090 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1096 if (rxq->rx_tail >= rxq->nb_rx_desc)
1099 /* received any packets this loop? */
1100 if (rxq->rx_nb_avail)
1101 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1106 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1108 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1113 if (unlikely(nb_pkts == 0))
1116 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1117 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1119 /* request is relatively large, chunk it up */
1123 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1124 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1125 nb_rx = (uint16_t)(nb_rx + ret);
1126 nb_pkts = (uint16_t)(nb_pkts - ret);
1133 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1136 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1139 struct igb_rx_queue *rxq;
1140 volatile union ixgbe_adv_rx_desc *rx_ring;
1141 volatile union ixgbe_adv_rx_desc *rxdp;
1142 struct igb_rx_entry *sw_ring;
1143 struct igb_rx_entry *rxe;
1144 struct rte_mbuf *rxm;
1145 struct rte_mbuf *nmb;
1146 union ixgbe_adv_rx_desc rxd;
1149 uint32_t hlen_type_rss;
1159 rx_id = rxq->rx_tail;
1160 rx_ring = rxq->rx_ring;
1161 sw_ring = rxq->sw_ring;
1162 while (nb_rx < nb_pkts) {
1164 * The order of operations here is important as the DD status
1165 * bit must not be read after any other descriptor fields.
1166 * rx_ring and rxdp are pointing to volatile data so the order
1167 * of accesses cannot be reordered by the compiler. If they were
1168 * not volatile, they could be reordered which could lead to
1169 * using invalid descriptor fields when read from rxd.
1171 rxdp = &rx_ring[rx_id];
1172 staterr = rxdp->wb.upper.status_error;
1173 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1180 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1181 * is likely to be invalid and to be dropped by the various
1182 * validation checks performed by the network stack.
1184 * Allocate a new mbuf to replenish the RX ring descriptor.
1185 * If the allocation fails:
1186 * - arrange for that RX descriptor to be the first one
1187 * being parsed the next time the receive function is
1188 * invoked [on the same queue].
1190 * - Stop parsing the RX ring and return immediately.
1192 * This policy do not drop the packet received in the RX
1193 * descriptor for which the allocation of a new mbuf failed.
1194 * Thus, it allows that packet to be later retrieved if
1195 * mbuf have been freed in the mean time.
1196 * As a side effect, holding RX descriptors instead of
1197 * systematically giving them back to the NIC may lead to
1198 * RX ring exhaustion situations.
1199 * However, the NIC can gracefully prevent such situations
1200 * to happen by sending specific "back-pressure" flow control
1201 * frames to its peer(s).
1203 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1204 "ext_err_stat=0x%08x pkt_len=%u",
1205 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1206 (unsigned) rx_id, (unsigned) staterr,
1207 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1209 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1211 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1212 "queue_id=%u", (unsigned) rxq->port_id,
1213 (unsigned) rxq->queue_id);
1214 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1219 rxe = &sw_ring[rx_id];
1221 if (rx_id == rxq->nb_rx_desc)
1224 /* Prefetch next mbuf while processing current one. */
1225 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1228 * When next RX descriptor is on a cache-line boundary,
1229 * prefetch the next 4 RX descriptors and the next 8 pointers
1232 if ((rx_id & 0x3) == 0) {
1233 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1234 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1240 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1241 rxdp->read.hdr_addr = dma_addr;
1242 rxdp->read.pkt_addr = dma_addr;
1245 * Initialize the returned mbuf.
1246 * 1) setup generic mbuf fields:
1247 * - number of segments,
1250 * - RX port identifier.
1251 * 2) integrate hardware offload data, if any:
1252 * - RSS flag & hash,
1253 * - IP checksum flag,
1254 * - VLAN TCI, if any,
1257 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1259 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1260 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1263 rxm->pkt_len = pkt_len;
1264 rxm->data_len = pkt_len;
1265 rxm->port = rxq->port_id;
1267 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1268 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1269 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1271 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1272 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1273 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1274 rxm->ol_flags = pkt_flags;
1276 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1277 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1278 else if (pkt_flags & PKT_RX_FDIR) {
1279 rxm->hash.fdir.hash =
1280 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1281 & IXGBE_ATR_HASH_MASK);
1282 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1285 * Store the mbuf address into the next entry of the array
1286 * of returned packets.
1288 rx_pkts[nb_rx++] = rxm;
1290 rxq->rx_tail = rx_id;
1293 * If the number of free RX descriptors is greater than the RX free
1294 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1296 * Update the RDT with the value of the last processed RX descriptor
1297 * minus 1, to guarantee that the RDT register is never equal to the
1298 * RDH register, which creates a "full" ring situtation from the
1299 * hardware point of view...
1301 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1302 if (nb_hold > rxq->rx_free_thresh) {
1303 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1304 "nb_hold=%u nb_rx=%u",
1305 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1306 (unsigned) rx_id, (unsigned) nb_hold,
1308 rx_id = (uint16_t) ((rx_id == 0) ?
1309 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1310 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1313 rxq->nb_rx_hold = nb_hold;
1318 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1321 struct igb_rx_queue *rxq;
1322 volatile union ixgbe_adv_rx_desc *rx_ring;
1323 volatile union ixgbe_adv_rx_desc *rxdp;
1324 struct igb_rx_entry *sw_ring;
1325 struct igb_rx_entry *rxe;
1326 struct rte_mbuf *first_seg;
1327 struct rte_mbuf *last_seg;
1328 struct rte_mbuf *rxm;
1329 struct rte_mbuf *nmb;
1330 union ixgbe_adv_rx_desc rxd;
1331 uint64_t dma; /* Physical address of mbuf data buffer */
1333 uint32_t hlen_type_rss;
1343 rx_id = rxq->rx_tail;
1344 rx_ring = rxq->rx_ring;
1345 sw_ring = rxq->sw_ring;
1348 * Retrieve RX context of current packet, if any.
1350 first_seg = rxq->pkt_first_seg;
1351 last_seg = rxq->pkt_last_seg;
1353 while (nb_rx < nb_pkts) {
1356 * The order of operations here is important as the DD status
1357 * bit must not be read after any other descriptor fields.
1358 * rx_ring and rxdp are pointing to volatile data so the order
1359 * of accesses cannot be reordered by the compiler. If they were
1360 * not volatile, they could be reordered which could lead to
1361 * using invalid descriptor fields when read from rxd.
1363 rxdp = &rx_ring[rx_id];
1364 staterr = rxdp->wb.upper.status_error;
1365 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1372 * Allocate a new mbuf to replenish the RX ring descriptor.
1373 * If the allocation fails:
1374 * - arrange for that RX descriptor to be the first one
1375 * being parsed the next time the receive function is
1376 * invoked [on the same queue].
1378 * - Stop parsing the RX ring and return immediately.
1380 * This policy does not drop the packet received in the RX
1381 * descriptor for which the allocation of a new mbuf failed.
1382 * Thus, it allows that packet to be later retrieved if
1383 * mbuf have been freed in the mean time.
1384 * As a side effect, holding RX descriptors instead of
1385 * systematically giving them back to the NIC may lead to
1386 * RX ring exhaustion situations.
1387 * However, the NIC can gracefully prevent such situations
1388 * to happen by sending specific "back-pressure" flow control
1389 * frames to its peer(s).
1391 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1392 "staterr=0x%x data_len=%u",
1393 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1394 (unsigned) rx_id, (unsigned) staterr,
1395 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1397 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1399 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1400 "queue_id=%u", (unsigned) rxq->port_id,
1401 (unsigned) rxq->queue_id);
1402 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1407 rxe = &sw_ring[rx_id];
1409 if (rx_id == rxq->nb_rx_desc)
1412 /* Prefetch next mbuf while processing current one. */
1413 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1416 * When next RX descriptor is on a cache-line boundary,
1417 * prefetch the next 4 RX descriptors and the next 8 pointers
1420 if ((rx_id & 0x3) == 0) {
1421 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1422 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1426 * Update RX descriptor with the physical address of the new
1427 * data buffer of the new allocated mbuf.
1431 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1432 rxdp->read.hdr_addr = dma;
1433 rxdp->read.pkt_addr = dma;
1436 * Set data length & data buffer address of mbuf.
1438 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1439 rxm->data_len = data_len;
1440 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1443 * If this is the first buffer of the received packet,
1444 * set the pointer to the first mbuf of the packet and
1445 * initialize its context.
1446 * Otherwise, update the total length and the number of segments
1447 * of the current scattered packet, and update the pointer to
1448 * the last mbuf of the current packet.
1450 if (first_seg == NULL) {
1452 first_seg->pkt_len = data_len;
1453 first_seg->nb_segs = 1;
1455 first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
1457 first_seg->nb_segs++;
1458 last_seg->next = rxm;
1462 * If this is not the last buffer of the received packet,
1463 * update the pointer to the last mbuf of the current scattered
1464 * packet and continue to parse the RX ring.
1466 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1472 * This is the last buffer of the received packet.
1473 * If the CRC is not stripped by the hardware:
1474 * - Subtract the CRC length from the total packet length.
1475 * - If the last buffer only contains the whole CRC or a part
1476 * of it, free the mbuf associated to the last buffer.
1477 * If part of the CRC is also contained in the previous
1478 * mbuf, subtract the length of that CRC part from the
1479 * data length of the previous mbuf.
1482 if (unlikely(rxq->crc_len > 0)) {
1483 first_seg->pkt_len -= ETHER_CRC_LEN;
1484 if (data_len <= ETHER_CRC_LEN) {
1485 rte_pktmbuf_free_seg(rxm);
1486 first_seg->nb_segs--;
1487 last_seg->data_len = (uint16_t)
1488 (last_seg->data_len -
1489 (ETHER_CRC_LEN - data_len));
1490 last_seg->next = NULL;
1493 (uint16_t) (data_len - ETHER_CRC_LEN);
1497 * Initialize the first mbuf of the returned packet:
1498 * - RX port identifier,
1499 * - hardware offload data, if any:
1500 * - RSS flag & hash,
1501 * - IP checksum flag,
1502 * - VLAN TCI, if any,
1505 first_seg->port = rxq->port_id;
1508 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1509 * set in the pkt_flags field.
1511 first_seg->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1512 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1513 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1514 pkt_flags = (uint16_t)(pkt_flags |
1515 rx_desc_status_to_pkt_flags(staterr));
1516 pkt_flags = (uint16_t)(pkt_flags |
1517 rx_desc_error_to_pkt_flags(staterr));
1518 first_seg->ol_flags = pkt_flags;
1520 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1521 first_seg->hash.rss = rxd.wb.lower.hi_dword.rss;
1522 else if (pkt_flags & PKT_RX_FDIR) {
1523 first_seg->hash.fdir.hash =
1524 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1525 & IXGBE_ATR_HASH_MASK);
1526 first_seg->hash.fdir.id =
1527 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1530 /* Prefetch data of first segment, if configured to do so. */
1531 rte_packet_prefetch((char *)first_seg->buf_addr +
1532 first_seg->data_off);
1535 * Store the mbuf address into the next entry of the array
1536 * of returned packets.
1538 rx_pkts[nb_rx++] = first_seg;
1541 * Setup receipt context for a new packet.
1547 * Record index of the next RX descriptor to probe.
1549 rxq->rx_tail = rx_id;
1552 * Save receive context.
1554 rxq->pkt_first_seg = first_seg;
1555 rxq->pkt_last_seg = last_seg;
1558 * If the number of free RX descriptors is greater than the RX free
1559 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1561 * Update the RDT with the value of the last processed RX descriptor
1562 * minus 1, to guarantee that the RDT register is never equal to the
1563 * RDH register, which creates a "full" ring situtation from the
1564 * hardware point of view...
1566 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1567 if (nb_hold > rxq->rx_free_thresh) {
1568 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1569 "nb_hold=%u nb_rx=%u",
1570 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1571 (unsigned) rx_id, (unsigned) nb_hold,
1573 rx_id = (uint16_t) ((rx_id == 0) ?
1574 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1575 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1578 rxq->nb_rx_hold = nb_hold;
1582 /*********************************************************************
1584 * Queue management functions
1586 **********************************************************************/
1589 * Rings setup and release.
1591 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1592 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1593 * also optimize cache line size effect. H/W supports up to cache line size 128.
1595 #define IXGBE_ALIGN 128
1598 * Maximum number of Ring Descriptors.
1600 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1601 * descriptors should meet the following condition:
1602 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1604 #define IXGBE_MIN_RING_DESC 32
1605 #define IXGBE_MAX_RING_DESC 4096
1608 * Create memzone for HW rings. malloc can't be used as the physical address is
1609 * needed. If the memzone is already created, then this function returns a ptr
1612 static const struct rte_memzone *
1613 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1614 uint16_t queue_id, uint32_t ring_size, int socket_id)
1616 char z_name[RTE_MEMZONE_NAMESIZE];
1617 const struct rte_memzone *mz;
1619 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1620 dev->driver->pci_drv.name, ring_name,
1621 dev->data->port_id, queue_id);
1623 mz = rte_memzone_lookup(z_name);
1627 #ifdef RTE_LIBRTE_XEN_DOM0
1628 return rte_memzone_reserve_bounded(z_name, ring_size,
1629 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1631 return rte_memzone_reserve_aligned(z_name, ring_size,
1632 socket_id, 0, IXGBE_ALIGN);
1637 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1641 if (txq->sw_ring != NULL) {
1642 for (i = 0; i < txq->nb_tx_desc; i++) {
1643 if (txq->sw_ring[i].mbuf != NULL) {
1644 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1645 txq->sw_ring[i].mbuf = NULL;
1652 ixgbe_tx_free_swring(struct igb_tx_queue *txq)
1655 txq->sw_ring != NULL)
1656 rte_free(txq->sw_ring);
1660 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1662 if (txq != NULL && txq->ops != NULL) {
1663 txq->ops->release_mbufs(txq);
1664 txq->ops->free_swring(txq);
1670 ixgbe_dev_tx_queue_release(void *txq)
1672 ixgbe_tx_queue_release(txq);
1675 /* (Re)set dynamic igb_tx_queue fields to defaults */
1677 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1679 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1681 struct igb_tx_entry *txe = txq->sw_ring;
1684 /* Zero out HW ring memory */
1685 for (i = 0; i < txq->nb_tx_desc; i++) {
1686 txq->tx_ring[i] = zeroed_desc;
1689 /* Initialize SW ring entries */
1690 prev = (uint16_t) (txq->nb_tx_desc - 1);
1691 for (i = 0; i < txq->nb_tx_desc; i++) {
1692 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1693 txd->wb.status = IXGBE_TXD_STAT_DD;
1696 txe[prev].next_id = i;
1700 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1701 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1704 txq->nb_tx_used = 0;
1706 * Always allow 1 descriptor to be un-allocated to avoid
1707 * a H/W race condition
1709 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1710 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1712 memset((void*)&txq->ctx_cache, 0,
1713 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1716 static struct ixgbe_txq_ops def_txq_ops = {
1717 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1718 .free_swring = ixgbe_tx_free_swring,
1719 .reset = ixgbe_reset_tx_queue,
1723 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1726 unsigned int socket_id,
1727 const struct rte_eth_txconf *tx_conf)
1729 const struct rte_memzone *tz;
1730 struct igb_tx_queue *txq;
1731 struct ixgbe_hw *hw;
1732 uint16_t tx_rs_thresh, tx_free_thresh;
1734 PMD_INIT_FUNC_TRACE();
1735 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1738 * Validate number of transmit descriptors.
1739 * It must not exceed hardware maximum, and must be multiple
1742 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1743 (nb_desc > IXGBE_MAX_RING_DESC) ||
1744 (nb_desc < IXGBE_MIN_RING_DESC)) {
1749 * The following two parameters control the setting of the RS bit on
1750 * transmit descriptors.
1751 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1752 * descriptors have been used.
1753 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1754 * descriptors are used or if the number of descriptors required
1755 * to transmit a packet is greater than the number of free TX
1757 * The following constraints must be satisfied:
1758 * tx_rs_thresh must be greater than 0.
1759 * tx_rs_thresh must be less than the size of the ring minus 2.
1760 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1761 * tx_rs_thresh must be a divisor of the ring size.
1762 * tx_free_thresh must be greater than 0.
1763 * tx_free_thresh must be less than the size of the ring minus 3.
1764 * One descriptor in the TX ring is used as a sentinel to avoid a
1765 * H/W race condition, hence the maximum threshold constraints.
1766 * When set to zero use default values.
1768 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1769 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1770 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1771 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1772 if (tx_rs_thresh >= (nb_desc - 2)) {
1773 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
1774 "of TX descriptors minus 2. (tx_rs_thresh=%u "
1775 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1776 (int)dev->data->port_id, (int)queue_idx);
1779 if (tx_free_thresh >= (nb_desc - 3)) {
1780 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1781 "tx_free_thresh must be less than the number of "
1782 "TX descriptors minus 3. (tx_free_thresh=%u "
1783 "port=%d queue=%d)",
1784 (unsigned int)tx_free_thresh,
1785 (int)dev->data->port_id, (int)queue_idx);
1788 if (tx_rs_thresh > tx_free_thresh) {
1789 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
1790 "tx_free_thresh. (tx_free_thresh=%u "
1791 "tx_rs_thresh=%u port=%d queue=%d)",
1792 (unsigned int)tx_free_thresh,
1793 (unsigned int)tx_rs_thresh,
1794 (int)dev->data->port_id,
1798 if ((nb_desc % tx_rs_thresh) != 0) {
1799 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1800 "number of TX descriptors. (tx_rs_thresh=%u "
1801 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1802 (int)dev->data->port_id, (int)queue_idx);
1807 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1808 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1809 * by the NIC and all descriptors are written back after the NIC
1810 * accumulates WTHRESH descriptors.
1812 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1813 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1814 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1815 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1816 (int)dev->data->port_id, (int)queue_idx);
1820 /* Free memory prior to re-allocation if needed... */
1821 if (dev->data->tx_queues[queue_idx] != NULL) {
1822 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1823 dev->data->tx_queues[queue_idx] = NULL;
1826 /* First allocate the tx queue data structure */
1827 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct igb_tx_queue),
1828 CACHE_LINE_SIZE, socket_id);
1833 * Allocate TX ring hardware descriptors. A memzone large enough to
1834 * handle the maximum ring size is allocated in order to allow for
1835 * resizing in later calls to the queue setup function.
1837 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1838 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1841 ixgbe_tx_queue_release(txq);
1845 txq->nb_tx_desc = nb_desc;
1846 txq->tx_rs_thresh = tx_rs_thresh;
1847 txq->tx_free_thresh = tx_free_thresh;
1848 txq->pthresh = tx_conf->tx_thresh.pthresh;
1849 txq->hthresh = tx_conf->tx_thresh.hthresh;
1850 txq->wthresh = tx_conf->tx_thresh.wthresh;
1851 txq->queue_id = queue_idx;
1852 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1853 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1854 txq->port_id = dev->data->port_id;
1855 txq->txq_flags = tx_conf->txq_flags;
1856 txq->ops = &def_txq_ops;
1857 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1860 * Modification to set VFTDT for virtual function if vf is detected
1862 if (hw->mac.type == ixgbe_mac_82599_vf)
1863 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1865 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1866 #ifndef RTE_LIBRTE_XEN_DOM0
1867 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1869 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1871 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1873 /* Allocate software ring */
1874 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1875 sizeof(struct igb_tx_entry) * nb_desc,
1876 CACHE_LINE_SIZE, socket_id);
1877 if (txq->sw_ring == NULL) {
1878 ixgbe_tx_queue_release(txq);
1881 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1882 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1884 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1885 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
1886 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1887 PMD_INIT_LOG(INFO, "Using simple tx code path");
1888 #ifdef RTE_IXGBE_INC_VECTOR
1889 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1890 ixgbe_txq_vec_setup(txq) == 0) {
1891 PMD_INIT_LOG(INFO, "Vector tx enabled.");
1892 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1896 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1898 PMD_INIT_LOG(INFO, "Using full-featured tx code path");
1899 PMD_INIT_LOG(INFO, " - txq_flags = %lx "
1900 "[IXGBE_SIMPLE_FLAGS=%lx]",
1901 (long unsigned)txq->txq_flags,
1902 (long unsigned)IXGBE_SIMPLE_FLAGS);
1903 PMD_INIT_LOG(INFO, " - tx_rs_thresh = %lu "
1904 "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
1905 (long unsigned)txq->tx_rs_thresh,
1906 (long unsigned)RTE_PMD_IXGBE_TX_MAX_BURST);
1907 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1910 txq->ops->reset(txq);
1912 dev->data->tx_queues[queue_idx] = txq;
1919 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1923 if (rxq->sw_ring != NULL) {
1924 for (i = 0; i < rxq->nb_rx_desc; i++) {
1925 if (rxq->sw_ring[i].mbuf != NULL) {
1926 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1927 rxq->sw_ring[i].mbuf = NULL;
1930 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1931 if (rxq->rx_nb_avail) {
1932 for (i = 0; i < rxq->rx_nb_avail; ++i) {
1933 struct rte_mbuf *mb;
1934 mb = rxq->rx_stage[rxq->rx_next_avail + i];
1935 rte_pktmbuf_free_seg(mb);
1937 rxq->rx_nb_avail = 0;
1944 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
1947 ixgbe_rx_queue_release_mbufs(rxq);
1948 rte_free(rxq->sw_ring);
1954 ixgbe_dev_rx_queue_release(void *rxq)
1956 ixgbe_rx_queue_release(rxq);
1960 * Check if Rx Burst Bulk Alloc function can be used.
1962 * 0: the preconditions are satisfied and the bulk allocation function
1964 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
1965 * function must be used.
1968 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1969 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
1971 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct igb_rx_queue *rxq)
1977 * Make sure the following pre-conditions are satisfied:
1978 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
1979 * rxq->rx_free_thresh < rxq->nb_rx_desc
1980 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
1981 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
1982 * Scattered packets are not supported. This should be checked
1983 * outside of this function.
1985 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1986 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
1987 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
1988 "rxq->rx_free_thresh=%d, "
1989 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
1990 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
1992 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
1993 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
1994 "rxq->rx_free_thresh=%d, "
1995 "rxq->nb_rx_desc=%d",
1996 rxq->rx_free_thresh, rxq->nb_rx_desc);
1998 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
1999 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2000 "rxq->nb_rx_desc=%d, "
2001 "rxq->rx_free_thresh=%d",
2002 rxq->nb_rx_desc, rxq->rx_free_thresh);
2004 } else if (!(rxq->nb_rx_desc <
2005 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2006 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2007 "rxq->nb_rx_desc=%d, "
2008 "IXGBE_MAX_RING_DESC=%d, "
2009 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2010 rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2011 RTE_PMD_IXGBE_RX_MAX_BURST);
2021 /* Reset dynamic igb_rx_queue fields back to defaults */
2023 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
2025 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
2031 * By default, the Rx queue setup function allocates enough memory for
2032 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2033 * extra memory at the end of the descriptor ring to be zero'd out. A
2034 * pre-condition for using the Rx burst bulk alloc function is that the
2035 * number of descriptors is less than or equal to
2036 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2037 * constraints here to see if we need to zero out memory after the end
2038 * of the H/W descriptor ring.
2040 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2041 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2042 /* zero out extra memory */
2043 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2046 /* do not zero out extra memory */
2047 len = rxq->nb_rx_desc;
2050 * Zero out HW ring memory. Zero out extra memory at the end of
2051 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2052 * reads extra memory as zeros.
2054 for (i = 0; i < len; i++) {
2055 rxq->rx_ring[i] = zeroed_desc;
2058 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2060 * initialize extra software ring entries. Space for these extra
2061 * entries is always allocated
2063 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2064 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2065 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2068 rxq->rx_nb_avail = 0;
2069 rxq->rx_next_avail = 0;
2070 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2071 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2073 rxq->nb_rx_hold = 0;
2074 rxq->pkt_first_seg = NULL;
2075 rxq->pkt_last_seg = NULL;
2079 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2082 unsigned int socket_id,
2083 const struct rte_eth_rxconf *rx_conf,
2084 struct rte_mempool *mp)
2086 const struct rte_memzone *rz;
2087 struct igb_rx_queue *rxq;
2088 struct ixgbe_hw *hw;
2089 int use_def_burst_func = 1;
2092 PMD_INIT_FUNC_TRACE();
2093 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2096 * Validate number of receive descriptors.
2097 * It must not exceed hardware maximum, and must be multiple
2100 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2101 (nb_desc > IXGBE_MAX_RING_DESC) ||
2102 (nb_desc < IXGBE_MIN_RING_DESC)) {
2106 /* Free memory prior to re-allocation if needed... */
2107 if (dev->data->rx_queues[queue_idx] != NULL) {
2108 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2109 dev->data->rx_queues[queue_idx] = NULL;
2112 /* First allocate the rx queue data structure */
2113 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct igb_rx_queue),
2114 CACHE_LINE_SIZE, socket_id);
2118 rxq->nb_rx_desc = nb_desc;
2119 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2120 rxq->queue_id = queue_idx;
2121 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2122 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2123 rxq->port_id = dev->data->port_id;
2124 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2126 rxq->drop_en = rx_conf->rx_drop_en;
2127 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2130 * Allocate RX ring hardware descriptors. A memzone large enough to
2131 * handle the maximum ring size is allocated in order to allow for
2132 * resizing in later calls to the queue setup function.
2134 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2135 RX_RING_SZ, socket_id);
2137 ixgbe_rx_queue_release(rxq);
2142 * Zero init all the descriptors in the ring.
2144 memset (rz->addr, 0, RX_RING_SZ);
2147 * Modified to setup VFRDT for Virtual Function
2149 if (hw->mac.type == ixgbe_mac_82599_vf) {
2151 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2153 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2157 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2159 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2161 #ifndef RTE_LIBRTE_XEN_DOM0
2162 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2164 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2166 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2169 * Allocate software ring. Allow for space at the end of the
2170 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2171 * function does not access an invalid memory region.
2173 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2174 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2178 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2179 sizeof(struct igb_rx_entry) * len,
2180 CACHE_LINE_SIZE, socket_id);
2181 if (rxq->sw_ring == NULL) {
2182 ixgbe_rx_queue_release(rxq);
2185 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2186 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2189 * Certain constraints must be met in order to use the bulk buffer
2190 * allocation Rx burst function.
2192 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2194 #ifdef RTE_IXGBE_INC_VECTOR
2195 ixgbe_rxq_vec_setup(rxq);
2197 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2198 if (!use_def_burst_func && !dev->data->scattered_rx) {
2199 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2200 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2201 "satisfied. Rx Burst Bulk Alloc function will be "
2202 "used on port=%d, queue=%d.",
2203 rxq->port_id, rxq->queue_id);
2204 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2205 #ifdef RTE_IXGBE_INC_VECTOR
2206 if (!ixgbe_rx_vec_condition_check(dev)) {
2207 PMD_INIT_LOG(INFO, "Vector rx enabled, please make "
2208 "sure RX burst size no less than 32.");
2209 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
2214 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2215 "are not satisfied, Scattered Rx is requested, "
2216 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2217 "enabled (port=%d, queue=%d).",
2218 rxq->port_id, rxq->queue_id);
2220 dev->data->rx_queues[queue_idx] = rxq;
2222 ixgbe_reset_rx_queue(rxq);
2228 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2230 #define IXGBE_RXQ_SCAN_INTERVAL 4
2231 volatile union ixgbe_adv_rx_desc *rxdp;
2232 struct igb_rx_queue *rxq;
2235 if (rx_queue_id >= dev->data->nb_rx_queues) {
2236 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2240 rxq = dev->data->rx_queues[rx_queue_id];
2241 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2243 while ((desc < rxq->nb_rx_desc) &&
2244 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2245 desc += IXGBE_RXQ_SCAN_INTERVAL;
2246 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2247 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2248 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2249 desc - rxq->nb_rx_desc]);
2256 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2258 volatile union ixgbe_adv_rx_desc *rxdp;
2259 struct igb_rx_queue *rxq = rx_queue;
2262 if (unlikely(offset >= rxq->nb_rx_desc))
2264 desc = rxq->rx_tail + offset;
2265 if (desc >= rxq->nb_rx_desc)
2266 desc -= rxq->nb_rx_desc;
2268 rxdp = &rxq->rx_ring[desc];
2269 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2273 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2277 PMD_INIT_FUNC_TRACE();
2279 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2280 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2282 txq->ops->release_mbufs(txq);
2283 txq->ops->reset(txq);
2287 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2288 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2290 ixgbe_rx_queue_release_mbufs(rxq);
2291 ixgbe_reset_rx_queue(rxq);
2296 /*********************************************************************
2298 * Device RX/TX init functions
2300 **********************************************************************/
2303 * Receive Side Scaling (RSS)
2304 * See section 7.1.2.8 in the following document:
2305 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2308 * The source and destination IP addresses of the IP header and the source
2309 * and destination ports of TCP/UDP headers, if any, of received packets are
2310 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2311 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2312 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2313 * RSS output index which is used as the RX queue index where to store the
2315 * The following output is supplied in the RX write-back descriptor:
2316 * - 32-bit result of the Microsoft RSS hash function,
2317 * - 4-bit RSS type field.
2321 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2322 * Used as the default key.
2324 static uint8_t rss_intel_key[40] = {
2325 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2326 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2327 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2328 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2329 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2333 ixgbe_rss_disable(struct rte_eth_dev *dev)
2335 struct ixgbe_hw *hw;
2338 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2339 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2340 mrqc &= ~IXGBE_MRQC_RSSEN;
2341 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2345 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2353 hash_key = rss_conf->rss_key;
2354 if (hash_key != NULL) {
2355 /* Fill in RSS hash key */
2356 for (i = 0; i < 10; i++) {
2357 rss_key = hash_key[(i * 4)];
2358 rss_key |= hash_key[(i * 4) + 1] << 8;
2359 rss_key |= hash_key[(i * 4) + 2] << 16;
2360 rss_key |= hash_key[(i * 4) + 3] << 24;
2361 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2365 /* Set configured hashing protocols in MRQC register */
2366 rss_hf = rss_conf->rss_hf;
2367 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2368 if (rss_hf & ETH_RSS_IPV4)
2369 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2370 if (rss_hf & ETH_RSS_IPV4_TCP)
2371 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2372 if (rss_hf & ETH_RSS_IPV6)
2373 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2374 if (rss_hf & ETH_RSS_IPV6_EX)
2375 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2376 if (rss_hf & ETH_RSS_IPV6_TCP)
2377 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2378 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2379 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2380 if (rss_hf & ETH_RSS_IPV4_UDP)
2381 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2382 if (rss_hf & ETH_RSS_IPV6_UDP)
2383 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2384 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2385 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2386 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2390 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2391 struct rte_eth_rss_conf *rss_conf)
2393 struct ixgbe_hw *hw;
2397 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2400 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2401 * "RSS enabling cannot be done dynamically while it must be
2402 * preceded by a software reset"
2403 * Before changing anything, first check that the update RSS operation
2404 * does not attempt to disable RSS, if RSS was enabled at
2405 * initialization time, or does not attempt to enable RSS, if RSS was
2406 * disabled at initialization time.
2408 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2409 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2410 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2411 if (rss_hf != 0) /* Enable RSS */
2413 return 0; /* Nothing to do */
2416 if (rss_hf == 0) /* Disable RSS */
2418 ixgbe_hw_rss_hash_set(hw, rss_conf);
2423 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2424 struct rte_eth_rss_conf *rss_conf)
2426 struct ixgbe_hw *hw;
2433 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2434 hash_key = rss_conf->rss_key;
2435 if (hash_key != NULL) {
2436 /* Return RSS hash key */
2437 for (i = 0; i < 10; i++) {
2438 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2439 hash_key[(i * 4)] = rss_key & 0x000000FF;
2440 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2441 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2442 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2446 /* Get RSS functions configured in MRQC register */
2447 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2448 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2449 rss_conf->rss_hf = 0;
2453 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2454 rss_hf |= ETH_RSS_IPV4;
2455 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2456 rss_hf |= ETH_RSS_IPV4_TCP;
2457 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2458 rss_hf |= ETH_RSS_IPV6;
2459 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2460 rss_hf |= ETH_RSS_IPV6_EX;
2461 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2462 rss_hf |= ETH_RSS_IPV6_TCP;
2463 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2464 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2465 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2466 rss_hf |= ETH_RSS_IPV4_UDP;
2467 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2468 rss_hf |= ETH_RSS_IPV6_UDP;
2469 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2470 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2471 rss_conf->rss_hf = rss_hf;
2476 ixgbe_rss_configure(struct rte_eth_dev *dev)
2478 struct rte_eth_rss_conf rss_conf;
2479 struct ixgbe_hw *hw;
2484 PMD_INIT_FUNC_TRACE();
2485 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2488 * Fill in redirection table
2489 * The byte-swap is needed because NIC registers are in
2490 * little-endian order.
2493 for (i = 0, j = 0; i < 128; i++, j++) {
2494 if (j == dev->data->nb_rx_queues)
2496 reta = (reta << 8) | j;
2498 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2503 * Configure the RSS key and the RSS protocols used to compute
2504 * the RSS hash of input packets.
2506 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2507 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2508 ixgbe_rss_disable(dev);
2511 if (rss_conf.rss_key == NULL)
2512 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2513 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2516 #define NUM_VFTA_REGISTERS 128
2517 #define NIC_RX_BUFFER_SIZE 0x200
2520 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2522 struct rte_eth_vmdq_dcb_conf *cfg;
2523 struct ixgbe_hw *hw;
2524 enum rte_eth_nb_pools num_pools;
2525 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2527 uint8_t nb_tcs; /* number of traffic classes */
2530 PMD_INIT_FUNC_TRACE();
2531 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2532 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2533 num_pools = cfg->nb_queue_pools;
2534 /* Check we have a valid number of pools */
2535 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2536 ixgbe_rss_disable(dev);
2539 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2540 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2544 * split rx buffer up into sections, each for 1 traffic class
2546 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2547 for (i = 0 ; i < nb_tcs; i++) {
2548 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2549 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2550 /* clear 10 bits. */
2551 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2552 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2554 /* zero alloc all unused TCs */
2555 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2556 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2557 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2558 /* clear 10 bits. */
2559 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2562 /* MRQC: enable vmdq and dcb */
2563 mrqc = ((num_pools == ETH_16_POOLS) ? \
2564 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2565 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2567 /* PFVTCTL: turn on virtualisation and set the default pool */
2568 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2569 if (cfg->enable_default_pool) {
2570 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2572 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2575 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2577 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2579 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2581 * mapping is done with 3 bits per priority,
2582 * so shift by i*3 each time
2584 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2586 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2588 /* RTRPCS: DCB related */
2589 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2591 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2592 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2593 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2594 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2596 /* VFTA - enable all vlan filters */
2597 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2598 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2601 /* VFRE: pool enabling for receive - 16 or 32 */
2602 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2603 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2606 * MPSAR - allow pools to read specific mac addresses
2607 * In this case, all pools should be able to read from mac addr 0
2609 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2610 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2612 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2613 for (i = 0; i < cfg->nb_pool_maps; i++) {
2614 /* set vlan id in VF register and set the valid bit */
2615 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2616 (cfg->pool_map[i].vlan_id & 0xFFF)));
2618 * Put the allowed pools in VFB reg. As we only have 16 or 32
2619 * pools, we only need to use the first half of the register
2622 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2627 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2628 * @hw: pointer to hardware structure
2629 * @dcb_config: pointer to ixgbe_dcb_config structure
2632 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2633 struct ixgbe_dcb_config *dcb_config)
2638 PMD_INIT_FUNC_TRACE();
2639 if (hw->mac.type != ixgbe_mac_82598EB) {
2640 /* Disable the Tx desc arbiter so that MTQC can be changed */
2641 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2642 reg |= IXGBE_RTTDCS_ARBDIS;
2643 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2645 /* Enable DCB for Tx with 8 TCs */
2646 if (dcb_config->num_tcs.pg_tcs == 8) {
2647 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2650 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2652 if (dcb_config->vt_mode)
2653 reg |= IXGBE_MTQC_VT_ENA;
2654 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2656 /* Disable drop for all queues */
2657 for (q = 0; q < 128; q++)
2658 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2659 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2661 /* Enable the Tx desc arbiter */
2662 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2663 reg &= ~IXGBE_RTTDCS_ARBDIS;
2664 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2666 /* Enable Security TX Buffer IFG for DCB */
2667 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2668 reg |= IXGBE_SECTX_DCB;
2669 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2675 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2676 * @dev: pointer to rte_eth_dev structure
2677 * @dcb_config: pointer to ixgbe_dcb_config structure
2680 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2681 struct ixgbe_dcb_config *dcb_config)
2683 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2684 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2685 struct ixgbe_hw *hw =
2686 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2688 PMD_INIT_FUNC_TRACE();
2689 if (hw->mac.type != ixgbe_mac_82598EB)
2690 /*PF VF Transmit Enable*/
2691 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2692 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2694 /*Configure general DCB TX parameters*/
2695 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2700 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2701 struct ixgbe_dcb_config *dcb_config)
2703 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2704 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2705 struct ixgbe_dcb_tc_config *tc;
2708 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2709 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2710 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2711 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2714 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2715 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2717 /* User Priority to Traffic Class mapping */
2718 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2719 j = vmdq_rx_conf->dcb_queue[i];
2720 tc = &dcb_config->tc_config[j];
2721 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2727 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2728 struct ixgbe_dcb_config *dcb_config)
2730 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2731 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2732 struct ixgbe_dcb_tc_config *tc;
2735 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2736 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2737 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2738 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2741 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2742 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2745 /* User Priority to Traffic Class mapping */
2746 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2747 j = vmdq_tx_conf->dcb_queue[i];
2748 tc = &dcb_config->tc_config[j];
2749 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2756 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2757 struct ixgbe_dcb_config *dcb_config)
2759 struct rte_eth_dcb_rx_conf *rx_conf =
2760 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2761 struct ixgbe_dcb_tc_config *tc;
2764 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2765 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2767 /* User Priority to Traffic Class mapping */
2768 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2769 j = rx_conf->dcb_queue[i];
2770 tc = &dcb_config->tc_config[j];
2771 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2777 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2778 struct ixgbe_dcb_config *dcb_config)
2780 struct rte_eth_dcb_tx_conf *tx_conf =
2781 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2782 struct ixgbe_dcb_tc_config *tc;
2785 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2786 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2788 /* User Priority to Traffic Class mapping */
2789 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2790 j = tx_conf->dcb_queue[i];
2791 tc = &dcb_config->tc_config[j];
2792 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2798 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2799 * @hw: pointer to hardware structure
2800 * @dcb_config: pointer to ixgbe_dcb_config structure
2803 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2804 struct ixgbe_dcb_config *dcb_config)
2810 PMD_INIT_FUNC_TRACE();
2812 * Disable the arbiter before changing parameters
2813 * (always enable recycle mode; WSP)
2815 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2816 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2818 if (hw->mac.type != ixgbe_mac_82598EB) {
2819 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2820 if (dcb_config->num_tcs.pg_tcs == 4) {
2821 if (dcb_config->vt_mode)
2822 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2823 IXGBE_MRQC_VMDQRT4TCEN;
2825 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2826 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2830 if (dcb_config->num_tcs.pg_tcs == 8) {
2831 if (dcb_config->vt_mode)
2832 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2833 IXGBE_MRQC_VMDQRT8TCEN;
2835 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2836 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2841 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2844 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2845 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2846 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2847 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2849 /* VFTA - enable all vlan filters */
2850 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2851 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2855 * Configure Rx packet plane (recycle mode; WSP) and
2858 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2859 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2865 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2866 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2868 switch (hw->mac.type) {
2869 case ixgbe_mac_82598EB:
2870 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2872 case ixgbe_mac_82599EB:
2873 case ixgbe_mac_X540:
2874 case ixgbe_mac_X550:
2875 case ixgbe_mac_X550EM_x:
2876 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2885 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2886 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2888 switch (hw->mac.type) {
2889 case ixgbe_mac_82598EB:
2890 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2891 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2893 case ixgbe_mac_82599EB:
2894 case ixgbe_mac_X540:
2895 case ixgbe_mac_X550:
2896 case ixgbe_mac_X550EM_x:
2897 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2898 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2905 #define DCB_RX_CONFIG 1
2906 #define DCB_TX_CONFIG 1
2907 #define DCB_TX_PB 1024
2909 * ixgbe_dcb_hw_configure - Enable DCB and configure
2910 * general DCB in VT mode and non-VT mode parameters
2911 * @dev: pointer to rte_eth_dev structure
2912 * @dcb_config: pointer to ixgbe_dcb_config structure
2915 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2916 struct ixgbe_dcb_config *dcb_config)
2919 uint8_t i,pfc_en,nb_tcs;
2921 uint8_t config_dcb_rx = 0;
2922 uint8_t config_dcb_tx = 0;
2923 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2924 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2925 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2926 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2927 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2928 struct ixgbe_dcb_tc_config *tc;
2929 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2930 struct ixgbe_hw *hw =
2931 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2933 switch(dev->data->dev_conf.rxmode.mq_mode){
2934 case ETH_MQ_RX_VMDQ_DCB:
2935 dcb_config->vt_mode = true;
2936 if (hw->mac.type != ixgbe_mac_82598EB) {
2937 config_dcb_rx = DCB_RX_CONFIG;
2939 *get dcb and VT rx configuration parameters
2942 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2943 /*Configure general VMDQ and DCB RX parameters*/
2944 ixgbe_vmdq_dcb_configure(dev);
2948 dcb_config->vt_mode = false;
2949 config_dcb_rx = DCB_RX_CONFIG;
2950 /* Get dcb TX configuration parameters from rte_eth_conf */
2951 ixgbe_dcb_rx_config(dev,dcb_config);
2952 /*Configure general DCB RX parameters*/
2953 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2956 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
2959 switch (dev->data->dev_conf.txmode.mq_mode) {
2960 case ETH_MQ_TX_VMDQ_DCB:
2961 dcb_config->vt_mode = true;
2962 config_dcb_tx = DCB_TX_CONFIG;
2963 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2964 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2965 /*Configure general VMDQ and DCB TX parameters*/
2966 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2970 dcb_config->vt_mode = false;
2971 config_dcb_tx = DCB_TX_CONFIG;
2972 /*get DCB TX configuration parameters from rte_eth_conf*/
2973 ixgbe_dcb_tx_config(dev,dcb_config);
2974 /*Configure general DCB TX parameters*/
2975 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2978 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
2982 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2984 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2985 if(nb_tcs == ETH_4_TCS) {
2986 /* Avoid un-configured priority mapping to TC0 */
2988 uint8_t mask = 0xFF;
2989 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
2990 mask = (uint8_t)(mask & (~ (1 << map[i])));
2991 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
2992 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
2996 /* Re-configure 4 TCs BW */
2997 for (i = 0; i < nb_tcs; i++) {
2998 tc = &dcb_config->tc_config[i];
2999 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3000 (uint8_t)(100 / nb_tcs);
3001 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3002 (uint8_t)(100 / nb_tcs);
3004 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3005 tc = &dcb_config->tc_config[i];
3006 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3007 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3012 /* Set RX buffer size */
3013 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3014 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3015 for (i = 0 ; i < nb_tcs; i++) {
3016 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3018 /* zero alloc all unused TCs */
3019 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3020 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3024 /* Only support an equally distributed Tx packet buffer strategy. */
3025 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3026 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3027 for (i = 0; i < nb_tcs; i++) {
3028 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3029 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3031 /* Clear unused TCs, if any, to zero buffer size*/
3032 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3033 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3034 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3038 /*Calculates traffic class credits*/
3039 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3040 IXGBE_DCB_TX_CONFIG);
3041 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3042 IXGBE_DCB_RX_CONFIG);
3045 /* Unpack CEE standard containers */
3046 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3047 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3048 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3049 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3050 /* Configure PG(ETS) RX */
3051 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3055 /* Unpack CEE standard containers */
3056 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3057 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3058 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3059 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3060 /* Configure PG(ETS) TX */
3061 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3064 /*Configure queue statistics registers*/
3065 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3067 /* Check if the PFC is supported */
3068 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3069 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3070 for (i = 0; i < nb_tcs; i++) {
3072 * If the TC count is 8,and the default high_water is 48,
3073 * the low_water is 16 as default.
3075 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3076 hw->fc.low_water[i] = pbsize / 4;
3077 /* Enable pfc for this TC */
3078 tc = &dcb_config->tc_config[i];
3079 tc->pfc = ixgbe_dcb_pfc_enabled;
3081 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3082 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3084 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3091 * ixgbe_configure_dcb - Configure DCB Hardware
3092 * @dev: pointer to rte_eth_dev
3094 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3096 struct ixgbe_dcb_config *dcb_cfg =
3097 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3098 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3100 PMD_INIT_FUNC_TRACE();
3102 /* check support mq_mode for DCB */
3103 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3104 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3107 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3110 /** Configure DCB hardware **/
3111 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3117 * VMDq only support for 10 GbE NIC.
3120 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3122 struct rte_eth_vmdq_rx_conf *cfg;
3123 struct ixgbe_hw *hw;
3124 enum rte_eth_nb_pools num_pools;
3125 uint32_t mrqc, vt_ctl, vlanctrl;
3129 PMD_INIT_FUNC_TRACE();
3130 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3131 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3132 num_pools = cfg->nb_queue_pools;
3134 ixgbe_rss_disable(dev);
3136 /* MRQC: enable vmdq */
3137 mrqc = IXGBE_MRQC_VMDQEN;
3138 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3140 /* PFVTCTL: turn on virtualisation and set the default pool */
3141 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3142 if (cfg->enable_default_pool)
3143 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3145 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3147 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3149 for (i = 0; i < (int)num_pools; i++) {
3150 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
3151 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
3154 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3155 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3156 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3157 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3159 /* VFTA - enable all vlan filters */
3160 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3161 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3163 /* VFRE: pool enabling for receive - 64 */
3164 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3165 if (num_pools == ETH_64_POOLS)
3166 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3169 * MPSAR - allow pools to read specific mac addresses
3170 * In this case, all pools should be able to read from mac addr 0
3172 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3173 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3175 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3176 for (i = 0; i < cfg->nb_pool_maps; i++) {
3177 /* set vlan id in VF register and set the valid bit */
3178 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3179 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3181 * Put the allowed pools in VFB reg. As we only have 16 or 64
3182 * pools, we only need to use the first half of the register
3185 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3186 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3187 (cfg->pool_map[i].pools & UINT32_MAX));
3189 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3190 ((cfg->pool_map[i].pools >> 32) \
3195 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3196 if (cfg->enable_loop_back) {
3197 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3198 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3199 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3202 IXGBE_WRITE_FLUSH(hw);
3206 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3207 * @hw: pointer to hardware structure
3210 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3215 PMD_INIT_FUNC_TRACE();
3216 /*PF VF Transmit Enable*/
3217 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3218 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3220 /* Disable the Tx desc arbiter so that MTQC can be changed */
3221 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3222 reg |= IXGBE_RTTDCS_ARBDIS;
3223 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3225 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3226 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3228 /* Disable drop for all queues */
3229 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3230 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3231 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3233 /* Enable the Tx desc arbiter */
3234 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3235 reg &= ~IXGBE_RTTDCS_ARBDIS;
3236 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3238 IXGBE_WRITE_FLUSH(hw);
3244 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
3246 struct igb_rx_entry *rxe = rxq->sw_ring;
3250 /* Initialize software ring entries */
3251 for (i = 0; i < rxq->nb_rx_desc; i++) {
3252 volatile union ixgbe_adv_rx_desc *rxd;
3253 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3255 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3256 (unsigned) rxq->queue_id);
3260 rte_mbuf_refcnt_set(mbuf, 1);
3262 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3264 mbuf->port = rxq->port_id;
3267 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3268 rxd = &rxq->rx_ring[i];
3269 rxd->read.hdr_addr = dma_addr;
3270 rxd->read.pkt_addr = dma_addr;
3278 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3280 struct ixgbe_hw *hw =
3281 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3283 if (hw->mac.type == ixgbe_mac_82598EB)
3286 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3288 * SRIOV inactive scheme
3289 * any DCB/RSS w/o VMDq multi-queue setting
3291 switch (dev->data->dev_conf.rxmode.mq_mode) {
3293 ixgbe_rss_configure(dev);
3296 case ETH_MQ_RX_VMDQ_DCB:
3297 ixgbe_vmdq_dcb_configure(dev);
3300 case ETH_MQ_RX_VMDQ_ONLY:
3301 ixgbe_vmdq_rx_hw_configure(dev);
3304 case ETH_MQ_RX_NONE:
3305 /* if mq_mode is none, disable rss mode.*/
3306 default: ixgbe_rss_disable(dev);
3309 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3311 * SRIOV active scheme
3312 * FIXME if support DCB/RSS together with VMDq & SRIOV
3315 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQEN);
3319 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT4TCEN);
3323 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT8TCEN);
3326 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3334 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3336 struct ixgbe_hw *hw =
3337 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3341 if (hw->mac.type == ixgbe_mac_82598EB)
3344 /* disable arbiter before setting MTQC */
3345 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3346 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3347 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3349 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3351 * SRIOV inactive scheme
3352 * any DCB w/o VMDq multi-queue setting
3354 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3355 ixgbe_vmdq_tx_hw_configure(hw);
3357 mtqc = IXGBE_MTQC_64Q_1PB;
3358 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3361 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3364 * SRIOV active scheme
3365 * FIXME if support DCB together with VMDq & SRIOV
3368 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3371 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3374 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3378 mtqc = IXGBE_MTQC_64Q_1PB;
3379 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3381 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3384 /* re-enable arbiter */
3385 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3386 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3392 * Initializes Receive Unit.
3395 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3397 struct ixgbe_hw *hw;
3398 struct igb_rx_queue *rxq;
3399 struct rte_pktmbuf_pool_private *mbp_priv;
3411 PMD_INIT_FUNC_TRACE();
3412 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3415 * Make sure receives are disabled while setting
3416 * up the RX context (registers, descriptor rings, etc.).
3418 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3419 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3421 /* Enable receipt of broadcasted frames */
3422 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3423 fctrl |= IXGBE_FCTRL_BAM;
3424 fctrl |= IXGBE_FCTRL_DPF;
3425 fctrl |= IXGBE_FCTRL_PMCF;
3426 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3429 * Configure CRC stripping, if any.
3431 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3432 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3433 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3435 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3438 * Configure jumbo frame support, if any.
3440 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3441 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3442 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3443 maxfrs &= 0x0000FFFF;
3444 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3445 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3447 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3450 * If loopback mode is configured for 82599, set LPBK bit.
3452 if (hw->mac.type == ixgbe_mac_82599EB &&
3453 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3454 hlreg0 |= IXGBE_HLREG0_LPBK;
3456 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3458 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3460 /* Setup RX queues */
3461 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3462 rxq = dev->data->rx_queues[i];
3465 * Reset crc_len in case it was changed after queue setup by a
3466 * call to configure.
3468 rxq->crc_len = (uint8_t)
3469 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3472 /* Setup the Base and Length of the Rx Descriptor Rings */
3473 bus_addr = rxq->rx_ring_phys_addr;
3474 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3475 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3476 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3477 (uint32_t)(bus_addr >> 32));
3478 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3479 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3480 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3481 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3483 /* Configure the SRRCTL register */
3484 #ifdef RTE_HEADER_SPLIT_ENABLE
3486 * Configure Header Split
3488 if (dev->data->dev_conf.rxmode.header_split) {
3489 if (hw->mac.type == ixgbe_mac_82599EB) {
3490 /* Must setup the PSRTYPE register */
3492 psrtype = IXGBE_PSRTYPE_TCPHDR |
3493 IXGBE_PSRTYPE_UDPHDR |
3494 IXGBE_PSRTYPE_IPV4HDR |
3495 IXGBE_PSRTYPE_IPV6HDR;
3496 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3498 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3499 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3500 IXGBE_SRRCTL_BSIZEHDR_MASK);
3501 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3504 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3506 /* Set if packets are dropped when no descriptors available */
3508 srrctl |= IXGBE_SRRCTL_DROP_EN;
3511 * Configure the RX buffer size in the BSIZEPACKET field of
3512 * the SRRCTL register of the queue.
3513 * The value is in 1 KB resolution. Valid values can be from
3516 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3517 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3518 RTE_PKTMBUF_HEADROOM);
3519 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3520 IXGBE_SRRCTL_BSIZEPKT_MASK);
3521 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3523 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3524 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3526 /* It adds dual VLAN length for supporting dual VLAN */
3527 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3528 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3529 if (!dev->data->scattered_rx)
3530 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
3531 dev->data->scattered_rx = 1;
3532 #ifdef RTE_IXGBE_INC_VECTOR
3533 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3535 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3540 if (dev->data->dev_conf.rxmode.enable_scatter) {
3541 if (!dev->data->scattered_rx)
3542 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
3543 #ifdef RTE_IXGBE_INC_VECTOR
3544 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3546 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3548 dev->data->scattered_rx = 1;
3552 * Device configured with multiple RX queues.
3554 ixgbe_dev_mq_rx_configure(dev);
3557 * Setup the Checksum Register.
3558 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3559 * Enable IP/L4 checkum computation by hardware if requested to do so.
3561 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3562 rxcsum |= IXGBE_RXCSUM_PCSD;
3563 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3564 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3566 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3568 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3570 if (hw->mac.type == ixgbe_mac_82599EB) {
3571 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3572 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3573 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3575 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3576 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3577 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3584 * Initializes Transmit Unit.
3587 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3589 struct ixgbe_hw *hw;
3590 struct igb_tx_queue *txq;
3596 PMD_INIT_FUNC_TRACE();
3597 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3599 /* Enable TX CRC (checksum offload requirement) */
3600 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3601 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
3602 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3604 /* Setup the Base and Length of the Tx Descriptor Rings */
3605 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3606 txq = dev->data->tx_queues[i];
3608 bus_addr = txq->tx_ring_phys_addr;
3609 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3610 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3611 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3612 (uint32_t)(bus_addr >> 32));
3613 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3614 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3615 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3616 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3617 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3620 * Disable Tx Head Writeback RO bit, since this hoses
3621 * bookkeeping if things aren't delivered in order.
3623 switch (hw->mac.type) {
3624 case ixgbe_mac_82598EB:
3625 txctrl = IXGBE_READ_REG(hw,
3626 IXGBE_DCA_TXCTRL(txq->reg_idx));
3627 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3628 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3632 case ixgbe_mac_82599EB:
3633 case ixgbe_mac_X540:
3634 case ixgbe_mac_X550:
3635 case ixgbe_mac_X550EM_x:
3637 txctrl = IXGBE_READ_REG(hw,
3638 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3639 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3640 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3646 /* Device configured with multiple TX queues. */
3647 ixgbe_dev_mq_tx_configure(dev);
3651 * Set up link for 82599 loopback mode Tx->Rx.
3654 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3656 PMD_INIT_FUNC_TRACE();
3658 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3659 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3661 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
3670 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3671 ixgbe_reset_pipeline_82599(hw);
3673 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3679 * Start Transmit and Receive Units.
3682 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3684 struct ixgbe_hw *hw;
3685 struct igb_tx_queue *txq;
3686 struct igb_rx_queue *rxq;
3692 PMD_INIT_FUNC_TRACE();
3693 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3695 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3696 txq = dev->data->tx_queues[i];
3697 /* Setup Transmit Threshold Registers */
3698 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3699 txdctl |= txq->pthresh & 0x7F;
3700 txdctl |= ((txq->hthresh & 0x7F) << 8);
3701 txdctl |= ((txq->wthresh & 0x7F) << 16);
3702 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3705 if (hw->mac.type != ixgbe_mac_82598EB) {
3706 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3707 dmatxctl |= IXGBE_DMATXCTL_TE;
3708 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3711 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3712 txq = dev->data->tx_queues[i];
3713 if (!txq->tx_deferred_start)
3714 ixgbe_dev_tx_queue_start(dev, i);
3717 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3718 rxq = dev->data->rx_queues[i];
3719 if (!rxq->rx_deferred_start)
3720 ixgbe_dev_rx_queue_start(dev, i);
3723 /* Enable Receive engine */
3724 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3725 if (hw->mac.type == ixgbe_mac_82598EB)
3726 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3727 rxctrl |= IXGBE_RXCTRL_RXEN;
3728 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3730 /* If loopback mode is enabled for 82599, set up the link accordingly */
3731 if (hw->mac.type == ixgbe_mac_82599EB &&
3732 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3733 ixgbe_setup_loopback_link_82599(hw);
3738 * Start Receive Units for specified queue.
3741 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3743 struct ixgbe_hw *hw;
3744 struct igb_rx_queue *rxq;
3748 PMD_INIT_FUNC_TRACE();
3749 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3751 if (rx_queue_id < dev->data->nb_rx_queues) {
3752 rxq = dev->data->rx_queues[rx_queue_id];
3754 /* Allocate buffers for descriptor rings */
3755 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
3756 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
3760 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3761 rxdctl |= IXGBE_RXDCTL_ENABLE;
3762 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3764 /* Wait until RX Enable ready */
3765 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3768 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3769 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3771 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
3774 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3775 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3783 * Stop Receive Units for specified queue.
3786 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3788 struct ixgbe_hw *hw;
3789 struct igb_rx_queue *rxq;
3793 PMD_INIT_FUNC_TRACE();
3794 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3796 if (rx_queue_id < dev->data->nb_rx_queues) {
3797 rxq = dev->data->rx_queues[rx_queue_id];
3799 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3800 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3801 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3803 /* Wait until RX Enable ready */
3804 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3807 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3808 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
3810 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
3813 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3815 ixgbe_rx_queue_release_mbufs(rxq);
3816 ixgbe_reset_rx_queue(rxq);
3825 * Start Transmit Units for specified queue.
3828 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3830 struct ixgbe_hw *hw;
3831 struct igb_tx_queue *txq;
3835 PMD_INIT_FUNC_TRACE();
3836 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3838 if (tx_queue_id < dev->data->nb_tx_queues) {
3839 txq = dev->data->tx_queues[tx_queue_id];
3840 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3841 txdctl |= IXGBE_TXDCTL_ENABLE;
3842 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3844 /* Wait until TX Enable ready */
3845 if (hw->mac.type == ixgbe_mac_82599EB) {
3846 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3849 txdctl = IXGBE_READ_REG(hw,
3850 IXGBE_TXDCTL(txq->reg_idx));
3851 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3853 PMD_INIT_LOG(ERR, "Could not enable "
3854 "Tx Queue %d", tx_queue_id);
3857 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3858 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3866 * Stop Transmit Units for specified queue.
3869 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3871 struct ixgbe_hw *hw;
3872 struct igb_tx_queue *txq;
3874 uint32_t txtdh, txtdt;
3877 PMD_INIT_FUNC_TRACE();
3878 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3880 if (tx_queue_id < dev->data->nb_tx_queues) {
3881 txq = dev->data->tx_queues[tx_queue_id];
3883 /* Wait until TX queue is empty */
3884 if (hw->mac.type == ixgbe_mac_82599EB) {
3885 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3887 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3888 txtdh = IXGBE_READ_REG(hw,
3889 IXGBE_TDH(txq->reg_idx));
3890 txtdt = IXGBE_READ_REG(hw,
3891 IXGBE_TDT(txq->reg_idx));
3892 } while (--poll_ms && (txtdh != txtdt));
3894 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
3895 "when stopping.", tx_queue_id);
3898 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3899 txdctl &= ~IXGBE_TXDCTL_ENABLE;
3900 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3902 /* Wait until TX Enable ready */
3903 if (hw->mac.type == ixgbe_mac_82599EB) {
3904 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3907 txdctl = IXGBE_READ_REG(hw,
3908 IXGBE_TXDCTL(txq->reg_idx));
3909 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
3911 PMD_INIT_LOG(ERR, "Could not disable "
3912 "Tx Queue %d", tx_queue_id);
3915 if (txq->ops != NULL) {
3916 txq->ops->release_mbufs(txq);
3917 txq->ops->reset(txq);
3926 * [VF] Initializes Receive Unit.
3929 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3931 struct ixgbe_hw *hw;
3932 struct igb_rx_queue *rxq;
3933 struct rte_pktmbuf_pool_private *mbp_priv;
3940 PMD_INIT_FUNC_TRACE();
3941 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3944 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
3945 * disables the VF receipt of packets if the PF MTU is > 1500.
3946 * This is done to deal with 82599 limitations that imposes
3947 * the PF and all VFs to share the same MTU.
3948 * Then, the PF driver enables again the VF receipt of packet when
3949 * the VF driver issues a IXGBE_VF_SET_LPE request.
3950 * In the meantime, the VF device cannot be used, even if the VF driver
3951 * and the Guest VM network stack are ready to accept packets with a
3952 * size up to the PF MTU.
3953 * As a work-around to this PF behaviour, force the call to
3954 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
3955 * VF packets received can work in all cases.
3957 ixgbevf_rlpml_set_vf(hw,
3958 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
3960 /* Setup RX queues */
3961 dev->rx_pkt_burst = ixgbe_recv_pkts;
3962 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3963 rxq = dev->data->rx_queues[i];
3965 /* Allocate buffers for descriptor rings */
3966 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3970 /* Setup the Base and Length of the Rx Descriptor Rings */
3971 bus_addr = rxq->rx_ring_phys_addr;
3973 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3974 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3975 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3976 (uint32_t)(bus_addr >> 32));
3977 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3978 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3979 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3980 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3983 /* Configure the SRRCTL register */
3984 #ifdef RTE_HEADER_SPLIT_ENABLE
3986 * Configure Header Split
3988 if (dev->data->dev_conf.rxmode.header_split) {
3990 /* Must setup the PSRTYPE register */
3992 psrtype = IXGBE_PSRTYPE_TCPHDR |
3993 IXGBE_PSRTYPE_UDPHDR |
3994 IXGBE_PSRTYPE_IPV4HDR |
3995 IXGBE_PSRTYPE_IPV6HDR;
3997 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
3999 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
4000 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4001 IXGBE_SRRCTL_BSIZEHDR_MASK);
4002 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4005 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4007 /* Set if packets are dropped when no descriptors available */
4009 srrctl |= IXGBE_SRRCTL_DROP_EN;
4012 * Configure the RX buffer size in the BSIZEPACKET field of
4013 * the SRRCTL register of the queue.
4014 * The value is in 1 KB resolution. Valid values can be from
4017 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
4018 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
4019 RTE_PKTMBUF_HEADROOM);
4020 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4021 IXGBE_SRRCTL_BSIZEPKT_MASK);
4024 * VF modification to write virtual function SRRCTL register
4026 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
4028 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4029 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4031 /* It adds dual VLAN length for supporting dual VLAN */
4032 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
4033 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
4034 if (!dev->data->scattered_rx)
4035 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4036 dev->data->scattered_rx = 1;
4037 #ifdef RTE_IXGBE_INC_VECTOR
4038 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4040 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
4045 if (dev->data->dev_conf.rxmode.enable_scatter) {
4046 if (!dev->data->scattered_rx)
4047 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4048 #ifdef RTE_IXGBE_INC_VECTOR
4049 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4051 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
4053 dev->data->scattered_rx = 1;
4060 * [VF] Initializes Transmit Unit.
4063 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4065 struct ixgbe_hw *hw;
4066 struct igb_tx_queue *txq;
4071 PMD_INIT_FUNC_TRACE();
4072 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4074 /* Setup the Base and Length of the Tx Descriptor Rings */
4075 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4076 txq = dev->data->tx_queues[i];
4077 bus_addr = txq->tx_ring_phys_addr;
4078 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4079 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4080 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4081 (uint32_t)(bus_addr >> 32));
4082 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4083 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4084 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4085 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4086 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4089 * Disable Tx Head Writeback RO bit, since this hoses
4090 * bookkeeping if things aren't delivered in order.
4092 txctrl = IXGBE_READ_REG(hw,
4093 IXGBE_VFDCA_TXCTRL(i));
4094 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4095 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4101 * [VF] Start Transmit and Receive Units.
4104 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4106 struct ixgbe_hw *hw;
4107 struct igb_tx_queue *txq;
4108 struct igb_rx_queue *rxq;
4114 PMD_INIT_FUNC_TRACE();
4115 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4117 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4118 txq = dev->data->tx_queues[i];
4119 /* Setup Transmit Threshold Registers */
4120 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4121 txdctl |= txq->pthresh & 0x7F;
4122 txdctl |= ((txq->hthresh & 0x7F) << 8);
4123 txdctl |= ((txq->wthresh & 0x7F) << 16);
4124 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4127 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4129 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4130 txdctl |= IXGBE_TXDCTL_ENABLE;
4131 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4134 /* Wait until TX Enable ready */
4137 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4138 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4140 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
4142 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4144 rxq = dev->data->rx_queues[i];
4146 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4147 rxdctl |= IXGBE_RXDCTL_ENABLE;
4148 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4150 /* Wait until RX Enable ready */
4154 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4155 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4157 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
4159 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);