4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
47 #include <rte_cycles.h>
49 #include <rte_debug.h>
50 #include <rte_interrupts.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_launch.h>
55 #include <rte_tailq.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
80 #include "ixgbe_rxtx.h"
82 #define IXGBE_RSS_OFFLOAD_ALL ( \
88 ETH_RSS_IPV6_TCP_EX | \
93 /* Bit Mask to indicate what bits required for building TX context */
94 #define IXGBE_TX_OFFLOAD_MASK ( \
99 static inline struct rte_mbuf *
100 rte_rxmbuf_alloc(struct rte_mempool *mp)
104 m = __rte_mbuf_raw_alloc(mp);
105 __rte_mbuf_sanity_check_raw(m, 0);
111 #define RTE_PMD_USE_PREFETCH
114 #ifdef RTE_PMD_USE_PREFETCH
116 * Prefetch a cache line into all cache levels.
118 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
120 #define rte_ixgbe_prefetch(p) do {} while(0)
123 /*********************************************************************
127 **********************************************************************/
130 * Check for descriptors with their DD bit set and free mbufs.
131 * Return the total number of buffers freed.
133 static inline int __attribute__((always_inline))
134 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
136 struct igb_tx_entry *txep;
140 /* check DD bit on threshold descriptor */
141 status = txq->tx_ring[txq->tx_next_dd].wb.status;
142 if (! (status & IXGBE_ADVTXD_STAT_DD))
146 * first buffer to free from S/W ring is at index
147 * tx_next_dd - (tx_rs_thresh-1)
149 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
151 /* free buffers one at a time */
152 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
153 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
154 txep->mbuf->next = NULL;
155 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
159 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
160 rte_pktmbuf_free_seg(txep->mbuf);
165 /* buffers were freed, update counters */
166 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
167 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
168 if (txq->tx_next_dd >= txq->nb_tx_desc)
169 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
171 return txq->tx_rs_thresh;
174 /* Populate 4 descriptors with data from 4 mbufs */
176 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
178 uint64_t buf_dma_addr;
182 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
183 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
184 pkt_len = (*pkts)->data_len;
186 /* write data to descriptor */
187 txdp->read.buffer_addr = buf_dma_addr;
188 txdp->read.cmd_type_len =
189 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
190 txdp->read.olinfo_status =
191 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
192 rte_prefetch0(&(*pkts)->pool);
196 /* Populate 1 descriptor with data from 1 mbuf */
198 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
200 uint64_t buf_dma_addr;
203 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
204 pkt_len = (*pkts)->data_len;
206 /* write data to descriptor */
207 txdp->read.buffer_addr = buf_dma_addr;
208 txdp->read.cmd_type_len =
209 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
210 txdp->read.olinfo_status =
211 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
212 rte_prefetch0(&(*pkts)->pool);
216 * Fill H/W descriptor ring with mbuf data.
217 * Copy mbuf pointers to the S/W ring.
220 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
223 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
224 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
225 const int N_PER_LOOP = 4;
226 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
227 int mainpart, leftover;
231 * Process most of the packets in chunks of N pkts. Any
232 * leftover packets will get processed one at a time.
234 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
235 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
236 for (i = 0; i < mainpart; i += N_PER_LOOP) {
237 /* Copy N mbuf pointers to the S/W ring */
238 for (j = 0; j < N_PER_LOOP; ++j) {
239 (txep + i + j)->mbuf = *(pkts + i + j);
241 tx4(txdp + i, pkts + i);
244 if (unlikely(leftover > 0)) {
245 for (i = 0; i < leftover; ++i) {
246 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
247 tx1(txdp + mainpart + i, pkts + mainpart + i);
252 static inline uint16_t
253 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
256 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
257 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
261 * Begin scanning the H/W ring for done descriptors when the
262 * number of available descriptors drops below tx_free_thresh. For
263 * each done descriptor, free the associated buffer.
265 if (txq->nb_tx_free < txq->tx_free_thresh)
266 ixgbe_tx_free_bufs(txq);
268 /* Only use descriptors that are available */
269 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
270 if (unlikely(nb_pkts == 0))
273 /* Use exactly nb_pkts descriptors */
274 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
277 * At this point, we know there are enough descriptors in the
278 * ring to transmit all the packets. This assumes that each
279 * mbuf contains a single segment, and that no new offloads
280 * are expected, which would require a new context descriptor.
284 * See if we're going to wrap-around. If so, handle the top
285 * of the descriptor ring first, then do the bottom. If not,
286 * the processing looks just like the "bottom" part anyway...
288 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
289 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
290 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
293 * We know that the last descriptor in the ring will need to
294 * have its RS bit set because tx_rs_thresh has to be
295 * a divisor of the ring size
297 tx_r[txq->tx_next_rs].read.cmd_type_len |=
298 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
299 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
304 /* Fill H/W descriptor ring with mbuf data */
305 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
306 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
309 * Determine if RS bit should be set
310 * This is what we actually want:
311 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
312 * but instead of subtracting 1 and doing >=, we can just do
313 * greater than without subtracting.
315 if (txq->tx_tail > txq->tx_next_rs) {
316 tx_r[txq->tx_next_rs].read.cmd_type_len |=
317 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
318 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
320 if (txq->tx_next_rs >= txq->nb_tx_desc)
321 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
325 * Check for wrap-around. This would only happen if we used
326 * up to the last descriptor in the ring, no more, no less.
328 if (txq->tx_tail >= txq->nb_tx_desc)
331 /* update tail pointer */
333 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
339 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
344 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
345 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
346 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
348 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
352 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
353 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
354 nb_tx = (uint16_t)(nb_tx + ret);
355 nb_pkts = (uint16_t)(nb_pkts - ret);
364 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
365 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
366 uint64_t ol_flags, uint32_t vlan_macip_lens)
368 uint32_t type_tucmd_mlhl;
369 uint32_t mss_l4len_idx;
373 ctx_idx = txq->ctx_curr;
377 if (ol_flags & PKT_TX_VLAN_PKT) {
378 cmp_mask |= TX_VLAN_CMP_MASK;
381 if (ol_flags & PKT_TX_IP_CKSUM) {
382 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
383 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
386 /* Specify which HW CTX to upload. */
387 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
388 switch (ol_flags & PKT_TX_L4_MASK) {
389 case PKT_TX_UDP_CKSUM:
390 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
391 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
392 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
393 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
395 case PKT_TX_TCP_CKSUM:
396 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
397 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
398 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
399 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
401 case PKT_TX_SCTP_CKSUM:
402 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
403 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
404 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
405 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
408 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
409 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
413 txq->ctx_cache[ctx_idx].flags = ol_flags;
414 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
415 txq->ctx_cache[ctx_idx].vlan_macip_lens.data =
416 vlan_macip_lens & cmp_mask;
418 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
419 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
420 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
421 ctx_txd->seqnum_seed = 0;
425 * Check which hardware context can be used. Use the existing match
426 * or create a new context descriptor.
428 static inline uint32_t
429 what_advctx_update(struct igb_tx_queue *txq, uint64_t flags,
430 uint32_t vlan_macip_lens)
432 /* If match with the current used context */
433 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
434 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
435 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
436 return txq->ctx_curr;
439 /* What if match with the next context */
441 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
442 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
443 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
444 return txq->ctx_curr;
447 /* Mismatch, use the previous context */
448 return (IXGBE_CTX_NUM);
451 static inline uint32_t
452 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
454 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
455 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
458 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
459 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
463 static inline uint32_t
464 tx_desc_vlan_flags_to_cmdtype(uint64_t ol_flags)
466 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
467 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
470 /* Default RS bit threshold values */
471 #ifndef DEFAULT_TX_RS_THRESH
472 #define DEFAULT_TX_RS_THRESH 32
474 #ifndef DEFAULT_TX_FREE_THRESH
475 #define DEFAULT_TX_FREE_THRESH 32
478 /* Reset transmit descriptors after they have been used */
480 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
482 struct igb_tx_entry *sw_ring = txq->sw_ring;
483 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
484 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
485 uint16_t nb_tx_desc = txq->nb_tx_desc;
486 uint16_t desc_to_clean_to;
487 uint16_t nb_tx_to_clean;
489 /* Determine the last descriptor needing to be cleaned */
490 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
491 if (desc_to_clean_to >= nb_tx_desc)
492 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
494 /* Check to make sure the last descriptor to clean is done */
495 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
496 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
498 PMD_TX_FREE_LOG(DEBUG,
499 "TX descriptor %4u is not done"
500 "(port=%d queue=%d)",
502 txq->port_id, txq->queue_id);
503 /* Failed to clean any descriptors, better luck next time */
507 /* Figure out how many descriptors will be cleaned */
508 if (last_desc_cleaned > desc_to_clean_to)
509 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
512 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
515 PMD_TX_FREE_LOG(DEBUG,
516 "Cleaning %4u TX descriptors: %4u to %4u "
517 "(port=%d queue=%d)",
518 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
519 txq->port_id, txq->queue_id);
522 * The last descriptor to clean is done, so that means all the
523 * descriptors from the last descriptor that was cleaned
524 * up to the last descriptor with the RS bit set
525 * are done. Only reset the threshold descriptor.
527 txr[desc_to_clean_to].wb.status = 0;
529 /* Update the txq to reflect the last descriptor that was cleaned */
530 txq->last_desc_cleaned = desc_to_clean_to;
531 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
538 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
541 struct igb_tx_queue *txq;
542 struct igb_tx_entry *sw_ring;
543 struct igb_tx_entry *txe, *txn;
544 volatile union ixgbe_adv_tx_desc *txr;
545 volatile union ixgbe_adv_tx_desc *txd;
546 struct rte_mbuf *tx_pkt;
547 struct rte_mbuf *m_seg;
548 union ixgbe_vlan_macip vlan_macip_lens;
556 uint64_t buf_dma_addr;
557 uint32_t olinfo_status;
558 uint32_t cmd_type_len;
571 sw_ring = txq->sw_ring;
573 tx_id = txq->tx_tail;
574 txe = &sw_ring[tx_id];
576 /* Determine if the descriptor ring needs to be cleaned. */
577 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
578 ixgbe_xmit_cleanup(txq);
581 rte_prefetch0(&txe->mbuf->pool);
584 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
587 pkt_len = tx_pkt->pkt_len;
590 * Determine how many (if any) context descriptors
591 * are needed for offload functionality.
593 ol_flags = tx_pkt->ol_flags;
595 /* If hardware offload required */
596 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
598 l2_l3_len.l2_len = tx_pkt->l2_len;
599 l2_l3_len.l3_len = tx_pkt->l3_len;
600 vlan_macip_lens.f.vlan_tci = tx_pkt->vlan_tci;
601 vlan_macip_lens.f.l2_l3_len = l2_l3_len.u16;
603 /* If new context need be built or reuse the exist ctx. */
604 ctx = what_advctx_update(txq, tx_ol_req,
605 vlan_macip_lens.data);
606 /* Only allocate context descriptor if required*/
607 new_ctx = (ctx == IXGBE_CTX_NUM);
612 * Keep track of how many descriptors are used this loop
613 * This will always be the number of segments + the number of
614 * Context descriptors required to transmit the packet
616 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
619 * The number of descriptors that must be allocated for a
620 * packet is the number of segments of that packet, plus 1
621 * Context Descriptor for the hardware offload, if any.
622 * Determine the last TX descriptor to allocate in the TX ring
623 * for the packet, starting from the current position (tx_id)
626 tx_last = (uint16_t) (tx_id + nb_used - 1);
629 if (tx_last >= txq->nb_tx_desc)
630 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
632 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
633 " tx_first=%u tx_last=%u",
634 (unsigned) txq->port_id,
635 (unsigned) txq->queue_id,
641 * Make sure there are enough TX descriptors available to
642 * transmit the entire packet.
643 * nb_used better be less than or equal to txq->tx_rs_thresh
645 if (nb_used > txq->nb_tx_free) {
646 PMD_TX_FREE_LOG(DEBUG,
647 "Not enough free TX descriptors "
648 "nb_used=%4u nb_free=%4u "
649 "(port=%d queue=%d)",
650 nb_used, txq->nb_tx_free,
651 txq->port_id, txq->queue_id);
653 if (ixgbe_xmit_cleanup(txq) != 0) {
654 /* Could not clean any descriptors */
660 /* nb_used better be <= txq->tx_rs_thresh */
661 if (unlikely(nb_used > txq->tx_rs_thresh)) {
662 PMD_TX_FREE_LOG(DEBUG,
663 "The number of descriptors needed to "
664 "transmit the packet exceeds the "
665 "RS bit threshold. This will impact "
667 "nb_used=%4u nb_free=%4u "
669 "(port=%d queue=%d)",
670 nb_used, txq->nb_tx_free,
672 txq->port_id, txq->queue_id);
674 * Loop here until there are enough TX
675 * descriptors or until the ring cannot be
678 while (nb_used > txq->nb_tx_free) {
679 if (ixgbe_xmit_cleanup(txq) != 0) {
681 * Could not clean any
693 * By now there are enough free TX descriptors to transmit
698 * Set common flags of all TX Data Descriptors.
700 * The following bits must be set in all Data Descriptors:
701 * - IXGBE_ADVTXD_DTYP_DATA
702 * - IXGBE_ADVTXD_DCMD_DEXT
704 * The following bits must be set in the first Data Descriptor
705 * and are ignored in the other ones:
706 * - IXGBE_ADVTXD_DCMD_IFCS
707 * - IXGBE_ADVTXD_MAC_1588
708 * - IXGBE_ADVTXD_DCMD_VLE
710 * The following bits must only be set in the last Data
712 * - IXGBE_TXD_CMD_EOP
714 * The following bits can be set in any Data Descriptor, but
715 * are only set in the last Data Descriptor:
718 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
719 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
720 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
721 #ifdef RTE_LIBRTE_IEEE1588
722 if (ol_flags & PKT_TX_IEEE1588_TMST)
723 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
728 * Setup the TX Advanced Context Descriptor if required
731 volatile struct ixgbe_adv_tx_context_desc *
734 ctx_txd = (volatile struct
735 ixgbe_adv_tx_context_desc *)
738 txn = &sw_ring[txe->next_id];
739 rte_prefetch0(&txn->mbuf->pool);
741 if (txe->mbuf != NULL) {
742 rte_pktmbuf_free_seg(txe->mbuf);
746 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
747 vlan_macip_lens.data);
749 txe->last_id = tx_last;
750 tx_id = txe->next_id;
755 * Setup the TX Advanced Data Descriptor,
756 * This path will go through
757 * whatever new/reuse the context descriptor
759 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
760 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
761 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
767 txn = &sw_ring[txe->next_id];
768 rte_prefetch0(&txn->mbuf->pool);
770 if (txe->mbuf != NULL)
771 rte_pktmbuf_free_seg(txe->mbuf);
775 * Set up Transmit Data Descriptor.
777 slen = m_seg->data_len;
778 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
779 txd->read.buffer_addr =
780 rte_cpu_to_le_64(buf_dma_addr);
781 txd->read.cmd_type_len =
782 rte_cpu_to_le_32(cmd_type_len | slen);
783 txd->read.olinfo_status =
784 rte_cpu_to_le_32(olinfo_status);
785 txe->last_id = tx_last;
786 tx_id = txe->next_id;
789 } while (m_seg != NULL);
792 * The last packet data descriptor needs End Of Packet (EOP)
794 cmd_type_len |= IXGBE_TXD_CMD_EOP;
795 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
796 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
798 /* Set RS bit only on threshold packets' last descriptor */
799 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
800 PMD_TX_FREE_LOG(DEBUG,
801 "Setting RS bit on TXD id="
802 "%4u (port=%d queue=%d)",
803 tx_last, txq->port_id, txq->queue_id);
805 cmd_type_len |= IXGBE_TXD_CMD_RS;
807 /* Update txq RS bit counters */
810 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
816 * Set the Transmit Descriptor Tail (TDT)
818 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
819 (unsigned) txq->port_id, (unsigned) txq->queue_id,
820 (unsigned) tx_id, (unsigned) nb_tx);
821 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
822 txq->tx_tail = tx_id;
827 /*********************************************************************
831 **********************************************************************/
832 static inline uint64_t
833 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
837 static uint64_t ip_pkt_types_map[16] = {
838 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
839 PKT_RX_IPV6_HDR, 0, 0, 0,
840 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
841 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
844 static uint64_t ip_rss_types_map[16] = {
845 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
846 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
847 PKT_RX_RSS_HASH, 0, 0, 0,
848 0, 0, 0, PKT_RX_FDIR,
851 #ifdef RTE_LIBRTE_IEEE1588
852 static uint64_t ip_pkt_etqf_map[8] = {
853 0, 0, 0, PKT_RX_IEEE1588_PTP,
857 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
858 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
859 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
861 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
862 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
865 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
868 static inline uint64_t
869 rx_desc_status_to_pkt_flags(uint32_t rx_status)
874 * Check if VLAN present only.
875 * Do not check whether L3/L4 rx checksum done by NIC or not,
876 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
878 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
880 #ifdef RTE_LIBRTE_IEEE1588
881 if (rx_status & IXGBE_RXD_STAT_TMST)
882 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
887 static inline uint64_t
888 rx_desc_error_to_pkt_flags(uint32_t rx_status)
891 * Bit 31: IPE, IPv4 checksum error
892 * Bit 30: L4I, L4I integrity error
894 static uint64_t error_to_pkt_flags_map[4] = {
895 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
896 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
898 return error_to_pkt_flags_map[(rx_status >>
899 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
902 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
904 * LOOK_AHEAD defines how many desc statuses to check beyond the
905 * current descriptor.
906 * It must be a pound define for optimal performance.
907 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
908 * function only works with LOOK_AHEAD=8.
911 #if (LOOK_AHEAD != 8)
912 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
915 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
917 volatile union ixgbe_adv_rx_desc *rxdp;
918 struct igb_rx_entry *rxep;
922 int s[LOOK_AHEAD], nb_dd;
926 /* get references to current descriptor and S/W ring entry */
927 rxdp = &rxq->rx_ring[rxq->rx_tail];
928 rxep = &rxq->sw_ring[rxq->rx_tail];
930 /* check to make sure there is at least 1 packet to receive */
931 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
935 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
936 * reference packets that are ready to be received.
938 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
939 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
941 /* Read desc statuses backwards to avoid race condition */
942 for (j = LOOK_AHEAD-1; j >= 0; --j)
943 s[j] = rxdp[j].wb.upper.status_error;
945 /* Compute how many status bits were set */
947 for (j = 0; j < LOOK_AHEAD; ++j)
948 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
952 /* Translate descriptor info to mbuf format */
953 for (j = 0; j < nb_dd; ++j) {
955 pkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len);
956 mb->data_len = pkt_len;
957 mb->pkt_len = pkt_len;
958 mb->vlan_tci = rxdp[j].wb.upper.vlan;
959 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
961 /* convert descriptor fields to rte mbuf flags */
962 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(
963 rxdp[j].wb.lower.lo_dword.data);
964 /* reuse status field from scan list */
965 pkt_flags |= rx_desc_status_to_pkt_flags(s[j]);
966 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
967 mb->ol_flags = pkt_flags;
969 if (likely(pkt_flags & PKT_RX_RSS_HASH))
970 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
971 else if (pkt_flags & PKT_RX_FDIR) {
973 (uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum)
974 & IXGBE_ATR_HASH_MASK);
975 mb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id;
979 /* Move mbuf pointers from the S/W ring to the stage */
980 for (j = 0; j < LOOK_AHEAD; ++j) {
981 rxq->rx_stage[i + j] = rxep[j].mbuf;
984 /* stop if all requested packets could not be received */
985 if (nb_dd != LOOK_AHEAD)
989 /* clear software ring entries so we can cleanup correctly */
990 for (i = 0; i < nb_rx; ++i) {
991 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
999 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
1001 volatile union ixgbe_adv_rx_desc *rxdp;
1002 struct igb_rx_entry *rxep;
1003 struct rte_mbuf *mb;
1008 /* allocate buffers in bulk directly into the S/W ring */
1009 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1010 (rxq->rx_free_thresh - 1));
1011 rxep = &rxq->sw_ring[alloc_idx];
1012 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1013 rxq->rx_free_thresh);
1014 if (unlikely(diag != 0))
1017 rxdp = &rxq->rx_ring[alloc_idx];
1018 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1019 /* populate the static rte mbuf fields */
1021 rte_mbuf_refcnt_set(mb, 1);
1023 mb->data_off = RTE_PKTMBUF_HEADROOM;
1025 mb->port = rxq->port_id;
1027 /* populate the descriptors */
1028 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1029 rxdp[i].read.hdr_addr = dma_addr;
1030 rxdp[i].read.pkt_addr = dma_addr;
1033 /* update tail pointer */
1035 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1037 /* update state of internal queue structure */
1038 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1039 rxq->rx_free_thresh);
1040 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1041 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1047 static inline uint16_t
1048 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1051 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1054 /* how many packets are ready to return? */
1055 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1057 /* copy mbuf pointers to the application's packet list */
1058 for (i = 0; i < nb_pkts; ++i)
1059 rx_pkts[i] = stage[i];
1061 /* update internal queue state */
1062 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1063 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1068 static inline uint16_t
1069 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1072 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1075 /* Any previously recv'd pkts will be returned from the Rx stage */
1076 if (rxq->rx_nb_avail)
1077 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1079 /* Scan the H/W ring for packets to receive */
1080 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1082 /* update internal queue state */
1083 rxq->rx_next_avail = 0;
1084 rxq->rx_nb_avail = nb_rx;
1085 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1087 /* if required, allocate new buffers to replenish descriptors */
1088 if (rxq->rx_tail > rxq->rx_free_trigger) {
1089 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1091 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1092 "queue_id=%u", (unsigned) rxq->port_id,
1093 (unsigned) rxq->queue_id);
1095 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1096 rxq->rx_free_thresh;
1099 * Need to rewind any previous receives if we cannot
1100 * allocate new buffers to replenish the old ones.
1102 rxq->rx_nb_avail = 0;
1103 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1104 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1105 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1111 if (rxq->rx_tail >= rxq->nb_rx_desc)
1114 /* received any packets this loop? */
1115 if (rxq->rx_nb_avail)
1116 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1121 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1123 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1128 if (unlikely(nb_pkts == 0))
1131 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1132 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1134 /* request is relatively large, chunk it up */
1138 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1139 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1140 nb_rx = (uint16_t)(nb_rx + ret);
1141 nb_pkts = (uint16_t)(nb_pkts - ret);
1148 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1151 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1154 struct igb_rx_queue *rxq;
1155 volatile union ixgbe_adv_rx_desc *rx_ring;
1156 volatile union ixgbe_adv_rx_desc *rxdp;
1157 struct igb_rx_entry *sw_ring;
1158 struct igb_rx_entry *rxe;
1159 struct rte_mbuf *rxm;
1160 struct rte_mbuf *nmb;
1161 union ixgbe_adv_rx_desc rxd;
1164 uint32_t hlen_type_rss;
1174 rx_id = rxq->rx_tail;
1175 rx_ring = rxq->rx_ring;
1176 sw_ring = rxq->sw_ring;
1177 while (nb_rx < nb_pkts) {
1179 * The order of operations here is important as the DD status
1180 * bit must not be read after any other descriptor fields.
1181 * rx_ring and rxdp are pointing to volatile data so the order
1182 * of accesses cannot be reordered by the compiler. If they were
1183 * not volatile, they could be reordered which could lead to
1184 * using invalid descriptor fields when read from rxd.
1186 rxdp = &rx_ring[rx_id];
1187 staterr = rxdp->wb.upper.status_error;
1188 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1195 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1196 * is likely to be invalid and to be dropped by the various
1197 * validation checks performed by the network stack.
1199 * Allocate a new mbuf to replenish the RX ring descriptor.
1200 * If the allocation fails:
1201 * - arrange for that RX descriptor to be the first one
1202 * being parsed the next time the receive function is
1203 * invoked [on the same queue].
1205 * - Stop parsing the RX ring and return immediately.
1207 * This policy do not drop the packet received in the RX
1208 * descriptor for which the allocation of a new mbuf failed.
1209 * Thus, it allows that packet to be later retrieved if
1210 * mbuf have been freed in the mean time.
1211 * As a side effect, holding RX descriptors instead of
1212 * systematically giving them back to the NIC may lead to
1213 * RX ring exhaustion situations.
1214 * However, the NIC can gracefully prevent such situations
1215 * to happen by sending specific "back-pressure" flow control
1216 * frames to its peer(s).
1218 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1219 "ext_err_stat=0x%08x pkt_len=%u",
1220 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1221 (unsigned) rx_id, (unsigned) staterr,
1222 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1224 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1226 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1227 "queue_id=%u", (unsigned) rxq->port_id,
1228 (unsigned) rxq->queue_id);
1229 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1234 rxe = &sw_ring[rx_id];
1236 if (rx_id == rxq->nb_rx_desc)
1239 /* Prefetch next mbuf while processing current one. */
1240 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1243 * When next RX descriptor is on a cache-line boundary,
1244 * prefetch the next 4 RX descriptors and the next 8 pointers
1247 if ((rx_id & 0x3) == 0) {
1248 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1249 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1255 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1256 rxdp->read.hdr_addr = dma_addr;
1257 rxdp->read.pkt_addr = dma_addr;
1260 * Initialize the returned mbuf.
1261 * 1) setup generic mbuf fields:
1262 * - number of segments,
1265 * - RX port identifier.
1266 * 2) integrate hardware offload data, if any:
1267 * - RSS flag & hash,
1268 * - IP checksum flag,
1269 * - VLAN TCI, if any,
1272 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1274 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1275 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1278 rxm->pkt_len = pkt_len;
1279 rxm->data_len = pkt_len;
1280 rxm->port = rxq->port_id;
1282 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1283 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1284 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1286 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1287 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1288 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1289 rxm->ol_flags = pkt_flags;
1291 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1292 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1293 else if (pkt_flags & PKT_RX_FDIR) {
1294 rxm->hash.fdir.hash =
1295 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1296 & IXGBE_ATR_HASH_MASK);
1297 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1300 * Store the mbuf address into the next entry of the array
1301 * of returned packets.
1303 rx_pkts[nb_rx++] = rxm;
1305 rxq->rx_tail = rx_id;
1308 * If the number of free RX descriptors is greater than the RX free
1309 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1311 * Update the RDT with the value of the last processed RX descriptor
1312 * minus 1, to guarantee that the RDT register is never equal to the
1313 * RDH register, which creates a "full" ring situtation from the
1314 * hardware point of view...
1316 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1317 if (nb_hold > rxq->rx_free_thresh) {
1318 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1319 "nb_hold=%u nb_rx=%u",
1320 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1321 (unsigned) rx_id, (unsigned) nb_hold,
1323 rx_id = (uint16_t) ((rx_id == 0) ?
1324 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1325 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1328 rxq->nb_rx_hold = nb_hold;
1333 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1336 struct igb_rx_queue *rxq;
1337 volatile union ixgbe_adv_rx_desc *rx_ring;
1338 volatile union ixgbe_adv_rx_desc *rxdp;
1339 struct igb_rx_entry *sw_ring;
1340 struct igb_rx_entry *rxe;
1341 struct rte_mbuf *first_seg;
1342 struct rte_mbuf *last_seg;
1343 struct rte_mbuf *rxm;
1344 struct rte_mbuf *nmb;
1345 union ixgbe_adv_rx_desc rxd;
1346 uint64_t dma; /* Physical address of mbuf data buffer */
1348 uint32_t hlen_type_rss;
1358 rx_id = rxq->rx_tail;
1359 rx_ring = rxq->rx_ring;
1360 sw_ring = rxq->sw_ring;
1363 * Retrieve RX context of current packet, if any.
1365 first_seg = rxq->pkt_first_seg;
1366 last_seg = rxq->pkt_last_seg;
1368 while (nb_rx < nb_pkts) {
1371 * The order of operations here is important as the DD status
1372 * bit must not be read after any other descriptor fields.
1373 * rx_ring and rxdp are pointing to volatile data so the order
1374 * of accesses cannot be reordered by the compiler. If they were
1375 * not volatile, they could be reordered which could lead to
1376 * using invalid descriptor fields when read from rxd.
1378 rxdp = &rx_ring[rx_id];
1379 staterr = rxdp->wb.upper.status_error;
1380 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1387 * Allocate a new mbuf to replenish the RX ring descriptor.
1388 * If the allocation fails:
1389 * - arrange for that RX descriptor to be the first one
1390 * being parsed the next time the receive function is
1391 * invoked [on the same queue].
1393 * - Stop parsing the RX ring and return immediately.
1395 * This policy does not drop the packet received in the RX
1396 * descriptor for which the allocation of a new mbuf failed.
1397 * Thus, it allows that packet to be later retrieved if
1398 * mbuf have been freed in the mean time.
1399 * As a side effect, holding RX descriptors instead of
1400 * systematically giving them back to the NIC may lead to
1401 * RX ring exhaustion situations.
1402 * However, the NIC can gracefully prevent such situations
1403 * to happen by sending specific "back-pressure" flow control
1404 * frames to its peer(s).
1406 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1407 "staterr=0x%x data_len=%u",
1408 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1409 (unsigned) rx_id, (unsigned) staterr,
1410 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1412 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1414 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1415 "queue_id=%u", (unsigned) rxq->port_id,
1416 (unsigned) rxq->queue_id);
1417 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1422 rxe = &sw_ring[rx_id];
1424 if (rx_id == rxq->nb_rx_desc)
1427 /* Prefetch next mbuf while processing current one. */
1428 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1431 * When next RX descriptor is on a cache-line boundary,
1432 * prefetch the next 4 RX descriptors and the next 8 pointers
1435 if ((rx_id & 0x3) == 0) {
1436 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1437 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1441 * Update RX descriptor with the physical address of the new
1442 * data buffer of the new allocated mbuf.
1446 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1447 rxdp->read.hdr_addr = dma;
1448 rxdp->read.pkt_addr = dma;
1451 * Set data length & data buffer address of mbuf.
1453 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1454 rxm->data_len = data_len;
1455 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1458 * If this is the first buffer of the received packet,
1459 * set the pointer to the first mbuf of the packet and
1460 * initialize its context.
1461 * Otherwise, update the total length and the number of segments
1462 * of the current scattered packet, and update the pointer to
1463 * the last mbuf of the current packet.
1465 if (first_seg == NULL) {
1467 first_seg->pkt_len = data_len;
1468 first_seg->nb_segs = 1;
1470 first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
1472 first_seg->nb_segs++;
1473 last_seg->next = rxm;
1477 * If this is not the last buffer of the received packet,
1478 * update the pointer to the last mbuf of the current scattered
1479 * packet and continue to parse the RX ring.
1481 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1487 * This is the last buffer of the received packet.
1488 * If the CRC is not stripped by the hardware:
1489 * - Subtract the CRC length from the total packet length.
1490 * - If the last buffer only contains the whole CRC or a part
1491 * of it, free the mbuf associated to the last buffer.
1492 * If part of the CRC is also contained in the previous
1493 * mbuf, subtract the length of that CRC part from the
1494 * data length of the previous mbuf.
1497 if (unlikely(rxq->crc_len > 0)) {
1498 first_seg->pkt_len -= ETHER_CRC_LEN;
1499 if (data_len <= ETHER_CRC_LEN) {
1500 rte_pktmbuf_free_seg(rxm);
1501 first_seg->nb_segs--;
1502 last_seg->data_len = (uint16_t)
1503 (last_seg->data_len -
1504 (ETHER_CRC_LEN - data_len));
1505 last_seg->next = NULL;
1508 (uint16_t) (data_len - ETHER_CRC_LEN);
1512 * Initialize the first mbuf of the returned packet:
1513 * - RX port identifier,
1514 * - hardware offload data, if any:
1515 * - RSS flag & hash,
1516 * - IP checksum flag,
1517 * - VLAN TCI, if any,
1520 first_seg->port = rxq->port_id;
1523 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1524 * set in the pkt_flags field.
1526 first_seg->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1527 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1528 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1529 pkt_flags = (pkt_flags |
1530 rx_desc_status_to_pkt_flags(staterr));
1531 pkt_flags = (pkt_flags |
1532 rx_desc_error_to_pkt_flags(staterr));
1533 first_seg->ol_flags = pkt_flags;
1535 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1536 first_seg->hash.rss = rxd.wb.lower.hi_dword.rss;
1537 else if (pkt_flags & PKT_RX_FDIR) {
1538 first_seg->hash.fdir.hash =
1539 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1540 & IXGBE_ATR_HASH_MASK);
1541 first_seg->hash.fdir.id =
1542 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1545 /* Prefetch data of first segment, if configured to do so. */
1546 rte_packet_prefetch((char *)first_seg->buf_addr +
1547 first_seg->data_off);
1550 * Store the mbuf address into the next entry of the array
1551 * of returned packets.
1553 rx_pkts[nb_rx++] = first_seg;
1556 * Setup receipt context for a new packet.
1562 * Record index of the next RX descriptor to probe.
1564 rxq->rx_tail = rx_id;
1567 * Save receive context.
1569 rxq->pkt_first_seg = first_seg;
1570 rxq->pkt_last_seg = last_seg;
1573 * If the number of free RX descriptors is greater than the RX free
1574 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1576 * Update the RDT with the value of the last processed RX descriptor
1577 * minus 1, to guarantee that the RDT register is never equal to the
1578 * RDH register, which creates a "full" ring situtation from the
1579 * hardware point of view...
1581 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1582 if (nb_hold > rxq->rx_free_thresh) {
1583 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1584 "nb_hold=%u nb_rx=%u",
1585 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1586 (unsigned) rx_id, (unsigned) nb_hold,
1588 rx_id = (uint16_t) ((rx_id == 0) ?
1589 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1590 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1593 rxq->nb_rx_hold = nb_hold;
1597 /*********************************************************************
1599 * Queue management functions
1601 **********************************************************************/
1604 * Rings setup and release.
1606 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1607 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1608 * also optimize cache line size effect. H/W supports up to cache line size 128.
1610 #define IXGBE_ALIGN 128
1613 * Maximum number of Ring Descriptors.
1615 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1616 * descriptors should meet the following condition:
1617 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1619 #define IXGBE_MIN_RING_DESC 32
1620 #define IXGBE_MAX_RING_DESC 4096
1623 * Create memzone for HW rings. malloc can't be used as the physical address is
1624 * needed. If the memzone is already created, then this function returns a ptr
1627 static const struct rte_memzone *
1628 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1629 uint16_t queue_id, uint32_t ring_size, int socket_id)
1631 char z_name[RTE_MEMZONE_NAMESIZE];
1632 const struct rte_memzone *mz;
1634 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1635 dev->driver->pci_drv.name, ring_name,
1636 dev->data->port_id, queue_id);
1638 mz = rte_memzone_lookup(z_name);
1642 #ifdef RTE_LIBRTE_XEN_DOM0
1643 return rte_memzone_reserve_bounded(z_name, ring_size,
1644 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1646 return rte_memzone_reserve_aligned(z_name, ring_size,
1647 socket_id, 0, IXGBE_ALIGN);
1652 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1656 if (txq->sw_ring != NULL) {
1657 for (i = 0; i < txq->nb_tx_desc; i++) {
1658 if (txq->sw_ring[i].mbuf != NULL) {
1659 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1660 txq->sw_ring[i].mbuf = NULL;
1667 ixgbe_tx_free_swring(struct igb_tx_queue *txq)
1670 txq->sw_ring != NULL)
1671 rte_free(txq->sw_ring);
1675 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1677 if (txq != NULL && txq->ops != NULL) {
1678 txq->ops->release_mbufs(txq);
1679 txq->ops->free_swring(txq);
1685 ixgbe_dev_tx_queue_release(void *txq)
1687 ixgbe_tx_queue_release(txq);
1690 /* (Re)set dynamic igb_tx_queue fields to defaults */
1692 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1694 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1696 struct igb_tx_entry *txe = txq->sw_ring;
1699 /* Zero out HW ring memory */
1700 for (i = 0; i < txq->nb_tx_desc; i++) {
1701 txq->tx_ring[i] = zeroed_desc;
1704 /* Initialize SW ring entries */
1705 prev = (uint16_t) (txq->nb_tx_desc - 1);
1706 for (i = 0; i < txq->nb_tx_desc; i++) {
1707 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1708 txd->wb.status = IXGBE_TXD_STAT_DD;
1711 txe[prev].next_id = i;
1715 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1716 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1719 txq->nb_tx_used = 0;
1721 * Always allow 1 descriptor to be un-allocated to avoid
1722 * a H/W race condition
1724 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1725 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1727 memset((void*)&txq->ctx_cache, 0,
1728 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1731 static struct ixgbe_txq_ops def_txq_ops = {
1732 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1733 .free_swring = ixgbe_tx_free_swring,
1734 .reset = ixgbe_reset_tx_queue,
1738 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1741 unsigned int socket_id,
1742 const struct rte_eth_txconf *tx_conf)
1744 const struct rte_memzone *tz;
1745 struct igb_tx_queue *txq;
1746 struct ixgbe_hw *hw;
1747 uint16_t tx_rs_thresh, tx_free_thresh;
1749 PMD_INIT_FUNC_TRACE();
1750 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1753 * Validate number of transmit descriptors.
1754 * It must not exceed hardware maximum, and must be multiple
1757 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1758 (nb_desc > IXGBE_MAX_RING_DESC) ||
1759 (nb_desc < IXGBE_MIN_RING_DESC)) {
1764 * The following two parameters control the setting of the RS bit on
1765 * transmit descriptors.
1766 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1767 * descriptors have been used.
1768 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1769 * descriptors are used or if the number of descriptors required
1770 * to transmit a packet is greater than the number of free TX
1772 * The following constraints must be satisfied:
1773 * tx_rs_thresh must be greater than 0.
1774 * tx_rs_thresh must be less than the size of the ring minus 2.
1775 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1776 * tx_rs_thresh must be a divisor of the ring size.
1777 * tx_free_thresh must be greater than 0.
1778 * tx_free_thresh must be less than the size of the ring minus 3.
1779 * One descriptor in the TX ring is used as a sentinel to avoid a
1780 * H/W race condition, hence the maximum threshold constraints.
1781 * When set to zero use default values.
1783 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1784 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1785 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1786 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1787 if (tx_rs_thresh >= (nb_desc - 2)) {
1788 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
1789 "of TX descriptors minus 2. (tx_rs_thresh=%u "
1790 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1791 (int)dev->data->port_id, (int)queue_idx);
1794 if (tx_free_thresh >= (nb_desc - 3)) {
1795 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1796 "tx_free_thresh must be less than the number of "
1797 "TX descriptors minus 3. (tx_free_thresh=%u "
1798 "port=%d queue=%d)",
1799 (unsigned int)tx_free_thresh,
1800 (int)dev->data->port_id, (int)queue_idx);
1803 if (tx_rs_thresh > tx_free_thresh) {
1804 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
1805 "tx_free_thresh. (tx_free_thresh=%u "
1806 "tx_rs_thresh=%u port=%d queue=%d)",
1807 (unsigned int)tx_free_thresh,
1808 (unsigned int)tx_rs_thresh,
1809 (int)dev->data->port_id,
1813 if ((nb_desc % tx_rs_thresh) != 0) {
1814 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1815 "number of TX descriptors. (tx_rs_thresh=%u "
1816 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1817 (int)dev->data->port_id, (int)queue_idx);
1822 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1823 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1824 * by the NIC and all descriptors are written back after the NIC
1825 * accumulates WTHRESH descriptors.
1827 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1828 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1829 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1830 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1831 (int)dev->data->port_id, (int)queue_idx);
1835 /* Free memory prior to re-allocation if needed... */
1836 if (dev->data->tx_queues[queue_idx] != NULL) {
1837 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1838 dev->data->tx_queues[queue_idx] = NULL;
1841 /* First allocate the tx queue data structure */
1842 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct igb_tx_queue),
1843 CACHE_LINE_SIZE, socket_id);
1848 * Allocate TX ring hardware descriptors. A memzone large enough to
1849 * handle the maximum ring size is allocated in order to allow for
1850 * resizing in later calls to the queue setup function.
1852 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1853 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1856 ixgbe_tx_queue_release(txq);
1860 txq->nb_tx_desc = nb_desc;
1861 txq->tx_rs_thresh = tx_rs_thresh;
1862 txq->tx_free_thresh = tx_free_thresh;
1863 txq->pthresh = tx_conf->tx_thresh.pthresh;
1864 txq->hthresh = tx_conf->tx_thresh.hthresh;
1865 txq->wthresh = tx_conf->tx_thresh.wthresh;
1866 txq->queue_id = queue_idx;
1867 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1868 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1869 txq->port_id = dev->data->port_id;
1870 txq->txq_flags = tx_conf->txq_flags;
1871 txq->ops = &def_txq_ops;
1872 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1875 * Modification to set VFTDT for virtual function if vf is detected
1877 if (hw->mac.type == ixgbe_mac_82599_vf)
1878 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1880 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1881 #ifndef RTE_LIBRTE_XEN_DOM0
1882 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1884 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1886 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1888 /* Allocate software ring */
1889 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1890 sizeof(struct igb_tx_entry) * nb_desc,
1891 CACHE_LINE_SIZE, socket_id);
1892 if (txq->sw_ring == NULL) {
1893 ixgbe_tx_queue_release(txq);
1896 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1897 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1899 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1900 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
1901 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1902 PMD_INIT_LOG(INFO, "Using simple tx code path");
1903 #ifdef RTE_IXGBE_INC_VECTOR
1904 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1905 ixgbe_txq_vec_setup(txq) == 0) {
1906 PMD_INIT_LOG(INFO, "Vector tx enabled.");
1907 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1911 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1913 PMD_INIT_LOG(INFO, "Using full-featured tx code path");
1914 PMD_INIT_LOG(INFO, " - txq_flags = %lx "
1915 "[IXGBE_SIMPLE_FLAGS=%lx]",
1916 (long unsigned)txq->txq_flags,
1917 (long unsigned)IXGBE_SIMPLE_FLAGS);
1918 PMD_INIT_LOG(INFO, " - tx_rs_thresh = %lu "
1919 "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
1920 (long unsigned)txq->tx_rs_thresh,
1921 (long unsigned)RTE_PMD_IXGBE_TX_MAX_BURST);
1922 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1925 txq->ops->reset(txq);
1927 dev->data->tx_queues[queue_idx] = txq;
1934 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1938 if (rxq->sw_ring != NULL) {
1939 for (i = 0; i < rxq->nb_rx_desc; i++) {
1940 if (rxq->sw_ring[i].mbuf != NULL) {
1941 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1942 rxq->sw_ring[i].mbuf = NULL;
1945 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1946 if (rxq->rx_nb_avail) {
1947 for (i = 0; i < rxq->rx_nb_avail; ++i) {
1948 struct rte_mbuf *mb;
1949 mb = rxq->rx_stage[rxq->rx_next_avail + i];
1950 rte_pktmbuf_free_seg(mb);
1952 rxq->rx_nb_avail = 0;
1959 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
1962 ixgbe_rx_queue_release_mbufs(rxq);
1963 rte_free(rxq->sw_ring);
1969 ixgbe_dev_rx_queue_release(void *rxq)
1971 ixgbe_rx_queue_release(rxq);
1975 * Check if Rx Burst Bulk Alloc function can be used.
1977 * 0: the preconditions are satisfied and the bulk allocation function
1979 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
1980 * function must be used.
1983 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1984 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
1986 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct igb_rx_queue *rxq)
1992 * Make sure the following pre-conditions are satisfied:
1993 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
1994 * rxq->rx_free_thresh < rxq->nb_rx_desc
1995 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
1996 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
1997 * Scattered packets are not supported. This should be checked
1998 * outside of this function.
2000 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2001 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2002 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2003 "rxq->rx_free_thresh=%d, "
2004 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2005 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2007 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2008 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2009 "rxq->rx_free_thresh=%d, "
2010 "rxq->nb_rx_desc=%d",
2011 rxq->rx_free_thresh, rxq->nb_rx_desc);
2013 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2014 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2015 "rxq->nb_rx_desc=%d, "
2016 "rxq->rx_free_thresh=%d",
2017 rxq->nb_rx_desc, rxq->rx_free_thresh);
2019 } else if (!(rxq->nb_rx_desc <
2020 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2021 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2022 "rxq->nb_rx_desc=%d, "
2023 "IXGBE_MAX_RING_DESC=%d, "
2024 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2025 rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2026 RTE_PMD_IXGBE_RX_MAX_BURST);
2036 /* Reset dynamic igb_rx_queue fields back to defaults */
2038 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
2040 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
2046 * By default, the Rx queue setup function allocates enough memory for
2047 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2048 * extra memory at the end of the descriptor ring to be zero'd out. A
2049 * pre-condition for using the Rx burst bulk alloc function is that the
2050 * number of descriptors is less than or equal to
2051 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2052 * constraints here to see if we need to zero out memory after the end
2053 * of the H/W descriptor ring.
2055 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2056 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2057 /* zero out extra memory */
2058 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2061 /* do not zero out extra memory */
2062 len = rxq->nb_rx_desc;
2065 * Zero out HW ring memory. Zero out extra memory at the end of
2066 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2067 * reads extra memory as zeros.
2069 for (i = 0; i < len; i++) {
2070 rxq->rx_ring[i] = zeroed_desc;
2073 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2075 * initialize extra software ring entries. Space for these extra
2076 * entries is always allocated
2078 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2079 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2080 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2083 rxq->rx_nb_avail = 0;
2084 rxq->rx_next_avail = 0;
2085 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2086 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2088 rxq->nb_rx_hold = 0;
2089 rxq->pkt_first_seg = NULL;
2090 rxq->pkt_last_seg = NULL;
2094 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2097 unsigned int socket_id,
2098 const struct rte_eth_rxconf *rx_conf,
2099 struct rte_mempool *mp)
2101 const struct rte_memzone *rz;
2102 struct igb_rx_queue *rxq;
2103 struct ixgbe_hw *hw;
2104 int use_def_burst_func = 1;
2107 PMD_INIT_FUNC_TRACE();
2108 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2111 * Validate number of receive descriptors.
2112 * It must not exceed hardware maximum, and must be multiple
2115 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2116 (nb_desc > IXGBE_MAX_RING_DESC) ||
2117 (nb_desc < IXGBE_MIN_RING_DESC)) {
2121 /* Free memory prior to re-allocation if needed... */
2122 if (dev->data->rx_queues[queue_idx] != NULL) {
2123 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2124 dev->data->rx_queues[queue_idx] = NULL;
2127 /* First allocate the rx queue data structure */
2128 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct igb_rx_queue),
2129 CACHE_LINE_SIZE, socket_id);
2133 rxq->nb_rx_desc = nb_desc;
2134 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2135 rxq->queue_id = queue_idx;
2136 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2137 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2138 rxq->port_id = dev->data->port_id;
2139 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2141 rxq->drop_en = rx_conf->rx_drop_en;
2142 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2145 * Allocate RX ring hardware descriptors. A memzone large enough to
2146 * handle the maximum ring size is allocated in order to allow for
2147 * resizing in later calls to the queue setup function.
2149 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2150 RX_RING_SZ, socket_id);
2152 ixgbe_rx_queue_release(rxq);
2157 * Zero init all the descriptors in the ring.
2159 memset (rz->addr, 0, RX_RING_SZ);
2162 * Modified to setup VFRDT for Virtual Function
2164 if (hw->mac.type == ixgbe_mac_82599_vf) {
2166 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2168 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2172 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2174 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2176 #ifndef RTE_LIBRTE_XEN_DOM0
2177 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2179 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2181 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2184 * Allocate software ring. Allow for space at the end of the
2185 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2186 * function does not access an invalid memory region.
2188 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2189 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2193 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2194 sizeof(struct igb_rx_entry) * len,
2195 CACHE_LINE_SIZE, socket_id);
2196 if (rxq->sw_ring == NULL) {
2197 ixgbe_rx_queue_release(rxq);
2200 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2201 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2204 * Certain constraints must be met in order to use the bulk buffer
2205 * allocation Rx burst function.
2207 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2209 #ifdef RTE_IXGBE_INC_VECTOR
2210 ixgbe_rxq_vec_setup(rxq);
2212 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2213 if (!use_def_burst_func && !dev->data->scattered_rx) {
2214 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2215 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2216 "satisfied. Rx Burst Bulk Alloc function will be "
2217 "used on port=%d, queue=%d.",
2218 rxq->port_id, rxq->queue_id);
2219 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2220 #ifdef RTE_IXGBE_INC_VECTOR
2221 if (!ixgbe_rx_vec_condition_check(dev)) {
2222 PMD_INIT_LOG(INFO, "Vector rx enabled, please make "
2223 "sure RX burst size no less than 32.");
2224 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
2229 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2230 "are not satisfied, Scattered Rx is requested, "
2231 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2232 "enabled (port=%d, queue=%d).",
2233 rxq->port_id, rxq->queue_id);
2235 dev->data->rx_queues[queue_idx] = rxq;
2237 ixgbe_reset_rx_queue(rxq);
2243 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2245 #define IXGBE_RXQ_SCAN_INTERVAL 4
2246 volatile union ixgbe_adv_rx_desc *rxdp;
2247 struct igb_rx_queue *rxq;
2250 if (rx_queue_id >= dev->data->nb_rx_queues) {
2251 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2255 rxq = dev->data->rx_queues[rx_queue_id];
2256 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2258 while ((desc < rxq->nb_rx_desc) &&
2259 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2260 desc += IXGBE_RXQ_SCAN_INTERVAL;
2261 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2262 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2263 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2264 desc - rxq->nb_rx_desc]);
2271 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2273 volatile union ixgbe_adv_rx_desc *rxdp;
2274 struct igb_rx_queue *rxq = rx_queue;
2277 if (unlikely(offset >= rxq->nb_rx_desc))
2279 desc = rxq->rx_tail + offset;
2280 if (desc >= rxq->nb_rx_desc)
2281 desc -= rxq->nb_rx_desc;
2283 rxdp = &rxq->rx_ring[desc];
2284 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2288 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2292 PMD_INIT_FUNC_TRACE();
2294 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2295 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2297 txq->ops->release_mbufs(txq);
2298 txq->ops->reset(txq);
2302 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2303 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2305 ixgbe_rx_queue_release_mbufs(rxq);
2306 ixgbe_reset_rx_queue(rxq);
2311 /*********************************************************************
2313 * Device RX/TX init functions
2315 **********************************************************************/
2318 * Receive Side Scaling (RSS)
2319 * See section 7.1.2.8 in the following document:
2320 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2323 * The source and destination IP addresses of the IP header and the source
2324 * and destination ports of TCP/UDP headers, if any, of received packets are
2325 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2326 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2327 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2328 * RSS output index which is used as the RX queue index where to store the
2330 * The following output is supplied in the RX write-back descriptor:
2331 * - 32-bit result of the Microsoft RSS hash function,
2332 * - 4-bit RSS type field.
2336 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2337 * Used as the default key.
2339 static uint8_t rss_intel_key[40] = {
2340 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2341 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2342 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2343 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2344 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2348 ixgbe_rss_disable(struct rte_eth_dev *dev)
2350 struct ixgbe_hw *hw;
2353 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2354 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2355 mrqc &= ~IXGBE_MRQC_RSSEN;
2356 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2360 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2368 hash_key = rss_conf->rss_key;
2369 if (hash_key != NULL) {
2370 /* Fill in RSS hash key */
2371 for (i = 0; i < 10; i++) {
2372 rss_key = hash_key[(i * 4)];
2373 rss_key |= hash_key[(i * 4) + 1] << 8;
2374 rss_key |= hash_key[(i * 4) + 2] << 16;
2375 rss_key |= hash_key[(i * 4) + 3] << 24;
2376 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2380 /* Set configured hashing protocols in MRQC register */
2381 rss_hf = rss_conf->rss_hf;
2382 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2383 if (rss_hf & ETH_RSS_IPV4)
2384 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2385 if (rss_hf & ETH_RSS_IPV4_TCP)
2386 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2387 if (rss_hf & ETH_RSS_IPV6)
2388 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2389 if (rss_hf & ETH_RSS_IPV6_EX)
2390 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2391 if (rss_hf & ETH_RSS_IPV6_TCP)
2392 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2393 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2394 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2395 if (rss_hf & ETH_RSS_IPV4_UDP)
2396 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2397 if (rss_hf & ETH_RSS_IPV6_UDP)
2398 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2399 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2400 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2401 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2405 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2406 struct rte_eth_rss_conf *rss_conf)
2408 struct ixgbe_hw *hw;
2412 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2415 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2416 * "RSS enabling cannot be done dynamically while it must be
2417 * preceded by a software reset"
2418 * Before changing anything, first check that the update RSS operation
2419 * does not attempt to disable RSS, if RSS was enabled at
2420 * initialization time, or does not attempt to enable RSS, if RSS was
2421 * disabled at initialization time.
2423 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2424 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2425 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2426 if (rss_hf != 0) /* Enable RSS */
2428 return 0; /* Nothing to do */
2431 if (rss_hf == 0) /* Disable RSS */
2433 ixgbe_hw_rss_hash_set(hw, rss_conf);
2438 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2439 struct rte_eth_rss_conf *rss_conf)
2441 struct ixgbe_hw *hw;
2448 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2449 hash_key = rss_conf->rss_key;
2450 if (hash_key != NULL) {
2451 /* Return RSS hash key */
2452 for (i = 0; i < 10; i++) {
2453 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2454 hash_key[(i * 4)] = rss_key & 0x000000FF;
2455 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2456 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2457 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2461 /* Get RSS functions configured in MRQC register */
2462 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2463 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2464 rss_conf->rss_hf = 0;
2468 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2469 rss_hf |= ETH_RSS_IPV4;
2470 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2471 rss_hf |= ETH_RSS_IPV4_TCP;
2472 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2473 rss_hf |= ETH_RSS_IPV6;
2474 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2475 rss_hf |= ETH_RSS_IPV6_EX;
2476 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2477 rss_hf |= ETH_RSS_IPV6_TCP;
2478 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2479 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2480 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2481 rss_hf |= ETH_RSS_IPV4_UDP;
2482 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2483 rss_hf |= ETH_RSS_IPV6_UDP;
2484 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2485 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2486 rss_conf->rss_hf = rss_hf;
2491 ixgbe_rss_configure(struct rte_eth_dev *dev)
2493 struct rte_eth_rss_conf rss_conf;
2494 struct ixgbe_hw *hw;
2499 PMD_INIT_FUNC_TRACE();
2500 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2503 * Fill in redirection table
2504 * The byte-swap is needed because NIC registers are in
2505 * little-endian order.
2508 for (i = 0, j = 0; i < 128; i++, j++) {
2509 if (j == dev->data->nb_rx_queues)
2511 reta = (reta << 8) | j;
2513 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2518 * Configure the RSS key and the RSS protocols used to compute
2519 * the RSS hash of input packets.
2521 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2522 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2523 ixgbe_rss_disable(dev);
2526 if (rss_conf.rss_key == NULL)
2527 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2528 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2531 #define NUM_VFTA_REGISTERS 128
2532 #define NIC_RX_BUFFER_SIZE 0x200
2535 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2537 struct rte_eth_vmdq_dcb_conf *cfg;
2538 struct ixgbe_hw *hw;
2539 enum rte_eth_nb_pools num_pools;
2540 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2542 uint8_t nb_tcs; /* number of traffic classes */
2545 PMD_INIT_FUNC_TRACE();
2546 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2547 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2548 num_pools = cfg->nb_queue_pools;
2549 /* Check we have a valid number of pools */
2550 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2551 ixgbe_rss_disable(dev);
2554 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2555 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2559 * split rx buffer up into sections, each for 1 traffic class
2561 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2562 for (i = 0 ; i < nb_tcs; i++) {
2563 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2564 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2565 /* clear 10 bits. */
2566 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2567 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2569 /* zero alloc all unused TCs */
2570 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2571 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2572 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2573 /* clear 10 bits. */
2574 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2577 /* MRQC: enable vmdq and dcb */
2578 mrqc = ((num_pools == ETH_16_POOLS) ? \
2579 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2580 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2582 /* PFVTCTL: turn on virtualisation and set the default pool */
2583 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2584 if (cfg->enable_default_pool) {
2585 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2587 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2590 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2592 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2594 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2596 * mapping is done with 3 bits per priority,
2597 * so shift by i*3 each time
2599 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2601 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2603 /* RTRPCS: DCB related */
2604 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2606 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2607 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2608 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2609 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2611 /* VFTA - enable all vlan filters */
2612 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2613 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2616 /* VFRE: pool enabling for receive - 16 or 32 */
2617 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2618 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2621 * MPSAR - allow pools to read specific mac addresses
2622 * In this case, all pools should be able to read from mac addr 0
2624 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2625 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2627 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2628 for (i = 0; i < cfg->nb_pool_maps; i++) {
2629 /* set vlan id in VF register and set the valid bit */
2630 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2631 (cfg->pool_map[i].vlan_id & 0xFFF)));
2633 * Put the allowed pools in VFB reg. As we only have 16 or 32
2634 * pools, we only need to use the first half of the register
2637 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2642 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2643 * @hw: pointer to hardware structure
2644 * @dcb_config: pointer to ixgbe_dcb_config structure
2647 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2648 struct ixgbe_dcb_config *dcb_config)
2653 PMD_INIT_FUNC_TRACE();
2654 if (hw->mac.type != ixgbe_mac_82598EB) {
2655 /* Disable the Tx desc arbiter so that MTQC can be changed */
2656 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2657 reg |= IXGBE_RTTDCS_ARBDIS;
2658 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2660 /* Enable DCB for Tx with 8 TCs */
2661 if (dcb_config->num_tcs.pg_tcs == 8) {
2662 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2665 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2667 if (dcb_config->vt_mode)
2668 reg |= IXGBE_MTQC_VT_ENA;
2669 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2671 /* Disable drop for all queues */
2672 for (q = 0; q < 128; q++)
2673 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2674 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2676 /* Enable the Tx desc arbiter */
2677 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2678 reg &= ~IXGBE_RTTDCS_ARBDIS;
2679 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2681 /* Enable Security TX Buffer IFG for DCB */
2682 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2683 reg |= IXGBE_SECTX_DCB;
2684 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2690 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2691 * @dev: pointer to rte_eth_dev structure
2692 * @dcb_config: pointer to ixgbe_dcb_config structure
2695 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2696 struct ixgbe_dcb_config *dcb_config)
2698 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2699 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2700 struct ixgbe_hw *hw =
2701 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2703 PMD_INIT_FUNC_TRACE();
2704 if (hw->mac.type != ixgbe_mac_82598EB)
2705 /*PF VF Transmit Enable*/
2706 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2707 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2709 /*Configure general DCB TX parameters*/
2710 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2715 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2716 struct ixgbe_dcb_config *dcb_config)
2718 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2719 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2720 struct ixgbe_dcb_tc_config *tc;
2723 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2724 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2725 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2726 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2729 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2730 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2732 /* User Priority to Traffic Class mapping */
2733 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2734 j = vmdq_rx_conf->dcb_queue[i];
2735 tc = &dcb_config->tc_config[j];
2736 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2742 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2743 struct ixgbe_dcb_config *dcb_config)
2745 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2746 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2747 struct ixgbe_dcb_tc_config *tc;
2750 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2751 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2752 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2753 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2756 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2757 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2760 /* User Priority to Traffic Class mapping */
2761 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2762 j = vmdq_tx_conf->dcb_queue[i];
2763 tc = &dcb_config->tc_config[j];
2764 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2771 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2772 struct ixgbe_dcb_config *dcb_config)
2774 struct rte_eth_dcb_rx_conf *rx_conf =
2775 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2776 struct ixgbe_dcb_tc_config *tc;
2779 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2780 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2782 /* User Priority to Traffic Class mapping */
2783 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2784 j = rx_conf->dcb_queue[i];
2785 tc = &dcb_config->tc_config[j];
2786 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2792 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2793 struct ixgbe_dcb_config *dcb_config)
2795 struct rte_eth_dcb_tx_conf *tx_conf =
2796 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2797 struct ixgbe_dcb_tc_config *tc;
2800 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2801 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2803 /* User Priority to Traffic Class mapping */
2804 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2805 j = tx_conf->dcb_queue[i];
2806 tc = &dcb_config->tc_config[j];
2807 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2813 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2814 * @hw: pointer to hardware structure
2815 * @dcb_config: pointer to ixgbe_dcb_config structure
2818 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2819 struct ixgbe_dcb_config *dcb_config)
2825 PMD_INIT_FUNC_TRACE();
2827 * Disable the arbiter before changing parameters
2828 * (always enable recycle mode; WSP)
2830 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2831 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2833 if (hw->mac.type != ixgbe_mac_82598EB) {
2834 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2835 if (dcb_config->num_tcs.pg_tcs == 4) {
2836 if (dcb_config->vt_mode)
2837 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2838 IXGBE_MRQC_VMDQRT4TCEN;
2840 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2841 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2845 if (dcb_config->num_tcs.pg_tcs == 8) {
2846 if (dcb_config->vt_mode)
2847 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2848 IXGBE_MRQC_VMDQRT8TCEN;
2850 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2851 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2856 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2859 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2860 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2861 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2862 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2864 /* VFTA - enable all vlan filters */
2865 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2866 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2870 * Configure Rx packet plane (recycle mode; WSP) and
2873 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2874 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2880 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2881 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2883 switch (hw->mac.type) {
2884 case ixgbe_mac_82598EB:
2885 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2887 case ixgbe_mac_82599EB:
2888 case ixgbe_mac_X540:
2889 case ixgbe_mac_X550:
2890 case ixgbe_mac_X550EM_x:
2891 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2900 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2901 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2903 switch (hw->mac.type) {
2904 case ixgbe_mac_82598EB:
2905 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2906 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2908 case ixgbe_mac_82599EB:
2909 case ixgbe_mac_X540:
2910 case ixgbe_mac_X550:
2911 case ixgbe_mac_X550EM_x:
2912 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2913 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2920 #define DCB_RX_CONFIG 1
2921 #define DCB_TX_CONFIG 1
2922 #define DCB_TX_PB 1024
2924 * ixgbe_dcb_hw_configure - Enable DCB and configure
2925 * general DCB in VT mode and non-VT mode parameters
2926 * @dev: pointer to rte_eth_dev structure
2927 * @dcb_config: pointer to ixgbe_dcb_config structure
2930 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2931 struct ixgbe_dcb_config *dcb_config)
2934 uint8_t i,pfc_en,nb_tcs;
2936 uint8_t config_dcb_rx = 0;
2937 uint8_t config_dcb_tx = 0;
2938 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2939 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2940 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2941 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2942 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2943 struct ixgbe_dcb_tc_config *tc;
2944 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2945 struct ixgbe_hw *hw =
2946 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2948 switch(dev->data->dev_conf.rxmode.mq_mode){
2949 case ETH_MQ_RX_VMDQ_DCB:
2950 dcb_config->vt_mode = true;
2951 if (hw->mac.type != ixgbe_mac_82598EB) {
2952 config_dcb_rx = DCB_RX_CONFIG;
2954 *get dcb and VT rx configuration parameters
2957 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2958 /*Configure general VMDQ and DCB RX parameters*/
2959 ixgbe_vmdq_dcb_configure(dev);
2963 dcb_config->vt_mode = false;
2964 config_dcb_rx = DCB_RX_CONFIG;
2965 /* Get dcb TX configuration parameters from rte_eth_conf */
2966 ixgbe_dcb_rx_config(dev,dcb_config);
2967 /*Configure general DCB RX parameters*/
2968 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2971 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
2974 switch (dev->data->dev_conf.txmode.mq_mode) {
2975 case ETH_MQ_TX_VMDQ_DCB:
2976 dcb_config->vt_mode = true;
2977 config_dcb_tx = DCB_TX_CONFIG;
2978 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2979 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2980 /*Configure general VMDQ and DCB TX parameters*/
2981 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2985 dcb_config->vt_mode = false;
2986 config_dcb_tx = DCB_TX_CONFIG;
2987 /*get DCB TX configuration parameters from rte_eth_conf*/
2988 ixgbe_dcb_tx_config(dev,dcb_config);
2989 /*Configure general DCB TX parameters*/
2990 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2993 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
2997 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2999 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3000 if(nb_tcs == ETH_4_TCS) {
3001 /* Avoid un-configured priority mapping to TC0 */
3003 uint8_t mask = 0xFF;
3004 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3005 mask = (uint8_t)(mask & (~ (1 << map[i])));
3006 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3007 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3011 /* Re-configure 4 TCs BW */
3012 for (i = 0; i < nb_tcs; i++) {
3013 tc = &dcb_config->tc_config[i];
3014 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3015 (uint8_t)(100 / nb_tcs);
3016 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3017 (uint8_t)(100 / nb_tcs);
3019 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3020 tc = &dcb_config->tc_config[i];
3021 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3022 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3027 /* Set RX buffer size */
3028 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3029 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3030 for (i = 0 ; i < nb_tcs; i++) {
3031 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3033 /* zero alloc all unused TCs */
3034 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3035 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3039 /* Only support an equally distributed Tx packet buffer strategy. */
3040 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3041 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3042 for (i = 0; i < nb_tcs; i++) {
3043 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3044 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3046 /* Clear unused TCs, if any, to zero buffer size*/
3047 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3048 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3049 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3053 /*Calculates traffic class credits*/
3054 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3055 IXGBE_DCB_TX_CONFIG);
3056 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3057 IXGBE_DCB_RX_CONFIG);
3060 /* Unpack CEE standard containers */
3061 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3062 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3063 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3064 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3065 /* Configure PG(ETS) RX */
3066 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3070 /* Unpack CEE standard containers */
3071 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3072 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3073 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3074 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3075 /* Configure PG(ETS) TX */
3076 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3079 /*Configure queue statistics registers*/
3080 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3082 /* Check if the PFC is supported */
3083 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3084 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3085 for (i = 0; i < nb_tcs; i++) {
3087 * If the TC count is 8,and the default high_water is 48,
3088 * the low_water is 16 as default.
3090 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3091 hw->fc.low_water[i] = pbsize / 4;
3092 /* Enable pfc for this TC */
3093 tc = &dcb_config->tc_config[i];
3094 tc->pfc = ixgbe_dcb_pfc_enabled;
3096 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3097 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3099 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3106 * ixgbe_configure_dcb - Configure DCB Hardware
3107 * @dev: pointer to rte_eth_dev
3109 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3111 struct ixgbe_dcb_config *dcb_cfg =
3112 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3113 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3115 PMD_INIT_FUNC_TRACE();
3117 /* check support mq_mode for DCB */
3118 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3119 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3122 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3125 /** Configure DCB hardware **/
3126 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3132 * VMDq only support for 10 GbE NIC.
3135 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3137 struct rte_eth_vmdq_rx_conf *cfg;
3138 struct ixgbe_hw *hw;
3139 enum rte_eth_nb_pools num_pools;
3140 uint32_t mrqc, vt_ctl, vlanctrl;
3144 PMD_INIT_FUNC_TRACE();
3145 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3146 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3147 num_pools = cfg->nb_queue_pools;
3149 ixgbe_rss_disable(dev);
3151 /* MRQC: enable vmdq */
3152 mrqc = IXGBE_MRQC_VMDQEN;
3153 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3155 /* PFVTCTL: turn on virtualisation and set the default pool */
3156 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3157 if (cfg->enable_default_pool)
3158 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3160 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3162 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3164 for (i = 0; i < (int)num_pools; i++) {
3165 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
3166 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
3169 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3170 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3171 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3172 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3174 /* VFTA - enable all vlan filters */
3175 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3176 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3178 /* VFRE: pool enabling for receive - 64 */
3179 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3180 if (num_pools == ETH_64_POOLS)
3181 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3184 * MPSAR - allow pools to read specific mac addresses
3185 * In this case, all pools should be able to read from mac addr 0
3187 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3188 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3190 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3191 for (i = 0; i < cfg->nb_pool_maps; i++) {
3192 /* set vlan id in VF register and set the valid bit */
3193 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3194 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3196 * Put the allowed pools in VFB reg. As we only have 16 or 64
3197 * pools, we only need to use the first half of the register
3200 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3201 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3202 (cfg->pool_map[i].pools & UINT32_MAX));
3204 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3205 ((cfg->pool_map[i].pools >> 32) \
3210 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3211 if (cfg->enable_loop_back) {
3212 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3213 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3214 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3217 IXGBE_WRITE_FLUSH(hw);
3221 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3222 * @hw: pointer to hardware structure
3225 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3230 PMD_INIT_FUNC_TRACE();
3231 /*PF VF Transmit Enable*/
3232 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3233 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3235 /* Disable the Tx desc arbiter so that MTQC can be changed */
3236 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3237 reg |= IXGBE_RTTDCS_ARBDIS;
3238 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3240 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3241 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3243 /* Disable drop for all queues */
3244 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3245 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3246 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3248 /* Enable the Tx desc arbiter */
3249 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3250 reg &= ~IXGBE_RTTDCS_ARBDIS;
3251 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3253 IXGBE_WRITE_FLUSH(hw);
3259 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
3261 struct igb_rx_entry *rxe = rxq->sw_ring;
3265 /* Initialize software ring entries */
3266 for (i = 0; i < rxq->nb_rx_desc; i++) {
3267 volatile union ixgbe_adv_rx_desc *rxd;
3268 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3270 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3271 (unsigned) rxq->queue_id);
3275 rte_mbuf_refcnt_set(mbuf, 1);
3277 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3279 mbuf->port = rxq->port_id;
3282 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3283 rxd = &rxq->rx_ring[i];
3284 rxd->read.hdr_addr = dma_addr;
3285 rxd->read.pkt_addr = dma_addr;
3293 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3295 struct ixgbe_hw *hw =
3296 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3298 if (hw->mac.type == ixgbe_mac_82598EB)
3301 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3303 * SRIOV inactive scheme
3304 * any DCB/RSS w/o VMDq multi-queue setting
3306 switch (dev->data->dev_conf.rxmode.mq_mode) {
3308 ixgbe_rss_configure(dev);
3311 case ETH_MQ_RX_VMDQ_DCB:
3312 ixgbe_vmdq_dcb_configure(dev);
3315 case ETH_MQ_RX_VMDQ_ONLY:
3316 ixgbe_vmdq_rx_hw_configure(dev);
3319 case ETH_MQ_RX_NONE:
3320 /* if mq_mode is none, disable rss mode.*/
3321 default: ixgbe_rss_disable(dev);
3324 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3326 * SRIOV active scheme
3327 * FIXME if support DCB/RSS together with VMDq & SRIOV
3330 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQEN);
3334 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT4TCEN);
3338 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT8TCEN);
3341 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3349 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3351 struct ixgbe_hw *hw =
3352 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3356 if (hw->mac.type == ixgbe_mac_82598EB)
3359 /* disable arbiter before setting MTQC */
3360 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3361 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3362 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3364 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3366 * SRIOV inactive scheme
3367 * any DCB w/o VMDq multi-queue setting
3369 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3370 ixgbe_vmdq_tx_hw_configure(hw);
3372 mtqc = IXGBE_MTQC_64Q_1PB;
3373 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3376 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3379 * SRIOV active scheme
3380 * FIXME if support DCB together with VMDq & SRIOV
3383 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3386 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3389 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3393 mtqc = IXGBE_MTQC_64Q_1PB;
3394 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3396 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3399 /* re-enable arbiter */
3400 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3401 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3407 * Initializes Receive Unit.
3410 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3412 struct ixgbe_hw *hw;
3413 struct igb_rx_queue *rxq;
3414 struct rte_pktmbuf_pool_private *mbp_priv;
3426 PMD_INIT_FUNC_TRACE();
3427 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3430 * Make sure receives are disabled while setting
3431 * up the RX context (registers, descriptor rings, etc.).
3433 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3434 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3436 /* Enable receipt of broadcasted frames */
3437 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3438 fctrl |= IXGBE_FCTRL_BAM;
3439 fctrl |= IXGBE_FCTRL_DPF;
3440 fctrl |= IXGBE_FCTRL_PMCF;
3441 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3444 * Configure CRC stripping, if any.
3446 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3447 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3448 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3450 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3453 * Configure jumbo frame support, if any.
3455 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3456 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3457 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3458 maxfrs &= 0x0000FFFF;
3459 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3460 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3462 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3465 * If loopback mode is configured for 82599, set LPBK bit.
3467 if (hw->mac.type == ixgbe_mac_82599EB &&
3468 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3469 hlreg0 |= IXGBE_HLREG0_LPBK;
3471 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3473 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3475 /* Setup RX queues */
3476 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3477 rxq = dev->data->rx_queues[i];
3480 * Reset crc_len in case it was changed after queue setup by a
3481 * call to configure.
3483 rxq->crc_len = (uint8_t)
3484 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3487 /* Setup the Base and Length of the Rx Descriptor Rings */
3488 bus_addr = rxq->rx_ring_phys_addr;
3489 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3490 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3491 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3492 (uint32_t)(bus_addr >> 32));
3493 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3494 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3495 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3496 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3498 /* Configure the SRRCTL register */
3499 #ifdef RTE_HEADER_SPLIT_ENABLE
3501 * Configure Header Split
3503 if (dev->data->dev_conf.rxmode.header_split) {
3504 if (hw->mac.type == ixgbe_mac_82599EB) {
3505 /* Must setup the PSRTYPE register */
3507 psrtype = IXGBE_PSRTYPE_TCPHDR |
3508 IXGBE_PSRTYPE_UDPHDR |
3509 IXGBE_PSRTYPE_IPV4HDR |
3510 IXGBE_PSRTYPE_IPV6HDR;
3511 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3513 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3514 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3515 IXGBE_SRRCTL_BSIZEHDR_MASK);
3516 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3519 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3521 /* Set if packets are dropped when no descriptors available */
3523 srrctl |= IXGBE_SRRCTL_DROP_EN;
3526 * Configure the RX buffer size in the BSIZEPACKET field of
3527 * the SRRCTL register of the queue.
3528 * The value is in 1 KB resolution. Valid values can be from
3531 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3532 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3533 RTE_PKTMBUF_HEADROOM);
3534 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3535 IXGBE_SRRCTL_BSIZEPKT_MASK);
3536 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3538 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3539 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3541 /* It adds dual VLAN length for supporting dual VLAN */
3542 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3543 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3544 if (!dev->data->scattered_rx)
3545 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
3546 dev->data->scattered_rx = 1;
3547 #ifdef RTE_IXGBE_INC_VECTOR
3548 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3550 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3555 if (dev->data->dev_conf.rxmode.enable_scatter) {
3556 if (!dev->data->scattered_rx)
3557 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
3558 #ifdef RTE_IXGBE_INC_VECTOR
3559 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3561 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3563 dev->data->scattered_rx = 1;
3567 * Device configured with multiple RX queues.
3569 ixgbe_dev_mq_rx_configure(dev);
3572 * Setup the Checksum Register.
3573 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3574 * Enable IP/L4 checkum computation by hardware if requested to do so.
3576 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3577 rxcsum |= IXGBE_RXCSUM_PCSD;
3578 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3579 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3581 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3583 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3585 if (hw->mac.type == ixgbe_mac_82599EB) {
3586 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3587 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3588 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3590 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3591 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3592 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3599 * Initializes Transmit Unit.
3602 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3604 struct ixgbe_hw *hw;
3605 struct igb_tx_queue *txq;
3611 PMD_INIT_FUNC_TRACE();
3612 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3614 /* Enable TX CRC (checksum offload requirement) */
3615 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3616 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
3617 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3619 /* Setup the Base and Length of the Tx Descriptor Rings */
3620 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3621 txq = dev->data->tx_queues[i];
3623 bus_addr = txq->tx_ring_phys_addr;
3624 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3625 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3626 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3627 (uint32_t)(bus_addr >> 32));
3628 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3629 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3630 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3631 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3632 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3635 * Disable Tx Head Writeback RO bit, since this hoses
3636 * bookkeeping if things aren't delivered in order.
3638 switch (hw->mac.type) {
3639 case ixgbe_mac_82598EB:
3640 txctrl = IXGBE_READ_REG(hw,
3641 IXGBE_DCA_TXCTRL(txq->reg_idx));
3642 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3643 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3647 case ixgbe_mac_82599EB:
3648 case ixgbe_mac_X540:
3649 case ixgbe_mac_X550:
3650 case ixgbe_mac_X550EM_x:
3652 txctrl = IXGBE_READ_REG(hw,
3653 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3654 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3655 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3661 /* Device configured with multiple TX queues. */
3662 ixgbe_dev_mq_tx_configure(dev);
3666 * Set up link for 82599 loopback mode Tx->Rx.
3669 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3671 PMD_INIT_FUNC_TRACE();
3673 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3674 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3676 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
3685 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3686 ixgbe_reset_pipeline_82599(hw);
3688 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3694 * Start Transmit and Receive Units.
3697 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3699 struct ixgbe_hw *hw;
3700 struct igb_tx_queue *txq;
3701 struct igb_rx_queue *rxq;
3707 PMD_INIT_FUNC_TRACE();
3708 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3710 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3711 txq = dev->data->tx_queues[i];
3712 /* Setup Transmit Threshold Registers */
3713 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3714 txdctl |= txq->pthresh & 0x7F;
3715 txdctl |= ((txq->hthresh & 0x7F) << 8);
3716 txdctl |= ((txq->wthresh & 0x7F) << 16);
3717 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3720 if (hw->mac.type != ixgbe_mac_82598EB) {
3721 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3722 dmatxctl |= IXGBE_DMATXCTL_TE;
3723 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3726 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3727 txq = dev->data->tx_queues[i];
3728 if (!txq->tx_deferred_start)
3729 ixgbe_dev_tx_queue_start(dev, i);
3732 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3733 rxq = dev->data->rx_queues[i];
3734 if (!rxq->rx_deferred_start)
3735 ixgbe_dev_rx_queue_start(dev, i);
3738 /* Enable Receive engine */
3739 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3740 if (hw->mac.type == ixgbe_mac_82598EB)
3741 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3742 rxctrl |= IXGBE_RXCTRL_RXEN;
3743 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3745 /* If loopback mode is enabled for 82599, set up the link accordingly */
3746 if (hw->mac.type == ixgbe_mac_82599EB &&
3747 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3748 ixgbe_setup_loopback_link_82599(hw);
3753 * Start Receive Units for specified queue.
3756 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3758 struct ixgbe_hw *hw;
3759 struct igb_rx_queue *rxq;
3763 PMD_INIT_FUNC_TRACE();
3764 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3766 if (rx_queue_id < dev->data->nb_rx_queues) {
3767 rxq = dev->data->rx_queues[rx_queue_id];
3769 /* Allocate buffers for descriptor rings */
3770 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
3771 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
3775 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3776 rxdctl |= IXGBE_RXDCTL_ENABLE;
3777 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3779 /* Wait until RX Enable ready */
3780 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3783 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3784 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3786 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
3789 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3790 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3798 * Stop Receive Units for specified queue.
3801 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3803 struct ixgbe_hw *hw;
3804 struct igb_rx_queue *rxq;
3808 PMD_INIT_FUNC_TRACE();
3809 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3811 if (rx_queue_id < dev->data->nb_rx_queues) {
3812 rxq = dev->data->rx_queues[rx_queue_id];
3814 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3815 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3816 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3818 /* Wait until RX Enable ready */
3819 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3822 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3823 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
3825 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
3828 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3830 ixgbe_rx_queue_release_mbufs(rxq);
3831 ixgbe_reset_rx_queue(rxq);
3840 * Start Transmit Units for specified queue.
3843 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3845 struct ixgbe_hw *hw;
3846 struct igb_tx_queue *txq;
3850 PMD_INIT_FUNC_TRACE();
3851 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3853 if (tx_queue_id < dev->data->nb_tx_queues) {
3854 txq = dev->data->tx_queues[tx_queue_id];
3855 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3856 txdctl |= IXGBE_TXDCTL_ENABLE;
3857 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3859 /* Wait until TX Enable ready */
3860 if (hw->mac.type == ixgbe_mac_82599EB) {
3861 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3864 txdctl = IXGBE_READ_REG(hw,
3865 IXGBE_TXDCTL(txq->reg_idx));
3866 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3868 PMD_INIT_LOG(ERR, "Could not enable "
3869 "Tx Queue %d", tx_queue_id);
3872 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3873 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3881 * Stop Transmit Units for specified queue.
3884 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3886 struct ixgbe_hw *hw;
3887 struct igb_tx_queue *txq;
3889 uint32_t txtdh, txtdt;
3892 PMD_INIT_FUNC_TRACE();
3893 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3895 if (tx_queue_id < dev->data->nb_tx_queues) {
3896 txq = dev->data->tx_queues[tx_queue_id];
3898 /* Wait until TX queue is empty */
3899 if (hw->mac.type == ixgbe_mac_82599EB) {
3900 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3902 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3903 txtdh = IXGBE_READ_REG(hw,
3904 IXGBE_TDH(txq->reg_idx));
3905 txtdt = IXGBE_READ_REG(hw,
3906 IXGBE_TDT(txq->reg_idx));
3907 } while (--poll_ms && (txtdh != txtdt));
3909 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
3910 "when stopping.", tx_queue_id);
3913 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3914 txdctl &= ~IXGBE_TXDCTL_ENABLE;
3915 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3917 /* Wait until TX Enable ready */
3918 if (hw->mac.type == ixgbe_mac_82599EB) {
3919 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3922 txdctl = IXGBE_READ_REG(hw,
3923 IXGBE_TXDCTL(txq->reg_idx));
3924 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
3926 PMD_INIT_LOG(ERR, "Could not disable "
3927 "Tx Queue %d", tx_queue_id);
3930 if (txq->ops != NULL) {
3931 txq->ops->release_mbufs(txq);
3932 txq->ops->reset(txq);
3941 * [VF] Initializes Receive Unit.
3944 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3946 struct ixgbe_hw *hw;
3947 struct igb_rx_queue *rxq;
3948 struct rte_pktmbuf_pool_private *mbp_priv;
3955 PMD_INIT_FUNC_TRACE();
3956 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3959 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
3960 * disables the VF receipt of packets if the PF MTU is > 1500.
3961 * This is done to deal with 82599 limitations that imposes
3962 * the PF and all VFs to share the same MTU.
3963 * Then, the PF driver enables again the VF receipt of packet when
3964 * the VF driver issues a IXGBE_VF_SET_LPE request.
3965 * In the meantime, the VF device cannot be used, even if the VF driver
3966 * and the Guest VM network stack are ready to accept packets with a
3967 * size up to the PF MTU.
3968 * As a work-around to this PF behaviour, force the call to
3969 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
3970 * VF packets received can work in all cases.
3972 ixgbevf_rlpml_set_vf(hw,
3973 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
3975 /* Setup RX queues */
3976 dev->rx_pkt_burst = ixgbe_recv_pkts;
3977 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3978 rxq = dev->data->rx_queues[i];
3980 /* Allocate buffers for descriptor rings */
3981 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3985 /* Setup the Base and Length of the Rx Descriptor Rings */
3986 bus_addr = rxq->rx_ring_phys_addr;
3988 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3989 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3990 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3991 (uint32_t)(bus_addr >> 32));
3992 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3993 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3994 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3995 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3998 /* Configure the SRRCTL register */
3999 #ifdef RTE_HEADER_SPLIT_ENABLE
4001 * Configure Header Split
4003 if (dev->data->dev_conf.rxmode.header_split) {
4005 /* Must setup the PSRTYPE register */
4007 psrtype = IXGBE_PSRTYPE_TCPHDR |
4008 IXGBE_PSRTYPE_UDPHDR |
4009 IXGBE_PSRTYPE_IPV4HDR |
4010 IXGBE_PSRTYPE_IPV6HDR;
4012 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
4014 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
4015 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4016 IXGBE_SRRCTL_BSIZEHDR_MASK);
4017 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4020 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4022 /* Set if packets are dropped when no descriptors available */
4024 srrctl |= IXGBE_SRRCTL_DROP_EN;
4027 * Configure the RX buffer size in the BSIZEPACKET field of
4028 * the SRRCTL register of the queue.
4029 * The value is in 1 KB resolution. Valid values can be from
4032 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
4033 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
4034 RTE_PKTMBUF_HEADROOM);
4035 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4036 IXGBE_SRRCTL_BSIZEPKT_MASK);
4039 * VF modification to write virtual function SRRCTL register
4041 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
4043 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4044 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4046 /* It adds dual VLAN length for supporting dual VLAN */
4047 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
4048 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
4049 if (!dev->data->scattered_rx)
4050 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4051 dev->data->scattered_rx = 1;
4052 #ifdef RTE_IXGBE_INC_VECTOR
4053 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4055 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
4060 if (dev->data->dev_conf.rxmode.enable_scatter) {
4061 if (!dev->data->scattered_rx)
4062 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4063 #ifdef RTE_IXGBE_INC_VECTOR
4064 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4066 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
4068 dev->data->scattered_rx = 1;
4075 * [VF] Initializes Transmit Unit.
4078 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4080 struct ixgbe_hw *hw;
4081 struct igb_tx_queue *txq;
4086 PMD_INIT_FUNC_TRACE();
4087 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4089 /* Setup the Base and Length of the Tx Descriptor Rings */
4090 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4091 txq = dev->data->tx_queues[i];
4092 bus_addr = txq->tx_ring_phys_addr;
4093 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4094 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4095 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4096 (uint32_t)(bus_addr >> 32));
4097 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4098 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4099 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4100 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4101 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4104 * Disable Tx Head Writeback RO bit, since this hoses
4105 * bookkeeping if things aren't delivered in order.
4107 txctrl = IXGBE_READ_REG(hw,
4108 IXGBE_VFDCA_TXCTRL(i));
4109 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4110 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4116 * [VF] Start Transmit and Receive Units.
4119 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4121 struct ixgbe_hw *hw;
4122 struct igb_tx_queue *txq;
4123 struct igb_rx_queue *rxq;
4129 PMD_INIT_FUNC_TRACE();
4130 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4132 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4133 txq = dev->data->tx_queues[i];
4134 /* Setup Transmit Threshold Registers */
4135 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4136 txdctl |= txq->pthresh & 0x7F;
4137 txdctl |= ((txq->hthresh & 0x7F) << 8);
4138 txdctl |= ((txq->wthresh & 0x7F) << 16);
4139 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4142 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4144 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4145 txdctl |= IXGBE_TXDCTL_ENABLE;
4146 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4149 /* Wait until TX Enable ready */
4152 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4153 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4155 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
4157 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4159 rxq = dev->data->rx_queues[i];
4161 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4162 rxdctl |= IXGBE_RXDCTL_ENABLE;
4163 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4165 /* Wait until RX Enable ready */
4169 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4170 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4172 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
4174 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);