4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5 * Copyright 2014 6WIND S.A.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * * Neither the name of Intel Corporation nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
46 #include <rte_byteorder.h>
47 #include <rte_common.h>
48 #include <rte_cycles.h>
50 #include <rte_debug.h>
51 #include <rte_interrupts.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_launch.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
80 #include "ixgbe_rxtx.h"
82 /* Bit Mask to indicate what bits required for building TX context */
83 #define IXGBE_TX_OFFLOAD_MASK ( \
89 static inline struct rte_mbuf *
90 rte_rxmbuf_alloc(struct rte_mempool *mp)
94 m = __rte_mbuf_raw_alloc(mp);
95 __rte_mbuf_sanity_check_raw(m, 0);
101 #define RTE_PMD_USE_PREFETCH
104 #ifdef RTE_PMD_USE_PREFETCH
106 * Prefetch a cache line into all cache levels.
108 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
110 #define rte_ixgbe_prefetch(p) do {} while(0)
113 /*********************************************************************
117 **********************************************************************/
120 * Check for descriptors with their DD bit set and free mbufs.
121 * Return the total number of buffers freed.
123 static inline int __attribute__((always_inline))
124 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
126 struct ixgbe_tx_entry *txep;
130 /* check DD bit on threshold descriptor */
131 status = txq->tx_ring[txq->tx_next_dd].wb.status;
132 if (! (status & IXGBE_ADVTXD_STAT_DD))
136 * first buffer to free from S/W ring is at index
137 * tx_next_dd - (tx_rs_thresh-1)
139 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
141 /* free buffers one at a time */
142 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
143 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
144 txep->mbuf->next = NULL;
145 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
149 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
150 rte_pktmbuf_free_seg(txep->mbuf);
155 /* buffers were freed, update counters */
156 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
157 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
158 if (txq->tx_next_dd >= txq->nb_tx_desc)
159 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
161 return txq->tx_rs_thresh;
164 /* Populate 4 descriptors with data from 4 mbufs */
166 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
168 uint64_t buf_dma_addr;
172 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
173 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
174 pkt_len = (*pkts)->data_len;
176 /* write data to descriptor */
177 txdp->read.buffer_addr = buf_dma_addr;
178 txdp->read.cmd_type_len =
179 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
180 txdp->read.olinfo_status =
181 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
182 rte_prefetch0(&(*pkts)->pool);
186 /* Populate 1 descriptor with data from 1 mbuf */
188 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
190 uint64_t buf_dma_addr;
193 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
194 pkt_len = (*pkts)->data_len;
196 /* write data to descriptor */
197 txdp->read.buffer_addr = buf_dma_addr;
198 txdp->read.cmd_type_len =
199 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
200 txdp->read.olinfo_status =
201 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
202 rte_prefetch0(&(*pkts)->pool);
206 * Fill H/W descriptor ring with mbuf data.
207 * Copy mbuf pointers to the S/W ring.
210 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
213 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
214 struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
215 const int N_PER_LOOP = 4;
216 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
217 int mainpart, leftover;
221 * Process most of the packets in chunks of N pkts. Any
222 * leftover packets will get processed one at a time.
224 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
225 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
226 for (i = 0; i < mainpart; i += N_PER_LOOP) {
227 /* Copy N mbuf pointers to the S/W ring */
228 for (j = 0; j < N_PER_LOOP; ++j) {
229 (txep + i + j)->mbuf = *(pkts + i + j);
231 tx4(txdp + i, pkts + i);
234 if (unlikely(leftover > 0)) {
235 for (i = 0; i < leftover; ++i) {
236 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
237 tx1(txdp + mainpart + i, pkts + mainpart + i);
242 static inline uint16_t
243 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
246 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
247 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
251 * Begin scanning the H/W ring for done descriptors when the
252 * number of available descriptors drops below tx_free_thresh. For
253 * each done descriptor, free the associated buffer.
255 if (txq->nb_tx_free < txq->tx_free_thresh)
256 ixgbe_tx_free_bufs(txq);
258 /* Only use descriptors that are available */
259 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
260 if (unlikely(nb_pkts == 0))
263 /* Use exactly nb_pkts descriptors */
264 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
267 * At this point, we know there are enough descriptors in the
268 * ring to transmit all the packets. This assumes that each
269 * mbuf contains a single segment, and that no new offloads
270 * are expected, which would require a new context descriptor.
274 * See if we're going to wrap-around. If so, handle the top
275 * of the descriptor ring first, then do the bottom. If not,
276 * the processing looks just like the "bottom" part anyway...
278 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
279 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
280 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
283 * We know that the last descriptor in the ring will need to
284 * have its RS bit set because tx_rs_thresh has to be
285 * a divisor of the ring size
287 tx_r[txq->tx_next_rs].read.cmd_type_len |=
288 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
289 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
294 /* Fill H/W descriptor ring with mbuf data */
295 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
296 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
299 * Determine if RS bit should be set
300 * This is what we actually want:
301 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
302 * but instead of subtracting 1 and doing >=, we can just do
303 * greater than without subtracting.
305 if (txq->tx_tail > txq->tx_next_rs) {
306 tx_r[txq->tx_next_rs].read.cmd_type_len |=
307 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
308 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
310 if (txq->tx_next_rs >= txq->nb_tx_desc)
311 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
315 * Check for wrap-around. This would only happen if we used
316 * up to the last descriptor in the ring, no more, no less.
318 if (txq->tx_tail >= txq->nb_tx_desc)
321 /* update tail pointer */
323 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
329 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
334 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
335 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
336 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
338 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
342 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
343 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
344 nb_tx = (uint16_t)(nb_tx + ret);
345 nb_pkts = (uint16_t)(nb_pkts - ret);
354 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
355 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
356 uint64_t ol_flags, union ixgbe_tx_offload tx_offload)
358 uint32_t type_tucmd_mlhl;
359 uint32_t mss_l4len_idx = 0;
361 uint32_t vlan_macip_lens;
362 union ixgbe_tx_offload tx_offload_mask;
364 ctx_idx = txq->ctx_curr;
365 tx_offload_mask.data = 0;
368 /* Specify which HW CTX to upload. */
369 mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
371 if (ol_flags & PKT_TX_VLAN_PKT) {
372 tx_offload_mask.vlan_tci |= ~0;
375 /* check if TCP segmentation required for this packet */
376 if (ol_flags & PKT_TX_TCP_SEG) {
377 /* implies IP cksum and TCP cksum */
378 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
379 IXGBE_ADVTXD_TUCMD_L4T_TCP |
380 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
382 tx_offload_mask.l2_len |= ~0;
383 tx_offload_mask.l3_len |= ~0;
384 tx_offload_mask.l4_len |= ~0;
385 tx_offload_mask.tso_segsz |= ~0;
386 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
387 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
388 } else { /* no TSO, check if hardware checksum is needed */
389 if (ol_flags & PKT_TX_IP_CKSUM) {
390 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
391 tx_offload_mask.l2_len |= ~0;
392 tx_offload_mask.l3_len |= ~0;
395 switch (ol_flags & PKT_TX_L4_MASK) {
396 case PKT_TX_UDP_CKSUM:
397 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
398 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
399 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
400 tx_offload_mask.l2_len |= ~0;
401 tx_offload_mask.l3_len |= ~0;
403 case PKT_TX_TCP_CKSUM:
404 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
405 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
406 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
407 tx_offload_mask.l2_len |= ~0;
408 tx_offload_mask.l3_len |= ~0;
409 tx_offload_mask.l4_len |= ~0;
411 case PKT_TX_SCTP_CKSUM:
412 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
413 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
414 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
415 tx_offload_mask.l2_len |= ~0;
416 tx_offload_mask.l3_len |= ~0;
419 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
420 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
425 txq->ctx_cache[ctx_idx].flags = ol_flags;
426 txq->ctx_cache[ctx_idx].tx_offload.data =
427 tx_offload_mask.data & tx_offload.data;
428 txq->ctx_cache[ctx_idx].tx_offload_mask = tx_offload_mask;
430 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
431 vlan_macip_lens = tx_offload.l3_len;
432 vlan_macip_lens |= (tx_offload.l2_len << IXGBE_ADVTXD_MACLEN_SHIFT);
433 vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
434 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
435 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
436 ctx_txd->seqnum_seed = 0;
440 * Check which hardware context can be used. Use the existing match
441 * or create a new context descriptor.
443 static inline uint32_t
444 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
445 union ixgbe_tx_offload tx_offload)
447 /* If match with the current used context */
448 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
449 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
450 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
451 return txq->ctx_curr;
454 /* What if match with the next context */
456 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
457 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
458 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
459 return txq->ctx_curr;
462 /* Mismatch, use the previous context */
463 return (IXGBE_CTX_NUM);
466 static inline uint32_t
467 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
470 if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
471 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
472 if (ol_flags & PKT_TX_IP_CKSUM)
473 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
474 if (ol_flags & PKT_TX_TCP_SEG)
475 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
479 static inline uint32_t
480 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
482 uint32_t cmdtype = 0;
483 if (ol_flags & PKT_TX_VLAN_PKT)
484 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
485 if (ol_flags & PKT_TX_TCP_SEG)
486 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
490 /* Default RS bit threshold values */
491 #ifndef DEFAULT_TX_RS_THRESH
492 #define DEFAULT_TX_RS_THRESH 32
494 #ifndef DEFAULT_TX_FREE_THRESH
495 #define DEFAULT_TX_FREE_THRESH 32
498 /* Reset transmit descriptors after they have been used */
500 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
502 struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
503 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
504 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
505 uint16_t nb_tx_desc = txq->nb_tx_desc;
506 uint16_t desc_to_clean_to;
507 uint16_t nb_tx_to_clean;
509 /* Determine the last descriptor needing to be cleaned */
510 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
511 if (desc_to_clean_to >= nb_tx_desc)
512 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
514 /* Check to make sure the last descriptor to clean is done */
515 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
516 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
518 PMD_TX_FREE_LOG(DEBUG,
519 "TX descriptor %4u is not done"
520 "(port=%d queue=%d)",
522 txq->port_id, txq->queue_id);
523 /* Failed to clean any descriptors, better luck next time */
527 /* Figure out how many descriptors will be cleaned */
528 if (last_desc_cleaned > desc_to_clean_to)
529 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
532 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
535 PMD_TX_FREE_LOG(DEBUG,
536 "Cleaning %4u TX descriptors: %4u to %4u "
537 "(port=%d queue=%d)",
538 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
539 txq->port_id, txq->queue_id);
542 * The last descriptor to clean is done, so that means all the
543 * descriptors from the last descriptor that was cleaned
544 * up to the last descriptor with the RS bit set
545 * are done. Only reset the threshold descriptor.
547 txr[desc_to_clean_to].wb.status = 0;
549 /* Update the txq to reflect the last descriptor that was cleaned */
550 txq->last_desc_cleaned = desc_to_clean_to;
551 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
558 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
561 struct ixgbe_tx_queue *txq;
562 struct ixgbe_tx_entry *sw_ring;
563 struct ixgbe_tx_entry *txe, *txn;
564 volatile union ixgbe_adv_tx_desc *txr;
565 volatile union ixgbe_adv_tx_desc *txd;
566 struct rte_mbuf *tx_pkt;
567 struct rte_mbuf *m_seg;
568 uint64_t buf_dma_addr;
569 uint32_t olinfo_status;
570 uint32_t cmd_type_len;
581 union ixgbe_tx_offload tx_offload = { .data = 0 };
584 sw_ring = txq->sw_ring;
586 tx_id = txq->tx_tail;
587 txe = &sw_ring[tx_id];
589 /* Determine if the descriptor ring needs to be cleaned. */
590 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
591 ixgbe_xmit_cleanup(txq);
594 rte_prefetch0(&txe->mbuf->pool);
597 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
600 pkt_len = tx_pkt->pkt_len;
603 * Determine how many (if any) context descriptors
604 * are needed for offload functionality.
606 ol_flags = tx_pkt->ol_flags;
608 /* If hardware offload required */
609 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
611 tx_offload.l2_len = tx_pkt->l2_len;
612 tx_offload.l3_len = tx_pkt->l3_len;
613 tx_offload.l4_len = tx_pkt->l4_len;
614 tx_offload.vlan_tci = tx_pkt->vlan_tci;
615 tx_offload.tso_segsz = tx_pkt->tso_segsz;
617 /* If new context need be built or reuse the exist ctx. */
618 ctx = what_advctx_update(txq, tx_ol_req,
620 /* Only allocate context descriptor if required*/
621 new_ctx = (ctx == IXGBE_CTX_NUM);
626 * Keep track of how many descriptors are used this loop
627 * This will always be the number of segments + the number of
628 * Context descriptors required to transmit the packet
630 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
633 * The number of descriptors that must be allocated for a
634 * packet is the number of segments of that packet, plus 1
635 * Context Descriptor for the hardware offload, if any.
636 * Determine the last TX descriptor to allocate in the TX ring
637 * for the packet, starting from the current position (tx_id)
640 tx_last = (uint16_t) (tx_id + nb_used - 1);
643 if (tx_last >= txq->nb_tx_desc)
644 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
646 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
647 " tx_first=%u tx_last=%u",
648 (unsigned) txq->port_id,
649 (unsigned) txq->queue_id,
655 * Make sure there are enough TX descriptors available to
656 * transmit the entire packet.
657 * nb_used better be less than or equal to txq->tx_rs_thresh
659 if (nb_used > txq->nb_tx_free) {
660 PMD_TX_FREE_LOG(DEBUG,
661 "Not enough free TX descriptors "
662 "nb_used=%4u nb_free=%4u "
663 "(port=%d queue=%d)",
664 nb_used, txq->nb_tx_free,
665 txq->port_id, txq->queue_id);
667 if (ixgbe_xmit_cleanup(txq) != 0) {
668 /* Could not clean any descriptors */
674 /* nb_used better be <= txq->tx_rs_thresh */
675 if (unlikely(nb_used > txq->tx_rs_thresh)) {
676 PMD_TX_FREE_LOG(DEBUG,
677 "The number of descriptors needed to "
678 "transmit the packet exceeds the "
679 "RS bit threshold. This will impact "
681 "nb_used=%4u nb_free=%4u "
683 "(port=%d queue=%d)",
684 nb_used, txq->nb_tx_free,
686 txq->port_id, txq->queue_id);
688 * Loop here until there are enough TX
689 * descriptors or until the ring cannot be
692 while (nb_used > txq->nb_tx_free) {
693 if (ixgbe_xmit_cleanup(txq) != 0) {
695 * Could not clean any
707 * By now there are enough free TX descriptors to transmit
712 * Set common flags of all TX Data Descriptors.
714 * The following bits must be set in all Data Descriptors:
715 * - IXGBE_ADVTXD_DTYP_DATA
716 * - IXGBE_ADVTXD_DCMD_DEXT
718 * The following bits must be set in the first Data Descriptor
719 * and are ignored in the other ones:
720 * - IXGBE_ADVTXD_DCMD_IFCS
721 * - IXGBE_ADVTXD_MAC_1588
722 * - IXGBE_ADVTXD_DCMD_VLE
724 * The following bits must only be set in the last Data
726 * - IXGBE_TXD_CMD_EOP
728 * The following bits can be set in any Data Descriptor, but
729 * are only set in the last Data Descriptor:
732 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
733 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
735 #ifdef RTE_LIBRTE_IEEE1588
736 if (ol_flags & PKT_TX_IEEE1588_TMST)
737 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
743 if (ol_flags & PKT_TX_TCP_SEG) {
744 /* when TSO is on, paylen in descriptor is the
745 * not the packet len but the tcp payload len */
746 pkt_len -= (tx_offload.l2_len +
747 tx_offload.l3_len + tx_offload.l4_len);
751 * Setup the TX Advanced Context Descriptor if required
754 volatile struct ixgbe_adv_tx_context_desc *
757 ctx_txd = (volatile struct
758 ixgbe_adv_tx_context_desc *)
761 txn = &sw_ring[txe->next_id];
762 rte_prefetch0(&txn->mbuf->pool);
764 if (txe->mbuf != NULL) {
765 rte_pktmbuf_free_seg(txe->mbuf);
769 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
772 txe->last_id = tx_last;
773 tx_id = txe->next_id;
778 * Setup the TX Advanced Data Descriptor,
779 * This path will go through
780 * whatever new/reuse the context descriptor
782 cmd_type_len |= tx_desc_ol_flags_to_cmdtype(ol_flags);
783 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
784 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
787 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
792 txn = &sw_ring[txe->next_id];
793 rte_prefetch0(&txn->mbuf->pool);
795 if (txe->mbuf != NULL)
796 rte_pktmbuf_free_seg(txe->mbuf);
800 * Set up Transmit Data Descriptor.
802 slen = m_seg->data_len;
803 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
804 txd->read.buffer_addr =
805 rte_cpu_to_le_64(buf_dma_addr);
806 txd->read.cmd_type_len =
807 rte_cpu_to_le_32(cmd_type_len | slen);
808 txd->read.olinfo_status =
809 rte_cpu_to_le_32(olinfo_status);
810 txe->last_id = tx_last;
811 tx_id = txe->next_id;
814 } while (m_seg != NULL);
817 * The last packet data descriptor needs End Of Packet (EOP)
819 cmd_type_len |= IXGBE_TXD_CMD_EOP;
820 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
821 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
823 /* Set RS bit only on threshold packets' last descriptor */
824 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
825 PMD_TX_FREE_LOG(DEBUG,
826 "Setting RS bit on TXD id="
827 "%4u (port=%d queue=%d)",
828 tx_last, txq->port_id, txq->queue_id);
830 cmd_type_len |= IXGBE_TXD_CMD_RS;
832 /* Update txq RS bit counters */
835 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
841 * Set the Transmit Descriptor Tail (TDT)
843 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
844 (unsigned) txq->port_id, (unsigned) txq->queue_id,
845 (unsigned) tx_id, (unsigned) nb_tx);
846 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
847 txq->tx_tail = tx_id;
852 /*********************************************************************
856 **********************************************************************/
857 static inline uint64_t
858 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
862 static const uint64_t ip_pkt_types_map[16] = {
863 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
864 PKT_RX_IPV6_HDR, 0, 0, 0,
865 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
866 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
869 static const uint64_t ip_rss_types_map[16] = {
870 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
871 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
872 PKT_RX_RSS_HASH, 0, 0, 0,
873 0, 0, 0, PKT_RX_FDIR,
876 #ifdef RTE_LIBRTE_IEEE1588
877 static uint64_t ip_pkt_etqf_map[8] = {
878 0, 0, 0, PKT_RX_IEEE1588_PTP,
882 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
883 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
884 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
886 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
887 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
890 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
893 static inline uint64_t
894 rx_desc_status_to_pkt_flags(uint32_t rx_status)
899 * Check if VLAN present only.
900 * Do not check whether L3/L4 rx checksum done by NIC or not,
901 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
903 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
905 #ifdef RTE_LIBRTE_IEEE1588
906 if (rx_status & IXGBE_RXD_STAT_TMST)
907 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
912 static inline uint64_t
913 rx_desc_error_to_pkt_flags(uint32_t rx_status)
916 * Bit 31: IPE, IPv4 checksum error
917 * Bit 30: L4I, L4I integrity error
919 static uint64_t error_to_pkt_flags_map[4] = {
920 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
921 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
923 return error_to_pkt_flags_map[(rx_status >>
924 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
927 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
929 * LOOK_AHEAD defines how many desc statuses to check beyond the
930 * current descriptor.
931 * It must be a pound define for optimal performance.
932 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
933 * function only works with LOOK_AHEAD=8.
936 #if (LOOK_AHEAD != 8)
937 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
940 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
942 volatile union ixgbe_adv_rx_desc *rxdp;
943 struct ixgbe_rx_entry *rxep;
947 int s[LOOK_AHEAD], nb_dd;
951 /* get references to current descriptor and S/W ring entry */
952 rxdp = &rxq->rx_ring[rxq->rx_tail];
953 rxep = &rxq->sw_ring[rxq->rx_tail];
955 /* check to make sure there is at least 1 packet to receive */
956 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
960 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
961 * reference packets that are ready to be received.
963 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
964 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
966 /* Read desc statuses backwards to avoid race condition */
967 for (j = LOOK_AHEAD-1; j >= 0; --j)
968 s[j] = rxdp[j].wb.upper.status_error;
970 /* Compute how many status bits were set */
972 for (j = 0; j < LOOK_AHEAD; ++j)
973 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
977 /* Translate descriptor info to mbuf format */
978 for (j = 0; j < nb_dd; ++j) {
980 pkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len);
981 mb->data_len = pkt_len;
982 mb->pkt_len = pkt_len;
983 mb->vlan_tci = rxdp[j].wb.upper.vlan;
984 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
986 /* convert descriptor fields to rte mbuf flags */
987 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(
988 rxdp[j].wb.lower.lo_dword.data);
989 /* reuse status field from scan list */
990 pkt_flags |= rx_desc_status_to_pkt_flags(s[j]);
991 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
992 mb->ol_flags = pkt_flags;
994 if (likely(pkt_flags & PKT_RX_RSS_HASH))
995 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
996 else if (pkt_flags & PKT_RX_FDIR) {
998 (uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum)
999 & IXGBE_ATR_HASH_MASK);
1000 mb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id;
1004 /* Move mbuf pointers from the S/W ring to the stage */
1005 for (j = 0; j < LOOK_AHEAD; ++j) {
1006 rxq->rx_stage[i + j] = rxep[j].mbuf;
1009 /* stop if all requested packets could not be received */
1010 if (nb_dd != LOOK_AHEAD)
1014 /* clear software ring entries so we can cleanup correctly */
1015 for (i = 0; i < nb_rx; ++i) {
1016 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1024 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)
1026 volatile union ixgbe_adv_rx_desc *rxdp;
1027 struct ixgbe_rx_entry *rxep;
1028 struct rte_mbuf *mb;
1033 /* allocate buffers in bulk directly into the S/W ring */
1034 alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1035 rxep = &rxq->sw_ring[alloc_idx];
1036 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1037 rxq->rx_free_thresh);
1038 if (unlikely(diag != 0))
1041 rxdp = &rxq->rx_ring[alloc_idx];
1042 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1043 /* populate the static rte mbuf fields */
1048 mb->port = rxq->port_id;
1051 rte_mbuf_refcnt_set(mb, 1);
1052 mb->data_off = RTE_PKTMBUF_HEADROOM;
1054 /* populate the descriptors */
1055 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
1056 rxdp[i].read.hdr_addr = dma_addr;
1057 rxdp[i].read.pkt_addr = dma_addr;
1060 /* update state of internal queue structure */
1061 rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
1062 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1063 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1069 static inline uint16_t
1070 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1073 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1076 /* how many packets are ready to return? */
1077 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1079 /* copy mbuf pointers to the application's packet list */
1080 for (i = 0; i < nb_pkts; ++i)
1081 rx_pkts[i] = stage[i];
1083 /* update internal queue state */
1084 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1085 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1090 static inline uint16_t
1091 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1094 struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1097 /* Any previously recv'd pkts will be returned from the Rx stage */
1098 if (rxq->rx_nb_avail)
1099 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1101 /* Scan the H/W ring for packets to receive */
1102 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1104 /* update internal queue state */
1105 rxq->rx_next_avail = 0;
1106 rxq->rx_nb_avail = nb_rx;
1107 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1109 /* if required, allocate new buffers to replenish descriptors */
1110 if (rxq->rx_tail > rxq->rx_free_trigger) {
1111 uint16_t cur_free_trigger = rxq->rx_free_trigger;
1113 if (ixgbe_rx_alloc_bufs(rxq, true) != 0) {
1115 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1116 "queue_id=%u", (unsigned) rxq->port_id,
1117 (unsigned) rxq->queue_id);
1119 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1120 rxq->rx_free_thresh;
1123 * Need to rewind any previous receives if we cannot
1124 * allocate new buffers to replenish the old ones.
1126 rxq->rx_nb_avail = 0;
1127 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1128 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1129 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1134 /* update tail pointer */
1136 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, cur_free_trigger);
1139 if (rxq->rx_tail >= rxq->nb_rx_desc)
1142 /* received any packets this loop? */
1143 if (rxq->rx_nb_avail)
1144 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1149 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1151 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1156 if (unlikely(nb_pkts == 0))
1159 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1160 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1162 /* request is relatively large, chunk it up */
1166 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1167 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1168 nb_rx = (uint16_t)(nb_rx + ret);
1169 nb_pkts = (uint16_t)(nb_pkts - ret);
1179 /* Stub to avoid extra ifdefs */
1181 ixgbe_recv_pkts_bulk_alloc(__rte_unused void *rx_queue,
1182 __rte_unused struct rte_mbuf **rx_pkts, __rte_unused uint16_t nb_pkts)
1188 ixgbe_rx_alloc_bufs(__rte_unused struct ixgbe_rx_queue *rxq,
1189 __rte_unused bool reset_mbuf)
1193 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1196 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1199 struct ixgbe_rx_queue *rxq;
1200 volatile union ixgbe_adv_rx_desc *rx_ring;
1201 volatile union ixgbe_adv_rx_desc *rxdp;
1202 struct ixgbe_rx_entry *sw_ring;
1203 struct ixgbe_rx_entry *rxe;
1204 struct rte_mbuf *rxm;
1205 struct rte_mbuf *nmb;
1206 union ixgbe_adv_rx_desc rxd;
1209 uint32_t hlen_type_rss;
1219 rx_id = rxq->rx_tail;
1220 rx_ring = rxq->rx_ring;
1221 sw_ring = rxq->sw_ring;
1222 while (nb_rx < nb_pkts) {
1224 * The order of operations here is important as the DD status
1225 * bit must not be read after any other descriptor fields.
1226 * rx_ring and rxdp are pointing to volatile data so the order
1227 * of accesses cannot be reordered by the compiler. If they were
1228 * not volatile, they could be reordered which could lead to
1229 * using invalid descriptor fields when read from rxd.
1231 rxdp = &rx_ring[rx_id];
1232 staterr = rxdp->wb.upper.status_error;
1233 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1240 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1241 * is likely to be invalid and to be dropped by the various
1242 * validation checks performed by the network stack.
1244 * Allocate a new mbuf to replenish the RX ring descriptor.
1245 * If the allocation fails:
1246 * - arrange for that RX descriptor to be the first one
1247 * being parsed the next time the receive function is
1248 * invoked [on the same queue].
1250 * - Stop parsing the RX ring and return immediately.
1252 * This policy do not drop the packet received in the RX
1253 * descriptor for which the allocation of a new mbuf failed.
1254 * Thus, it allows that packet to be later retrieved if
1255 * mbuf have been freed in the mean time.
1256 * As a side effect, holding RX descriptors instead of
1257 * systematically giving them back to the NIC may lead to
1258 * RX ring exhaustion situations.
1259 * However, the NIC can gracefully prevent such situations
1260 * to happen by sending specific "back-pressure" flow control
1261 * frames to its peer(s).
1263 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1264 "ext_err_stat=0x%08x pkt_len=%u",
1265 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1266 (unsigned) rx_id, (unsigned) staterr,
1267 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1269 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1271 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1272 "queue_id=%u", (unsigned) rxq->port_id,
1273 (unsigned) rxq->queue_id);
1274 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1279 rxe = &sw_ring[rx_id];
1281 if (rx_id == rxq->nb_rx_desc)
1284 /* Prefetch next mbuf while processing current one. */
1285 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1288 * When next RX descriptor is on a cache-line boundary,
1289 * prefetch the next 4 RX descriptors and the next 8 pointers
1292 if ((rx_id & 0x3) == 0) {
1293 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1294 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1300 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1301 rxdp->read.hdr_addr = dma_addr;
1302 rxdp->read.pkt_addr = dma_addr;
1305 * Initialize the returned mbuf.
1306 * 1) setup generic mbuf fields:
1307 * - number of segments,
1310 * - RX port identifier.
1311 * 2) integrate hardware offload data, if any:
1312 * - RSS flag & hash,
1313 * - IP checksum flag,
1314 * - VLAN TCI, if any,
1317 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1319 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1320 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1323 rxm->pkt_len = pkt_len;
1324 rxm->data_len = pkt_len;
1325 rxm->port = rxq->port_id;
1327 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1328 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1329 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1331 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1332 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1333 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1334 rxm->ol_flags = pkt_flags;
1336 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1337 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1338 else if (pkt_flags & PKT_RX_FDIR) {
1339 rxm->hash.fdir.hash =
1340 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1341 & IXGBE_ATR_HASH_MASK);
1342 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1345 * Store the mbuf address into the next entry of the array
1346 * of returned packets.
1348 rx_pkts[nb_rx++] = rxm;
1350 rxq->rx_tail = rx_id;
1353 * If the number of free RX descriptors is greater than the RX free
1354 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1356 * Update the RDT with the value of the last processed RX descriptor
1357 * minus 1, to guarantee that the RDT register is never equal to the
1358 * RDH register, which creates a "full" ring situtation from the
1359 * hardware point of view...
1361 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1362 if (nb_hold > rxq->rx_free_thresh) {
1363 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1364 "nb_hold=%u nb_rx=%u",
1365 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1366 (unsigned) rx_id, (unsigned) nb_hold,
1368 rx_id = (uint16_t) ((rx_id == 0) ?
1369 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1370 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1373 rxq->nb_rx_hold = nb_hold;
1378 * Detect an RSC descriptor.
1380 static inline uint32_t
1381 ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
1383 return (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &
1384 IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
1388 * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
1390 * Fill the following info in the HEAD buffer of the Rx cluster:
1391 * - RX port identifier
1392 * - hardware offload data, if any:
1394 * - IP checksum flag
1395 * - VLAN TCI, if any
1397 * @head HEAD of the packet cluster
1398 * @desc HW descriptor to get data from
1399 * @port_id Port ID of the Rx queue
1402 ixgbe_fill_cluster_head_buf(
1403 struct rte_mbuf *head,
1404 union ixgbe_adv_rx_desc *desc,
1408 uint32_t hlen_type_rss;
1411 head->port = port_id;
1414 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1415 * set in the pkt_flags field.
1417 head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1418 hlen_type_rss = rte_le_to_cpu_32(desc->wb.lower.lo_dword.data);
1419 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1420 pkt_flags |= rx_desc_status_to_pkt_flags(staterr);
1421 pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1422 head->ol_flags = pkt_flags;
1424 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1425 head->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);
1426 else if (pkt_flags & PKT_RX_FDIR) {
1427 head->hash.fdir.hash =
1428 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)
1429 & IXGBE_ATR_HASH_MASK;
1430 head->hash.fdir.id =
1431 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);
1436 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1439 struct ixgbe_rx_queue *rxq;
1440 volatile union ixgbe_adv_rx_desc *rx_ring;
1441 volatile union ixgbe_adv_rx_desc *rxdp;
1442 struct ixgbe_rx_entry *sw_ring;
1443 struct ixgbe_rx_entry *rxe;
1444 struct rte_mbuf *first_seg;
1445 struct rte_mbuf *last_seg;
1446 struct rte_mbuf *rxm;
1447 struct rte_mbuf *nmb;
1448 union ixgbe_adv_rx_desc rxd;
1449 uint64_t dma; /* Physical address of mbuf data buffer */
1459 rx_id = rxq->rx_tail;
1460 rx_ring = rxq->rx_ring;
1461 sw_ring = rxq->sw_ring;
1464 * Retrieve RX context of current packet, if any.
1466 first_seg = rxq->pkt_first_seg;
1467 last_seg = rxq->pkt_last_seg;
1469 while (nb_rx < nb_pkts) {
1472 * The order of operations here is important as the DD status
1473 * bit must not be read after any other descriptor fields.
1474 * rx_ring and rxdp are pointing to volatile data so the order
1475 * of accesses cannot be reordered by the compiler. If they were
1476 * not volatile, they could be reordered which could lead to
1477 * using invalid descriptor fields when read from rxd.
1479 rxdp = &rx_ring[rx_id];
1480 staterr = rxdp->wb.upper.status_error;
1481 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1488 * Allocate a new mbuf to replenish the RX ring descriptor.
1489 * If the allocation fails:
1490 * - arrange for that RX descriptor to be the first one
1491 * being parsed the next time the receive function is
1492 * invoked [on the same queue].
1494 * - Stop parsing the RX ring and return immediately.
1496 * This policy does not drop the packet received in the RX
1497 * descriptor for which the allocation of a new mbuf failed.
1498 * Thus, it allows that packet to be later retrieved if
1499 * mbuf have been freed in the mean time.
1500 * As a side effect, holding RX descriptors instead of
1501 * systematically giving them back to the NIC may lead to
1502 * RX ring exhaustion situations.
1503 * However, the NIC can gracefully prevent such situations
1504 * to happen by sending specific "back-pressure" flow control
1505 * frames to its peer(s).
1507 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1508 "staterr=0x%x data_len=%u",
1509 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1510 (unsigned) rx_id, (unsigned) staterr,
1511 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1513 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1515 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1516 "queue_id=%u", (unsigned) rxq->port_id,
1517 (unsigned) rxq->queue_id);
1518 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1523 rxe = &sw_ring[rx_id];
1525 if (rx_id == rxq->nb_rx_desc)
1528 /* Prefetch next mbuf while processing current one. */
1529 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1532 * When next RX descriptor is on a cache-line boundary,
1533 * prefetch the next 4 RX descriptors and the next 8 pointers
1536 if ((rx_id & 0x3) == 0) {
1537 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1538 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1542 * Update RX descriptor with the physical address of the new
1543 * data buffer of the new allocated mbuf.
1547 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1548 rxdp->read.hdr_addr = dma;
1549 rxdp->read.pkt_addr = dma;
1552 * Set data length & data buffer address of mbuf.
1554 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1555 rxm->data_len = data_len;
1556 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1559 * If this is the first buffer of the received packet,
1560 * set the pointer to the first mbuf of the packet and
1561 * initialize its context.
1562 * Otherwise, update the total length and the number of segments
1563 * of the current scattered packet, and update the pointer to
1564 * the last mbuf of the current packet.
1566 if (first_seg == NULL) {
1568 first_seg->pkt_len = data_len;
1569 first_seg->nb_segs = 1;
1571 first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
1573 first_seg->nb_segs++;
1574 last_seg->next = rxm;
1578 * If this is not the last buffer of the received packet,
1579 * update the pointer to the last mbuf of the current scattered
1580 * packet and continue to parse the RX ring.
1582 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1588 * This is the last buffer of the received packet.
1589 * If the CRC is not stripped by the hardware:
1590 * - Subtract the CRC length from the total packet length.
1591 * - If the last buffer only contains the whole CRC or a part
1592 * of it, free the mbuf associated to the last buffer.
1593 * If part of the CRC is also contained in the previous
1594 * mbuf, subtract the length of that CRC part from the
1595 * data length of the previous mbuf.
1598 if (unlikely(rxq->crc_len > 0)) {
1599 first_seg->pkt_len -= ETHER_CRC_LEN;
1600 if (data_len <= ETHER_CRC_LEN) {
1601 rte_pktmbuf_free_seg(rxm);
1602 first_seg->nb_segs--;
1603 last_seg->data_len = (uint16_t)
1604 (last_seg->data_len -
1605 (ETHER_CRC_LEN - data_len));
1606 last_seg->next = NULL;
1609 (uint16_t) (data_len - ETHER_CRC_LEN);
1612 /* Initialize the first mbuf of the returned packet */
1613 ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq->port_id,
1616 /* Prefetch data of first segment, if configured to do so. */
1617 rte_packet_prefetch((char *)first_seg->buf_addr +
1618 first_seg->data_off);
1621 * Store the mbuf address into the next entry of the array
1622 * of returned packets.
1624 rx_pkts[nb_rx++] = first_seg;
1627 * Setup receipt context for a new packet.
1633 * Record index of the next RX descriptor to probe.
1635 rxq->rx_tail = rx_id;
1638 * Save receive context.
1640 rxq->pkt_first_seg = first_seg;
1641 rxq->pkt_last_seg = last_seg;
1644 * If the number of free RX descriptors is greater than the RX free
1645 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1647 * Update the RDT with the value of the last processed RX descriptor
1648 * minus 1, to guarantee that the RDT register is never equal to the
1649 * RDH register, which creates a "full" ring situtation from the
1650 * hardware point of view...
1652 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1653 if (nb_hold > rxq->rx_free_thresh) {
1654 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1655 "nb_hold=%u nb_rx=%u",
1656 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1657 (unsigned) rx_id, (unsigned) nb_hold,
1659 rx_id = (uint16_t) ((rx_id == 0) ?
1660 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1661 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1664 rxq->nb_rx_hold = nb_hold;
1668 /*********************************************************************
1670 * Queue management functions
1672 **********************************************************************/
1675 * Rings setup and release.
1677 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1678 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1679 * also optimize cache line size effect. H/W supports up to cache line size 128.
1681 #define IXGBE_ALIGN 128
1684 * Maximum number of Ring Descriptors.
1686 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1687 * descriptors should meet the following condition:
1688 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1690 #define IXGBE_MIN_RING_DESC 32
1691 #define IXGBE_MAX_RING_DESC 4096
1694 * Create memzone for HW rings. malloc can't be used as the physical address is
1695 * needed. If the memzone is already created, then this function returns a ptr
1698 static const struct rte_memzone *
1699 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1700 uint16_t queue_id, uint32_t ring_size, int socket_id)
1702 char z_name[RTE_MEMZONE_NAMESIZE];
1703 const struct rte_memzone *mz;
1705 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1706 dev->driver->pci_drv.name, ring_name,
1707 dev->data->port_id, queue_id);
1709 mz = rte_memzone_lookup(z_name);
1713 #ifdef RTE_LIBRTE_XEN_DOM0
1714 return rte_memzone_reserve_bounded(z_name, ring_size,
1715 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1717 return rte_memzone_reserve_aligned(z_name, ring_size,
1718 socket_id, 0, IXGBE_ALIGN);
1723 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
1727 if (txq->sw_ring != NULL) {
1728 for (i = 0; i < txq->nb_tx_desc; i++) {
1729 if (txq->sw_ring[i].mbuf != NULL) {
1730 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1731 txq->sw_ring[i].mbuf = NULL;
1738 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
1741 txq->sw_ring != NULL)
1742 rte_free(txq->sw_ring);
1746 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
1748 if (txq != NULL && txq->ops != NULL) {
1749 txq->ops->release_mbufs(txq);
1750 txq->ops->free_swring(txq);
1756 ixgbe_dev_tx_queue_release(void *txq)
1758 ixgbe_tx_queue_release(txq);
1761 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
1763 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
1765 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1767 struct ixgbe_tx_entry *txe = txq->sw_ring;
1770 /* Zero out HW ring memory */
1771 for (i = 0; i < txq->nb_tx_desc; i++) {
1772 txq->tx_ring[i] = zeroed_desc;
1775 /* Initialize SW ring entries */
1776 prev = (uint16_t) (txq->nb_tx_desc - 1);
1777 for (i = 0; i < txq->nb_tx_desc; i++) {
1778 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1779 txd->wb.status = IXGBE_TXD_STAT_DD;
1782 txe[prev].next_id = i;
1786 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1787 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1790 txq->nb_tx_used = 0;
1792 * Always allow 1 descriptor to be un-allocated to avoid
1793 * a H/W race condition
1795 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1796 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1798 memset((void*)&txq->ctx_cache, 0,
1799 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1802 static const struct ixgbe_txq_ops def_txq_ops = {
1803 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1804 .free_swring = ixgbe_tx_free_swring,
1805 .reset = ixgbe_reset_tx_queue,
1808 /* Takes an ethdev and a queue and sets up the tx function to be used based on
1809 * the queue parameters. Used in tx_queue_setup by primary process and then
1810 * in dev_init by secondary process when attaching to an existing ethdev.
1813 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
1815 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1816 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS)
1817 && (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1818 PMD_INIT_LOG(INFO, "Using simple tx code path");
1819 #ifdef RTE_IXGBE_INC_VECTOR
1820 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1821 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
1822 ixgbe_txq_vec_setup(txq) == 0)) {
1823 PMD_INIT_LOG(INFO, "Vector tx enabled.");
1824 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1827 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1829 PMD_INIT_LOG(INFO, "Using full-featured tx code path");
1831 " - txq_flags = %lx " "[IXGBE_SIMPLE_FLAGS=%lx]",
1832 (unsigned long)txq->txq_flags,
1833 (unsigned long)IXGBE_SIMPLE_FLAGS);
1835 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
1836 (unsigned long)txq->tx_rs_thresh,
1837 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
1838 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1843 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1846 unsigned int socket_id,
1847 const struct rte_eth_txconf *tx_conf)
1849 const struct rte_memzone *tz;
1850 struct ixgbe_tx_queue *txq;
1851 struct ixgbe_hw *hw;
1852 uint16_t tx_rs_thresh, tx_free_thresh;
1854 PMD_INIT_FUNC_TRACE();
1855 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858 * Validate number of transmit descriptors.
1859 * It must not exceed hardware maximum, and must be multiple
1862 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1863 (nb_desc > IXGBE_MAX_RING_DESC) ||
1864 (nb_desc < IXGBE_MIN_RING_DESC)) {
1869 * The following two parameters control the setting of the RS bit on
1870 * transmit descriptors.
1871 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1872 * descriptors have been used.
1873 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1874 * descriptors are used or if the number of descriptors required
1875 * to transmit a packet is greater than the number of free TX
1877 * The following constraints must be satisfied:
1878 * tx_rs_thresh must be greater than 0.
1879 * tx_rs_thresh must be less than the size of the ring minus 2.
1880 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1881 * tx_rs_thresh must be a divisor of the ring size.
1882 * tx_free_thresh must be greater than 0.
1883 * tx_free_thresh must be less than the size of the ring minus 3.
1884 * One descriptor in the TX ring is used as a sentinel to avoid a
1885 * H/W race condition, hence the maximum threshold constraints.
1886 * When set to zero use default values.
1888 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1889 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1890 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1891 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1892 if (tx_rs_thresh >= (nb_desc - 2)) {
1893 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
1894 "of TX descriptors minus 2. (tx_rs_thresh=%u "
1895 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1896 (int)dev->data->port_id, (int)queue_idx);
1899 if (tx_free_thresh >= (nb_desc - 3)) {
1900 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1901 "tx_free_thresh must be less than the number of "
1902 "TX descriptors minus 3. (tx_free_thresh=%u "
1903 "port=%d queue=%d)",
1904 (unsigned int)tx_free_thresh,
1905 (int)dev->data->port_id, (int)queue_idx);
1908 if (tx_rs_thresh > tx_free_thresh) {
1909 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
1910 "tx_free_thresh. (tx_free_thresh=%u "
1911 "tx_rs_thresh=%u port=%d queue=%d)",
1912 (unsigned int)tx_free_thresh,
1913 (unsigned int)tx_rs_thresh,
1914 (int)dev->data->port_id,
1918 if ((nb_desc % tx_rs_thresh) != 0) {
1919 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1920 "number of TX descriptors. (tx_rs_thresh=%u "
1921 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1922 (int)dev->data->port_id, (int)queue_idx);
1927 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1928 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1929 * by the NIC and all descriptors are written back after the NIC
1930 * accumulates WTHRESH descriptors.
1932 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1933 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1934 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1935 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1936 (int)dev->data->port_id, (int)queue_idx);
1940 /* Free memory prior to re-allocation if needed... */
1941 if (dev->data->tx_queues[queue_idx] != NULL) {
1942 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1943 dev->data->tx_queues[queue_idx] = NULL;
1946 /* First allocate the tx queue data structure */
1947 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
1948 RTE_CACHE_LINE_SIZE, socket_id);
1953 * Allocate TX ring hardware descriptors. A memzone large enough to
1954 * handle the maximum ring size is allocated in order to allow for
1955 * resizing in later calls to the queue setup function.
1957 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1958 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1961 ixgbe_tx_queue_release(txq);
1965 txq->nb_tx_desc = nb_desc;
1966 txq->tx_rs_thresh = tx_rs_thresh;
1967 txq->tx_free_thresh = tx_free_thresh;
1968 txq->pthresh = tx_conf->tx_thresh.pthresh;
1969 txq->hthresh = tx_conf->tx_thresh.hthresh;
1970 txq->wthresh = tx_conf->tx_thresh.wthresh;
1971 txq->queue_id = queue_idx;
1972 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1973 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1974 txq->port_id = dev->data->port_id;
1975 txq->txq_flags = tx_conf->txq_flags;
1976 txq->ops = &def_txq_ops;
1977 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1980 * Modification to set VFTDT for virtual function if vf is detected
1982 if (hw->mac.type == ixgbe_mac_82599_vf ||
1983 hw->mac.type == ixgbe_mac_X540_vf ||
1984 hw->mac.type == ixgbe_mac_X550_vf ||
1985 hw->mac.type == ixgbe_mac_X550EM_x_vf)
1986 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1988 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1989 #ifndef RTE_LIBRTE_XEN_DOM0
1990 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1992 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1994 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1996 /* Allocate software ring */
1997 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1998 sizeof(struct ixgbe_tx_entry) * nb_desc,
1999 RTE_CACHE_LINE_SIZE, socket_id);
2000 if (txq->sw_ring == NULL) {
2001 ixgbe_tx_queue_release(txq);
2004 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2005 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
2007 /* set up vector or scalar TX function as appropriate */
2008 ixgbe_set_tx_function(dev, txq);
2010 txq->ops->reset(txq);
2012 dev->data->tx_queues[queue_idx] = txq;
2019 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
2023 if (rxq->sw_ring != NULL) {
2024 for (i = 0; i < rxq->nb_rx_desc; i++) {
2025 if (rxq->sw_ring[i].mbuf != NULL) {
2026 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2027 rxq->sw_ring[i].mbuf = NULL;
2030 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2031 if (rxq->rx_nb_avail) {
2032 for (i = 0; i < rxq->rx_nb_avail; ++i) {
2033 struct rte_mbuf *mb;
2034 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2035 rte_pktmbuf_free_seg(mb);
2037 rxq->rx_nb_avail = 0;
2044 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2047 ixgbe_rx_queue_release_mbufs(rxq);
2048 rte_free(rxq->sw_ring);
2054 ixgbe_dev_rx_queue_release(void *rxq)
2056 ixgbe_rx_queue_release(rxq);
2060 * Check if Rx Burst Bulk Alloc function can be used.
2062 * 0: the preconditions are satisfied and the bulk allocation function
2064 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2065 * function must be used.
2068 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2069 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2071 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct ixgbe_rx_queue *rxq)
2077 * Make sure the following pre-conditions are satisfied:
2078 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2079 * rxq->rx_free_thresh < rxq->nb_rx_desc
2080 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2081 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2082 * Scattered packets are not supported. This should be checked
2083 * outside of this function.
2085 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2086 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2087 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2088 "rxq->rx_free_thresh=%d, "
2089 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2090 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2092 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2093 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2094 "rxq->rx_free_thresh=%d, "
2095 "rxq->nb_rx_desc=%d",
2096 rxq->rx_free_thresh, rxq->nb_rx_desc);
2098 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2099 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2100 "rxq->nb_rx_desc=%d, "
2101 "rxq->rx_free_thresh=%d",
2102 rxq->nb_rx_desc, rxq->rx_free_thresh);
2104 } else if (!(rxq->nb_rx_desc <
2105 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2106 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2107 "rxq->nb_rx_desc=%d, "
2108 "IXGBE_MAX_RING_DESC=%d, "
2109 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2110 rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2111 RTE_PMD_IXGBE_RX_MAX_BURST);
2121 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2123 ixgbe_reset_rx_queue(struct ixgbe_hw *hw, struct ixgbe_rx_queue *rxq)
2125 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
2128 uint16_t len = rxq->nb_rx_desc;
2131 * By default, the Rx queue setup function allocates enough memory for
2132 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2133 * extra memory at the end of the descriptor ring to be zero'd out. A
2134 * pre-condition for using the Rx burst bulk alloc function is that the
2135 * number of descriptors is less than or equal to
2136 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2137 * constraints here to see if we need to zero out memory after the end
2138 * of the H/W descriptor ring.
2140 if (hw->rx_bulk_alloc_allowed)
2141 /* zero out extra memory */
2142 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2145 * Zero out HW ring memory. Zero out extra memory at the end of
2146 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2147 * reads extra memory as zeros.
2149 for (i = 0; i < len; i++) {
2150 rxq->rx_ring[i] = zeroed_desc;
2153 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2155 * initialize extra software ring entries. Space for these extra
2156 * entries is always allocated
2158 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2159 for (i = rxq->nb_rx_desc; i < len; ++i) {
2160 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2163 rxq->rx_nb_avail = 0;
2164 rxq->rx_next_avail = 0;
2165 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2166 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2168 rxq->nb_rx_hold = 0;
2169 rxq->pkt_first_seg = NULL;
2170 rxq->pkt_last_seg = NULL;
2174 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2177 unsigned int socket_id,
2178 const struct rte_eth_rxconf *rx_conf,
2179 struct rte_mempool *mp)
2181 const struct rte_memzone *rz;
2182 struct ixgbe_rx_queue *rxq;
2183 struct ixgbe_hw *hw;
2186 PMD_INIT_FUNC_TRACE();
2187 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2190 * Validate number of receive descriptors.
2191 * It must not exceed hardware maximum, and must be multiple
2194 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2195 (nb_desc > IXGBE_MAX_RING_DESC) ||
2196 (nb_desc < IXGBE_MIN_RING_DESC)) {
2200 /* Free memory prior to re-allocation if needed... */
2201 if (dev->data->rx_queues[queue_idx] != NULL) {
2202 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2203 dev->data->rx_queues[queue_idx] = NULL;
2206 /* First allocate the rx queue data structure */
2207 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2208 RTE_CACHE_LINE_SIZE, socket_id);
2212 rxq->nb_rx_desc = nb_desc;
2213 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2214 rxq->queue_id = queue_idx;
2215 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2216 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2217 rxq->port_id = dev->data->port_id;
2218 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2220 rxq->drop_en = rx_conf->rx_drop_en;
2221 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2224 * Allocate RX ring hardware descriptors. A memzone large enough to
2225 * handle the maximum ring size is allocated in order to allow for
2226 * resizing in later calls to the queue setup function.
2228 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2229 RX_RING_SZ, socket_id);
2231 ixgbe_rx_queue_release(rxq);
2236 * Zero init all the descriptors in the ring.
2238 memset (rz->addr, 0, RX_RING_SZ);
2241 * Modified to setup VFRDT for Virtual Function
2243 if (hw->mac.type == ixgbe_mac_82599_vf ||
2244 hw->mac.type == ixgbe_mac_X540_vf ||
2245 hw->mac.type == ixgbe_mac_X550_vf ||
2246 hw->mac.type == ixgbe_mac_X550EM_x_vf) {
2248 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2250 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2254 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2256 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2258 #ifndef RTE_LIBRTE_XEN_DOM0
2259 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2261 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2263 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2266 * Certain constraints must be met in order to use the bulk buffer
2267 * allocation Rx burst function. If any of Rx queues doesn't meet them
2268 * the feature should be disabled for the whole port.
2270 if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
2271 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
2272 "preconditions - canceling the feature for "
2273 "the whole port[%d]",
2274 rxq->queue_id, rxq->port_id);
2275 hw->rx_bulk_alloc_allowed = false;
2279 * Allocate software ring. Allow for space at the end of the
2280 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2281 * function does not access an invalid memory region.
2284 if (hw->rx_bulk_alloc_allowed)
2285 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2287 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2288 sizeof(struct ixgbe_rx_entry) * len,
2289 RTE_CACHE_LINE_SIZE, socket_id);
2290 if (rxq->sw_ring == NULL) {
2291 ixgbe_rx_queue_release(rxq);
2294 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2295 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2297 if (!rte_is_power_of_2(nb_desc)) {
2298 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
2299 "preconditions - canceling the feature for "
2300 "the whole port[%d]",
2301 rxq->queue_id, rxq->port_id);
2302 hw->rx_vec_allowed = false;
2304 ixgbe_rxq_vec_setup(rxq);
2306 dev->data->rx_queues[queue_idx] = rxq;
2308 ixgbe_reset_rx_queue(hw, rxq);
2314 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2316 #define IXGBE_RXQ_SCAN_INTERVAL 4
2317 volatile union ixgbe_adv_rx_desc *rxdp;
2318 struct ixgbe_rx_queue *rxq;
2321 if (rx_queue_id >= dev->data->nb_rx_queues) {
2322 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2326 rxq = dev->data->rx_queues[rx_queue_id];
2327 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2329 while ((desc < rxq->nb_rx_desc) &&
2330 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2331 desc += IXGBE_RXQ_SCAN_INTERVAL;
2332 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2333 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2334 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2335 desc - rxq->nb_rx_desc]);
2342 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2344 volatile union ixgbe_adv_rx_desc *rxdp;
2345 struct ixgbe_rx_queue *rxq = rx_queue;
2348 if (unlikely(offset >= rxq->nb_rx_desc))
2350 desc = rxq->rx_tail + offset;
2351 if (desc >= rxq->nb_rx_desc)
2352 desc -= rxq->nb_rx_desc;
2354 rxdp = &rxq->rx_ring[desc];
2355 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2359 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2362 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2364 PMD_INIT_FUNC_TRACE();
2366 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2367 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
2369 txq->ops->release_mbufs(txq);
2370 txq->ops->reset(txq);
2374 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2375 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
2377 ixgbe_rx_queue_release_mbufs(rxq);
2378 ixgbe_reset_rx_queue(hw, rxq);
2383 /*********************************************************************
2385 * Device RX/TX init functions
2387 **********************************************************************/
2390 * Receive Side Scaling (RSS)
2391 * See section 7.1.2.8 in the following document:
2392 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2395 * The source and destination IP addresses of the IP header and the source
2396 * and destination ports of TCP/UDP headers, if any, of received packets are
2397 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2398 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2399 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2400 * RSS output index which is used as the RX queue index where to store the
2402 * The following output is supplied in the RX write-back descriptor:
2403 * - 32-bit result of the Microsoft RSS hash function,
2404 * - 4-bit RSS type field.
2408 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2409 * Used as the default key.
2411 static uint8_t rss_intel_key[40] = {
2412 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2413 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2414 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2415 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2416 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2420 ixgbe_rss_disable(struct rte_eth_dev *dev)
2422 struct ixgbe_hw *hw;
2425 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2426 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2427 mrqc &= ~IXGBE_MRQC_RSSEN;
2428 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2432 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2440 hash_key = rss_conf->rss_key;
2441 if (hash_key != NULL) {
2442 /* Fill in RSS hash key */
2443 for (i = 0; i < 10; i++) {
2444 rss_key = hash_key[(i * 4)];
2445 rss_key |= hash_key[(i * 4) + 1] << 8;
2446 rss_key |= hash_key[(i * 4) + 2] << 16;
2447 rss_key |= hash_key[(i * 4) + 3] << 24;
2448 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2452 /* Set configured hashing protocols in MRQC register */
2453 rss_hf = rss_conf->rss_hf;
2454 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2455 if (rss_hf & ETH_RSS_IPV4)
2456 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2457 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2458 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2459 if (rss_hf & ETH_RSS_IPV6)
2460 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2461 if (rss_hf & ETH_RSS_IPV6_EX)
2462 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2463 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2464 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2465 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2466 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2467 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2468 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2469 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2470 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2471 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2472 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2473 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2477 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2478 struct rte_eth_rss_conf *rss_conf)
2480 struct ixgbe_hw *hw;
2484 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2487 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2488 * "RSS enabling cannot be done dynamically while it must be
2489 * preceded by a software reset"
2490 * Before changing anything, first check that the update RSS operation
2491 * does not attempt to disable RSS, if RSS was enabled at
2492 * initialization time, or does not attempt to enable RSS, if RSS was
2493 * disabled at initialization time.
2495 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2496 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2497 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2498 if (rss_hf != 0) /* Enable RSS */
2500 return 0; /* Nothing to do */
2503 if (rss_hf == 0) /* Disable RSS */
2505 ixgbe_hw_rss_hash_set(hw, rss_conf);
2510 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2511 struct rte_eth_rss_conf *rss_conf)
2513 struct ixgbe_hw *hw;
2520 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2521 hash_key = rss_conf->rss_key;
2522 if (hash_key != NULL) {
2523 /* Return RSS hash key */
2524 for (i = 0; i < 10; i++) {
2525 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2526 hash_key[(i * 4)] = rss_key & 0x000000FF;
2527 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2528 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2529 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2533 /* Get RSS functions configured in MRQC register */
2534 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2535 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2536 rss_conf->rss_hf = 0;
2540 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2541 rss_hf |= ETH_RSS_IPV4;
2542 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2543 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2544 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2545 rss_hf |= ETH_RSS_IPV6;
2546 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2547 rss_hf |= ETH_RSS_IPV6_EX;
2548 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2549 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2550 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2551 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2552 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2553 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2554 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2555 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2556 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2557 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2558 rss_conf->rss_hf = rss_hf;
2563 ixgbe_rss_configure(struct rte_eth_dev *dev)
2565 struct rte_eth_rss_conf rss_conf;
2566 struct ixgbe_hw *hw;
2571 PMD_INIT_FUNC_TRACE();
2572 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2575 * Fill in redirection table
2576 * The byte-swap is needed because NIC registers are in
2577 * little-endian order.
2580 for (i = 0, j = 0; i < 128; i++, j++) {
2581 if (j == dev->data->nb_rx_queues)
2583 reta = (reta << 8) | j;
2585 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2590 * Configure the RSS key and the RSS protocols used to compute
2591 * the RSS hash of input packets.
2593 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2594 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2595 ixgbe_rss_disable(dev);
2598 if (rss_conf.rss_key == NULL)
2599 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2600 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2603 #define NUM_VFTA_REGISTERS 128
2604 #define NIC_RX_BUFFER_SIZE 0x200
2607 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2609 struct rte_eth_vmdq_dcb_conf *cfg;
2610 struct ixgbe_hw *hw;
2611 enum rte_eth_nb_pools num_pools;
2612 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2614 uint8_t nb_tcs; /* number of traffic classes */
2617 PMD_INIT_FUNC_TRACE();
2618 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2619 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2620 num_pools = cfg->nb_queue_pools;
2621 /* Check we have a valid number of pools */
2622 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2623 ixgbe_rss_disable(dev);
2626 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2627 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2631 * split rx buffer up into sections, each for 1 traffic class
2633 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2634 for (i = 0 ; i < nb_tcs; i++) {
2635 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2636 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2637 /* clear 10 bits. */
2638 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2639 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2641 /* zero alloc all unused TCs */
2642 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2643 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2644 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2645 /* clear 10 bits. */
2646 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2649 /* MRQC: enable vmdq and dcb */
2650 mrqc = ((num_pools == ETH_16_POOLS) ? \
2651 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2652 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2654 /* PFVTCTL: turn on virtualisation and set the default pool */
2655 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2656 if (cfg->enable_default_pool) {
2657 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2659 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2662 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2664 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2666 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2668 * mapping is done with 3 bits per priority,
2669 * so shift by i*3 each time
2671 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2673 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2675 /* RTRPCS: DCB related */
2676 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2678 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2679 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2680 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2681 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2683 /* VFTA - enable all vlan filters */
2684 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2685 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2688 /* VFRE: pool enabling for receive - 16 or 32 */
2689 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2690 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2693 * MPSAR - allow pools to read specific mac addresses
2694 * In this case, all pools should be able to read from mac addr 0
2696 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2697 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2699 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2700 for (i = 0; i < cfg->nb_pool_maps; i++) {
2701 /* set vlan id in VF register and set the valid bit */
2702 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2703 (cfg->pool_map[i].vlan_id & 0xFFF)));
2705 * Put the allowed pools in VFB reg. As we only have 16 or 32
2706 * pools, we only need to use the first half of the register
2709 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2714 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2715 * @hw: pointer to hardware structure
2716 * @dcb_config: pointer to ixgbe_dcb_config structure
2719 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2720 struct ixgbe_dcb_config *dcb_config)
2725 PMD_INIT_FUNC_TRACE();
2726 if (hw->mac.type != ixgbe_mac_82598EB) {
2727 /* Disable the Tx desc arbiter so that MTQC can be changed */
2728 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2729 reg |= IXGBE_RTTDCS_ARBDIS;
2730 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2732 /* Enable DCB for Tx with 8 TCs */
2733 if (dcb_config->num_tcs.pg_tcs == 8) {
2734 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2737 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2739 if (dcb_config->vt_mode)
2740 reg |= IXGBE_MTQC_VT_ENA;
2741 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2743 /* Disable drop for all queues */
2744 for (q = 0; q < 128; q++)
2745 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2746 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2748 /* Enable the Tx desc arbiter */
2749 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2750 reg &= ~IXGBE_RTTDCS_ARBDIS;
2751 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2753 /* Enable Security TX Buffer IFG for DCB */
2754 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2755 reg |= IXGBE_SECTX_DCB;
2756 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2762 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2763 * @dev: pointer to rte_eth_dev structure
2764 * @dcb_config: pointer to ixgbe_dcb_config structure
2767 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2768 struct ixgbe_dcb_config *dcb_config)
2770 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2771 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2772 struct ixgbe_hw *hw =
2773 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2775 PMD_INIT_FUNC_TRACE();
2776 if (hw->mac.type != ixgbe_mac_82598EB)
2777 /*PF VF Transmit Enable*/
2778 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2779 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2781 /*Configure general DCB TX parameters*/
2782 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2787 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2788 struct ixgbe_dcb_config *dcb_config)
2790 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2791 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2792 struct ixgbe_dcb_tc_config *tc;
2795 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2796 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2797 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2798 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2801 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2802 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2804 /* User Priority to Traffic Class mapping */
2805 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2806 j = vmdq_rx_conf->dcb_queue[i];
2807 tc = &dcb_config->tc_config[j];
2808 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2814 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2815 struct ixgbe_dcb_config *dcb_config)
2817 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2818 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2819 struct ixgbe_dcb_tc_config *tc;
2822 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2823 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2824 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2825 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2828 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2829 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2832 /* User Priority to Traffic Class mapping */
2833 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2834 j = vmdq_tx_conf->dcb_queue[i];
2835 tc = &dcb_config->tc_config[j];
2836 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2843 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2844 struct ixgbe_dcb_config *dcb_config)
2846 struct rte_eth_dcb_rx_conf *rx_conf =
2847 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2848 struct ixgbe_dcb_tc_config *tc;
2851 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2852 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2854 /* User Priority to Traffic Class mapping */
2855 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2856 j = rx_conf->dcb_queue[i];
2857 tc = &dcb_config->tc_config[j];
2858 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2864 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2865 struct ixgbe_dcb_config *dcb_config)
2867 struct rte_eth_dcb_tx_conf *tx_conf =
2868 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2869 struct ixgbe_dcb_tc_config *tc;
2872 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2873 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2875 /* User Priority to Traffic Class mapping */
2876 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2877 j = tx_conf->dcb_queue[i];
2878 tc = &dcb_config->tc_config[j];
2879 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2885 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2886 * @hw: pointer to hardware structure
2887 * @dcb_config: pointer to ixgbe_dcb_config structure
2890 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2891 struct ixgbe_dcb_config *dcb_config)
2897 PMD_INIT_FUNC_TRACE();
2899 * Disable the arbiter before changing parameters
2900 * (always enable recycle mode; WSP)
2902 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2903 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2905 if (hw->mac.type != ixgbe_mac_82598EB) {
2906 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2907 if (dcb_config->num_tcs.pg_tcs == 4) {
2908 if (dcb_config->vt_mode)
2909 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2910 IXGBE_MRQC_VMDQRT4TCEN;
2912 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2913 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2917 if (dcb_config->num_tcs.pg_tcs == 8) {
2918 if (dcb_config->vt_mode)
2919 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2920 IXGBE_MRQC_VMDQRT8TCEN;
2922 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2923 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2928 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2931 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2932 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2933 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2934 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2936 /* VFTA - enable all vlan filters */
2937 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2938 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2942 * Configure Rx packet plane (recycle mode; WSP) and
2945 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2946 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2952 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2953 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2955 switch (hw->mac.type) {
2956 case ixgbe_mac_82598EB:
2957 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2959 case ixgbe_mac_82599EB:
2960 case ixgbe_mac_X540:
2961 case ixgbe_mac_X550:
2962 case ixgbe_mac_X550EM_x:
2963 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2972 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2973 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2975 switch (hw->mac.type) {
2976 case ixgbe_mac_82598EB:
2977 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2978 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2980 case ixgbe_mac_82599EB:
2981 case ixgbe_mac_X540:
2982 case ixgbe_mac_X550:
2983 case ixgbe_mac_X550EM_x:
2984 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2985 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2992 #define DCB_RX_CONFIG 1
2993 #define DCB_TX_CONFIG 1
2994 #define DCB_TX_PB 1024
2996 * ixgbe_dcb_hw_configure - Enable DCB and configure
2997 * general DCB in VT mode and non-VT mode parameters
2998 * @dev: pointer to rte_eth_dev structure
2999 * @dcb_config: pointer to ixgbe_dcb_config structure
3002 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
3003 struct ixgbe_dcb_config *dcb_config)
3006 uint8_t i,pfc_en,nb_tcs;
3008 uint8_t config_dcb_rx = 0;
3009 uint8_t config_dcb_tx = 0;
3010 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3011 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3012 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3013 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3014 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3015 struct ixgbe_dcb_tc_config *tc;
3016 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3017 struct ixgbe_hw *hw =
3018 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3020 switch(dev->data->dev_conf.rxmode.mq_mode){
3021 case ETH_MQ_RX_VMDQ_DCB:
3022 dcb_config->vt_mode = true;
3023 if (hw->mac.type != ixgbe_mac_82598EB) {
3024 config_dcb_rx = DCB_RX_CONFIG;
3026 *get dcb and VT rx configuration parameters
3029 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
3030 /*Configure general VMDQ and DCB RX parameters*/
3031 ixgbe_vmdq_dcb_configure(dev);
3035 dcb_config->vt_mode = false;
3036 config_dcb_rx = DCB_RX_CONFIG;
3037 /* Get dcb TX configuration parameters from rte_eth_conf */
3038 ixgbe_dcb_rx_config(dev,dcb_config);
3039 /*Configure general DCB RX parameters*/
3040 ixgbe_dcb_rx_hw_config(hw, dcb_config);
3043 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3046 switch (dev->data->dev_conf.txmode.mq_mode) {
3047 case ETH_MQ_TX_VMDQ_DCB:
3048 dcb_config->vt_mode = true;
3049 config_dcb_tx = DCB_TX_CONFIG;
3050 /* get DCB and VT TX configuration parameters from rte_eth_conf */
3051 ixgbe_dcb_vt_tx_config(dev,dcb_config);
3052 /*Configure general VMDQ and DCB TX parameters*/
3053 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
3057 dcb_config->vt_mode = false;
3058 config_dcb_tx = DCB_TX_CONFIG;
3059 /*get DCB TX configuration parameters from rte_eth_conf*/
3060 ixgbe_dcb_tx_config(dev,dcb_config);
3061 /*Configure general DCB TX parameters*/
3062 ixgbe_dcb_tx_hw_config(hw, dcb_config);
3065 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3069 nb_tcs = dcb_config->num_tcs.pfc_tcs;
3071 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3072 if(nb_tcs == ETH_4_TCS) {
3073 /* Avoid un-configured priority mapping to TC0 */
3075 uint8_t mask = 0xFF;
3076 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3077 mask = (uint8_t)(mask & (~ (1 << map[i])));
3078 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3079 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3083 /* Re-configure 4 TCs BW */
3084 for (i = 0; i < nb_tcs; i++) {
3085 tc = &dcb_config->tc_config[i];
3086 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3087 (uint8_t)(100 / nb_tcs);
3088 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3089 (uint8_t)(100 / nb_tcs);
3091 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3092 tc = &dcb_config->tc_config[i];
3093 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3094 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3099 /* Set RX buffer size */
3100 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3101 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3102 for (i = 0 ; i < nb_tcs; i++) {
3103 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3105 /* zero alloc all unused TCs */
3106 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3107 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3111 /* Only support an equally distributed Tx packet buffer strategy. */
3112 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3113 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3114 for (i = 0; i < nb_tcs; i++) {
3115 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3116 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3118 /* Clear unused TCs, if any, to zero buffer size*/
3119 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3120 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3121 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3125 /*Calculates traffic class credits*/
3126 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3127 IXGBE_DCB_TX_CONFIG);
3128 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3129 IXGBE_DCB_RX_CONFIG);
3132 /* Unpack CEE standard containers */
3133 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3134 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3135 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3136 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3137 /* Configure PG(ETS) RX */
3138 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3142 /* Unpack CEE standard containers */
3143 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3144 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3145 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3146 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3147 /* Configure PG(ETS) TX */
3148 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3151 /*Configure queue statistics registers*/
3152 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3154 /* Check if the PFC is supported */
3155 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3156 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3157 for (i = 0; i < nb_tcs; i++) {
3159 * If the TC count is 8,and the default high_water is 48,
3160 * the low_water is 16 as default.
3162 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3163 hw->fc.low_water[i] = pbsize / 4;
3164 /* Enable pfc for this TC */
3165 tc = &dcb_config->tc_config[i];
3166 tc->pfc = ixgbe_dcb_pfc_enabled;
3168 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3169 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3171 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3178 * ixgbe_configure_dcb - Configure DCB Hardware
3179 * @dev: pointer to rte_eth_dev
3181 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3183 struct ixgbe_dcb_config *dcb_cfg =
3184 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3185 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3187 PMD_INIT_FUNC_TRACE();
3189 /* check support mq_mode for DCB */
3190 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3191 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3194 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3197 /** Configure DCB hardware **/
3198 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3204 * VMDq only support for 10 GbE NIC.
3207 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3209 struct rte_eth_vmdq_rx_conf *cfg;
3210 struct ixgbe_hw *hw;
3211 enum rte_eth_nb_pools num_pools;
3212 uint32_t mrqc, vt_ctl, vlanctrl;
3216 PMD_INIT_FUNC_TRACE();
3217 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3218 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3219 num_pools = cfg->nb_queue_pools;
3221 ixgbe_rss_disable(dev);
3223 /* MRQC: enable vmdq */
3224 mrqc = IXGBE_MRQC_VMDQEN;
3225 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3227 /* PFVTCTL: turn on virtualisation and set the default pool */
3228 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3229 if (cfg->enable_default_pool)
3230 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3232 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3234 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3236 for (i = 0; i < (int)num_pools; i++) {
3237 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
3238 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
3241 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3242 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3243 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3244 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3246 /* VFTA - enable all vlan filters */
3247 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3248 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3250 /* VFRE: pool enabling for receive - 64 */
3251 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3252 if (num_pools == ETH_64_POOLS)
3253 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3256 * MPSAR - allow pools to read specific mac addresses
3257 * In this case, all pools should be able to read from mac addr 0
3259 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3260 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3262 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3263 for (i = 0; i < cfg->nb_pool_maps; i++) {
3264 /* set vlan id in VF register and set the valid bit */
3265 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3266 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3268 * Put the allowed pools in VFB reg. As we only have 16 or 64
3269 * pools, we only need to use the first half of the register
3272 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3273 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3274 (cfg->pool_map[i].pools & UINT32_MAX));
3276 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3277 ((cfg->pool_map[i].pools >> 32) \
3282 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3283 if (cfg->enable_loop_back) {
3284 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3285 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3286 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3289 IXGBE_WRITE_FLUSH(hw);
3293 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3294 * @hw: pointer to hardware structure
3297 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3302 PMD_INIT_FUNC_TRACE();
3303 /*PF VF Transmit Enable*/
3304 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3305 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3307 /* Disable the Tx desc arbiter so that MTQC can be changed */
3308 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3309 reg |= IXGBE_RTTDCS_ARBDIS;
3310 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3312 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3313 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3315 /* Disable drop for all queues */
3316 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3317 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3318 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3320 /* Enable the Tx desc arbiter */
3321 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3322 reg &= ~IXGBE_RTTDCS_ARBDIS;
3323 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3325 IXGBE_WRITE_FLUSH(hw);
3331 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
3333 struct ixgbe_rx_entry *rxe = rxq->sw_ring;
3337 /* Initialize software ring entries */
3338 for (i = 0; i < rxq->nb_rx_desc; i++) {
3339 volatile union ixgbe_adv_rx_desc *rxd;
3340 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3342 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3343 (unsigned) rxq->queue_id);
3347 rte_mbuf_refcnt_set(mbuf, 1);
3349 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3351 mbuf->port = rxq->port_id;
3354 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3355 rxd = &rxq->rx_ring[i];
3356 rxd->read.hdr_addr = dma_addr;
3357 rxd->read.pkt_addr = dma_addr;
3365 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
3367 struct ixgbe_hw *hw;
3370 ixgbe_rss_configure(dev);
3372 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3374 /* MRQC: enable VF RSS */
3375 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
3376 mrqc &= ~IXGBE_MRQC_MRQE_MASK;
3377 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3379 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
3383 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
3387 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
3391 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3397 ixgbe_config_vf_default(struct rte_eth_dev *dev)
3399 struct ixgbe_hw *hw =
3400 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3402 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3404 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3409 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3410 IXGBE_MRQC_VMDQRT4TCEN);
3414 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3415 IXGBE_MRQC_VMDQRT8TCEN);
3419 "invalid pool number in IOV mode");
3426 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3428 struct ixgbe_hw *hw =
3429 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3431 if (hw->mac.type == ixgbe_mac_82598EB)
3434 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3436 * SRIOV inactive scheme
3437 * any DCB/RSS w/o VMDq multi-queue setting
3439 switch (dev->data->dev_conf.rxmode.mq_mode) {
3441 ixgbe_rss_configure(dev);
3444 case ETH_MQ_RX_VMDQ_DCB:
3445 ixgbe_vmdq_dcb_configure(dev);
3448 case ETH_MQ_RX_VMDQ_ONLY:
3449 ixgbe_vmdq_rx_hw_configure(dev);
3452 case ETH_MQ_RX_NONE:
3453 /* if mq_mode is none, disable rss mode.*/
3454 default: ixgbe_rss_disable(dev);
3458 * SRIOV active scheme
3459 * Support RSS together with VMDq & SRIOV
3461 switch (dev->data->dev_conf.rxmode.mq_mode) {
3463 case ETH_MQ_RX_VMDQ_RSS:
3464 ixgbe_config_vf_rss(dev);
3467 /* FIXME if support DCB/RSS together with VMDq & SRIOV */
3468 case ETH_MQ_RX_VMDQ_DCB:
3469 case ETH_MQ_RX_VMDQ_DCB_RSS:
3471 "Could not support DCB with VMDq & SRIOV");
3474 ixgbe_config_vf_default(dev);
3483 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3485 struct ixgbe_hw *hw =
3486 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3490 if (hw->mac.type == ixgbe_mac_82598EB)
3493 /* disable arbiter before setting MTQC */
3494 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3495 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3496 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3498 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3500 * SRIOV inactive scheme
3501 * any DCB w/o VMDq multi-queue setting
3503 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3504 ixgbe_vmdq_tx_hw_configure(hw);
3506 mtqc = IXGBE_MTQC_64Q_1PB;
3507 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3510 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3513 * SRIOV active scheme
3514 * FIXME if support DCB together with VMDq & SRIOV
3517 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3520 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3523 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3527 mtqc = IXGBE_MTQC_64Q_1PB;
3528 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3530 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3533 /* re-enable arbiter */
3534 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3535 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3540 void ixgbe_set_rx_function(struct rte_eth_dev *dev)
3542 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3545 * In order to allow Vector Rx there are a few configuration
3546 * conditions to be met and Rx Bulk Allocation should be allowed.
3548 if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
3549 !hw->rx_bulk_alloc_allowed) {
3550 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
3551 "preconditions or RTE_IXGBE_INC_VECTOR is "
3553 dev->data->port_id);
3555 hw->rx_vec_allowed = false;
3558 if (dev->data->scattered_rx) {
3560 * Set the non-LRO scattered callback: there are Vector and
3561 * single allocation versions.
3563 if (hw->rx_vec_allowed) {
3564 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3565 "callback (port=%d).",
3566 dev->data->port_id);
3568 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3570 PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector) "
3571 "Scattered Rx callback "
3573 dev->data->port_id);
3575 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3578 * Below we set "simple" callbacks according to port/queues parameters.
3579 * If parameters allow we are going to choose between the following
3583 * - Single buffer allocation (the simplest one)
3585 } else if (hw->rx_vec_allowed) {
3586 PMD_INIT_LOG(INFO, "Vector rx enabled, please make sure RX "
3587 "burst size no less than 32.");
3589 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
3590 } else if (hw->rx_bulk_alloc_allowed) {
3591 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3592 "satisfied. Rx Burst Bulk Alloc function "
3593 "will be used on port=%d.",
3594 dev->data->port_id);
3596 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
3598 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3599 "satisfied, or Scattered Rx is requested, "
3600 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC "
3601 "is not enabled (port=%d).",
3602 dev->data->port_id);
3604 dev->rx_pkt_burst = ixgbe_recv_pkts;
3609 * Initializes Receive Unit.
3612 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3614 struct ixgbe_hw *hw;
3615 struct ixgbe_rx_queue *rxq;
3616 struct rte_pktmbuf_pool_private *mbp_priv;
3627 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
3629 PMD_INIT_FUNC_TRACE();
3630 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3633 * Make sure receives are disabled while setting
3634 * up the RX context (registers, descriptor rings, etc.).
3636 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3637 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3639 /* Enable receipt of broadcasted frames */
3640 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3641 fctrl |= IXGBE_FCTRL_BAM;
3642 fctrl |= IXGBE_FCTRL_DPF;
3643 fctrl |= IXGBE_FCTRL_PMCF;
3644 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3647 * Configure CRC stripping, if any.
3649 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3650 if (rx_conf->hw_strip_crc)
3651 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3653 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3656 * Configure jumbo frame support, if any.
3658 if (rx_conf->jumbo_frame == 1) {
3659 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3660 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3661 maxfrs &= 0x0000FFFF;
3662 maxfrs |= (rx_conf->max_rx_pkt_len << 16);
3663 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3665 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3668 * If loopback mode is configured for 82599, set LPBK bit.
3670 if (hw->mac.type == ixgbe_mac_82599EB &&
3671 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3672 hlreg0 |= IXGBE_HLREG0_LPBK;
3674 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3676 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3678 /* Setup RX queues */
3679 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3680 rxq = dev->data->rx_queues[i];
3683 * Reset crc_len in case it was changed after queue setup by a
3684 * call to configure.
3686 rxq->crc_len = rx_conf->hw_strip_crc ? 0 : ETHER_CRC_LEN;
3688 /* Setup the Base and Length of the Rx Descriptor Rings */
3689 bus_addr = rxq->rx_ring_phys_addr;
3690 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3691 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3692 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3693 (uint32_t)(bus_addr >> 32));
3694 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3695 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3696 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3697 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3699 /* Configure the SRRCTL register */
3700 #ifdef RTE_HEADER_SPLIT_ENABLE
3702 * Configure Header Split
3704 if (rx_conf->header_split) {
3705 if (hw->mac.type == ixgbe_mac_82599EB) {
3706 /* Must setup the PSRTYPE register */
3708 psrtype = IXGBE_PSRTYPE_TCPHDR |
3709 IXGBE_PSRTYPE_UDPHDR |
3710 IXGBE_PSRTYPE_IPV4HDR |
3711 IXGBE_PSRTYPE_IPV6HDR;
3712 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3714 srrctl = ((rx_conf->split_hdr_size <<
3715 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3716 IXGBE_SRRCTL_BSIZEHDR_MASK);
3717 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3720 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3722 /* Set if packets are dropped when no descriptors available */
3724 srrctl |= IXGBE_SRRCTL_DROP_EN;
3727 * Configure the RX buffer size in the BSIZEPACKET field of
3728 * the SRRCTL register of the queue.
3729 * The value is in 1 KB resolution. Valid values can be from
3732 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3733 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3734 RTE_PKTMBUF_HEADROOM);
3735 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3736 IXGBE_SRRCTL_BSIZEPKT_MASK);
3737 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3739 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3740 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3742 /* It adds dual VLAN length for supporting dual VLAN */
3743 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
3744 2 * IXGBE_VLAN_TAG_SIZE > buf_size)
3745 dev->data->scattered_rx = 1;
3748 if (rx_conf->enable_scatter)
3749 dev->data->scattered_rx = 1;
3751 ixgbe_set_rx_function(dev);
3754 * Device configured with multiple RX queues.
3756 ixgbe_dev_mq_rx_configure(dev);
3759 * Setup the Checksum Register.
3760 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3761 * Enable IP/L4 checkum computation by hardware if requested to do so.
3763 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3764 rxcsum |= IXGBE_RXCSUM_PCSD;
3765 if (rx_conf->hw_ip_checksum)
3766 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3768 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3770 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3772 if (hw->mac.type == ixgbe_mac_82599EB ||
3773 hw->mac.type == ixgbe_mac_X540) {
3774 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3775 if (rx_conf->hw_strip_crc)
3776 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3778 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3779 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3780 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3787 * Initializes Transmit Unit.
3790 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3792 struct ixgbe_hw *hw;
3793 struct ixgbe_tx_queue *txq;
3799 PMD_INIT_FUNC_TRACE();
3800 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3802 /* Enable TX CRC (checksum offload requirement) and hw padding
3803 * (TSO requirement) */
3804 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3805 hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
3806 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3808 /* Setup the Base and Length of the Tx Descriptor Rings */
3809 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3810 txq = dev->data->tx_queues[i];
3812 bus_addr = txq->tx_ring_phys_addr;
3813 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3814 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3815 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3816 (uint32_t)(bus_addr >> 32));
3817 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3818 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3819 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3820 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3821 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3824 * Disable Tx Head Writeback RO bit, since this hoses
3825 * bookkeeping if things aren't delivered in order.
3827 switch (hw->mac.type) {
3828 case ixgbe_mac_82598EB:
3829 txctrl = IXGBE_READ_REG(hw,
3830 IXGBE_DCA_TXCTRL(txq->reg_idx));
3831 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3832 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3836 case ixgbe_mac_82599EB:
3837 case ixgbe_mac_X540:
3838 case ixgbe_mac_X550:
3839 case ixgbe_mac_X550EM_x:
3841 txctrl = IXGBE_READ_REG(hw,
3842 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3843 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3844 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3850 /* Device configured with multiple TX queues. */
3851 ixgbe_dev_mq_tx_configure(dev);
3855 * Set up link for 82599 loopback mode Tx->Rx.
3858 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3860 PMD_INIT_FUNC_TRACE();
3862 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3863 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3865 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
3874 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3875 ixgbe_reset_pipeline_82599(hw);
3877 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3883 * Start Transmit and Receive Units.
3886 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3888 struct ixgbe_hw *hw;
3889 struct ixgbe_tx_queue *txq;
3890 struct ixgbe_rx_queue *rxq;
3897 PMD_INIT_FUNC_TRACE();
3898 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3900 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3901 txq = dev->data->tx_queues[i];
3902 /* Setup Transmit Threshold Registers */
3903 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3904 txdctl |= txq->pthresh & 0x7F;
3905 txdctl |= ((txq->hthresh & 0x7F) << 8);
3906 txdctl |= ((txq->wthresh & 0x7F) << 16);
3907 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3910 if (hw->mac.type != ixgbe_mac_82598EB) {
3911 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3912 dmatxctl |= IXGBE_DMATXCTL_TE;
3913 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3916 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3917 txq = dev->data->tx_queues[i];
3918 if (!txq->tx_deferred_start) {
3919 ret = ixgbe_dev_tx_queue_start(dev, i);
3925 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3926 rxq = dev->data->rx_queues[i];
3927 if (!rxq->rx_deferred_start) {
3928 ret = ixgbe_dev_rx_queue_start(dev, i);
3934 /* Enable Receive engine */
3935 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3936 if (hw->mac.type == ixgbe_mac_82598EB)
3937 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3938 rxctrl |= IXGBE_RXCTRL_RXEN;
3939 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3941 /* If loopback mode is enabled for 82599, set up the link accordingly */
3942 if (hw->mac.type == ixgbe_mac_82599EB &&
3943 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3944 ixgbe_setup_loopback_link_82599(hw);
3950 * Start Receive Units for specified queue.
3953 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3955 struct ixgbe_hw *hw;
3956 struct ixgbe_rx_queue *rxq;
3960 PMD_INIT_FUNC_TRACE();
3961 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3963 if (rx_queue_id < dev->data->nb_rx_queues) {
3964 rxq = dev->data->rx_queues[rx_queue_id];
3966 /* Allocate buffers for descriptor rings */
3967 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
3968 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
3972 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3973 rxdctl |= IXGBE_RXDCTL_ENABLE;
3974 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3976 /* Wait until RX Enable ready */
3977 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3980 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3981 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3983 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
3986 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3987 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3995 * Stop Receive Units for specified queue.
3998 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4000 struct ixgbe_hw *hw;
4001 struct ixgbe_rx_queue *rxq;
4005 PMD_INIT_FUNC_TRACE();
4006 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4008 if (rx_queue_id < dev->data->nb_rx_queues) {
4009 rxq = dev->data->rx_queues[rx_queue_id];
4011 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4012 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
4013 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
4015 /* Wait until RX Enable ready */
4016 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4019 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4020 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
4022 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
4025 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4027 ixgbe_rx_queue_release_mbufs(rxq);
4028 ixgbe_reset_rx_queue(hw, rxq);
4037 * Start Transmit Units for specified queue.
4040 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4042 struct ixgbe_hw *hw;
4043 struct ixgbe_tx_queue *txq;
4047 PMD_INIT_FUNC_TRACE();
4048 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4050 if (tx_queue_id < dev->data->nb_tx_queues) {
4051 txq = dev->data->tx_queues[tx_queue_id];
4052 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4053 txdctl |= IXGBE_TXDCTL_ENABLE;
4054 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4056 /* Wait until TX Enable ready */
4057 if (hw->mac.type == ixgbe_mac_82599EB) {
4058 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4061 txdctl = IXGBE_READ_REG(hw,
4062 IXGBE_TXDCTL(txq->reg_idx));
4063 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4065 PMD_INIT_LOG(ERR, "Could not enable "
4066 "Tx Queue %d", tx_queue_id);
4069 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4070 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4078 * Stop Transmit Units for specified queue.
4081 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4083 struct ixgbe_hw *hw;
4084 struct ixgbe_tx_queue *txq;
4086 uint32_t txtdh, txtdt;
4089 PMD_INIT_FUNC_TRACE();
4090 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4092 if (tx_queue_id < dev->data->nb_tx_queues) {
4093 txq = dev->data->tx_queues[tx_queue_id];
4095 /* Wait until TX queue is empty */
4096 if (hw->mac.type == ixgbe_mac_82599EB) {
4097 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4099 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4100 txtdh = IXGBE_READ_REG(hw,
4101 IXGBE_TDH(txq->reg_idx));
4102 txtdt = IXGBE_READ_REG(hw,
4103 IXGBE_TDT(txq->reg_idx));
4104 } while (--poll_ms && (txtdh != txtdt));
4106 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
4107 "when stopping.", tx_queue_id);
4110 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4111 txdctl &= ~IXGBE_TXDCTL_ENABLE;
4112 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4114 /* Wait until TX Enable ready */
4115 if (hw->mac.type == ixgbe_mac_82599EB) {
4116 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4119 txdctl = IXGBE_READ_REG(hw,
4120 IXGBE_TXDCTL(txq->reg_idx));
4121 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
4123 PMD_INIT_LOG(ERR, "Could not disable "
4124 "Tx Queue %d", tx_queue_id);
4127 if (txq->ops != NULL) {
4128 txq->ops->release_mbufs(txq);
4129 txq->ops->reset(txq);
4138 * [VF] Initializes Receive Unit.
4141 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
4143 struct ixgbe_hw *hw;
4144 struct ixgbe_rx_queue *rxq;
4145 struct rte_pktmbuf_pool_private *mbp_priv;
4147 uint32_t srrctl, psrtype = 0;
4152 PMD_INIT_FUNC_TRACE();
4153 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4155 if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
4156 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4157 "it should be power of 2");
4161 if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
4162 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4163 "it should be equal to or less than %d",
4164 hw->mac.max_rx_queues);
4169 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
4170 * disables the VF receipt of packets if the PF MTU is > 1500.
4171 * This is done to deal with 82599 limitations that imposes
4172 * the PF and all VFs to share the same MTU.
4173 * Then, the PF driver enables again the VF receipt of packet when
4174 * the VF driver issues a IXGBE_VF_SET_LPE request.
4175 * In the meantime, the VF device cannot be used, even if the VF driver
4176 * and the Guest VM network stack are ready to accept packets with a
4177 * size up to the PF MTU.
4178 * As a work-around to this PF behaviour, force the call to
4179 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
4180 * VF packets received can work in all cases.
4182 ixgbevf_rlpml_set_vf(hw,
4183 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
4185 /* Setup RX queues */
4186 dev->rx_pkt_burst = ixgbe_recv_pkts;
4187 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4188 rxq = dev->data->rx_queues[i];
4190 /* Allocate buffers for descriptor rings */
4191 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
4195 /* Setup the Base and Length of the Rx Descriptor Rings */
4196 bus_addr = rxq->rx_ring_phys_addr;
4198 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
4199 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4200 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
4201 (uint32_t)(bus_addr >> 32));
4202 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
4203 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4204 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
4205 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
4208 /* Configure the SRRCTL register */
4209 #ifdef RTE_HEADER_SPLIT_ENABLE
4211 * Configure Header Split
4213 if (dev->data->dev_conf.rxmode.header_split) {
4214 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
4215 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4216 IXGBE_SRRCTL_BSIZEHDR_MASK);
4217 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4220 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4222 /* Set if packets are dropped when no descriptors available */
4224 srrctl |= IXGBE_SRRCTL_DROP_EN;
4227 * Configure the RX buffer size in the BSIZEPACKET field of
4228 * the SRRCTL register of the queue.
4229 * The value is in 1 KB resolution. Valid values can be from
4232 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
4233 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
4234 RTE_PKTMBUF_HEADROOM);
4235 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4236 IXGBE_SRRCTL_BSIZEPKT_MASK);
4239 * VF modification to write virtual function SRRCTL register
4241 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
4243 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4244 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4246 if (dev->data->dev_conf.rxmode.enable_scatter ||
4247 /* It adds dual VLAN length for supporting dual VLAN */
4248 (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4249 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
4250 if (!dev->data->scattered_rx)
4251 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4252 dev->data->scattered_rx = 1;
4253 #ifdef RTE_IXGBE_INC_VECTOR
4254 if (rte_is_power_of_2(rxq->nb_rx_desc))
4256 ixgbe_recv_scattered_pkts_vec;
4259 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
4263 #ifdef RTE_HEADER_SPLIT_ENABLE
4264 if (dev->data->dev_conf.rxmode.header_split)
4265 /* Must setup the PSRTYPE register */
4266 psrtype = IXGBE_PSRTYPE_TCPHDR |
4267 IXGBE_PSRTYPE_UDPHDR |
4268 IXGBE_PSRTYPE_IPV4HDR |
4269 IXGBE_PSRTYPE_IPV6HDR;
4272 /* Set RQPL for VF RSS according to max Rx queue */
4273 psrtype |= (dev->data->nb_rx_queues >> 1) <<
4274 IXGBE_PSRTYPE_RQPL_SHIFT;
4275 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
4281 * [VF] Initializes Transmit Unit.
4284 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4286 struct ixgbe_hw *hw;
4287 struct ixgbe_tx_queue *txq;
4292 PMD_INIT_FUNC_TRACE();
4293 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4295 /* Setup the Base and Length of the Tx Descriptor Rings */
4296 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4297 txq = dev->data->tx_queues[i];
4298 bus_addr = txq->tx_ring_phys_addr;
4299 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4300 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4301 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4302 (uint32_t)(bus_addr >> 32));
4303 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4304 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4305 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4306 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4307 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4310 * Disable Tx Head Writeback RO bit, since this hoses
4311 * bookkeeping if things aren't delivered in order.
4313 txctrl = IXGBE_READ_REG(hw,
4314 IXGBE_VFDCA_TXCTRL(i));
4315 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4316 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4322 * [VF] Start Transmit and Receive Units.
4325 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4327 struct ixgbe_hw *hw;
4328 struct ixgbe_tx_queue *txq;
4329 struct ixgbe_rx_queue *rxq;
4335 PMD_INIT_FUNC_TRACE();
4336 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4338 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4339 txq = dev->data->tx_queues[i];
4340 /* Setup Transmit Threshold Registers */
4341 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4342 txdctl |= txq->pthresh & 0x7F;
4343 txdctl |= ((txq->hthresh & 0x7F) << 8);
4344 txdctl |= ((txq->wthresh & 0x7F) << 16);
4345 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4348 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4350 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4351 txdctl |= IXGBE_TXDCTL_ENABLE;
4352 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4355 /* Wait until TX Enable ready */
4358 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4359 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4361 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
4363 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4365 rxq = dev->data->rx_queues[i];
4367 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4368 rxdctl |= IXGBE_RXDCTL_ENABLE;
4369 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4371 /* Wait until RX Enable ready */
4375 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4376 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4378 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
4380 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
4385 /* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */
4386 int __attribute__((weak))
4387 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
4392 uint16_t __attribute__((weak))
4393 ixgbe_recv_pkts_vec(
4394 void __rte_unused *rx_queue,
4395 struct rte_mbuf __rte_unused **rx_pkts,
4396 uint16_t __rte_unused nb_pkts)
4401 uint16_t __attribute__((weak))
4402 ixgbe_recv_scattered_pkts_vec(
4403 void __rte_unused *rx_queue,
4404 struct rte_mbuf __rte_unused **rx_pkts,
4405 uint16_t __rte_unused nb_pkts)
4410 int __attribute__((weak))
4411 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)