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34 #ifndef _IXGBE_RXTX_H_
35 #define _IXGBE_RXTX_H_
38 #define RTE_PMD_IXGBE_TX_MAX_BURST 32
40 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
41 #define RTE_PMD_IXGBE_RX_MAX_BURST 32
42 #define RTE_IXGBE_DESCS_PER_LOOP 4
44 #define RTE_IXGBE_DESCS_PER_LOOP 1
47 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
48 (uint64_t) ((mb)->buf_physaddr + (uint64_t)((char *)((mb)->pkt.data) - \
49 (char *)(mb)->buf_addr))
51 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
52 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
54 #ifdef RTE_IXGBE_INC_VECTOR
55 #define RTE_IXGBE_VPMD_RX_BURST 32
56 #define RTE_IXGBE_VPMD_TX_BURST 32
57 #define RTE_IXGBE_RXQ_REARM_THRESH RTE_IXGBE_VPMD_RX_BURST
58 #define RTE_IXGBE_TX_MAX_FREE_BUF_SZ 64
61 #define RX_RING_SZ ((IXGBE_MAX_RING_DESC + RTE_IXGBE_DESCS_PER_LOOP - 1) * \
62 sizeof(union ixgbe_adv_rx_desc))
64 #ifdef RTE_PMD_PACKET_PREFETCH
65 #define rte_packet_prefetch(p) rte_prefetch1(p)
67 #define rte_packet_prefetch(p) do {} while(0)
70 #define RTE_IXGBE_REGISTER_POLL_WAIT_10_MS 10
71 #define RTE_IXGBE_WAIT_100_US 100
72 #define RTE_IXGBE_VMTXSW_REGISTER_COUNT 2
75 * Structure associated with each descriptor of the RX ring of a RX queue.
78 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
82 * Structure associated with each descriptor of the TX ring of a TX queue.
85 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
86 uint16_t next_id; /**< Index of next descriptor in ring. */
87 uint16_t last_id; /**< Index of last scattered descriptor. */
91 * Structure associated with each descriptor of the TX ring of a TX queue.
93 struct igb_tx_entry_v {
94 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
98 * continuous entry sequence, gather by the same mempool
100 struct igb_tx_entry_seq {
101 const struct rte_mempool* pool;
106 * Structure associated with each RX queue.
108 struct igb_rx_queue {
109 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
110 volatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
111 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
112 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
113 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
114 struct igb_rx_entry *sw_ring; /**< address of RX software ring. */
115 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
116 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
117 uint16_t nb_rx_desc; /**< number of RX descriptors. */
118 uint16_t rx_tail; /**< current value of RDT register. */
119 uint16_t nb_rx_hold; /**< number of held free RX desc. */
120 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
121 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
122 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
123 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
125 #ifdef RTE_IXGBE_INC_VECTOR
126 uint16_t rxrearm_nb; /**< the idx we start the re-arming from */
127 uint16_t rxrearm_start; /**< number of remaining to be re-armed */
128 __m128i misc_info; /**< cache XMM combine port_id/crc/nb_segs */
130 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
131 uint16_t queue_id; /**< RX queue index. */
132 uint16_t reg_idx; /**< RX queue register index. */
133 uint8_t port_id; /**< Device port identifier. */
134 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
135 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
136 uint8_t start_rx_per_q;
137 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
138 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */
139 struct rte_mbuf fake_mbuf;
140 /** hold packets to return to application */
141 struct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2];
146 * IXGBE CTX Constants
148 enum ixgbe_advctx_num {
149 IXGBE_CTX_0 = 0, /**< CTX0 */
150 IXGBE_CTX_1 = 1, /**< CTX1 */
151 IXGBE_CTX_NUM = 2, /**< CTX NUMBER */
155 * Structure to check if new context need be built
158 struct ixgbe_advctx_info {
159 uint16_t flags; /**< ol_flags for context build. */
160 uint32_t cmp_mask; /**< compare mask for vlan_macip_lens */
161 union rte_vlan_macip vlan_macip_lens; /**< vlan, mac ip length. */
165 * Structure associated with each TX queue.
167 struct igb_tx_queue {
168 /** TX ring virtual address. */
169 volatile union ixgbe_adv_tx_desc *tx_ring;
170 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
171 struct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */
172 #ifdef RTE_IXGBE_INC_VECTOR
173 /** continuous tx entry sequence within the same mempool */
174 struct igb_tx_entry_seq *sw_ring_seq;
176 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
177 uint16_t nb_tx_desc; /**< number of TX descriptors. */
178 uint16_t tx_tail; /**< current value of TDT reg. */
179 uint16_t tx_free_thresh;/**< minimum TX before freeing. */
180 /** Number of TX descriptors to use before RS bit is set. */
181 uint16_t tx_rs_thresh;
182 /** Number of TX descriptors used since RS bit was set. */
184 /** Index to last TX descriptor to have been cleaned. */
185 uint16_t last_desc_cleaned;
186 /** Total number of TX descriptors ready to be allocated. */
188 uint16_t tx_next_dd; /**< next desc to scan for DD bit */
189 uint16_t tx_next_rs; /**< next desc to set RS bit */
190 uint16_t queue_id; /**< TX queue index. */
191 uint16_t reg_idx; /**< TX queue register index. */
192 uint8_t port_id; /**< Device port identifier. */
193 uint8_t pthresh; /**< Prefetch threshold register. */
194 uint8_t hthresh; /**< Host threshold register. */
195 uint8_t wthresh; /**< Write-back threshold reg. */
196 uint32_t txq_flags; /**< Holds flags for this TXq */
197 uint32_t ctx_curr; /**< Hardware context states. */
198 /** Hardware context0 history. */
199 struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM];
200 struct ixgbe_txq_ops *ops; /**< txq ops */
201 uint8_t start_tx_per_q;
204 struct ixgbe_txq_ops {
205 void (*release_mbufs)(struct igb_tx_queue *txq);
206 void (*free_swring)(struct igb_tx_queue *txq);
207 void (*reset)(struct igb_tx_queue *txq);
211 * The "simple" TX queue functions require that the following
212 * flags are set when the TX queue is configured:
213 * - ETH_TXQ_FLAGS_NOMULTSEGS
214 * - ETH_TXQ_FLAGS_NOVLANOFFL
215 * - ETH_TXQ_FLAGS_NOXSUMSCTP
216 * - ETH_TXQ_FLAGS_NOXSUMUDP
217 * - ETH_TXQ_FLAGS_NOXSUMTCP
218 * and that the RS bit threshold (tx_rs_thresh) is at least equal to
219 * RTE_PMD_IXGBE_TX_MAX_BURST.
221 #define IXGBE_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
222 ETH_TXQ_FLAGS_NOOFFLOADS)
225 * Populate descriptors with the following info:
226 * 1.) buffer_addr = phys_addr + headroom
227 * 2.) cmd_type_len = DCMD_DTYP_FLAGS | pkt_len
228 * 3.) olinfo_status = pkt_len << PAYLEN_SHIFT
231 /* Defines for Tx descriptor */
232 #define DCMD_DTYP_FLAGS (IXGBE_ADVTXD_DTYP_DATA |\
233 IXGBE_ADVTXD_DCMD_IFCS |\
234 IXGBE_ADVTXD_DCMD_DEXT |\
235 IXGBE_ADVTXD_DCMD_EOP)
237 #ifdef RTE_IXGBE_INC_VECTOR
238 uint16_t ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
239 uint16_t ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts);
240 int ixgbe_txq_vec_setup(struct igb_tx_queue *txq, unsigned int socket_id);
241 int ixgbe_rxq_vec_setup(struct igb_rx_queue *rxq, unsigned int socket_id);
242 int ixgbe_rx_vec_condition_check(struct rte_eth_dev *dev);