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34 #ifndef _IXGBE_RXTX_H_
35 #define _IXGBE_RXTX_H_
38 #define RTE_PMD_IXGBE_TX_MAX_BURST 32
40 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
41 #define RTE_PMD_IXGBE_RX_MAX_BURST 32
42 #define RTE_IXGBE_DESCS_PER_LOOP 4
43 #elif defined(RTE_IXGBE_INC_VECTOR)
44 #define RTE_IXGBE_DESCS_PER_LOOP 4
46 #define RTE_IXGBE_DESCS_PER_LOOP 1
49 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
50 (uint64_t) ((mb)->buf_physaddr + (uint64_t)((char *)((mb)->data) - \
51 (char *)(mb)->buf_addr))
53 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
54 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
56 #ifdef RTE_IXGBE_INC_VECTOR
57 #define RTE_IXGBE_VPMD_RX_BURST 32
58 #define RTE_IXGBE_VPMD_TX_BURST 32
59 #define RTE_IXGBE_RXQ_REARM_THRESH RTE_IXGBE_VPMD_RX_BURST
60 #define RTE_IXGBE_TX_MAX_FREE_BUF_SZ 64
63 #define RX_RING_SZ ((IXGBE_MAX_RING_DESC + RTE_IXGBE_DESCS_PER_LOOP - 1) * \
64 sizeof(union ixgbe_adv_rx_desc))
66 #ifdef RTE_PMD_PACKET_PREFETCH
67 #define rte_packet_prefetch(p) rte_prefetch1(p)
69 #define rte_packet_prefetch(p) do {} while(0)
72 #define RTE_IXGBE_REGISTER_POLL_WAIT_10_MS 10
73 #define RTE_IXGBE_WAIT_100_US 100
74 #define RTE_IXGBE_VMTXSW_REGISTER_COUNT 2
77 * Structure associated with each descriptor of the RX ring of a RX queue.
80 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
84 * Structure associated with each descriptor of the TX ring of a TX queue.
87 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
88 uint16_t next_id; /**< Index of next descriptor in ring. */
89 uint16_t last_id; /**< Index of last scattered descriptor. */
93 * Structure associated with each descriptor of the TX ring of a TX queue.
95 struct igb_tx_entry_v {
96 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
100 * continuous entry sequence, gather by the same mempool
102 struct igb_tx_entry_seq {
103 const struct rte_mempool* pool;
108 * Structure associated with each RX queue.
110 struct igb_rx_queue {
111 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
112 volatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
113 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
114 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
115 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
116 struct igb_rx_entry *sw_ring; /**< address of RX software ring. */
117 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
118 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
119 uint16_t nb_rx_desc; /**< number of RX descriptors. */
120 uint16_t rx_tail; /**< current value of RDT register. */
121 uint16_t nb_rx_hold; /**< number of held free RX desc. */
122 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
123 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
124 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
125 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
127 #ifdef RTE_IXGBE_INC_VECTOR
128 uint16_t rxrearm_nb; /**< the idx we start the re-arming from */
129 uint16_t rxrearm_start; /**< number of remaining to be re-armed */
130 __m128i misc_info; /**< cache XMM combine port_id/crc/nb_segs */
132 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
133 uint16_t queue_id; /**< RX queue index. */
134 uint16_t reg_idx; /**< RX queue register index. */
135 uint8_t port_id; /**< Device port identifier. */
136 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
137 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
138 uint8_t start_rx_per_q;
139 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
140 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */
141 struct rte_mbuf fake_mbuf;
142 /** hold packets to return to application */
143 struct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2];
148 * IXGBE CTX Constants
150 enum ixgbe_advctx_num {
151 IXGBE_CTX_0 = 0, /**< CTX0 */
152 IXGBE_CTX_1 = 1, /**< CTX1 */
153 IXGBE_CTX_NUM = 2, /**< CTX NUMBER */
156 /** Offload features */
157 union ixgbe_vlan_macip {
160 uint16_t l2_l3_len; /**< combined 9-bit l3, 7-bit l2 lengths */
162 /**< VLAN Tag Control Identifier (CPU order). */
167 * Compare mask for vlan_macip_len.data,
168 * should be in sync with ixgbe_vlan_macip.f layout.
170 #define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - 16-bits. */
171 #define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. */
172 #define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */
173 /** MAC+IP length. */
174 #define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK)
177 * Structure to check if new context need be built
180 struct ixgbe_advctx_info {
181 uint16_t flags; /**< ol_flags for context build. */
182 uint32_t cmp_mask; /**< compare mask for vlan_macip_lens */
183 union ixgbe_vlan_macip vlan_macip_lens; /**< vlan, mac ip length. */
187 * Structure associated with each TX queue.
189 struct igb_tx_queue {
190 /** TX ring virtual address. */
191 volatile union ixgbe_adv_tx_desc *tx_ring;
192 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
193 struct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */
194 #ifdef RTE_IXGBE_INC_VECTOR
195 /** continuous tx entry sequence within the same mempool */
196 struct igb_tx_entry_seq *sw_ring_seq;
198 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
199 uint16_t nb_tx_desc; /**< number of TX descriptors. */
200 uint16_t tx_tail; /**< current value of TDT reg. */
201 uint16_t tx_free_thresh;/**< minimum TX before freeing. */
202 /** Number of TX descriptors to use before RS bit is set. */
203 uint16_t tx_rs_thresh;
204 /** Number of TX descriptors used since RS bit was set. */
206 /** Index to last TX descriptor to have been cleaned. */
207 uint16_t last_desc_cleaned;
208 /** Total number of TX descriptors ready to be allocated. */
210 uint16_t tx_next_dd; /**< next desc to scan for DD bit */
211 uint16_t tx_next_rs; /**< next desc to set RS bit */
212 uint16_t queue_id; /**< TX queue index. */
213 uint16_t reg_idx; /**< TX queue register index. */
214 uint8_t port_id; /**< Device port identifier. */
215 uint8_t pthresh; /**< Prefetch threshold register. */
216 uint8_t hthresh; /**< Host threshold register. */
217 uint8_t wthresh; /**< Write-back threshold reg. */
218 uint32_t txq_flags; /**< Holds flags for this TXq */
219 uint32_t ctx_curr; /**< Hardware context states. */
220 /** Hardware context0 history. */
221 struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM];
222 struct ixgbe_txq_ops *ops; /**< txq ops */
223 uint8_t start_tx_per_q;
226 struct ixgbe_txq_ops {
227 void (*release_mbufs)(struct igb_tx_queue *txq);
228 void (*free_swring)(struct igb_tx_queue *txq);
229 void (*reset)(struct igb_tx_queue *txq);
233 * The "simple" TX queue functions require that the following
234 * flags are set when the TX queue is configured:
235 * - ETH_TXQ_FLAGS_NOMULTSEGS
236 * - ETH_TXQ_FLAGS_NOVLANOFFL
237 * - ETH_TXQ_FLAGS_NOXSUMSCTP
238 * - ETH_TXQ_FLAGS_NOXSUMUDP
239 * - ETH_TXQ_FLAGS_NOXSUMTCP
240 * and that the RS bit threshold (tx_rs_thresh) is at least equal to
241 * RTE_PMD_IXGBE_TX_MAX_BURST.
243 #define IXGBE_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
244 ETH_TXQ_FLAGS_NOOFFLOADS)
247 * Populate descriptors with the following info:
248 * 1.) buffer_addr = phys_addr + headroom
249 * 2.) cmd_type_len = DCMD_DTYP_FLAGS | pkt_len
250 * 3.) olinfo_status = pkt_len << PAYLEN_SHIFT
253 /* Defines for Tx descriptor */
254 #define DCMD_DTYP_FLAGS (IXGBE_ADVTXD_DTYP_DATA |\
255 IXGBE_ADVTXD_DCMD_IFCS |\
256 IXGBE_ADVTXD_DCMD_DEXT |\
257 IXGBE_ADVTXD_DCMD_EOP)
259 #ifdef RTE_IXGBE_INC_VECTOR
260 uint16_t ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
261 uint16_t ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts);
262 int ixgbe_txq_vec_setup(struct igb_tx_queue *txq, unsigned int socket_id);
263 int ixgbe_rxq_vec_setup(struct igb_rx_queue *rxq, unsigned int socket_id);
264 int ixgbe_rx_vec_condition_check(struct rte_eth_dev *dev);