4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _IXGBE_RXTX_H_
35 #define _IXGBE_RXTX_H_
38 #define RTE_PMD_IXGBE_TX_MAX_BURST 32
40 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
41 #define RTE_PMD_IXGBE_RX_MAX_BURST 32
42 #define RTE_IXGBE_DESCS_PER_LOOP 4
44 #define RTE_IXGBE_DESCS_PER_LOOP 1
47 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
48 (uint64_t) ((mb)->buf_physaddr + (uint64_t)((char *)((mb)->pkt.data) - \
49 (char *)(mb)->buf_addr))
51 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
52 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
54 #ifdef RTE_IXGBE_INC_VECTOR
55 #define RTE_IXGBE_VPMD_RX_BURST 32
56 #define RTE_IXGBE_VPMD_TX_BURST 32
57 #define RTE_IXGBE_RXQ_REARM_THRESH RTE_IXGBE_VPMD_RX_BURST
58 #define RTE_IXGBE_TX_MAX_FREE_BUF_SZ 64
61 #define RX_RING_SZ ((IXGBE_MAX_RING_DESC + RTE_IXGBE_DESCS_PER_LOOP - 1) * \
62 sizeof(union ixgbe_adv_rx_desc))
64 #ifdef RTE_PMD_PACKET_PREFETCH
65 #define rte_packet_prefetch(p) rte_prefetch1(p)
67 #define rte_packet_prefetch(p) do {} while(0)
71 * Structure associated with each descriptor of the RX ring of a RX queue.
74 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
78 * Structure associated with each descriptor of the TX ring of a TX queue.
81 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
82 uint16_t next_id; /**< Index of next descriptor in ring. */
83 uint16_t last_id; /**< Index of last scattered descriptor. */
87 * Structure associated with each descriptor of the TX ring of a TX queue.
89 struct igb_tx_entry_v {
90 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
94 * continous entry sequence, gather by the same mempool
96 struct igb_tx_entry_seq {
97 const struct rte_mempool* pool;
102 * Structure associated with each RX queue.
104 struct igb_rx_queue {
105 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
106 volatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
107 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
108 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
109 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
110 struct igb_rx_entry *sw_ring; /**< address of RX software ring. */
111 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
112 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
113 uint16_t nb_rx_desc; /**< number of RX descriptors. */
114 uint16_t rx_tail; /**< current value of RDT register. */
115 uint16_t nb_rx_hold; /**< number of held free RX desc. */
116 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
117 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
118 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
119 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
121 #ifdef RTE_IXGBE_INC_VECTOR
122 uint16_t rxrearm_nb; /**< the idx we start the re-arming from */
123 uint16_t rxrearm_start; /**< number of remaining to be re-armed */
124 __m128i misc_info; /**< cache XMM combine port_id/crc/nb_segs */
126 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
127 uint16_t queue_id; /**< RX queue index. */
128 uint16_t reg_idx; /**< RX queue register index. */
129 uint8_t port_id; /**< Device port identifier. */
130 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
131 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
132 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
133 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */
134 struct rte_mbuf fake_mbuf;
135 /** hold packets to return to application */
136 struct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2];
141 * IXGBE CTX Constants
143 enum ixgbe_advctx_num {
144 IXGBE_CTX_0 = 0, /**< CTX0 */
145 IXGBE_CTX_1 = 1, /**< CTX1 */
146 IXGBE_CTX_NUM = 2, /**< CTX NUMBER */
150 * Structure to check if new context need be built
153 struct ixgbe_advctx_info {
154 uint16_t flags; /**< ol_flags for context build. */
155 uint32_t cmp_mask; /**< compare mask for vlan_macip_lens */
156 union rte_vlan_macip vlan_macip_lens; /**< vlan, mac ip length. */
160 * Structure associated with each TX queue.
162 struct igb_tx_queue {
163 /** TX ring virtual address. */
164 volatile union ixgbe_adv_tx_desc *tx_ring;
165 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
166 struct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */
167 #ifdef RTE_IXGBE_INC_VECTOR
168 /** continous tx entry sequence within the same mempool */
169 struct igb_tx_entry_seq *sw_ring_seq;
171 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
172 uint16_t nb_tx_desc; /**< number of TX descriptors. */
173 uint16_t tx_tail; /**< current value of TDT reg. */
174 uint16_t tx_free_thresh;/**< minimum TX before freeing. */
175 /** Number of TX descriptors to use before RS bit is set. */
176 uint16_t tx_rs_thresh;
177 /** Number of TX descriptors used since RS bit was set. */
179 /** Index to last TX descriptor to have been cleaned. */
180 uint16_t last_desc_cleaned;
181 /** Total number of TX descriptors ready to be allocated. */
183 uint16_t tx_next_dd; /**< next desc to scan for DD bit */
184 uint16_t tx_next_rs; /**< next desc to set RS bit */
185 uint16_t queue_id; /**< TX queue index. */
186 uint16_t reg_idx; /**< TX queue register index. */
187 uint8_t port_id; /**< Device port identifier. */
188 uint8_t pthresh; /**< Prefetch threshold register. */
189 uint8_t hthresh; /**< Host threshold register. */
190 uint8_t wthresh; /**< Write-back threshold reg. */
191 uint32_t txq_flags; /**< Holds flags for this TXq */
192 uint32_t ctx_curr; /**< Hardware context states. */
193 /** Hardware context0 history. */
194 struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM];
195 struct ixgbe_txq_ops *ops; /**< txq ops */
198 struct ixgbe_txq_ops {
199 void (*release_mbufs)(struct igb_tx_queue *txq);
200 void (*free_swring)(struct igb_tx_queue *txq);
201 void (*reset)(struct igb_tx_queue *txq);
205 * The "simple" TX queue functions require that the following
206 * flags are set when the TX queue is configured:
207 * - ETH_TXQ_FLAGS_NOMULTSEGS
208 * - ETH_TXQ_FLAGS_NOVLANOFFL
209 * - ETH_TXQ_FLAGS_NOXSUMSCTP
210 * - ETH_TXQ_FLAGS_NOXSUMUDP
211 * - ETH_TXQ_FLAGS_NOXSUMTCP
212 * and that the RS bit threshold (tx_rs_thresh) is at least equal to
213 * RTE_PMD_IXGBE_TX_MAX_BURST.
215 #define IXGBE_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
216 ETH_TXQ_FLAGS_NOOFFLOADS)
219 * Populate descriptors with the following info:
220 * 1.) buffer_addr = phys_addr + headroom
221 * 2.) cmd_type_len = DCMD_DTYP_FLAGS | pkt_len
222 * 3.) olinfo_status = pkt_len << PAYLEN_SHIFT
225 /* Defines for Tx descriptor */
226 #define DCMD_DTYP_FLAGS (IXGBE_ADVTXD_DTYP_DATA |\
227 IXGBE_ADVTXD_DCMD_IFCS |\
228 IXGBE_ADVTXD_DCMD_DEXT |\
229 IXGBE_ADVTXD_DCMD_EOP)
231 #ifdef RTE_IXGBE_INC_VECTOR
232 uint16_t ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
233 uint16_t ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts);
234 int ixgbe_txq_vec_setup(struct igb_tx_queue *txq, unsigned int socket_id);
235 int ixgbe_rxq_vec_setup(struct igb_rx_queue *rxq, unsigned int socket_id);
236 int ixgbe_rx_vec_condition_check(struct rte_eth_dev *dev);