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35 #include <rte_ethdev.h>
36 #include <rte_malloc.h>
38 #include "ixgbe_ethdev.h"
39 #include "ixgbe_rxtx.h"
41 #include <tmmintrin.h>
43 #ifndef __INTEL_COMPILER
44 #pragma GCC diagnostic ignored "-Wcast-qual"
48 ixgbe_rxq_rearm(struct igb_rx_queue *rxq)
52 volatile union ixgbe_adv_rx_desc *rxdp;
53 struct igb_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
54 struct rte_mbuf *mb0, *mb1;
55 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
56 RTE_PKTMBUF_HEADROOM);
57 __m128i dma_addr0, dma_addr1;
59 rxdp = rxq->rx_ring + rxq->rxrearm_start;
61 /* Pull 'n' more MBUFs into the software ring */
62 if (rte_mempool_get_bulk(rxq->mb_pool,
64 RTE_IXGBE_RXQ_REARM_THRESH) < 0) {
65 if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >=
67 dma_addr0 = _mm_setzero_si128();
68 for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) {
69 rxep[i].mbuf = &rxq->fake_mbuf;
70 _mm_store_si128((__m128i *)&rxdp[i].read,
74 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
75 RTE_IXGBE_RXQ_REARM_THRESH;
79 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
80 for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
81 __m128i vaddr0, vaddr1;
86 /* flush mbuf with pkt template */
87 mb0->rearm_data[0] = rxq->mbuf_initializer;
88 mb1->rearm_data[0] = rxq->mbuf_initializer;
90 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
91 vaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));
92 vaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));
94 /* convert pa to dma_addr hdr/data */
95 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
96 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
98 /* add headroom to pa values */
99 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
100 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
102 /* flush desc with pa dma_addr */
103 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
104 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
107 rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;
108 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
109 rxq->rxrearm_start = 0;
111 rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH;
113 rx_id = (uint16_t) ((rxq->rxrearm_start == 0) ?
114 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
116 /* Update the tail pointer on the NIC */
117 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
120 /* Handling the offload flags (olflags) field takes computation
121 * time when receiving packets. Therefore we provide a flag to disable
122 * the processing of the olflags field when they are not needed. This
123 * gives improved performance, at the cost of losing the offload info
124 * in the received packet
126 #ifdef RTE_IXGBE_RX_OLFLAGS_ENABLE
128 #define OLFLAGS_MASK ((uint16_t)(PKT_RX_VLAN_PKT | PKT_RX_IPV4_HDR |\
129 PKT_RX_IPV4_HDR_EXT | PKT_RX_IPV6_HDR |\
130 PKT_RX_IPV6_HDR_EXT))
131 #define OLFLAGS_MASK_V (((uint64_t)OLFLAGS_MASK << 48) | \
132 ((uint64_t)OLFLAGS_MASK << 32) | \
133 ((uint64_t)OLFLAGS_MASK << 16) | \
134 ((uint64_t)OLFLAGS_MASK))
135 #define PTYPE_SHIFT (1)
136 #define VTAG_SHIFT (3)
139 desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
141 __m128i ptype0, ptype1, vtag0, vtag1;
147 ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
148 ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
149 vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
150 vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
152 ptype1 = _mm_unpacklo_epi32(ptype0, ptype1);
153 vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
155 ptype1 = _mm_slli_epi16(ptype1, PTYPE_SHIFT);
156 vtag1 = _mm_srli_epi16(vtag1, VTAG_SHIFT);
158 ptype1 = _mm_or_si128(ptype1, vtag1);
159 vol.dword = _mm_cvtsi128_si64(ptype1) & OLFLAGS_MASK_V;
161 rx_pkts[0]->ol_flags = vol.e[0];
162 rx_pkts[1]->ol_flags = vol.e[1];
163 rx_pkts[2]->ol_flags = vol.e[2];
164 rx_pkts[3]->ol_flags = vol.e[3];
167 #define desc_to_olflags_v(desc, rx_pkts) do {} while (0)
171 * vPMD receive routine, now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)
175 * - nb_pkts < RTE_IXGBE_VPMD_RX_BURST, just return no packet
176 * - nb_pkts > RTE_IXGBE_VPMD_RX_BURST, only scan RTE_IXGBE_VPMD_RX_BURST
178 * - don't support ol_flags for rss and csum err
180 static inline uint16_t
181 _recv_raw_pkts_vec(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
182 uint16_t nb_pkts, uint8_t *split_packet)
184 volatile union ixgbe_adv_rx_desc *rxdp;
185 struct igb_rx_entry *sw_ring;
186 uint16_t nb_pkts_recd;
190 __m128i crc_adjust = _mm_set_epi16(
191 0, 0, 0, 0, /* ignore non-length fields */
192 0, /* ignore high-16bits of pkt_len */
193 -rxq->crc_len, /* sub crc on pkt_len */
194 -rxq->crc_len, /* sub crc on data_len */
195 0 /* ignore pkt_type field */
197 __m128i dd_check, eop_check;
199 if (unlikely(nb_pkts < RTE_IXGBE_VPMD_RX_BURST))
202 /* Just the act of getting into the function from the application is
203 * going to cost about 7 cycles */
204 rxdp = rxq->rx_ring + rxq->rx_tail;
206 _mm_prefetch((const void *)rxdp, _MM_HINT_T0);
208 /* See if we need to rearm the RX queue - gives the prefetch a bit
210 if (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH)
211 ixgbe_rxq_rearm(rxq);
213 /* Before we start moving massive data around, check to see if
214 * there is actually a packet available */
215 if (!(rxdp->wb.upper.status_error &
216 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
219 /* 4 packets DD mask */
220 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
222 /* 4 packets EOP mask */
223 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
225 /* mask to shuffle from desc. to mbuf */
226 shuf_msk = _mm_set_epi8(
227 7, 6, 5, 4, /* octet 4~7, 32bits rss */
228 0xFF, 0xFF, /* skip high 16 bits vlan_macip, zero out */
229 15, 14, /* octet 14~15, low 16 bits vlan_macip */
230 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
231 13, 12, /* octet 12~13, low 16 bits pkt_len */
232 13, 12, /* octet 12~13, 16 bits data_len */
233 0xFF, 0xFF /* skip pkt_type field */
236 /* Cache is empty -> need to scan the buffer rings, but first move
237 * the next 'n' mbufs into the cache */
238 sw_ring = &rxq->sw_ring[rxq->rx_tail];
241 * A. load 4 packet in one loop
242 * B. copy 4 mbuf point from swring to rx_pkts
243 * C. calc the number of DD bits among the 4 packets
244 * [C*. extract the end-of-packet bit, if requested]
245 * D. fill info. from desc to mbuf
247 for (pos = 0, nb_pkts_recd = 0; pos < RTE_IXGBE_VPMD_RX_BURST;
248 pos += RTE_IXGBE_DESCS_PER_LOOP,
249 rxdp += RTE_IXGBE_DESCS_PER_LOOP) {
250 __m128i descs[RTE_IXGBE_DESCS_PER_LOOP];
251 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
252 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
253 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
256 rte_prefetch0(&rx_pkts[pos]->cacheline1);
257 rte_prefetch0(&rx_pkts[pos + 1]->cacheline1);
258 rte_prefetch0(&rx_pkts[pos + 2]->cacheline1);
259 rte_prefetch0(&rx_pkts[pos + 3]->cacheline1);
262 /* B.1 load 1 mbuf point */
263 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
265 /* Read desc statuses backwards to avoid race condition */
266 /* A.1 load 4 pkts desc */
267 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
269 /* B.2 copy 2 mbuf point into rx_pkts */
270 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
272 /* B.1 load 1 mbuf point */
273 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
275 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
276 /* B.1 load 2 mbuf point */
277 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
278 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
280 /* B.2 copy 2 mbuf point into rx_pkts */
281 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
283 /* avoid compiler reorder optimization */
284 rte_compiler_barrier();
286 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
287 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
288 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
290 /* C.1 4=>2 filter staterr info only */
291 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
292 /* C.1 4=>2 filter staterr info only */
293 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
295 /* set ol_flags with packet type and vlan tag */
296 desc_to_olflags_v(descs, &rx_pkts[pos]);
298 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
299 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
300 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
302 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
303 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
304 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
306 /* C.2 get 4 pkts staterr value */
307 zero = _mm_xor_si128(dd_check, dd_check);
308 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
310 /* D.3 copy final 3,4 data to rx_pkts */
311 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
313 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
316 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
317 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
318 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
320 /* C* extract and record EOP bit */
322 __m128i eop_shuf_mask = _mm_set_epi8(
323 0xFF, 0xFF, 0xFF, 0xFF,
324 0xFF, 0xFF, 0xFF, 0xFF,
325 0xFF, 0xFF, 0xFF, 0xFF,
326 0x04, 0x0C, 0x00, 0x08
329 /* and with mask to extract bits, flipping 1-0 */
330 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
331 /* the staterr values are not in order, as the count
332 * count of dd bits doesn't care. However, for end of
333 * packet tracking, we do care, so shuffle. This also
334 * compresses the 32-bit values to 8-bit */
335 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
336 /* store the resulting 32-bit value */
337 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
338 split_packet += RTE_IXGBE_DESCS_PER_LOOP;
340 /* zero-out next pointers */
341 rx_pkts[pos]->next = NULL;
342 rx_pkts[pos + 1]->next = NULL;
343 rx_pkts[pos + 2]->next = NULL;
344 rx_pkts[pos + 3]->next = NULL;
347 /* C.3 calc available number of desc */
348 staterr = _mm_and_si128(staterr, dd_check);
349 staterr = _mm_packs_epi32(staterr, zero);
351 /* D.3 copy final 1,2 data to rx_pkts */
352 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
354 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
357 /* C.4 calc avaialbe number of desc */
358 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
360 if (likely(var != RTE_IXGBE_DESCS_PER_LOOP))
364 /* Update our internal tail pointer */
365 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
366 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
367 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
373 * vPMD receive routine, now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)
377 * - nb_pkts < RTE_IXGBE_VPMD_RX_BURST, just return no packet
378 * - nb_pkts > RTE_IXGBE_VPMD_RX_BURST, only scan RTE_IXGBE_VPMD_RX_BURST
380 * - don't support ol_flags for rss and csum err
383 ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
386 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
389 static inline uint16_t
390 reassemble_packets(struct igb_rx_queue *rxq, struct rte_mbuf **rx_bufs,
391 uint16_t nb_bufs, uint8_t *split_flags)
393 struct rte_mbuf *pkts[RTE_IXGBE_VPMD_RX_BURST]; /*finished pkts*/
394 struct rte_mbuf *start = rxq->pkt_first_seg;
395 struct rte_mbuf *end = rxq->pkt_last_seg;
396 unsigned pkt_idx = 0, buf_idx = 0;
399 while (buf_idx < nb_bufs) {
401 /* processing a split packet */
402 end->next = rx_bufs[buf_idx];
403 rx_bufs[buf_idx]->data_len += rxq->crc_len;
406 start->pkt_len += rx_bufs[buf_idx]->data_len;
409 if (!split_flags[buf_idx]) {
410 /* it's the last packet of the set */
411 start->hash = end->hash;
412 start->ol_flags = end->ol_flags;
413 /* we need to strip crc for the whole packet */
414 start->pkt_len -= rxq->crc_len;
415 if (end->data_len > rxq->crc_len)
416 end->data_len -= rxq->crc_len;
418 /* free up last mbuf */
419 struct rte_mbuf *secondlast = start;
420 while (secondlast->next != end)
421 secondlast = secondlast->next;
422 secondlast->data_len -= (rxq->crc_len -
424 secondlast->next = NULL;
425 rte_pktmbuf_free_seg(end);
428 pkts[pkt_idx++] = start;
432 /* not processing a split packet */
433 if (!split_flags[buf_idx]) {
434 /* not a split packet, save and skip */
435 pkts[pkt_idx++] = rx_bufs[buf_idx];
438 end = start = rx_bufs[buf_idx];
439 rx_bufs[buf_idx]->data_len += rxq->crc_len;
440 rx_bufs[buf_idx]->pkt_len += rxq->crc_len;
445 /* save the partial packet for next time */
446 rxq->pkt_first_seg = start;
447 rxq->pkt_last_seg = end;
448 memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
453 * vPMD receive routine that reassembles scattered packets
456 * - don't support ol_flags for rss and csum err
457 * - now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)
460 ixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
463 struct igb_rx_queue *rxq = rx_queue;
464 uint8_t split_flags[RTE_IXGBE_VPMD_RX_BURST] = {0};
466 /* get some new buffers */
467 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
472 /* happy day case, full burst + no packets to be joined */
473 const uint32_t *split_fl32 = (uint32_t *)split_flags;
474 if (rxq->pkt_first_seg == NULL &&
475 split_fl32[0] == 0 && split_fl32[1] == 0 &&
476 split_fl32[2] == 0 && split_fl32[3] == 0)
479 /* reassemble any packets that need reassembly*/
481 if (rxq->pkt_first_seg == NULL) {
482 /* find the first split flag, and only reassemble then*/
483 while (!split_flags[i] && i < nb_bufs)
488 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
493 vtx1(volatile union ixgbe_adv_tx_desc *txdp,
494 struct rte_mbuf *pkt, uint64_t flags)
496 __m128i descriptor = _mm_set_epi64x((uint64_t)pkt->pkt_len << 46 |
497 flags | pkt->data_len,
498 pkt->buf_physaddr + pkt->data_off);
499 _mm_store_si128((__m128i *)&txdp->read, descriptor);
503 vtx(volatile union ixgbe_adv_tx_desc *txdp,
504 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
507 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
508 vtx1(txdp, *pkt, flags);
511 static inline int __attribute__((always_inline))
512 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
514 struct igb_tx_entry_v *txep;
519 struct rte_mbuf *m, *free[RTE_IXGBE_TX_MAX_FREE_BUF_SZ];
521 /* check DD bit on threshold descriptor */
522 status = txq->tx_ring[txq->tx_next_dd].wb.status;
523 if (!(status & IXGBE_ADVTXD_STAT_DD))
526 n = txq->tx_rs_thresh;
529 * first buffer to free from S/W ring is at index
530 * tx_next_dd - (tx_rs_thresh-1)
532 txep = &((struct igb_tx_entry_v *)txq->sw_ring)[txq->tx_next_dd -
534 #ifdef RTE_MBUF_REFCNT
535 m = __rte_pktmbuf_prefree_seg(txep[0].mbuf);
539 if (likely(m != NULL)) {
542 for (i = 1; i < n; i++) {
543 #ifdef RTE_MBUF_REFCNT
544 m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
548 if (likely(m != NULL)) {
549 if (likely(m->pool == free[0]->pool))
552 rte_mempool_put_bulk(free[0]->pool,
553 (void *)free, nb_free);
559 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
561 for (i = 1; i < n; i++) {
562 m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
564 rte_mempool_put(m->pool, m);
568 /* buffers were freed, update counters */
569 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
570 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
571 if (txq->tx_next_dd >= txq->nb_tx_desc)
572 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
574 return txq->tx_rs_thresh;
577 static inline void __attribute__((always_inline))
578 tx_backlog_entry(struct igb_tx_entry_v *txep,
579 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
582 for (i = 0; i < (int)nb_pkts; ++i)
583 txep[i].mbuf = tx_pkts[i];
587 ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
590 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
591 volatile union ixgbe_adv_tx_desc *txdp;
592 struct igb_tx_entry_v *txep;
593 uint16_t n, nb_commit, tx_id;
594 uint64_t flags = DCMD_DTYP_FLAGS;
595 uint64_t rs = IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS;
598 if (unlikely(nb_pkts > RTE_IXGBE_VPMD_TX_BURST))
599 nb_pkts = RTE_IXGBE_VPMD_TX_BURST;
601 if (txq->nb_tx_free < txq->tx_free_thresh)
602 ixgbe_tx_free_bufs(txq);
604 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
605 if (unlikely(nb_pkts == 0))
608 tx_id = txq->tx_tail;
609 txdp = &txq->tx_ring[tx_id];
610 txep = &((struct igb_tx_entry_v *)txq->sw_ring)[tx_id];
612 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
614 n = (uint16_t)(txq->nb_tx_desc - tx_id);
615 if (nb_commit >= n) {
617 tx_backlog_entry(txep, tx_pkts, n);
619 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
620 vtx1(txdp, *tx_pkts, flags);
622 vtx1(txdp, *tx_pkts++, rs);
624 nb_commit = (uint16_t)(nb_commit - n);
627 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
629 /* avoid reach the end of ring */
630 txdp = &(txq->tx_ring[tx_id]);
631 txep = &(((struct igb_tx_entry_v *)txq->sw_ring)[tx_id]);
634 tx_backlog_entry(txep, tx_pkts, nb_commit);
636 vtx(txdp, tx_pkts, nb_commit, flags);
638 tx_id = (uint16_t)(tx_id + nb_commit);
639 if (tx_id > txq->tx_next_rs) {
640 txq->tx_ring[txq->tx_next_rs].read.cmd_type_len |=
641 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
642 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
646 txq->tx_tail = tx_id;
648 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
654 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
657 struct igb_tx_entry_v *txe;
658 uint16_t nb_free, max_desc;
660 if (txq->sw_ring != NULL) {
661 /* release the used mbufs in sw_ring */
662 nb_free = txq->nb_tx_free;
663 max_desc = (uint16_t)(txq->nb_tx_desc - 1);
664 for (i = txq->tx_next_dd - (txq->tx_rs_thresh - 1);
665 nb_free < max_desc && i != txq->tx_tail;
666 i = (i + 1) & max_desc) {
667 txe = (struct igb_tx_entry_v *)&txq->sw_ring[i];
668 if (txe->mbuf != NULL)
669 rte_pktmbuf_free_seg(txe->mbuf);
672 for (i = 0; i < txq->nb_tx_desc; i++) {
673 txe = (struct igb_tx_entry_v *)&txq->sw_ring[i];
680 ixgbe_tx_free_swring(struct igb_tx_queue *txq)
685 if (txq->sw_ring != NULL) {
686 rte_free((struct igb_rx_entry *)txq->sw_ring - 1);
692 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
694 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
696 struct igb_tx_entry_v *txe = (struct igb_tx_entry_v *)txq->sw_ring;
699 /* Zero out HW ring memory */
700 for (i = 0; i < txq->nb_tx_desc; i++)
701 txq->tx_ring[i] = zeroed_desc;
703 /* Initialize SW ring entries */
704 for (i = 0; i < txq->nb_tx_desc; i++) {
705 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
706 txd->wb.status = IXGBE_TXD_STAT_DD;
710 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
711 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
716 * Always allow 1 descriptor to be un-allocated to avoid
717 * a H/W race condition
719 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
720 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
722 memset((void *)&txq->ctx_cache, 0,
723 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
726 static struct ixgbe_txq_ops vec_txq_ops = {
727 .release_mbufs = ixgbe_tx_queue_release_mbufs,
728 .free_swring = ixgbe_tx_free_swring,
729 .reset = ixgbe_reset_tx_queue,
733 ixgbe_rxq_vec_setup(struct igb_rx_queue *rxq)
735 struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
738 mb_def.data_off = RTE_PKTMBUF_HEADROOM;
739 mb_def.buf_len = rxq->mb_pool->elt_size - sizeof(struct rte_mbuf);
740 mb_def.port = rxq->port_id;
741 rte_mbuf_refcnt_set(&mb_def, 1);
743 /* prevent compiler reordering: rearm_data covers previous fields */
744 rte_compiler_barrier();
745 rxq->mbuf_initializer = *((uint64_t *)&mb_def.rearm_data);
749 int ixgbe_txq_vec_setup(struct igb_tx_queue *txq)
751 if (txq->sw_ring == NULL)
754 /* leave the first one for overflow */
755 txq->sw_ring = (struct igb_tx_entry *)
756 ((struct igb_tx_entry_v *)txq->sw_ring + 1);
757 txq->ops = &vec_txq_ops;
762 int ixgbe_rx_vec_condition_check(struct rte_eth_dev *dev)
764 #ifndef RTE_LIBRTE_IEEE1588
765 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
766 struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
768 #ifndef RTE_IXGBE_RX_OLFLAGS_ENABLE
769 /* whithout rx ol_flags, no VP flag report */
770 if (rxmode->hw_vlan_strip != 0 ||
771 rxmode->hw_vlan_extend != 0)
775 /* no fdir support */
776 if (fconf->mode != RTE_FDIR_MODE_NONE)
780 * - no csum error report support
781 * - no header split support
783 if (rxmode->hw_ip_checksum == 1 ||
784 rxmode->header_split == 1)