4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_atomic.h>
61 #include <rte_string_fns.h>
62 #include <rte_malloc.h>
65 #include "vmxnet3/vmxnet3_defs.h"
67 #include "vmxnet3_ring.h"
68 #include "vmxnet3_logs.h"
69 #include "vmxnet3_ethdev.h"
71 #define PROCESS_SYS_EVENTS 0
73 static int eth_vmxnet3_dev_init(struct eth_driver *eth_drv,
74 struct rte_eth_dev *eth_dev);
75 static int vmxnet3_dev_configure(struct rte_eth_dev *dev);
76 static int vmxnet3_dev_start(struct rte_eth_dev *dev);
77 static void vmxnet3_dev_stop(struct rte_eth_dev *dev);
78 static void vmxnet3_dev_close(struct rte_eth_dev *dev);
79 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set);
80 static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev);
81 static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev);
82 static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev);
83 static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev);
84 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev,
85 int wait_to_complete);
86 static void vmxnet3_dev_stats_get(struct rte_eth_dev *dev,
87 struct rte_eth_stats *stats);
88 static void vmxnet3_dev_info_get(struct rte_eth_dev *dev,
89 struct rte_eth_dev_info *dev_info);
90 #if PROCESS_SYS_EVENTS == 1
91 static void vmxnet3_process_events(struct vmxnet3_hw *);
94 * The set of PCI devices this driver supports
96 static struct rte_pci_id pci_id_vmxnet3_map[] = {
98 #define RTE_PCI_DEV_ID_DECL_VMXNET3(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
99 #include "rte_pci_dev_ids.h"
101 { .vendor_id = 0, /* sentinel */ },
104 static struct eth_dev_ops vmxnet3_eth_dev_ops = {
105 .dev_configure = vmxnet3_dev_configure,
106 .dev_start = vmxnet3_dev_start,
107 .dev_stop = vmxnet3_dev_stop,
108 .dev_close = vmxnet3_dev_close,
109 .promiscuous_enable = vmxnet3_dev_promiscuous_enable,
110 .promiscuous_disable = vmxnet3_dev_promiscuous_disable,
111 .allmulticast_enable = vmxnet3_dev_allmulticast_enable,
112 .allmulticast_disable = vmxnet3_dev_allmulticast_disable,
113 .link_update = vmxnet3_dev_link_update,
114 .stats_get = vmxnet3_dev_stats_get,
115 .dev_infos_get = vmxnet3_dev_info_get,
116 .rx_queue_setup = vmxnet3_dev_rx_queue_setup,
117 .rx_queue_release = vmxnet3_dev_rx_queue_release,
118 .tx_queue_setup = vmxnet3_dev_tx_queue_setup,
119 .tx_queue_release = vmxnet3_dev_tx_queue_release,
122 static const struct rte_memzone *
123 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,
124 const char *post_string, int socket_id, uint16_t align)
126 char z_name[RTE_MEMZONE_NAMESIZE];
127 const struct rte_memzone *mz;
129 rte_snprintf(z_name, sizeof(z_name), "%s_%d_%s",
130 dev->driver->pci_drv.name, dev->data->port_id, post_string);
132 mz = rte_memzone_lookup(z_name);
136 return rte_memzone_reserve_aligned(z_name, size,
137 socket_id, 0, align);
141 * Atomically reads the link status information from global
142 * structure rte_eth_dev.
145 * - Pointer to the structure rte_eth_dev to read from.
146 * - Pointer to the buffer to be saved with the link status.
149 * - On success, zero.
150 * - On failure, negative value.
153 rte_vmxnet3_dev_atomic_write_link_status(struct rte_eth_dev *dev,
154 struct rte_eth_link *link)
156 struct rte_eth_link *dst = &(dev->data->dev_link);
157 struct rte_eth_link *src = link;
159 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
160 *(uint64_t *)src) == 0)
167 * This function is based on vmxnet3_disable_intr()
170 vmxnet3_disable_intr(struct vmxnet3_hw *hw)
174 PMD_INIT_FUNC_TRACE();
176 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
177 for (i = 0; i < VMXNET3_MAX_INTRS; i++)
178 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1);
182 * It returns 0 on success.
185 eth_vmxnet3_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
186 struct rte_eth_dev *eth_dev)
188 struct rte_pci_device *pci_dev;
189 struct vmxnet3_hw *hw =
190 VMXNET3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
191 uint32_t mac_hi, mac_lo, ver;
193 PMD_INIT_FUNC_TRACE();
195 eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
196 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
197 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
198 pci_dev = eth_dev->pci_dev;
201 * for secondary processes, we don't initialise any further as primary
202 * has already done this work.
204 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
207 /* Vendor and Device ID need to be set before init of shared code */
208 hw->device_id = pci_dev->id.device_id;
209 hw->vendor_id = pci_dev->id.vendor_id;
210 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
211 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;
213 hw->num_rx_queues = 1;
214 hw->num_tx_queues = 1;
215 hw->cur_mtu = ETHER_MTU;
216 hw->bufs_per_pkt = 1;
218 /* Check h/w version compatibility with driver. */
219 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
220 PMD_INIT_LOG(DEBUG, "Harware version : %d\n", ver);
222 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 1);
224 PMD_INIT_LOG(ERR, "Uncompatiable h/w version, should be 0x1\n");
228 /* Check UPT version compatibility with driver. */
229 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
230 PMD_INIT_LOG(DEBUG, "UPT harware version : %d\n", ver);
232 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
234 PMD_INIT_LOG(ERR, "Incompatiable UPT version.\n");
238 /* Getting MAC Address */
239 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
240 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
241 memcpy(hw->perm_addr , &mac_lo, 4);
242 memcpy(hw->perm_addr+4, &mac_hi, 2);
244 /* Allocate memory for storing MAC addresses */
245 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN *
246 VMXNET3_MAX_MAC_ADDRS, 0);
247 if (eth_dev->data->mac_addrs == NULL) {
249 "Failed to allocate %d bytes needed to store MAC addresses",
250 ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
253 /* Copy the permanent MAC address */
254 ether_addr_copy((struct ether_addr *) hw->perm_addr,
255 ð_dev->data->mac_addrs[0]);
257 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x \n",
258 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
259 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
261 /* Put device in Quiesce Mode */
262 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
267 static struct eth_driver rte_vmxnet3_pmd = {
269 .name = "rte_vmxnet3_pmd",
270 .id_table = pci_id_vmxnet3_map,
271 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
273 .eth_dev_init = eth_vmxnet3_dev_init,
274 .dev_private_size = sizeof(struct vmxnet3_adapter),
278 * Driver initialization routine.
279 * Invoked once at EAL init time.
280 * Register itself as the [Poll Mode] Driver of Virtual PCI VMXNET3 devices.
283 rte_vmxnet3_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
285 PMD_INIT_FUNC_TRACE();
287 rte_eth_driver_register(&rte_vmxnet3_pmd);
292 vmxnet3_dev_configure(struct rte_eth_dev *dev)
294 const struct rte_memzone *mz;
295 struct vmxnet3_hw *hw =
296 VMXNET3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
299 PMD_INIT_FUNC_TRACE();
301 if (dev->data->nb_rx_queues > UINT8_MAX ||
302 dev->data->nb_tx_queues > UINT8_MAX)
305 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
306 dev->data->nb_tx_queues * sizeof (struct Vmxnet3_RxQueueDesc);
308 if (size > UINT16_MAX)
311 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues;
312 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues;
315 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead
318 mz = gpa_zone_reserve(dev, sizeof (struct Vmxnet3_DriverShared),
319 "shared", rte_socket_id(), 8);
322 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone\n");
325 memset(mz->addr, 0, mz->len);
327 hw->shared = mz->addr;
328 hw->sharedPA = mz->phys_addr;
331 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc
334 mz = gpa_zone_reserve(dev, size, "queuedesc",
335 rte_socket_id(), VMXNET3_QUEUE_DESC_ALIGN);
337 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone\n");
340 memset(mz->addr, 0, mz->len);
342 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr;
343 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues);
345 hw->queueDescPA = mz->phys_addr;
346 hw->queue_desc_len = (uint16_t)size;
348 if(dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
350 /* Allocate memory structure for UPT1_RSSConf and configure */
351 mz = gpa_zone_reserve(dev, sizeof (struct VMXNET3_RSSConf), "rss_conf",
352 rte_socket_id(), CACHE_LINE_SIZE);
354 PMD_INIT_LOG(ERR, "ERROR: Creating rss_conf structure zone\n");
357 memset(mz->addr, 0, mz->len);
359 hw->rss_conf = mz->addr;
360 hw->rss_confPA = mz->phys_addr;
367 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
369 struct rte_eth_conf port_conf = dev->data->dev_conf;
370 struct vmxnet3_hw *hw = VMXNET3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
371 Vmxnet3_DriverShared *shared = hw->shared;
372 Vmxnet3_DSDevRead *devRead = &shared->devRead;
377 shared->magic = VMXNET3_REV1_MAGIC;
378 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;
380 /* Setting up Guest OS information */
381 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ?
382 VMXNET3_GOS_BITS_32 :
384 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
385 devRead->misc.driverInfo.vmxnet3RevSpt = 1;
386 devRead->misc.driverInfo.uptVerSpt = 1;
388 devRead->misc.queueDescPA = hw->queueDescPA;
389 devRead->misc.queueDescLen = hw->queue_desc_len;
390 devRead->misc.mtu = hw->cur_mtu;
391 devRead->misc.numTxQueues = hw->num_tx_queues;
392 devRead->misc.numRxQueues = hw->num_rx_queues;
395 * Set number of interrupts to 1
396 * PMD disables all the interrupts but this is MUST to activate device
397 * It needs at least one interrupt for link events to handle
398 * So we'll disable it later after device activation if needed
400 devRead->intrConf.numIntrs = 1;
401 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
403 for (i = 0; i < hw->num_tx_queues; i++) {
404 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i];
405 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i];
407 tqd->ctrl.txNumDeferred = 0;
408 tqd->ctrl.txThreshold = 1;
409 tqd->conf.txRingBasePA = txq->cmd_ring.basePA;
410 tqd->conf.compRingBasePA = txq->comp_ring.basePA;
412 tqd->conf.txRingSize = txq->cmd_ring.size;
413 tqd->conf.compRingSize = txq->comp_ring.size;
414 tqd->conf.intrIdx = txq->comp_ring.intr_idx;
415 tqd->status.stopped = TRUE;
416 tqd->status.error = 0;
417 memset(&tqd->stats, 0, sizeof(tqd->stats));
420 for (i = 0; i < hw->num_rx_queues; i++) {
421 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i];
422 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
424 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA;
425 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA;
426 rqd->conf.compRingBasePA = rxq->comp_ring.basePA;
428 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size;
429 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size;
430 rqd->conf.compRingSize = rxq->comp_ring.size;
431 rqd->conf.intrIdx = rxq->comp_ring.intr_idx;
432 rqd->status.stopped = TRUE;
433 rqd->status.error = 0;
434 memset(&rqd->stats, 0, sizeof(rqd->stats));
437 /* RxMode set to 0 of VMXNET3_RXM_xxx */
438 devRead->rxFilterConf.rxMode = 0;
440 /* Setting up feature flags */
441 if(dev->data->dev_conf.rxmode.hw_ip_checksum) {
442 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM;
445 if(dev->data->dev_conf.rxmode.hw_vlan_strip) {
446 devRead->misc.uptFeatures |= VMXNET3_F_RXVLAN;
449 if(port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
450 ret = vmxnet3_rss_configure(dev);
451 if(ret != VMXNET3_SUCCESS) {
454 devRead->misc.uptFeatures |= VMXNET3_F_RSS;
455 devRead->rssConfDesc.confVer = 1;
456 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf);
457 devRead->rssConfDesc.confPA = hw->rss_confPA;
460 if(dev->data->dev_conf.rxmode.hw_vlan_filter) {
461 ret = vmxnet3_vlan_configure(dev);
462 if(ret != VMXNET3_SUCCESS) {
467 PMD_INIT_LOG(DEBUG, "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x \n",
468 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
469 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
471 /* Write MAC Address back to device */
472 mac_ptr = (uint32_t *)hw->perm_addr;
474 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val);
476 val = (hw->perm_addr[5] << 8) | hw->perm_addr[4];
477 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val);
479 return VMXNET3_SUCCESS;
483 * Configure device link speed and setup link.
484 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail
485 * It returns 0 on success.
488 vmxnet3_dev_start(struct rte_eth_dev *dev)
491 struct vmxnet3_hw *hw = VMXNET3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
493 PMD_INIT_FUNC_TRACE();
495 ret = vmxnet3_setup_driver_shared(dev);
496 if(ret != VMXNET3_SUCCESS) {
500 /* Exchange shared data with device */
501 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
503 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
506 /* Activate device by register write */
507 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);
508 status = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
511 PMD_INIT_LOG(ERR, "Device activation in %s(): UNSUCCESSFUL\n", __func__);
515 /* Disable interrupts */
516 vmxnet3_disable_intr(hw);
519 * Load RX queues with blank mbufs and update next2fill index for device
520 * Update RxMode of the device
522 ret = vmxnet3_dev_rxtx_init(dev);
523 if(ret != VMXNET3_SUCCESS) {
524 PMD_INIT_LOG(ERR, "Device receive init in %s: UNSUCCESSFUL\n", __func__);
528 /* Setting proper Rx Mode and issue Rx Mode Update command */
529 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_ALL_MULTI, 1);
532 * Don't need to handle events for now
534 #if PROCESS_SYS_EVENTS == 1
535 events = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_ECR);
536 PMD_INIT_LOG(DEBUG, "Reading events: 0x%X\n\n", events);
537 vmxnet3_process_events(hw);
543 * Stop device: disable rx and tx functions to allow for reconfiguring.
546 vmxnet3_dev_stop(struct rte_eth_dev *dev)
548 struct rte_eth_link link;
549 struct vmxnet3_hw *hw =
550 VMXNET3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
552 PMD_INIT_FUNC_TRACE();
554 if(hw->adapter_stopped == TRUE) {
555 PMD_INIT_LOG(DEBUG, "Device already closed.\n");
559 /* disable interrupts */
560 vmxnet3_disable_intr(hw);
562 /* quiesce the device first */
563 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
564 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);
565 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);
567 /* reset the device */
568 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
569 PMD_INIT_LOG(DEBUG, "Device reset.\n");
570 hw->adapter_stopped = FALSE;
572 vmxnet3_dev_clear_queues(dev);
574 /* Clear recorded link status */
575 memset(&link, 0, sizeof(link));
576 rte_vmxnet3_dev_atomic_write_link_status(dev, &link);
580 * Reset and stop device.
583 vmxnet3_dev_close(struct rte_eth_dev *dev)
585 struct vmxnet3_hw *hw =
586 VMXNET3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
588 PMD_INIT_FUNC_TRACE();
590 vmxnet3_dev_stop(dev);
591 hw->adapter_stopped = TRUE;
596 vmxnet3_dev_stats_get( struct rte_eth_dev *dev, struct rte_eth_stats *stats)
599 struct vmxnet3_hw *hw = VMXNET3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
601 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
608 stats->rx_nombuf = 0;
611 stats->fdirmatch = 0;
614 for (i = 0; i < hw->num_tx_queues; i++) {
615 stats->opackets += hw->tqd_start[i].stats.ucastPktsTxOK +
616 hw->tqd_start[i].stats.mcastPktsTxOK +
617 hw->tqd_start[i].stats.bcastPktsTxOK;
618 stats->obytes += hw->tqd_start[i].stats.ucastBytesTxOK +
619 hw->tqd_start[i].stats.mcastBytesTxOK +
620 hw->tqd_start[i].stats.bcastBytesTxOK;
621 stats->oerrors += hw->tqd_start[i].stats.pktsTxError +
622 hw->tqd_start[i].stats.pktsTxDiscard;
625 for (i = 0; i < hw->num_rx_queues; i++) {
626 stats->ipackets += hw->rqd_start[i].stats.ucastPktsRxOK +
627 hw->rqd_start[i].stats.mcastPktsRxOK +
628 hw->rqd_start[i].stats.bcastPktsRxOK;
629 stats->ibytes += hw->rqd_start[i].stats.ucastBytesRxOK +
630 hw->rqd_start[i].stats.mcastBytesRxOK +
631 hw->rqd_start[i].stats.bcastBytesRxOK;
632 stats->rx_nombuf += hw->rqd_start[i].stats.pktsRxOutOfBuf;
633 stats->ierrors += hw->rqd_start[i].stats.pktsRxError;
639 vmxnet3_dev_info_get(__attribute__((unused))struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
641 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;
642 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;
643 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;
644 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */
645 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS;
648 /* return 0 means link status changed, -1 means not changed */
650 vmxnet3_dev_link_update(struct rte_eth_dev *dev, __attribute__((unused)) int wait_to_complete)
652 struct vmxnet3_hw *hw = VMXNET3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
653 struct rte_eth_link link;
656 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
657 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
660 PMD_INIT_LOG(ERR, "Link Status Negative : %s()\n", __func__);
665 link.link_status = 1;
666 link.link_duplex = ETH_LINK_FULL_DUPLEX;
667 link.link_speed = ETH_LINK_SPEED_10000;
669 rte_vmxnet3_dev_atomic_write_link_status(dev, &link);
677 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */
679 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) {
681 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
683 rxConf->rxMode = rxConf->rxMode | feature;
685 rxConf->rxMode = rxConf->rxMode & (~feature);
687 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);
690 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
692 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev)
694 struct vmxnet3_hw *hw = VMXNET3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
695 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);
698 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
700 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev)
702 struct vmxnet3_hw *hw = VMXNET3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
703 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);
706 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
708 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev)
710 struct vmxnet3_hw *hw = VMXNET3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
711 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);
714 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
716 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev)
718 struct vmxnet3_hw *hw = VMXNET3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
719 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);
722 #if PROCESS_SYS_EVENTS == 1
724 vmxnet3_process_events(struct vmxnet3_hw *hw)
726 uint32_t events = hw->shared->ecr;
728 PMD_INIT_LOG(ERR, "No events to process in %s()\n", __func__);
733 * ECR bits when written with 1b are cleared. Hence write
734 * events back to ECR so that the bits which were set will be reset.
736 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events);
738 /* Check if link state has changed */
739 if (events & VMXNET3_ECR_LINK){
740 PMD_INIT_LOG(ERR, "Process events in %s(): VMXNET3_ECR_LINK event\n", __func__);
743 /* Check if there is an error on xmit/recv queues */
744 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
745 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_QUEUE_STATUS);
747 if (hw->tqd_start->status.stopped)
748 PMD_INIT_LOG(ERR, "tq error 0x%x\n",
749 hw->tqd_start->status.error);
751 if (hw->rqd_start->status.stopped)
752 PMD_INIT_LOG(ERR, "rq error 0x%x\n",
753 hw->rqd_start->status.error);
755 /* Reset the device */
756 /* Have to reset the device */
759 if (events & VMXNET3_ECR_DIC)
760 PMD_INIT_LOG(ERR, "Device implementation change event.\n");
762 if (events & VMXNET3_ECR_DEBUG)
763 PMD_INIT_LOG(ERR, "Debug event generated by device.\n");
768 static struct rte_driver rte_vmxnet3_driver = {
770 .init = rte_vmxnet3_pmd_init,
773 PMD_REGISTER_DRIVER(rte_vmxnet3_driver);