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34 #ifndef _VMXNET3_ETHDEV_H_
35 #define _VMXNET3_ETHDEV_H_
37 #ifdef RTE_LIBRTE_VMXNET3_DEBUG_DRIVER
38 #define VMXNET3_ASSERT(x) do { \
39 if (!(x)) rte_panic("VMXNET3: x"); \
43 #define VMXNET3_MAX_MAC_ADDRS 1
45 /* UPT feature to negotiate */
46 #define VMXNET3_F_RXCSUM 0x0001
47 #define VMXNET3_F_RSS 0x0002
48 #define VMXNET3_F_RXVLAN 0x0004
49 #define VMXNET3_F_LRO 0x0008
51 /* Hash Types supported by device */
52 #define VMXNET3_RSS_HASH_TYPE_NONE 0x0
53 #define VMXNET3_RSS_HASH_TYPE_IPV4 0x01
54 #define VMXNET3_RSS_HASH_TYPE_TCP_IPV4 0x02
55 #define VMXNET3_RSS_HASH_TYPE_IPV6 0x04
56 #define VMXNET3_RSS_HASH_TYPE_TCP_IPV6 0x08
58 #define VMXNET3_RSS_HASH_FUNC_NONE 0x0
59 #define VMXNET3_RSS_HASH_FUNC_TOEPLITZ 0x01
61 #define VMXNET3_RSS_MAX_KEY_SIZE 40
62 #define VMXNET3_RSS_MAX_IND_TABLE_SIZE 128
64 /* RSS configuration structure - shared with device through GPA */
66 struct VMXNET3_RSSConf {
70 uint16_t indTableSize;
71 uint8_t hashKey[VMXNET3_RSS_MAX_KEY_SIZE];
73 * indTable is only element that can be changed without
74 * device quiesce-reset-update-activation cycle
76 uint8_t indTable[VMXNET3_RSS_MAX_IND_TABLE_SIZE];
80 struct vmxnet3_mf_table {
81 void *mfTableBase; /* Multicast addresses list */
82 uint64_t mfTablePA; /* Physical address of the list */
83 uint16_t num_addrs; /* number of multicast addrs */
88 uint8_t *hw_addr0; /* BAR0: PT-Passthrough Regs */
89 uint8_t *hw_addr1; /* BAR1: VD-Virtual Device Regs */
90 /* BAR2: MSI-X Regs */
96 uint16_t subsystem_device_id;
97 uint16_t subsystem_vendor_id;
100 uint8_t perm_addr[ETHER_ADDR_LEN];
101 uint8_t num_tx_queues;
102 uint8_t num_rx_queues;
103 uint8_t bufs_per_pkt;
106 Vmxnet3_TxQueueDesc *tqd_start; /* start address of all tx queue desc */
107 Vmxnet3_RxQueueDesc *rqd_start; /* start address of all rx queue desc */
109 Vmxnet3_DriverShared *shared;
112 uint64_t queueDescPA;
113 uint16_t queue_desc_len;
115 VMXNET3_RSSConf *rss_conf;
117 vmxnet3_mf_table_t *mf_table;
120 #define VMXNET3_GET_ADDR_LO(reg) ((uint32_t)(reg))
121 #define VMXNET3_GET_ADDR_HI(reg) ((uint32_t)(((uint64_t)(reg)) >> 32))
123 /* Config space read/writes */
125 #define VMXNET3_PCI_REG(reg) (*((volatile uint32_t *)(reg)))
127 static inline uint32_t vmxnet3_read_addr(volatile void *addr)
129 return VMXNET3_PCI_REG(addr);
132 #define VMXNET3_PCI_REG_WRITE(reg, value) do { \
133 VMXNET3_PCI_REG((reg)) = (value); \
136 #define VMXNET3_PCI_BAR0_REG_ADDR(hw, reg) \
137 ((volatile uint32_t *)((char *)(hw)->hw_addr0 + (reg)))
138 #define VMXNET3_READ_BAR0_REG(hw, reg) \
139 vmxnet3_read_addr(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)))
140 #define VMXNET3_WRITE_BAR0_REG(hw, reg, value) \
141 VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)), (value))
143 #define VMXNET3_PCI_BAR1_REG_ADDR(hw, reg) \
144 ((volatile uint32_t *)((char *)(hw)->hw_addr1 + (reg)))
145 #define VMXNET3_READ_BAR1_REG(hw, reg) \
146 vmxnet3_read_addr(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)))
147 #define VMXNET3_WRITE_BAR1_REG(hw, reg, value) \
148 VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)), (value))
151 * RX/TX function prototypes
154 void vmxnet3_dev_clear_queues(struct rte_eth_dev *dev);
156 void vmxnet3_dev_rx_queue_release(void *rxq);
157 void vmxnet3_dev_tx_queue_release(void *txq);
159 int vmxnet3_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
160 uint16_t nb_rx_desc, unsigned int socket_id,
161 const struct rte_eth_rxconf *rx_conf,
162 struct rte_mempool *mb_pool);
163 int vmxnet3_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
164 uint16_t nb_tx_desc, unsigned int socket_id,
165 const struct rte_eth_txconf *tx_conf);
167 int vmxnet3_dev_rxtx_init(struct rte_eth_dev *dev);
169 int vmxnet3_rss_configure(struct rte_eth_dev *dev);
170 int vmxnet3_vlan_configure(struct rte_eth_dev *dev);
172 uint16_t vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
174 uint16_t vmxnet3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
177 #endif /* _VMXNET3_ETHDEV_H_ */