4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <rte_common.h>
39 #include <rte_memory.h>
40 #include <rte_malloc.h>
41 #include <rte_cycles.h>
42 #include <rte_prefetch.h>
43 #include <rte_branch_prediction.h>
46 #include "rte_sched.h"
47 #include "rte_bitmap.h"
48 #include "rte_sched_common.h"
49 #include "rte_approx.h"
51 #ifdef __INTEL_COMPILER
52 #pragma warning(disable:2259) /* conversion may lose significant bits */
55 #ifndef RTE_SCHED_OPTIMIZATIONS
56 #define RTE_SCHED_OPTIMIZATIONS 0
59 #if RTE_SCHED_OPTIMIZATIONS
60 #include <immintrin.h>
63 #ifndef RTE_SCHED_TB_RATE_CONFIG_ERR
64 #define RTE_SCHED_TB_RATE_CONFIG_ERR (1e-7)
67 #ifndef RTE_SCHED_WRR_SHIFT
68 #define RTE_SCHED_WRR_SHIFT 3
71 #ifndef RTE_SCHED_PORT_N_GRINDERS
72 #define RTE_SCHED_PORT_N_GRINDERS 8
74 #if (RTE_SCHED_PORT_N_GRINDERS == 0) || (RTE_SCHED_PORT_N_GRINDERS & (RTE_SCHED_PORT_N_GRINDERS - 1))
75 #error Number of grinders must be non-zero and a power of 2
77 #if (RTE_SCHED_OPTIMIZATIONS && (RTE_SCHED_PORT_N_GRINDERS != 8))
78 #error Number of grinders must be 8 when RTE_SCHED_OPTIMIZATIONS is set
81 #define RTE_SCHED_GRINDER_PCACHE_SIZE (64 / RTE_SCHED_QUEUES_PER_PIPE)
83 #define RTE_SCHED_PIPE_INVALID UINT32_MAX
85 #define RTE_SCHED_BMP_POS_INVALID UINT32_MAX
87 struct rte_sched_subport {
88 /* Token bucket (TB) */
89 uint64_t tb_time; /* time of last update */
91 uint32_t tb_credits_per_period;
95 /* Traffic classes (TCs) */
96 uint64_t tc_time; /* time of next update */
97 uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
98 uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
101 /* TC oversubscription */
103 uint32_t tc_ov_wm_min;
104 uint32_t tc_ov_wm_max;
105 uint8_t tc_ov_period_id;
111 struct rte_sched_subport_stats stats;
114 struct rte_sched_pipe_profile {
115 /* Token bucket (TB) */
117 uint32_t tb_credits_per_period;
120 /* Pipe traffic classes */
122 uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
123 uint8_t tc_ov_weight;
126 uint8_t wrr_cost[RTE_SCHED_QUEUES_PER_PIPE];
129 struct rte_sched_pipe {
130 /* Token bucket (TB) */
131 uint64_t tb_time; /* time of last update */
134 /* Pipe profile and flags */
137 /* Traffic classes (TCs) */
138 uint64_t tc_time; /* time of next update */
139 uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
141 /* Weighted Round Robin (WRR) */
142 uint8_t wrr_tokens[RTE_SCHED_QUEUES_PER_PIPE];
144 /* TC oversubscription */
145 uint32_t tc_ov_credits;
146 uint8_t tc_ov_period_id;
148 } __rte_cache_aligned;
150 struct rte_sched_queue {
155 struct rte_sched_queue_extra {
156 struct rte_sched_queue_stats stats;
163 e_GRINDER_PREFETCH_PIPE = 0,
164 e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS,
165 e_GRINDER_PREFETCH_MBUF,
170 * Path through the scheduler hierarchy used by the scheduler enqueue
171 * operation to identify the destination queue for the current
172 * packet. Stored in the field pkt.hash.sched of struct rte_mbuf of
173 * each packet, typically written by the classification stage and read
174 * by scheduler enqueue.
176 struct rte_sched_port_hierarchy {
177 uint32_t queue:2; /**< Queue ID (0 .. 3) */
178 uint32_t traffic_class:2; /**< Traffic class ID (0 .. 3)*/
179 uint32_t pipe:20; /**< Pipe ID */
180 uint32_t subport:6; /**< Subport ID */
181 uint32_t color:2; /**< Color */
184 struct rte_sched_grinder {
186 uint16_t pcache_qmask[RTE_SCHED_GRINDER_PCACHE_SIZE];
187 uint32_t pcache_qindex[RTE_SCHED_GRINDER_PCACHE_SIZE];
192 enum grinder_state state;
195 struct rte_sched_subport *subport;
196 struct rte_sched_pipe *pipe;
197 struct rte_sched_pipe_profile *pipe_params;
200 uint8_t tccache_qmask[4];
201 uint32_t tccache_qindex[4];
207 struct rte_sched_queue *queue[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
208 struct rte_mbuf **qbase[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
209 uint32_t qindex[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
213 struct rte_mbuf *pkt;
216 uint16_t wrr_tokens[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
217 uint16_t wrr_mask[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
218 uint8_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
221 struct rte_sched_port {
222 /* User parameters */
223 uint32_t n_subports_per_port;
224 uint32_t n_pipes_per_subport;
227 uint32_t frame_overhead;
228 uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
229 uint32_t n_pipe_profiles;
230 uint32_t pipe_tc3_rate_max;
232 struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][e_RTE_METER_COLORS];
236 uint64_t time_cpu_cycles; /* Current CPU time measured in CPU cyles */
237 uint64_t time_cpu_bytes; /* Current CPU time measured in bytes */
238 uint64_t time; /* Current NIC TX time measured in bytes */
239 double cycles_per_byte; /* CPU cycles per byte */
241 /* Scheduling loop detection */
243 uint32_t pipe_exhaustion;
246 struct rte_bitmap *bmp;
247 uint32_t grinder_base_bmp_pos[RTE_SCHED_PORT_N_GRINDERS] __rte_aligned_16;
250 struct rte_sched_grinder grinder[RTE_SCHED_PORT_N_GRINDERS];
251 uint32_t busy_grinders;
252 struct rte_mbuf **pkts_out;
255 /* Queue base calculation */
256 uint32_t qsize_add[RTE_SCHED_QUEUES_PER_PIPE];
259 /* Large data structures */
260 struct rte_sched_subport *subport;
261 struct rte_sched_pipe *pipe;
262 struct rte_sched_queue *queue;
263 struct rte_sched_queue_extra *queue_extra;
264 struct rte_sched_pipe_profile *pipe_profiles;
266 struct rte_mbuf **queue_array;
267 uint8_t memory[0] __rte_cache_aligned;
268 } __rte_cache_aligned;
270 enum rte_sched_port_array {
271 e_RTE_SCHED_PORT_ARRAY_SUBPORT = 0,
272 e_RTE_SCHED_PORT_ARRAY_PIPE,
273 e_RTE_SCHED_PORT_ARRAY_QUEUE,
274 e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA,
275 e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES,
276 e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY,
277 e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY,
278 e_RTE_SCHED_PORT_ARRAY_TOTAL,
281 #ifdef RTE_SCHED_COLLECT_STATS
283 static inline uint32_t
284 rte_sched_port_queues_per_subport(struct rte_sched_port *port)
286 return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport;
291 static inline uint32_t
292 rte_sched_port_queues_per_port(struct rte_sched_port *port)
294 return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport * port->n_subports_per_port;
298 rte_sched_port_check_params(struct rte_sched_port_params *params)
302 if (params == NULL) {
307 if ((params->socket < 0) || (params->socket >= RTE_MAX_NUMA_NODES)) {
312 if (params->rate == 0) {
317 if (params->mtu == 0) {
321 /* n_subports_per_port: non-zero, power of 2 */
322 if ((params->n_subports_per_port == 0) || (!rte_is_power_of_2(params->n_subports_per_port))) {
326 /* n_pipes_per_subport: non-zero, power of 2 */
327 if ((params->n_pipes_per_subport == 0) || (!rte_is_power_of_2(params->n_pipes_per_subport))) {
331 /* qsize: non-zero, power of 2,
332 * no bigger than 32K (due to 16-bit read/write pointers) */
333 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
334 uint16_t qsize = params->qsize[i];
336 if ((qsize == 0) || (!rte_is_power_of_2(qsize))) {
341 /* pipe_profiles and n_pipe_profiles */
342 if ((params->pipe_profiles == NULL) ||
343 (params->n_pipe_profiles == 0) ||
344 (params->n_pipe_profiles > RTE_SCHED_PIPE_PROFILES_PER_PORT)) {
348 for (i = 0; i < params->n_pipe_profiles; i ++) {
349 struct rte_sched_pipe_params *p = params->pipe_profiles + i;
351 /* TB rate: non-zero, not greater than port rate */
352 if ((p->tb_rate == 0) || (p->tb_rate > params->rate)) {
356 /* TB size: non-zero */
357 if (p->tb_size == 0) {
361 /* TC rate: non-zero, less than pipe rate */
362 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
363 if ((p->tc_rate[j] == 0) || (p->tc_rate[j] > p->tb_rate)) {
368 /* TC period: non-zero */
369 if (p->tc_period == 0) {
373 #ifdef RTE_SCHED_SUBPORT_TC_OV
374 /* TC3 oversubscription weight: non-zero */
375 if (p->tc_ov_weight == 0) {
380 /* Queue WRR weights: non-zero */
381 for (j = 0; j < RTE_SCHED_QUEUES_PER_PIPE; j ++) {
382 if (p->wrr_weights[j] == 0) {
392 rte_sched_port_get_array_base(struct rte_sched_port_params *params, enum rte_sched_port_array array)
394 uint32_t n_subports_per_port = params->n_subports_per_port;
395 uint32_t n_pipes_per_subport = params->n_pipes_per_subport;
396 uint32_t n_pipes_per_port = n_pipes_per_subport * n_subports_per_port;
397 uint32_t n_queues_per_port = RTE_SCHED_QUEUES_PER_PIPE * n_pipes_per_subport * n_subports_per_port;
399 uint32_t size_subport = n_subports_per_port * sizeof(struct rte_sched_subport);
400 uint32_t size_pipe = n_pipes_per_port * sizeof(struct rte_sched_pipe);
401 uint32_t size_queue = n_queues_per_port * sizeof(struct rte_sched_queue);
402 uint32_t size_queue_extra = n_queues_per_port * sizeof(struct rte_sched_queue_extra);
403 uint32_t size_pipe_profiles = RTE_SCHED_PIPE_PROFILES_PER_PORT * sizeof(struct rte_sched_pipe_profile);
404 uint32_t size_bmp_array = rte_bitmap_get_memory_footprint(n_queues_per_port);
405 uint32_t size_per_pipe_queue_array, size_queue_array;
409 size_per_pipe_queue_array = 0;
410 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
411 size_per_pipe_queue_array += RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS * params->qsize[i] * sizeof(struct rte_mbuf *);
413 size_queue_array = n_pipes_per_port * size_per_pipe_queue_array;
417 if (array == e_RTE_SCHED_PORT_ARRAY_SUBPORT) return base;
418 base += RTE_CACHE_LINE_ROUNDUP(size_subport);
420 if (array == e_RTE_SCHED_PORT_ARRAY_PIPE) return base;
421 base += RTE_CACHE_LINE_ROUNDUP(size_pipe);
423 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE) return base;
424 base += RTE_CACHE_LINE_ROUNDUP(size_queue);
426 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA) return base;
427 base += RTE_CACHE_LINE_ROUNDUP(size_queue_extra);
429 if (array == e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES) return base;
430 base += RTE_CACHE_LINE_ROUNDUP(size_pipe_profiles);
432 if (array == e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY) return base;
433 base += RTE_CACHE_LINE_ROUNDUP(size_bmp_array);
435 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY) return base;
436 base += RTE_CACHE_LINE_ROUNDUP(size_queue_array);
442 rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)
444 uint32_t size0, size1;
447 status = rte_sched_port_check_params(params);
449 RTE_LOG(NOTICE, SCHED,
450 "Port scheduler params check failed (%d)\n", status);
455 size0 = sizeof(struct rte_sched_port);
456 size1 = rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_TOTAL);
458 return (size0 + size1);
462 rte_sched_port_config_qsize(struct rte_sched_port *port)
465 port->qsize_add[0] = 0;
466 port->qsize_add[1] = port->qsize_add[0] + port->qsize[0];
467 port->qsize_add[2] = port->qsize_add[1] + port->qsize[0];
468 port->qsize_add[3] = port->qsize_add[2] + port->qsize[0];
471 port->qsize_add[4] = port->qsize_add[3] + port->qsize[0];
472 port->qsize_add[5] = port->qsize_add[4] + port->qsize[1];
473 port->qsize_add[6] = port->qsize_add[5] + port->qsize[1];
474 port->qsize_add[7] = port->qsize_add[6] + port->qsize[1];
477 port->qsize_add[8] = port->qsize_add[7] + port->qsize[1];
478 port->qsize_add[9] = port->qsize_add[8] + port->qsize[2];
479 port->qsize_add[10] = port->qsize_add[9] + port->qsize[2];
480 port->qsize_add[11] = port->qsize_add[10] + port->qsize[2];
483 port->qsize_add[12] = port->qsize_add[11] + port->qsize[2];
484 port->qsize_add[13] = port->qsize_add[12] + port->qsize[3];
485 port->qsize_add[14] = port->qsize_add[13] + port->qsize[3];
486 port->qsize_add[15] = port->qsize_add[14] + port->qsize[3];
488 port->qsize_sum = port->qsize_add[15] + port->qsize[3];
492 rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)
494 struct rte_sched_pipe_profile *p = port->pipe_profiles + i;
496 RTE_LOG(DEBUG, SCHED, "Low level config for pipe profile %u:\n"
497 " Token bucket: period = %u, credits per period = %u, size = %u\n"
498 " Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\n"
499 " Traffic class 3 oversubscription: weight = %hhu\n"
500 " WRR cost: [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu]\n",
505 p->tb_credits_per_period,
508 /* Traffic classes */
510 p->tc_credits_per_period[0],
511 p->tc_credits_per_period[1],
512 p->tc_credits_per_period[2],
513 p->tc_credits_per_period[3],
515 /* Traffic class 3 oversubscription */
519 p->wrr_cost[ 0], p->wrr_cost[ 1], p->wrr_cost[ 2], p->wrr_cost[ 3],
520 p->wrr_cost[ 4], p->wrr_cost[ 5], p->wrr_cost[ 6], p->wrr_cost[ 7],
521 p->wrr_cost[ 8], p->wrr_cost[ 9], p->wrr_cost[10], p->wrr_cost[11],
522 p->wrr_cost[12], p->wrr_cost[13], p->wrr_cost[14], p->wrr_cost[15]);
525 static inline uint64_t
526 rte_sched_time_ms_to_bytes(uint32_t time_ms, uint32_t rate)
528 uint64_t time = time_ms;
529 time = (time * rate) / 1000;
535 rte_sched_port_config_pipe_profile_table(struct rte_sched_port *port, struct rte_sched_port_params *params)
539 for (i = 0; i < port->n_pipe_profiles; i ++) {
540 struct rte_sched_pipe_params *src = params->pipe_profiles + i;
541 struct rte_sched_pipe_profile *dst = port->pipe_profiles + i;
544 if (src->tb_rate == params->rate) {
545 dst->tb_credits_per_period = 1;
548 double tb_rate = ((double) src->tb_rate) / ((double) params->rate);
549 double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
551 rte_approx(tb_rate, d, &dst->tb_credits_per_period, &dst->tb_period);
553 dst->tb_size = src->tb_size;
555 /* Traffic Classes */
556 dst->tc_period = (uint32_t) rte_sched_time_ms_to_bytes(src->tc_period, params->rate);
557 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
558 dst->tc_credits_per_period[j] = (uint32_t) rte_sched_time_ms_to_bytes(src->tc_period, src->tc_rate[j]);
560 #ifdef RTE_SCHED_SUBPORT_TC_OV
561 dst->tc_ov_weight = src->tc_ov_weight;
565 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
566 uint32_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
567 uint32_t lcd, lcd1, lcd2;
570 qindex = j * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS;
572 wrr_cost[0] = src->wrr_weights[qindex];
573 wrr_cost[1] = src->wrr_weights[qindex + 1];
574 wrr_cost[2] = src->wrr_weights[qindex + 2];
575 wrr_cost[3] = src->wrr_weights[qindex + 3];
577 lcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]);
578 lcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]);
579 lcd = rte_get_lcd(lcd1, lcd2);
581 wrr_cost[0] = lcd / wrr_cost[0];
582 wrr_cost[1] = lcd / wrr_cost[1];
583 wrr_cost[2] = lcd / wrr_cost[2];
584 wrr_cost[3] = lcd / wrr_cost[3];
586 dst->wrr_cost[qindex] = (uint8_t) wrr_cost[0];
587 dst->wrr_cost[qindex + 1] = (uint8_t) wrr_cost[1];
588 dst->wrr_cost[qindex + 2] = (uint8_t) wrr_cost[2];
589 dst->wrr_cost[qindex + 3] = (uint8_t) wrr_cost[3];
592 rte_sched_port_log_pipe_profile(port, i);
595 port->pipe_tc3_rate_max = 0;
596 for (i = 0; i < port->n_pipe_profiles; i ++) {
597 struct rte_sched_pipe_params *src = params->pipe_profiles + i;
598 uint32_t pipe_tc3_rate = src->tc_rate[3];
600 if (port->pipe_tc3_rate_max < pipe_tc3_rate) {
601 port->pipe_tc3_rate_max = pipe_tc3_rate;
606 struct rte_sched_port *
607 rte_sched_port_config(struct rte_sched_port_params *params)
609 struct rte_sched_port *port = NULL;
610 uint32_t mem_size, bmp_mem_size, n_queues_per_port, i;
612 /* Check user parameters. Determine the amount of memory to allocate */
613 mem_size = rte_sched_port_get_memory_footprint(params);
618 /* Allocate memory to store the data structures */
619 port = rte_zmalloc("qos_params", mem_size, RTE_CACHE_LINE_SIZE);
624 /* User parameters */
625 port->n_subports_per_port = params->n_subports_per_port;
626 port->n_pipes_per_subport = params->n_pipes_per_subport;
627 port->rate = params->rate;
628 port->mtu = params->mtu + params->frame_overhead;
629 port->frame_overhead = params->frame_overhead;
630 memcpy(port->qsize, params->qsize, sizeof(params->qsize));
631 port->n_pipe_profiles = params->n_pipe_profiles;
634 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
637 for (j = 0; j < e_RTE_METER_COLORS; j++) {
638 /* if min/max are both zero, then RED is disabled */
639 if ((params->red_params[i][j].min_th |
640 params->red_params[i][j].max_th) == 0) {
644 if (rte_red_config_init(&port->red_config[i][j],
645 params->red_params[i][j].wq_log2,
646 params->red_params[i][j].min_th,
647 params->red_params[i][j].max_th,
648 params->red_params[i][j].maxp_inv) != 0) {
656 port->time_cpu_cycles = rte_get_tsc_cycles();
657 port->time_cpu_bytes = 0;
659 port->cycles_per_byte = ((double) rte_get_tsc_hz()) / ((double) params->rate);
661 /* Scheduling loop detection */
662 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
663 port->pipe_exhaustion = 0;
666 port->busy_grinders = 0;
667 port->pkts_out = NULL;
668 port->n_pkts_out = 0;
670 /* Queue base calculation */
671 rte_sched_port_config_qsize(port);
673 /* Large data structures */
674 port->subport = (struct rte_sched_subport *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_SUBPORT));
675 port->pipe = (struct rte_sched_pipe *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_PIPE));
676 port->queue = (struct rte_sched_queue *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE));
677 port->queue_extra = (struct rte_sched_queue_extra *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA));
678 port->pipe_profiles = (struct rte_sched_pipe_profile *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES));
679 port->bmp_array = port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY);
680 port->queue_array = (struct rte_mbuf **) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY));
682 /* Pipe profile table */
683 rte_sched_port_config_pipe_profile_table(port, params);
686 n_queues_per_port = rte_sched_port_queues_per_port(port);
687 bmp_mem_size = rte_bitmap_get_memory_footprint(n_queues_per_port);
688 port->bmp = rte_bitmap_init(n_queues_per_port, port->bmp_array, bmp_mem_size);
689 if (port->bmp == NULL) {
690 RTE_LOG(ERR, SCHED, "Bitmap init error\n");
693 for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i ++) {
694 port->grinder_base_bmp_pos[i] = RTE_SCHED_PIPE_INVALID;
701 rte_sched_port_free(struct rte_sched_port *port)
703 /* Check user parameters */
708 rte_bitmap_free(port->bmp);
713 rte_sched_port_log_subport_config(struct rte_sched_port *port, uint32_t i)
715 struct rte_sched_subport *s = port->subport + i;
717 RTE_LOG(DEBUG, SCHED, "Low level config for subport %u:\n"
718 " Token bucket: period = %u, credits per period = %u, size = %u\n"
719 " Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\n"
720 " Traffic class 3 oversubscription: wm min = %u, wm max = %u\n",
725 s->tb_credits_per_period,
728 /* Traffic classes */
730 s->tc_credits_per_period[0],
731 s->tc_credits_per_period[1],
732 s->tc_credits_per_period[2],
733 s->tc_credits_per_period[3],
735 /* Traffic class 3 oversubscription */
741 rte_sched_subport_config(struct rte_sched_port *port,
743 struct rte_sched_subport_params *params)
745 struct rte_sched_subport *s;
748 /* Check user parameters */
749 if ((port == NULL) ||
750 (subport_id >= port->n_subports_per_port) ||
755 if ((params->tb_rate == 0) || (params->tb_rate > port->rate)) {
759 if (params->tb_size == 0) {
763 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
764 if ((params->tc_rate[i] == 0) || (params->tc_rate[i] > params->tb_rate)) {
769 if (params->tc_period == 0) {
773 s = port->subport + subport_id;
775 /* Token Bucket (TB) */
776 if (params->tb_rate == port->rate) {
777 s->tb_credits_per_period = 1;
780 double tb_rate = ((double) params->tb_rate) / ((double) port->rate);
781 double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
783 rte_approx(tb_rate, d, &s->tb_credits_per_period, &s->tb_period);
785 s->tb_size = params->tb_size;
786 s->tb_time = port->time;
787 s->tb_credits = s->tb_size / 2;
789 /* Traffic Classes (TCs) */
790 s->tc_period = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, port->rate);
791 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
792 s->tc_credits_per_period[i] = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, params->tc_rate[i]);
794 s->tc_time = port->time + s->tc_period;
795 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
796 s->tc_credits[i] = s->tc_credits_per_period[i];
799 #ifdef RTE_SCHED_SUBPORT_TC_OV
800 /* TC oversubscription */
801 s->tc_ov_wm_min = port->mtu;
802 s->tc_ov_wm_max = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, port->pipe_tc3_rate_max);
803 s->tc_ov_wm = s->tc_ov_wm_max;
804 s->tc_ov_period_id = 0;
810 rte_sched_port_log_subport_config(port, subport_id);
816 rte_sched_pipe_config(struct rte_sched_port *port,
819 int32_t pipe_profile)
821 struct rte_sched_subport *s;
822 struct rte_sched_pipe *p;
823 struct rte_sched_pipe_profile *params;
824 uint32_t deactivate, profile, i;
826 /* Check user parameters */
827 profile = (uint32_t) pipe_profile;
828 deactivate = (pipe_profile < 0);
829 if ((port == NULL) ||
830 (subport_id >= port->n_subports_per_port) ||
831 (pipe_id >= port->n_pipes_per_subport) ||
832 ((!deactivate) && (profile >= port->n_pipe_profiles))) {
836 /* Check that subport configuration is valid */
837 s = port->subport + subport_id;
838 if (s->tb_period == 0) {
842 p = port->pipe + (subport_id * port->n_pipes_per_subport + pipe_id);
844 /* Handle the case when pipe already has a valid configuration */
846 params = port->pipe_profiles + p->profile;
848 #ifdef RTE_SCHED_SUBPORT_TC_OV
849 double subport_tc3_rate = ((double) s->tc_credits_per_period[3]) / ((double) s->tc_period);
850 double pipe_tc3_rate = ((double) params->tc_credits_per_period[3]) / ((double) params->tc_period);
851 uint32_t tc3_ov = s->tc_ov;
853 /* Unplug pipe from its subport */
854 s->tc_ov_n -= params->tc_ov_weight;
855 s->tc_ov_rate -= pipe_tc3_rate;
856 s->tc_ov = s->tc_ov_rate > subport_tc3_rate;
858 if (s->tc_ov != tc3_ov) {
859 RTE_LOG(DEBUG, SCHED,
860 "Subport %u TC3 oversubscription is OFF (%.4lf >= %.4lf)\n",
861 subport_id, subport_tc3_rate, s->tc_ov_rate);
866 memset(p, 0, sizeof(struct rte_sched_pipe));
873 /* Apply the new pipe configuration */
874 p->profile = profile;
875 params = port->pipe_profiles + p->profile;
877 /* Token Bucket (TB) */
878 p->tb_time = port->time;
879 p->tb_credits = params->tb_size / 2;
881 /* Traffic Classes (TCs) */
882 p->tc_time = port->time + params->tc_period;
883 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
884 p->tc_credits[i] = params->tc_credits_per_period[i];
887 #ifdef RTE_SCHED_SUBPORT_TC_OV
889 /* Subport TC3 oversubscription */
890 double subport_tc3_rate = ((double) s->tc_credits_per_period[3]) / ((double) s->tc_period);
891 double pipe_tc3_rate = ((double) params->tc_credits_per_period[3]) / ((double) params->tc_period);
892 uint32_t tc3_ov = s->tc_ov;
894 s->tc_ov_n += params->tc_ov_weight;
895 s->tc_ov_rate += pipe_tc3_rate;
896 s->tc_ov = s->tc_ov_rate > subport_tc3_rate;
898 if (s->tc_ov != tc3_ov) {
899 RTE_LOG(DEBUG, SCHED,
900 "Subport %u TC3 oversubscription is ON (%.4lf < %.4lf)\n",
901 subport_id, subport_tc3_rate, s->tc_ov_rate);
903 p->tc_ov_period_id = s->tc_ov_period_id;
904 p->tc_ov_credits = s->tc_ov_wm;
912 rte_sched_port_pkt_write(struct rte_mbuf *pkt,
913 uint32_t subport, uint32_t pipe, uint32_t traffic_class,
914 uint32_t queue, enum rte_meter_color color)
916 struct rte_sched_port_hierarchy *sched
917 = (struct rte_sched_port_hierarchy *) &pkt->hash.sched;
919 sched->color = (uint32_t) color;
920 sched->subport = subport;
922 sched->traffic_class = traffic_class;
923 sched->queue = queue;
927 rte_sched_port_pkt_read_tree_path(const struct rte_mbuf *pkt,
928 uint32_t *subport, uint32_t *pipe,
929 uint32_t *traffic_class, uint32_t *queue)
931 const struct rte_sched_port_hierarchy *sched
932 = (const struct rte_sched_port_hierarchy *) &pkt->hash.sched;
934 *subport = sched->subport;
936 *traffic_class = sched->traffic_class;
937 *queue = sched->queue;
942 rte_sched_port_pkt_read_color(const struct rte_mbuf *pkt)
944 const struct rte_sched_port_hierarchy *sched
945 = (const struct rte_sched_port_hierarchy *) &pkt->hash.sched;
947 return (enum rte_meter_color) sched->color;
951 rte_sched_subport_read_stats(struct rte_sched_port *port,
953 struct rte_sched_subport_stats *stats,
956 struct rte_sched_subport *s;
958 /* Check user parameters */
959 if ((port == NULL) ||
960 (subport_id >= port->n_subports_per_port) ||
965 s = port->subport + subport_id;
967 /* Copy subport stats and clear */
968 memcpy(stats, &s->stats, sizeof(struct rte_sched_subport_stats));
969 memset(&s->stats, 0, sizeof(struct rte_sched_subport_stats));
971 /* Subport TC ovesubscription status */
978 rte_sched_queue_read_stats(struct rte_sched_port *port,
980 struct rte_sched_queue_stats *stats,
983 struct rte_sched_queue *q;
984 struct rte_sched_queue_extra *qe;
986 /* Check user parameters */
987 if ((port == NULL) ||
988 (queue_id >= rte_sched_port_queues_per_port(port)) ||
993 q = port->queue + queue_id;
994 qe = port->queue_extra + queue_id;
996 /* Copy queue stats and clear */
997 memcpy(stats, &qe->stats, sizeof(struct rte_sched_queue_stats));
998 memset(&qe->stats, 0, sizeof(struct rte_sched_queue_stats));
1001 *qlen = q->qw - q->qr;
1006 static inline uint32_t
1007 rte_sched_port_qindex(struct rte_sched_port *port, uint32_t subport, uint32_t pipe, uint32_t traffic_class, uint32_t queue)
1011 result = subport * port->n_pipes_per_subport + pipe;
1012 result = result * RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE + traffic_class;
1013 result = result * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS + queue;
1018 static inline struct rte_mbuf **
1019 rte_sched_port_qbase(struct rte_sched_port *port, uint32_t qindex)
1021 uint32_t pindex = qindex >> 4;
1022 uint32_t qpos = qindex & 0xF;
1024 return (port->queue_array + pindex * port->qsize_sum + port->qsize_add[qpos]);
1027 static inline uint16_t
1028 rte_sched_port_qsize(struct rte_sched_port *port, uint32_t qindex)
1030 uint32_t tc = (qindex >> 2) & 0x3;
1032 return port->qsize[tc];
1035 #ifdef RTE_SCHED_DEBUG
1038 rte_sched_port_queue_is_empty(struct rte_sched_port *port, uint32_t qindex)
1040 struct rte_sched_queue *queue = port->queue + qindex;
1042 return (queue->qr == queue->qw);
1046 rte_sched_port_queue_is_full(struct rte_sched_port *port, uint32_t qindex)
1048 struct rte_sched_queue *queue = port->queue + qindex;
1049 uint16_t qsize = rte_sched_port_qsize(port, qindex);
1050 uint16_t qlen = queue->qw - queue->qr;
1052 return (qlen >= qsize);
1055 #endif /* RTE_SCHED_DEBUG */
1057 #ifdef RTE_SCHED_COLLECT_STATS
1060 rte_sched_port_update_subport_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1062 struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1063 uint32_t tc_index = (qindex >> 2) & 0x3;
1064 uint32_t pkt_len = pkt->pkt_len;
1066 s->stats.n_pkts_tc[tc_index] += 1;
1067 s->stats.n_bytes_tc[tc_index] += pkt_len;
1071 rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1073 struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1074 uint32_t tc_index = (qindex >> 2) & 0x3;
1075 uint32_t pkt_len = pkt->pkt_len;
1077 s->stats.n_pkts_tc_dropped[tc_index] += 1;
1078 s->stats.n_bytes_tc_dropped[tc_index] += pkt_len;
1082 rte_sched_port_update_queue_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1084 struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1085 uint32_t pkt_len = pkt->pkt_len;
1087 qe->stats.n_pkts += 1;
1088 qe->stats.n_bytes += pkt_len;
1092 rte_sched_port_update_queue_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1094 struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1095 uint32_t pkt_len = pkt->pkt_len;
1097 qe->stats.n_pkts_dropped += 1;
1098 qe->stats.n_bytes_dropped += pkt_len;
1101 #endif /* RTE_SCHED_COLLECT_STATS */
1103 #ifdef RTE_SCHED_RED
1106 rte_sched_port_red_drop(struct rte_sched_port *port, struct rte_mbuf *pkt, uint32_t qindex, uint16_t qlen)
1108 struct rte_sched_queue_extra *qe;
1109 struct rte_red_config *red_cfg;
1110 struct rte_red *red;
1112 enum rte_meter_color color;
1114 tc_index = (qindex >> 2) & 0x3;
1115 color = rte_sched_port_pkt_read_color(pkt);
1116 red_cfg = &port->red_config[tc_index][color];
1118 if ((red_cfg->min_th | red_cfg->max_th) == 0)
1121 qe = port->queue_extra + qindex;
1124 return rte_red_enqueue(red_cfg, red, qlen, port->time);
1128 rte_sched_port_set_queue_empty_timestamp(struct rte_sched_port *port, uint32_t qindex)
1130 struct rte_sched_queue_extra *qe;
1131 struct rte_red *red;
1133 qe = port->queue_extra + qindex;
1136 rte_red_mark_queue_empty(red, port->time);
1141 #define rte_sched_port_red_drop(port, pkt, qindex, qlen) 0
1143 #define rte_sched_port_set_queue_empty_timestamp(port, qindex)
1145 #endif /* RTE_SCHED_RED */
1147 #ifdef RTE_SCHED_DEBUG
1150 debug_pipe_is_empty(struct rte_sched_port *port, uint32_t pindex)
1154 qindex = pindex << 4;
1156 for (i = 0; i < 16; i ++){
1157 uint32_t queue_empty = rte_sched_port_queue_is_empty(port, qindex + i);
1158 uint32_t bmp_bit_clear = (rte_bitmap_get(port->bmp, qindex + i) == 0);
1160 if (queue_empty != bmp_bit_clear){
1161 rte_panic("Queue status mismatch for queue %u of pipe %u\n", i, pindex);
1173 debug_check_queue_slab(struct rte_sched_port *port, uint32_t bmp_pos, uint64_t bmp_slab)
1179 rte_panic("Empty slab at position %u\n", bmp_pos);
1183 for (i = 0, mask = 1; i < 64; i ++, mask <<= 1) {
1184 if (mask & bmp_slab){
1185 if (rte_sched_port_queue_is_empty(port, bmp_pos + i)) {
1186 printf("Queue %u (slab offset %u) is empty\n", bmp_pos + i, i);
1193 rte_panic("Empty queues in slab 0x%" PRIx64 "starting at position %u\n",
1198 #endif /* RTE_SCHED_DEBUG */
1200 static inline uint32_t
1201 rte_sched_port_enqueue_qptrs_prefetch0(struct rte_sched_port *port, struct rte_mbuf *pkt)
1203 struct rte_sched_queue *q;
1204 #ifdef RTE_SCHED_COLLECT_STATS
1205 struct rte_sched_queue_extra *qe;
1207 uint32_t subport, pipe, traffic_class, queue, qindex;
1209 rte_sched_port_pkt_read_tree_path(pkt, &subport, &pipe, &traffic_class, &queue);
1211 qindex = rte_sched_port_qindex(port, subport, pipe, traffic_class, queue);
1212 q = port->queue + qindex;
1214 #ifdef RTE_SCHED_COLLECT_STATS
1215 qe = port->queue_extra + qindex;
1223 rte_sched_port_enqueue_qwa_prefetch0(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf **qbase)
1225 struct rte_sched_queue *q;
1226 struct rte_mbuf **q_qw;
1229 q = port->queue + qindex;
1230 qsize = rte_sched_port_qsize(port, qindex);
1231 q_qw = qbase + (q->qw & (qsize - 1));
1233 rte_prefetch0(q_qw);
1234 rte_bitmap_prefetch0(port->bmp, qindex);
1238 rte_sched_port_enqueue_qwa(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf **qbase, struct rte_mbuf *pkt)
1240 struct rte_sched_queue *q;
1244 q = port->queue + qindex;
1245 qsize = rte_sched_port_qsize(port, qindex);
1246 qlen = q->qw - q->qr;
1248 /* Drop the packet (and update drop stats) when queue is full */
1249 if (unlikely(rte_sched_port_red_drop(port, pkt, qindex, qlen) || (qlen >= qsize))) {
1250 rte_pktmbuf_free(pkt);
1251 #ifdef RTE_SCHED_COLLECT_STATS
1252 rte_sched_port_update_subport_stats_on_drop(port, qindex, pkt);
1253 rte_sched_port_update_queue_stats_on_drop(port, qindex, pkt);
1258 /* Enqueue packet */
1259 qbase[q->qw & (qsize - 1)] = pkt;
1262 /* Activate queue in the port bitmap */
1263 rte_bitmap_set(port->bmp, qindex);
1266 #ifdef RTE_SCHED_COLLECT_STATS
1267 rte_sched_port_update_subport_stats(port, qindex, pkt);
1268 rte_sched_port_update_queue_stats(port, qindex, pkt);
1276 * The enqueue function implements a 4-level pipeline with each stage processing
1277 * two different packets. The purpose of using a pipeline is to hide the latency
1278 * of prefetching the data structures. The naming convention is presented in the
1281 * p00 _______ p10 _______ p20 _______ p30 _______
1282 * ----->| |----->| |----->| |----->| |----->
1283 * | 0 | | 1 | | 2 | | 3 |
1284 * ----->|_______|----->|_______|----->|_______|----->|_______|----->
1289 rte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
1291 struct rte_mbuf *pkt00, *pkt01, *pkt10, *pkt11, *pkt20, *pkt21, *pkt30, *pkt31, *pkt_last;
1292 struct rte_mbuf **q00_base, **q01_base, **q10_base, **q11_base, **q20_base, **q21_base, **q30_base, **q31_base, **q_last_base;
1293 uint32_t q00, q01, q10, q11, q20, q21, q30, q31, q_last;
1294 uint32_t r00, r01, r10, r11, r20, r21, r30, r31, r_last;
1299 /* Less then 6 input packets available, which is not enough to feed the pipeline */
1300 if (unlikely(n_pkts < 6)) {
1301 struct rte_mbuf **q_base[5];
1304 /* Prefetch the mbuf structure of each packet */
1305 for (i = 0; i < n_pkts; i ++) {
1306 rte_prefetch0(pkts[i]);
1309 /* Prefetch the queue structure for each queue */
1310 for (i = 0; i < n_pkts; i ++) {
1311 q[i] = rte_sched_port_enqueue_qptrs_prefetch0(port, pkts[i]);
1314 /* Prefetch the write pointer location of each queue */
1315 for (i = 0; i < n_pkts; i ++) {
1316 q_base[i] = rte_sched_port_qbase(port, q[i]);
1317 rte_sched_port_enqueue_qwa_prefetch0(port, q[i], q_base[i]);
1320 /* Write each packet to its queue */
1321 for (i = 0; i < n_pkts; i ++) {
1322 result += rte_sched_port_enqueue_qwa(port, q[i], q_base[i], pkts[i]);
1328 /* Feed the first 3 stages of the pipeline (6 packets needed) */
1331 rte_prefetch0(pkt20);
1332 rte_prefetch0(pkt21);
1336 rte_prefetch0(pkt10);
1337 rte_prefetch0(pkt11);
1339 q20 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt20);
1340 q21 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt21);
1344 rte_prefetch0(pkt00);
1345 rte_prefetch0(pkt01);
1347 q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1348 q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1350 q20_base = rte_sched_port_qbase(port, q20);
1351 q21_base = rte_sched_port_qbase(port, q21);
1352 rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1353 rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1355 /* Run the pipeline */
1356 for (i = 6; i < (n_pkts & (~1)); i += 2) {
1357 /* Propagate stage inputs */
1368 q30_base = q20_base;
1369 q31_base = q21_base;
1371 /* Stage 0: Get packets in */
1373 pkt01 = pkts[i + 1];
1374 rte_prefetch0(pkt00);
1375 rte_prefetch0(pkt01);
1377 /* Stage 1: Prefetch queue structure storing queue pointers */
1378 q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1379 q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1381 /* Stage 2: Prefetch queue write location */
1382 q20_base = rte_sched_port_qbase(port, q20);
1383 q21_base = rte_sched_port_qbase(port, q21);
1384 rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1385 rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1387 /* Stage 3: Write packet to queue and activate queue */
1388 r30 = rte_sched_port_enqueue_qwa(port, q30, q30_base, pkt30);
1389 r31 = rte_sched_port_enqueue_qwa(port, q31, q31_base, pkt31);
1390 result += r30 + r31;
1393 /* Drain the pipeline (exactly 6 packets). Handle the last packet in the case
1394 of an odd number of input packets. */
1395 pkt_last = pkts[n_pkts - 1];
1396 rte_prefetch0(pkt_last);
1398 q00 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt00);
1399 q01 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt01);
1401 q10_base = rte_sched_port_qbase(port, q10);
1402 q11_base = rte_sched_port_qbase(port, q11);
1403 rte_sched_port_enqueue_qwa_prefetch0(port, q10, q10_base);
1404 rte_sched_port_enqueue_qwa_prefetch0(port, q11, q11_base);
1406 r20 = rte_sched_port_enqueue_qwa(port, q20, q20_base, pkt20);
1407 r21 = rte_sched_port_enqueue_qwa(port, q21, q21_base, pkt21);
1408 result += r20 + r21;
1410 q_last = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt_last);
1412 q00_base = rte_sched_port_qbase(port, q00);
1413 q01_base = rte_sched_port_qbase(port, q01);
1414 rte_sched_port_enqueue_qwa_prefetch0(port, q00, q00_base);
1415 rte_sched_port_enqueue_qwa_prefetch0(port, q01, q01_base);
1417 r10 = rte_sched_port_enqueue_qwa(port, q10, q10_base, pkt10);
1418 r11 = rte_sched_port_enqueue_qwa(port, q11, q11_base, pkt11);
1419 result += r10 + r11;
1421 q_last_base = rte_sched_port_qbase(port, q_last);
1422 rte_sched_port_enqueue_qwa_prefetch0(port, q_last, q_last_base);
1424 r00 = rte_sched_port_enqueue_qwa(port, q00, q00_base, pkt00);
1425 r01 = rte_sched_port_enqueue_qwa(port, q01, q01_base, pkt01);
1426 result += r00 + r01;
1429 r_last = rte_sched_port_enqueue_qwa(port, q_last, q_last_base, pkt_last);
1436 #ifndef RTE_SCHED_SUBPORT_TC_OV
1439 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1441 struct rte_sched_grinder *grinder = port->grinder + pos;
1442 struct rte_sched_subport *subport = grinder->subport;
1443 struct rte_sched_pipe *pipe = grinder->pipe;
1444 struct rte_sched_pipe_profile *params = grinder->pipe_params;
1448 n_periods = (port->time - subport->tb_time) / subport->tb_period;
1449 subport->tb_credits += n_periods * subport->tb_credits_per_period;
1450 subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1451 subport->tb_time += n_periods * subport->tb_period;
1454 n_periods = (port->time - pipe->tb_time) / params->tb_period;
1455 pipe->tb_credits += n_periods * params->tb_credits_per_period;
1456 pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1457 pipe->tb_time += n_periods * params->tb_period;
1460 if (unlikely(port->time >= subport->tc_time)) {
1461 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1462 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1463 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1464 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1465 subport->tc_time = port->time + subport->tc_period;
1469 if (unlikely(port->time >= pipe->tc_time)) {
1470 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1471 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1472 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1473 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1474 pipe->tc_time = port->time + params->tc_period;
1480 static inline uint32_t
1481 grinder_tc_ov_credits_update(struct rte_sched_port *port, uint32_t pos)
1483 struct rte_sched_grinder *grinder = port->grinder + pos;
1484 struct rte_sched_subport *subport = grinder->subport;
1485 uint32_t tc_ov_consumption[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
1486 uint32_t tc_ov_consumption_max;
1487 uint32_t tc_ov_wm = subport->tc_ov_wm;
1489 if (subport->tc_ov == 0) {
1490 return subport->tc_ov_wm_max;
1493 tc_ov_consumption[0] = subport->tc_credits_per_period[0] - subport->tc_credits[0];
1494 tc_ov_consumption[1] = subport->tc_credits_per_period[1] - subport->tc_credits[1];
1495 tc_ov_consumption[2] = subport->tc_credits_per_period[2] - subport->tc_credits[2];
1496 tc_ov_consumption[3] = subport->tc_credits_per_period[3] - subport->tc_credits[3];
1498 tc_ov_consumption_max = subport->tc_credits_per_period[3] -
1499 (tc_ov_consumption[0] + tc_ov_consumption[1] + tc_ov_consumption[2]);
1501 if (tc_ov_consumption[3] > (tc_ov_consumption_max - port->mtu)) {
1502 tc_ov_wm -= tc_ov_wm >> 7;
1503 if (tc_ov_wm < subport->tc_ov_wm_min) {
1504 tc_ov_wm = subport->tc_ov_wm_min;
1509 tc_ov_wm += (tc_ov_wm >> 7) + 1;
1510 if (tc_ov_wm > subport->tc_ov_wm_max) {
1511 tc_ov_wm = subport->tc_ov_wm_max;
1517 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1519 struct rte_sched_grinder *grinder = port->grinder + pos;
1520 struct rte_sched_subport *subport = grinder->subport;
1521 struct rte_sched_pipe *pipe = grinder->pipe;
1522 struct rte_sched_pipe_profile *params = grinder->pipe_params;
1526 n_periods = (port->time - subport->tb_time) / subport->tb_period;
1527 subport->tb_credits += n_periods * subport->tb_credits_per_period;
1528 subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1529 subport->tb_time += n_periods * subport->tb_period;
1532 n_periods = (port->time - pipe->tb_time) / params->tb_period;
1533 pipe->tb_credits += n_periods * params->tb_credits_per_period;
1534 pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1535 pipe->tb_time += n_periods * params->tb_period;
1538 if (unlikely(port->time >= subport->tc_time)) {
1539 subport->tc_ov_wm = grinder_tc_ov_credits_update(port, pos);
1541 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1542 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1543 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1544 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1546 subport->tc_time = port->time + subport->tc_period;
1547 subport->tc_ov_period_id ++;
1551 if (unlikely(port->time >= pipe->tc_time)) {
1552 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1553 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1554 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1555 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1556 pipe->tc_time = port->time + params->tc_period;
1559 /* Pipe TCs - Oversubscription */
1560 if (unlikely(pipe->tc_ov_period_id != subport->tc_ov_period_id)) {
1561 pipe->tc_ov_credits = subport->tc_ov_wm * params->tc_ov_weight;
1563 pipe->tc_ov_period_id = subport->tc_ov_period_id;
1567 #endif /* RTE_SCHED_TS_CREDITS_UPDATE, RTE_SCHED_SUBPORT_TC_OV */
1570 #ifndef RTE_SCHED_SUBPORT_TC_OV
1573 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1575 struct rte_sched_grinder *grinder = port->grinder + pos;
1576 struct rte_sched_subport *subport = grinder->subport;
1577 struct rte_sched_pipe *pipe = grinder->pipe;
1578 struct rte_mbuf *pkt = grinder->pkt;
1579 uint32_t tc_index = grinder->tc_index;
1580 uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1581 uint32_t subport_tb_credits = subport->tb_credits;
1582 uint32_t subport_tc_credits = subport->tc_credits[tc_index];
1583 uint32_t pipe_tb_credits = pipe->tb_credits;
1584 uint32_t pipe_tc_credits = pipe->tc_credits[tc_index];
1587 /* Check queue credits */
1588 enough_credits = (pkt_len <= subport_tb_credits) &&
1589 (pkt_len <= subport_tc_credits) &&
1590 (pkt_len <= pipe_tb_credits) &&
1591 (pkt_len <= pipe_tc_credits);
1593 if (!enough_credits) {
1597 /* Update port credits */
1598 subport->tb_credits -= pkt_len;
1599 subport->tc_credits[tc_index] -= pkt_len;
1600 pipe->tb_credits -= pkt_len;
1601 pipe->tc_credits[tc_index] -= pkt_len;
1609 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1611 struct rte_sched_grinder *grinder = port->grinder + pos;
1612 struct rte_sched_subport *subport = grinder->subport;
1613 struct rte_sched_pipe *pipe = grinder->pipe;
1614 struct rte_mbuf *pkt = grinder->pkt;
1615 uint32_t tc_index = grinder->tc_index;
1616 uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1617 uint32_t subport_tb_credits = subport->tb_credits;
1618 uint32_t subport_tc_credits = subport->tc_credits[tc_index];
1619 uint32_t pipe_tb_credits = pipe->tb_credits;
1620 uint32_t pipe_tc_credits = pipe->tc_credits[tc_index];
1621 uint32_t pipe_tc_ov_mask1[] = {UINT32_MAX, UINT32_MAX, UINT32_MAX, pipe->tc_ov_credits};
1622 uint32_t pipe_tc_ov_mask2[] = {0, 0, 0, UINT32_MAX};
1623 uint32_t pipe_tc_ov_credits = pipe_tc_ov_mask1[tc_index];
1626 /* Check pipe and subport credits */
1627 enough_credits = (pkt_len <= subport_tb_credits) &&
1628 (pkt_len <= subport_tc_credits) &&
1629 (pkt_len <= pipe_tb_credits) &&
1630 (pkt_len <= pipe_tc_credits) &&
1631 (pkt_len <= pipe_tc_ov_credits);
1633 if (!enough_credits) {
1637 /* Update pipe and subport credits */
1638 subport->tb_credits -= pkt_len;
1639 subport->tc_credits[tc_index] -= pkt_len;
1640 pipe->tb_credits -= pkt_len;
1641 pipe->tc_credits[tc_index] -= pkt_len;
1642 pipe->tc_ov_credits -= pipe_tc_ov_mask2[tc_index] & pkt_len;
1647 #endif /* RTE_SCHED_SUBPORT_TC_OV */
1651 grinder_schedule(struct rte_sched_port *port, uint32_t pos)
1653 struct rte_sched_grinder *grinder = port->grinder + pos;
1654 struct rte_sched_queue *queue = grinder->queue[grinder->qpos];
1655 struct rte_mbuf *pkt = grinder->pkt;
1656 uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1658 if (!grinder_credits_check(port, pos)) {
1662 /* Advance port time */
1663 port->time += pkt_len;
1666 port->pkts_out[port->n_pkts_out ++] = pkt;
1668 grinder->wrr_tokens[grinder->qpos] += pkt_len * grinder->wrr_cost[grinder->qpos];
1669 if (queue->qr == queue->qw) {
1670 uint32_t qindex = grinder->qindex[grinder->qpos];
1672 rte_bitmap_clear(port->bmp, qindex);
1673 grinder->qmask &= ~(1 << grinder->qpos);
1674 grinder->wrr_mask[grinder->qpos] = 0;
1675 rte_sched_port_set_queue_empty_timestamp(port, qindex);
1678 /* Reset pipe loop detection */
1679 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1680 grinder->productive = 1;
1685 #if RTE_SCHED_OPTIMIZATIONS
1688 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1690 __m128i index = _mm_set1_epi32 (base_pipe);
1691 __m128i pipes = _mm_load_si128((__m128i *)port->grinder_base_bmp_pos);
1692 __m128i res = _mm_cmpeq_epi32(pipes, index);
1693 pipes = _mm_load_si128((__m128i *)(port->grinder_base_bmp_pos + 4));
1694 pipes = _mm_cmpeq_epi32(pipes, index);
1695 res = _mm_or_si128(res, pipes);
1697 if (_mm_testz_si128(res, res))
1706 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1710 for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i ++) {
1711 if (port->grinder_base_bmp_pos[i] == base_pipe) {
1719 #endif /* RTE_SCHED_OPTIMIZATIONS */
1722 grinder_pcache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t bmp_pos, uint64_t bmp_slab)
1724 struct rte_sched_grinder *grinder = port->grinder + pos;
1727 grinder->pcache_w = 0;
1728 grinder->pcache_r = 0;
1730 w[0] = (uint16_t) bmp_slab;
1731 w[1] = (uint16_t) (bmp_slab >> 16);
1732 w[2] = (uint16_t) (bmp_slab >> 32);
1733 w[3] = (uint16_t) (bmp_slab >> 48);
1735 grinder->pcache_qmask[grinder->pcache_w] = w[0];
1736 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos;
1737 grinder->pcache_w += (w[0] != 0);
1739 grinder->pcache_qmask[grinder->pcache_w] = w[1];
1740 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 16;
1741 grinder->pcache_w += (w[1] != 0);
1743 grinder->pcache_qmask[grinder->pcache_w] = w[2];
1744 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 32;
1745 grinder->pcache_w += (w[2] != 0);
1747 grinder->pcache_qmask[grinder->pcache_w] = w[3];
1748 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 48;
1749 grinder->pcache_w += (w[3] != 0);
1753 grinder_tccache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t qindex, uint16_t qmask)
1755 struct rte_sched_grinder *grinder = port->grinder + pos;
1758 grinder->tccache_w = 0;
1759 grinder->tccache_r = 0;
1761 b[0] = (uint8_t) (qmask & 0xF);
1762 b[1] = (uint8_t) ((qmask >> 4) & 0xF);
1763 b[2] = (uint8_t) ((qmask >> 8) & 0xF);
1764 b[3] = (uint8_t) ((qmask >> 12) & 0xF);
1766 grinder->tccache_qmask[grinder->tccache_w] = b[0];
1767 grinder->tccache_qindex[grinder->tccache_w] = qindex;
1768 grinder->tccache_w += (b[0] != 0);
1770 grinder->tccache_qmask[grinder->tccache_w] = b[1];
1771 grinder->tccache_qindex[grinder->tccache_w] = qindex + 4;
1772 grinder->tccache_w += (b[1] != 0);
1774 grinder->tccache_qmask[grinder->tccache_w] = b[2];
1775 grinder->tccache_qindex[grinder->tccache_w] = qindex + 8;
1776 grinder->tccache_w += (b[2] != 0);
1778 grinder->tccache_qmask[grinder->tccache_w] = b[3];
1779 grinder->tccache_qindex[grinder->tccache_w] = qindex + 12;
1780 grinder->tccache_w += (b[3] != 0);
1784 grinder_next_tc(struct rte_sched_port *port, uint32_t pos)
1786 struct rte_sched_grinder *grinder = port->grinder + pos;
1787 struct rte_mbuf **qbase;
1791 if (grinder->tccache_r == grinder->tccache_w) {
1795 qindex = grinder->tccache_qindex[grinder->tccache_r];
1796 qbase = rte_sched_port_qbase(port, qindex);
1797 qsize = rte_sched_port_qsize(port, qindex);
1799 grinder->tc_index = (qindex >> 2) & 0x3;
1800 grinder->qmask = grinder->tccache_qmask[grinder->tccache_r];
1801 grinder->qsize = qsize;
1803 grinder->qindex[0] = qindex;
1804 grinder->qindex[1] = qindex + 1;
1805 grinder->qindex[2] = qindex + 2;
1806 grinder->qindex[3] = qindex + 3;
1808 grinder->queue[0] = port->queue + qindex;
1809 grinder->queue[1] = port->queue + qindex + 1;
1810 grinder->queue[2] = port->queue + qindex + 2;
1811 grinder->queue[3] = port->queue + qindex + 3;
1813 grinder->qbase[0] = qbase;
1814 grinder->qbase[1] = qbase + qsize;
1815 grinder->qbase[2] = qbase + 2 * qsize;
1816 grinder->qbase[3] = qbase + 3 * qsize;
1818 grinder->tccache_r ++;
1823 grinder_next_pipe(struct rte_sched_port *port, uint32_t pos)
1825 struct rte_sched_grinder *grinder = port->grinder + pos;
1826 uint32_t pipe_qindex;
1827 uint16_t pipe_qmask;
1829 if (grinder->pcache_r < grinder->pcache_w) {
1830 pipe_qmask = grinder->pcache_qmask[grinder->pcache_r];
1831 pipe_qindex = grinder->pcache_qindex[grinder->pcache_r];
1832 grinder->pcache_r ++;
1834 uint64_t bmp_slab = 0;
1835 uint32_t bmp_pos = 0;
1837 /* Get another non-empty pipe group */
1838 if (unlikely(rte_bitmap_scan(port->bmp, &bmp_pos, &bmp_slab) <= 0)) {
1842 #ifdef RTE_SCHED_DEBUG
1843 debug_check_queue_slab(port, bmp_pos, bmp_slab);
1846 /* Return if pipe group already in one of the other grinders */
1847 port->grinder_base_bmp_pos[pos] = RTE_SCHED_BMP_POS_INVALID;
1848 if (unlikely(grinder_pipe_exists(port, bmp_pos))) {
1851 port->grinder_base_bmp_pos[pos] = bmp_pos;
1853 /* Install new pipe group into grinder's pipe cache */
1854 grinder_pcache_populate(port, pos, bmp_pos, bmp_slab);
1856 pipe_qmask = grinder->pcache_qmask[0];
1857 pipe_qindex = grinder->pcache_qindex[0];
1858 grinder->pcache_r = 1;
1861 /* Install new pipe in the grinder */
1862 grinder->pindex = pipe_qindex >> 4;
1863 grinder->subport = port->subport + (grinder->pindex / port->n_pipes_per_subport);
1864 grinder->pipe = port->pipe + grinder->pindex;
1865 grinder->pipe_params = NULL; /* to be set after the pipe structure is prefetched */
1866 grinder->productive = 0;
1868 grinder_tccache_populate(port, pos, pipe_qindex, pipe_qmask);
1869 grinder_next_tc(port, pos);
1871 /* Check for pipe exhaustion */
1872 if (grinder->pindex == port->pipe_loop) {
1873 port->pipe_exhaustion = 1;
1874 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1882 grinder_wrr_load(struct rte_sched_port *port, uint32_t pos)
1884 struct rte_sched_grinder *grinder = port->grinder + pos;
1885 struct rte_sched_pipe *pipe = grinder->pipe;
1886 struct rte_sched_pipe_profile *pipe_params = grinder->pipe_params;
1887 uint32_t tc_index = grinder->tc_index;
1888 uint32_t qmask = grinder->qmask;
1891 qindex = tc_index * 4;
1893 grinder->wrr_tokens[0] = ((uint16_t) pipe->wrr_tokens[qindex]) << RTE_SCHED_WRR_SHIFT;
1894 grinder->wrr_tokens[1] = ((uint16_t) pipe->wrr_tokens[qindex + 1]) << RTE_SCHED_WRR_SHIFT;
1895 grinder->wrr_tokens[2] = ((uint16_t) pipe->wrr_tokens[qindex + 2]) << RTE_SCHED_WRR_SHIFT;
1896 grinder->wrr_tokens[3] = ((uint16_t) pipe->wrr_tokens[qindex + 3]) << RTE_SCHED_WRR_SHIFT;
1898 grinder->wrr_mask[0] = (qmask & 0x1) * 0xFFFF;
1899 grinder->wrr_mask[1] = ((qmask >> 1) & 0x1) * 0xFFFF;
1900 grinder->wrr_mask[2] = ((qmask >> 2) & 0x1) * 0xFFFF;
1901 grinder->wrr_mask[3] = ((qmask >> 3) & 0x1) * 0xFFFF;
1903 grinder->wrr_cost[0] = pipe_params->wrr_cost[qindex];
1904 grinder->wrr_cost[1] = pipe_params->wrr_cost[qindex + 1];
1905 grinder->wrr_cost[2] = pipe_params->wrr_cost[qindex + 2];
1906 grinder->wrr_cost[3] = pipe_params->wrr_cost[qindex + 3];
1910 grinder_wrr_store(struct rte_sched_port *port, uint32_t pos)
1912 struct rte_sched_grinder *grinder = port->grinder + pos;
1913 struct rte_sched_pipe *pipe = grinder->pipe;
1914 uint32_t tc_index = grinder->tc_index;
1917 qindex = tc_index * 4;
1919 pipe->wrr_tokens[qindex] = (uint8_t) ((grinder->wrr_tokens[0] & grinder->wrr_mask[0]) >> RTE_SCHED_WRR_SHIFT);
1920 pipe->wrr_tokens[qindex + 1] = (uint8_t) ((grinder->wrr_tokens[1] & grinder->wrr_mask[1]) >> RTE_SCHED_WRR_SHIFT);
1921 pipe->wrr_tokens[qindex + 2] = (uint8_t) ((grinder->wrr_tokens[2] & grinder->wrr_mask[2]) >> RTE_SCHED_WRR_SHIFT);
1922 pipe->wrr_tokens[qindex + 3] = (uint8_t) ((grinder->wrr_tokens[3] & grinder->wrr_mask[3]) >> RTE_SCHED_WRR_SHIFT);
1926 grinder_wrr(struct rte_sched_port *port, uint32_t pos)
1928 struct rte_sched_grinder *grinder = port->grinder + pos;
1929 uint16_t wrr_tokens_min;
1931 grinder->wrr_tokens[0] |= ~grinder->wrr_mask[0];
1932 grinder->wrr_tokens[1] |= ~grinder->wrr_mask[1];
1933 grinder->wrr_tokens[2] |= ~grinder->wrr_mask[2];
1934 grinder->wrr_tokens[3] |= ~grinder->wrr_mask[3];
1936 grinder->qpos = rte_min_pos_4_u16(grinder->wrr_tokens);
1937 wrr_tokens_min = grinder->wrr_tokens[grinder->qpos];
1939 grinder->wrr_tokens[0] -= wrr_tokens_min;
1940 grinder->wrr_tokens[1] -= wrr_tokens_min;
1941 grinder->wrr_tokens[2] -= wrr_tokens_min;
1942 grinder->wrr_tokens[3] -= wrr_tokens_min;
1946 #define grinder_evict(port, pos)
1949 grinder_prefetch_pipe(struct rte_sched_port *port, uint32_t pos)
1951 struct rte_sched_grinder *grinder = port->grinder + pos;
1953 rte_prefetch0(grinder->pipe);
1954 rte_prefetch0(grinder->queue[0]);
1958 grinder_prefetch_tc_queue_arrays(struct rte_sched_port *port, uint32_t pos)
1960 struct rte_sched_grinder *grinder = port->grinder + pos;
1961 uint16_t qsize, qr[4];
1963 qsize = grinder->qsize;
1964 qr[0] = grinder->queue[0]->qr & (qsize - 1);
1965 qr[1] = grinder->queue[1]->qr & (qsize - 1);
1966 qr[2] = grinder->queue[2]->qr & (qsize - 1);
1967 qr[3] = grinder->queue[3]->qr & (qsize - 1);
1969 rte_prefetch0(grinder->qbase[0] + qr[0]);
1970 rte_prefetch0(grinder->qbase[1] + qr[1]);
1972 grinder_wrr_load(port, pos);
1973 grinder_wrr(port, pos);
1975 rte_prefetch0(grinder->qbase[2] + qr[2]);
1976 rte_prefetch0(grinder->qbase[3] + qr[3]);
1980 grinder_prefetch_mbuf(struct rte_sched_port *port, uint32_t pos)
1982 struct rte_sched_grinder *grinder = port->grinder + pos;
1983 uint32_t qpos = grinder->qpos;
1984 struct rte_mbuf **qbase = grinder->qbase[qpos];
1985 uint16_t qsize = grinder->qsize;
1986 uint16_t qr = grinder->queue[qpos]->qr & (qsize - 1);
1988 grinder->pkt = qbase[qr];
1989 rte_prefetch0(grinder->pkt);
1991 if (unlikely((qr & 0x7) == 7)) {
1992 uint16_t qr_next = (grinder->queue[qpos]->qr + 1) & (qsize - 1);
1994 rte_prefetch0(qbase + qr_next);
1998 static inline uint32_t
1999 grinder_handle(struct rte_sched_port *port, uint32_t pos)
2001 struct rte_sched_grinder *grinder = port->grinder + pos;
2003 switch (grinder->state) {
2004 case e_GRINDER_PREFETCH_PIPE:
2006 if (grinder_next_pipe(port, pos)) {
2007 grinder_prefetch_pipe(port, pos);
2008 port->busy_grinders ++;
2010 grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2017 case e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS:
2019 struct rte_sched_pipe *pipe = grinder->pipe;
2021 grinder->pipe_params = port->pipe_profiles + pipe->profile;
2022 grinder_prefetch_tc_queue_arrays(port, pos);
2023 grinder_credits_update(port, pos);
2025 grinder->state = e_GRINDER_PREFETCH_MBUF;
2029 case e_GRINDER_PREFETCH_MBUF:
2031 grinder_prefetch_mbuf(port, pos);
2033 grinder->state = e_GRINDER_READ_MBUF;
2037 case e_GRINDER_READ_MBUF:
2039 uint32_t result = 0;
2041 result = grinder_schedule(port, pos);
2043 /* Look for next packet within the same TC */
2044 if (result && grinder->qmask) {
2045 grinder_wrr(port, pos);
2046 grinder_prefetch_mbuf(port, pos);
2050 grinder_wrr_store(port, pos);
2052 /* Look for another active TC within same pipe */
2053 if (grinder_next_tc(port, pos)) {
2054 grinder_prefetch_tc_queue_arrays(port, pos);
2056 grinder->state = e_GRINDER_PREFETCH_MBUF;
2059 if ((grinder->productive == 0) && (port->pipe_loop == RTE_SCHED_PIPE_INVALID)) {
2060 port->pipe_loop = grinder->pindex;
2062 grinder_evict(port, pos);
2064 /* Look for another active pipe */
2065 if (grinder_next_pipe(port, pos)) {
2066 grinder_prefetch_pipe(port, pos);
2068 grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2072 /* No active pipe found */
2073 port->busy_grinders --;
2075 grinder->state = e_GRINDER_PREFETCH_PIPE;
2080 rte_panic("Algorithmic error (invalid state)\n");
2086 rte_sched_port_time_resync(struct rte_sched_port *port)
2088 uint64_t cycles = rte_get_tsc_cycles();
2089 uint64_t cycles_diff = cycles - port->time_cpu_cycles;
2090 double bytes_diff = ((double) cycles_diff) / port->cycles_per_byte;
2092 /* Advance port time */
2093 port->time_cpu_cycles = cycles;
2094 port->time_cpu_bytes += (uint64_t) bytes_diff;
2095 if (port->time < port->time_cpu_bytes) {
2096 port->time = port->time_cpu_bytes;
2099 /* Reset pipe loop detection */
2100 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
2104 rte_sched_port_exceptions(struct rte_sched_port *port, int second_pass)
2108 /* Check if any exception flag is set */
2109 exceptions = (second_pass && port->busy_grinders == 0) ||
2110 (port->pipe_exhaustion == 1);
2112 /* Clear exception flags */
2113 port->pipe_exhaustion = 0;
2119 rte_sched_port_dequeue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
2123 port->pkts_out = pkts;
2124 port->n_pkts_out = 0;
2126 rte_sched_port_time_resync(port);
2128 /* Take each queue in the grinder one step further */
2129 for (i = 0, count = 0; ; i ++) {
2130 count += grinder_handle(port, i & (RTE_SCHED_PORT_N_GRINDERS - 1));
2131 if ((count == n_pkts) ||
2132 rte_sched_port_exceptions(port, i >= RTE_SCHED_PORT_N_GRINDERS)) {