4 * Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
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38 #include <rte_common.h>
40 #include <rte_memory.h>
41 #include <rte_memzone.h>
42 #include <rte_cycles.h>
43 #include <rte_prefetch.h>
44 #include <rte_branch_prediction.h>
47 #include "rte_sched.h"
48 #include "rte_bitmap.h"
49 #include "rte_sched_common.h"
50 #include "rte_approx.h"
52 #ifdef __INTEL_COMPILER
53 #pragma warning(disable:2259) /* conversion may lose significant bits */
56 #ifndef RTE_SCHED_DEBUG
57 #define RTE_SCHED_DEBUG 0
60 #ifndef RTE_SCHED_OPTIMIZATIONS
61 #define RTE_SCHED_OPTIMIZATIONS 0
64 #if RTE_SCHED_OPTIMIZATIONS
65 #include <immintrin.h>
68 #define RTE_SCHED_ENQUEUE 1
70 #define RTE_SCHED_TS 1
72 #if RTE_SCHED_TS == 0 /* Infinite credits. Traffic shaping disabled. */
73 #define RTE_SCHED_TS_CREDITS_UPDATE 0
74 #define RTE_SCHED_TS_CREDITS_CHECK 0
75 #else /* Real Credits. Full traffic shaping implemented. */
76 #define RTE_SCHED_TS_CREDITS_UPDATE 1
77 #define RTE_SCHED_TS_CREDITS_CHECK 1
80 #ifndef RTE_SCHED_TB_RATE_CONFIG_ERR
81 #define RTE_SCHED_TB_RATE_CONFIG_ERR (1e-7)
84 #define RTE_SCHED_WRR 1
86 #ifndef RTE_SCHED_WRR_SHIFT
87 #define RTE_SCHED_WRR_SHIFT 3
90 #ifndef RTE_SCHED_PORT_N_GRINDERS
91 #define RTE_SCHED_PORT_N_GRINDERS 8
93 #if (RTE_SCHED_PORT_N_GRINDERS == 0) || (RTE_SCHED_PORT_N_GRINDERS & (RTE_SCHED_PORT_N_GRINDERS - 1))
94 #error Number of grinders must be non-zero and a power of 2
96 #if (RTE_SCHED_OPTIMIZATIONS && (RTE_SCHED_PORT_N_GRINDERS != 8))
97 #error Number of grinders must be 8 when RTE_SCHED_OPTIMIZATIONS is set
100 #define RTE_SCHED_GRINDER_PCACHE_SIZE (64 / RTE_SCHED_QUEUES_PER_PIPE)
102 #define RTE_SCHED_PIPE_INVALID UINT32_MAX
104 #define RTE_SCHED_BMP_POS_INVALID UINT32_MAX
106 struct rte_sched_subport {
107 /* Token bucket (TB) */
108 uint64_t tb_time; /* time of last update */
110 uint32_t tb_credits_per_period;
114 /* Traffic classes (TCs) */
115 uint64_t tc_time; /* time of next update */
116 uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
117 uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
120 /* TC oversubscription */
121 uint32_t tc_ov_period;
123 uint32_t tc_ov_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
124 uint8_t tc_ov_period_id;
125 uint8_t tc_ov[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
126 uint32_t tc_ov_n[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
127 double tc_ov_rate[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
130 struct rte_sched_subport_stats stats;
133 struct rte_sched_pipe_profile {
134 /* Token bucket (TB) */
136 uint32_t tb_credits_per_period;
139 /* Pipe traffic classes */
141 uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
142 uint8_t tc_ov_weight[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
145 uint8_t wrr_cost[RTE_SCHED_QUEUES_PER_PIPE];
148 struct rte_sched_pipe {
149 /* Token bucket (TB) */
150 uint64_t tb_time; /* time of last update */
153 /* Pipe profile and flags */
156 /* Traffic classes (TCs) */
157 uint64_t tc_time; /* time of next update */
158 uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
160 /* Weighted Round Robin (WRR) */
161 uint8_t wrr_tokens[RTE_SCHED_QUEUES_PER_PIPE];
163 /* TC oversubscription */
164 #ifdef RTE_SCHED_SUBPORT_TC_OV
165 uint32_t tc_ov_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
166 uint8_t tc_ov_period_id;
170 } __rte_cache_aligned;
172 struct rte_sched_queue {
177 struct rte_sched_queue_extra {
178 struct rte_sched_queue_stats stats;
185 e_GRINDER_PREFETCH_PIPE = 0,
186 e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS,
187 e_GRINDER_PREFETCH_MBUF,
191 struct rte_sched_grinder {
193 uint16_t pcache_qmask[RTE_SCHED_GRINDER_PCACHE_SIZE];
194 uint32_t pcache_qindex[RTE_SCHED_GRINDER_PCACHE_SIZE];
199 enum grinder_state state;
202 struct rte_sched_subport *subport;
203 struct rte_sched_pipe *pipe;
204 struct rte_sched_pipe_profile *pipe_params;
207 uint8_t tccache_qmask[4];
208 uint32_t tccache_qindex[4];
214 struct rte_sched_queue *queue[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
215 struct rte_mbuf **qbase[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
216 uint32_t qindex[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
220 struct rte_mbuf *pkt;
224 uint16_t wrr_tokens[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
225 uint16_t wrr_mask[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
226 uint8_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
229 struct rte_sched_port {
230 /* User parameters */
231 uint32_t n_subports_per_port;
232 uint32_t n_pipes_per_subport;
235 uint32_t frame_overhead;
236 uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
237 uint32_t n_pipe_profiles;
239 struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][e_RTE_METER_COLORS];
243 uint64_t time_cpu_cycles; /* Current CPU time measured in CPU cyles */
244 uint64_t time_cpu_bytes; /* Current CPU time measured in bytes */
245 uint64_t time; /* Current NIC TX time measured in bytes */
246 double cycles_per_byte; /* CPU cycles per byte */
248 /* Scheduling loop detection */
250 uint32_t pipe_exhaustion;
253 struct rte_bitmap *bmp;
254 uint32_t grinder_base_bmp_pos[RTE_SCHED_PORT_N_GRINDERS] __rte_aligned_16;
257 struct rte_sched_grinder grinder[RTE_SCHED_PORT_N_GRINDERS];
258 uint32_t busy_grinders;
259 struct rte_mbuf **pkts_out;
262 /* Queue base calculation */
263 uint32_t qsize_add[RTE_SCHED_QUEUES_PER_PIPE];
266 /* Large data structures */
267 struct rte_sched_subport *subport;
268 struct rte_sched_pipe *pipe;
269 struct rte_sched_queue *queue;
270 struct rte_sched_queue_extra *queue_extra;
271 struct rte_sched_pipe_profile *pipe_profiles;
273 struct rte_mbuf **queue_array;
274 uint8_t memory[0] __rte_cache_aligned;
275 } __rte_cache_aligned;
277 enum rte_sched_port_array {
278 e_RTE_SCHED_PORT_ARRAY_SUBPORT = 0,
279 e_RTE_SCHED_PORT_ARRAY_PIPE,
280 e_RTE_SCHED_PORT_ARRAY_QUEUE,
281 e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA,
282 e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES,
283 e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY,
284 e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY,
285 e_RTE_SCHED_PORT_ARRAY_TOTAL,
288 #ifdef RTE_SCHED_COLLECT_STATS
290 static inline uint32_t
291 rte_sched_port_queues_per_subport(struct rte_sched_port *port)
293 return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport;
298 static inline uint32_t
299 rte_sched_port_queues_per_port(struct rte_sched_port *port)
301 return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport * port->n_subports_per_port;
305 rte_sched_port_check_params(struct rte_sched_port_params *params)
309 if (params == NULL) {
314 if (params->name == NULL) {
319 if ((params->socket < 0) || (params->socket >= RTE_MAX_NUMA_NODES)) {
324 if (params->rate == 0) {
329 if (params->mtu == 0) {
333 /* n_subports_per_port: non-zero, power of 2 */
334 if ((params->n_subports_per_port == 0) || (!rte_is_power_of_2(params->n_subports_per_port))) {
338 /* n_pipes_per_subport: non-zero, power of 2 */
339 if ((params->n_pipes_per_subport == 0) || (!rte_is_power_of_2(params->n_pipes_per_subport))) {
343 /* qsize: non-zero, power of 2, no bigger than 32K (due to 16-bit read/write pointers) */
344 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
345 uint16_t qsize = params->qsize[i];
347 if ((qsize == 0) || (!rte_is_power_of_2(qsize))) {
352 /* pipe_profiles and n_pipe_profiles */
353 if ((params->pipe_profiles == NULL) ||
354 (params->n_pipe_profiles == 0) ||
355 (params->n_pipe_profiles > RTE_SCHED_PIPE_PROFILES_PER_PORT)) {
359 for (i = 0; i < params->n_pipe_profiles; i ++) {
360 struct rte_sched_pipe_params *p = params->pipe_profiles + i;
362 /* TB rate: non-zero, not greater than port rate */
363 if ((p->tb_rate == 0) || (p->tb_rate > params->rate)) {
367 /* TB size: non-zero */
368 if (p->tb_size == 0) {
372 /* TC rate: non-zero, less than pipe rate */
373 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
374 if ((p->tc_rate[j] == 0) || (p->tc_rate[j] > p->tb_rate)) {
379 /* TC period: non-zero */
380 if (p->tc_period == 0) {
384 #ifdef RTE_SCHED_SUBPORT_TC_OV
385 /* TC oversubscription weights: non-zero */
386 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
387 if (p->tc_ov_weight[j] == 0) {
393 /* Queue WRR weights: non-zero */
394 for (j = 0; j < RTE_SCHED_QUEUES_PER_PIPE; j ++) {
395 if (p->wrr_weights[j] == 0) {
405 rte_sched_port_get_array_base(struct rte_sched_port_params *params, enum rte_sched_port_array array)
407 uint32_t n_subports_per_port = params->n_subports_per_port;
408 uint32_t n_pipes_per_subport = params->n_pipes_per_subport;
409 uint32_t n_pipes_per_port = n_pipes_per_subport * n_subports_per_port;
410 uint32_t n_queues_per_port = RTE_SCHED_QUEUES_PER_PIPE * n_pipes_per_subport * n_subports_per_port;
412 uint32_t size_subport = n_subports_per_port * sizeof(struct rte_sched_subport);
413 uint32_t size_pipe = n_pipes_per_port * sizeof(struct rte_sched_pipe);
414 uint32_t size_queue = n_queues_per_port * sizeof(struct rte_sched_queue);
415 uint32_t size_queue_extra = n_queues_per_port * sizeof(struct rte_sched_queue_extra);
416 uint32_t size_pipe_profiles = RTE_SCHED_PIPE_PROFILES_PER_PORT * sizeof(struct rte_sched_pipe_profile);
417 uint32_t size_bmp_array = rte_bitmap_get_memory_footprint(n_queues_per_port);
418 uint32_t size_per_pipe_queue_array, size_queue_array;
422 size_per_pipe_queue_array = 0;
423 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
424 size_per_pipe_queue_array += RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS * params->qsize[i] * sizeof(struct rte_mbuf *);
426 size_queue_array = n_pipes_per_port * size_per_pipe_queue_array;
430 if (array == e_RTE_SCHED_PORT_ARRAY_SUBPORT) return base;
431 base += CACHE_LINE_ROUNDUP(size_subport);
433 if (array == e_RTE_SCHED_PORT_ARRAY_PIPE) return base;
434 base += CACHE_LINE_ROUNDUP(size_pipe);
436 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE) return base;
437 base += CACHE_LINE_ROUNDUP(size_queue);
439 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA) return base;
440 base += CACHE_LINE_ROUNDUP(size_queue_extra);
442 if (array == e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES) return base;
443 base += CACHE_LINE_ROUNDUP(size_pipe_profiles);
445 if (array == e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY) return base;
446 base += CACHE_LINE_ROUNDUP(size_bmp_array);
448 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY) return base;
449 base += CACHE_LINE_ROUNDUP(size_queue_array);
455 rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)
457 uint32_t size0, size1;
460 status = rte_sched_port_check_params(params);
462 RTE_LOG(INFO, SCHED, "Port scheduler params check failed (%d)\n", status);
467 size0 = sizeof(struct rte_sched_port);
468 size1 = rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_TOTAL);
470 return (size0 + size1);
474 rte_sched_port_config_qsize(struct rte_sched_port *port)
477 port->qsize_add[0] = 0;
478 port->qsize_add[1] = port->qsize_add[0] + port->qsize[0];
479 port->qsize_add[2] = port->qsize_add[1] + port->qsize[0];
480 port->qsize_add[3] = port->qsize_add[2] + port->qsize[0];
483 port->qsize_add[4] = port->qsize_add[3] + port->qsize[0];
484 port->qsize_add[5] = port->qsize_add[4] + port->qsize[1];
485 port->qsize_add[6] = port->qsize_add[5] + port->qsize[1];
486 port->qsize_add[7] = port->qsize_add[6] + port->qsize[1];
489 port->qsize_add[8] = port->qsize_add[7] + port->qsize[1];
490 port->qsize_add[9] = port->qsize_add[8] + port->qsize[2];
491 port->qsize_add[10] = port->qsize_add[9] + port->qsize[2];
492 port->qsize_add[11] = port->qsize_add[10] + port->qsize[2];
495 port->qsize_add[12] = port->qsize_add[11] + port->qsize[2];
496 port->qsize_add[13] = port->qsize_add[12] + port->qsize[3];
497 port->qsize_add[14] = port->qsize_add[13] + port->qsize[3];
498 port->qsize_add[15] = port->qsize_add[14] + port->qsize[3];
500 port->qsize_sum = port->qsize_add[15] + port->qsize[3];
504 rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)
506 struct rte_sched_pipe_profile *p = port->pipe_profiles + i;
508 RTE_LOG(INFO, SCHED, "Low level config for pipe profile %u:\n"
509 "\tToken bucket: period = %u, credits per period = %u, size = %u\n"
510 "\tTraffic classes: period = %u, credits per period = [%u, %u, %u, %u], ov weights = [%hhu, %hhu, %hhu, %hhu]\n"
511 "\tWRR cost: [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu]\n",
516 p->tb_credits_per_period,
519 /* Traffic classes */
521 p->tc_credits_per_period[0],
522 p->tc_credits_per_period[1],
523 p->tc_credits_per_period[2],
524 p->tc_credits_per_period[3],
531 p->wrr_cost[ 0], p->wrr_cost[ 1], p->wrr_cost[ 2], p->wrr_cost[ 3],
532 p->wrr_cost[ 4], p->wrr_cost[ 5], p->wrr_cost[ 6], p->wrr_cost[ 7],
533 p->wrr_cost[ 8], p->wrr_cost[ 9], p->wrr_cost[10], p->wrr_cost[11],
534 p->wrr_cost[12], p->wrr_cost[13], p->wrr_cost[14], p->wrr_cost[15]);
537 static inline uint64_t
538 rte_sched_time_ms_to_bytes(uint32_t time_ms, uint32_t rate)
540 uint64_t time = time_ms;
541 time = (time * rate) / 1000;
547 rte_sched_port_config_pipe_profile_table(struct rte_sched_port *port, struct rte_sched_port_params *params)
551 for (i = 0; i < port->n_pipe_profiles; i ++) {
552 struct rte_sched_pipe_params *src = params->pipe_profiles + i;
553 struct rte_sched_pipe_profile *dst = port->pipe_profiles + i;
556 if (src->tb_rate == params->rate) {
557 dst->tb_credits_per_period = 1;
560 double tb_rate = ((double) src->tb_rate) / ((double) params->rate);
561 double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
563 rte_approx(tb_rate, d, &dst->tb_credits_per_period, &dst->tb_period);
565 dst->tb_size = src->tb_size;
567 /* Traffic Classes */
568 dst->tc_period = (uint32_t) rte_sched_time_ms_to_bytes(src->tc_period, params->rate);
569 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
570 dst->tc_credits_per_period[j] = (uint32_t) rte_sched_time_ms_to_bytes(src->tc_period, src->tc_rate[j]);
572 #ifdef RTE_SCHED_SUBPORT_TC_OV
573 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
574 dst->tc_ov_weight[j] = src->tc_ov_weight[j];
579 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
580 uint32_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
581 uint32_t lcd, lcd1, lcd2;
584 qindex = j * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS;
586 wrr_cost[0] = src->wrr_weights[qindex];
587 wrr_cost[1] = src->wrr_weights[qindex + 1];
588 wrr_cost[2] = src->wrr_weights[qindex + 2];
589 wrr_cost[3] = src->wrr_weights[qindex + 3];
591 lcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]);
592 lcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]);
593 lcd = rte_get_lcd(lcd1, lcd2);
595 wrr_cost[0] = lcd / wrr_cost[0];
596 wrr_cost[1] = lcd / wrr_cost[1];
597 wrr_cost[2] = lcd / wrr_cost[2];
598 wrr_cost[3] = lcd / wrr_cost[3];
600 dst->wrr_cost[qindex] = (uint8_t) wrr_cost[0];
601 dst->wrr_cost[qindex + 1] = (uint8_t) wrr_cost[1];
602 dst->wrr_cost[qindex + 2] = (uint8_t) wrr_cost[2];
603 dst->wrr_cost[qindex + 3] = (uint8_t) wrr_cost[3];
606 rte_sched_port_log_pipe_profile(port, i);
610 struct rte_sched_port *
611 rte_sched_port_config(struct rte_sched_port_params *params)
613 struct rte_sched_port *port = NULL;
614 const struct rte_memzone *mz = NULL;
615 uint32_t mem_size, bmp_mem_size, n_queues_per_port, i;
617 /* Check user parameters. Determine the amount of memory to allocate */
618 mem_size = rte_sched_port_get_memory_footprint(params);
623 /* Allocate memory to store the data structures */
624 mz = rte_memzone_lookup(params->name);
626 /* Use existing memzone, provided that its size is big enough */
627 if (mz->len < mem_size) {
631 /* Create new memzone */
632 mz = rte_memzone_reserve(params->name, mem_size, params->socket, 0);
637 memset(mz->addr, 0, mem_size);
638 port = (struct rte_sched_port *) mz->addr;
640 /* User parameters */
641 port->n_subports_per_port = params->n_subports_per_port;
642 port->n_pipes_per_subport = params->n_pipes_per_subport;
643 port->rate = params->rate;
644 port->mtu = params->mtu + params->frame_overhead;
645 port->frame_overhead = params->frame_overhead;
646 memcpy(port->qsize, params->qsize, sizeof(params->qsize));
647 port->n_pipe_profiles = params->n_pipe_profiles;
650 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
653 for (j = 0; j < e_RTE_METER_COLORS; j++) {
654 if (rte_red_config_init(&port->red_config[i][j],
655 params->red_params[i][j].wq_log2,
656 params->red_params[i][j].min_th,
657 params->red_params[i][j].max_th,
658 params->red_params[i][j].maxp_inv) != 0) {
666 port->time_cpu_cycles = rte_get_tsc_cycles();
667 port->time_cpu_bytes = 0;
669 port->cycles_per_byte = ((double) rte_get_tsc_hz()) / ((double) params->rate);
671 /* Scheduling loop detection */
672 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
673 port->pipe_exhaustion = 0;
676 port->busy_grinders = 0;
677 port->pkts_out = NULL;
678 port->n_pkts_out = 0;
680 /* Queue base calculation */
681 rte_sched_port_config_qsize(port);
683 /* Large data structures */
684 port->subport = (struct rte_sched_subport *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_SUBPORT));
685 port->pipe = (struct rte_sched_pipe *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_PIPE));
686 port->queue = (struct rte_sched_queue *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE));
687 port->queue_extra = (struct rte_sched_queue_extra *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA));
688 port->pipe_profiles = (struct rte_sched_pipe_profile *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES));
689 port->bmp_array = port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY);
690 port->queue_array = (struct rte_mbuf **) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY));
692 /* Pipe profile table */
693 rte_sched_port_config_pipe_profile_table(port, params);
696 n_queues_per_port = rte_sched_port_queues_per_port(port);
697 bmp_mem_size = rte_bitmap_get_memory_footprint(n_queues_per_port);
698 port->bmp = rte_bitmap_init(n_queues_per_port, port->bmp_array, bmp_mem_size);
699 if (port->bmp == NULL) {
700 RTE_LOG(INFO, SCHED, "Bitmap init error\n");
703 for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i ++) {
704 port->grinder_base_bmp_pos[i] = RTE_SCHED_PIPE_INVALID;
711 rte_sched_port_free(struct rte_sched_port *port)
713 /* Check user parameters */
717 rte_bitmap_free(port->bmp);
723 rte_sched_port_log_subport_config(struct rte_sched_port *port, uint32_t i)
725 struct rte_sched_subport *s = port->subport + i;
727 RTE_LOG(INFO, SCHED, "Low level config for subport %u:\n"
728 "\tToken bucket: period = %u, credits per period = %u, size = %u\n"
729 "\tTraffic classes: period = %u, credits per period = [%u, %u, %u, %u], ov period = %u\n",
734 s->tb_credits_per_period,
737 /* Traffic classes */
739 s->tc_credits_per_period[0],
740 s->tc_credits_per_period[1],
741 s->tc_credits_per_period[2],
742 s->tc_credits_per_period[3],
747 rte_sched_subport_config(struct rte_sched_port *port,
749 struct rte_sched_subport_params *params)
751 struct rte_sched_subport *s;
754 /* Check user parameters */
755 if ((port == NULL) ||
756 (subport_id >= port->n_subports_per_port) ||
761 if ((params->tb_rate == 0) || (params->tb_rate > port->rate)) {
765 if (params->tb_size == 0) {
769 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
770 if ((params->tc_rate[i] == 0) || (params->tc_rate[i] > params->tb_rate)) {
775 if (params->tc_period == 0) {
779 #ifdef RTE_SCHED_SUBPORT_TC_OV
780 if ((params->tc_ov_period == 0) || (params->tc_ov_period > params->tc_period)) {
785 s = port->subport + subport_id;
787 /* Token Bucket (TB) */
788 if (params->tb_rate == port->rate) {
789 s->tb_credits_per_period = 1;
792 double tb_rate = ((double) params->tb_rate) / ((double) port->rate);
793 double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
795 rte_approx(tb_rate, d, &s->tb_credits_per_period, &s->tb_period);
797 s->tb_size = params->tb_size;
798 s->tb_time = port->time;
799 s->tb_credits = s->tb_size / 2;
801 /* Traffic Classes (TCs) */
802 s->tc_period = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, port->rate);
803 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
804 s->tc_credits_per_period[i] = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, params->tc_rate[i]);
806 s->tc_time = port->time + s->tc_period;
807 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
808 s->tc_credits[i] = s->tc_credits_per_period[i];
811 #ifdef RTE_SCHED_SUBPORT_TC_OV
812 /* TC oversubscription */
813 s->tc_ov_period = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_ov_period, port->rate);
814 s->tc_ov_time = port->time + s->tc_ov_period;
815 s->tc_ov_period_id = 0;
816 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
819 s->tc_ov_rate[i] = 0;
820 s->tc_ov_credits[i] = 0;
824 rte_sched_port_log_subport_config(port, subport_id);
830 rte_sched_pipe_config(struct rte_sched_port *port,
833 int32_t pipe_profile)
835 struct rte_sched_subport *s;
836 struct rte_sched_pipe *p;
837 struct rte_sched_pipe_profile *params;
838 uint32_t deactivate, profile, i;
840 /* Check user parameters */
841 profile = (uint32_t) pipe_profile;
842 deactivate = (pipe_profile < 0);
843 if ((port == NULL) ||
844 (subport_id >= port->n_subports_per_port) ||
845 (pipe_id >= port->n_pipes_per_subport) ||
846 ((!deactivate) && (profile >= port->n_pipe_profiles))) {
850 /* Check that subport configuration is valid */
851 s = port->subport + subport_id;
852 if (s->tb_period == 0) {
856 p = port->pipe + (subport_id * port->n_pipes_per_subport + pipe_id);
858 /* Handle the case when pipe already has a valid configuration */
860 params = port->pipe_profiles + p->profile;
862 #ifdef RTE_SCHED_SUBPORT_TC_OV
863 /* Unplug pipe from its subport */
864 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
865 s->tc_ov_n[i] -= params->tc_ov_weight[i];
866 s->tc_ov_rate[i] -= ((double) params->tc_credits_per_period[i]) / ((double) params->tc_period);
867 s->tc_ov[i] = s->tc_ov_rate[i] > (((double) s->tc_credits_per_period[i]) / ((double) s->tc_period));
872 memset(p, 0, sizeof(struct rte_sched_pipe));
879 /* Apply the new pipe configuration */
880 p->profile = profile;
881 params = port->pipe_profiles + p->profile;
883 /* Token Bucket (TB) */
884 p->tb_time = port->time;
885 p->tb_credits = params->tb_size / 2;
887 /* Traffic Classes (TCs) */
888 p->tc_time = port->time + params->tc_period;
889 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
890 p->tc_credits[i] = params->tc_credits_per_period[i];
893 #ifdef RTE_SCHED_SUBPORT_TC_OV
894 /* Subport TC oversubscription */
895 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
896 s->tc_ov_n[i] += params->tc_ov_weight[i];
897 s->tc_ov_rate[i] += ((double) params->tc_credits_per_period[i]) / ((double) params->tc_period);
898 s->tc_ov[i] = s->tc_ov_rate[i] > (((double) s->tc_credits_per_period[i]) / ((double) s->tc_period));
900 p->tc_ov_period_id = s->tc_ov_period_id;
901 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
902 p->tc_ov_credits[i] = 0;
910 rte_sched_subport_read_stats(struct rte_sched_port *port,
912 struct rte_sched_subport_stats *stats,
915 struct rte_sched_subport *s;
918 /* Check user parameters */
919 if ((port == NULL) ||
920 (subport_id >= port->n_subports_per_port) ||
925 s = port->subport + subport_id;
927 /* Copy subport stats and clear */
928 memcpy(stats, &s->stats, sizeof(struct rte_sched_subport_stats));
929 memset(&s->stats, 0, sizeof(struct rte_sched_subport_stats));
931 /* Subport TC ovesubscription status */
933 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
934 mask |= ((uint32_t) s->tc_ov[i]) << i;
942 rte_sched_queue_read_stats(struct rte_sched_port *port,
944 struct rte_sched_queue_stats *stats,
947 struct rte_sched_queue *q;
948 struct rte_sched_queue_extra *qe;
950 /* Check user parameters */
951 if ((port == NULL) ||
952 (queue_id >= rte_sched_port_queues_per_port(port)) ||
957 q = port->queue + queue_id;
958 qe = port->queue_extra + queue_id;
960 /* Copy queue stats and clear */
961 memcpy(stats, &qe->stats, sizeof(struct rte_sched_queue_stats));
962 memset(&qe->stats, 0, sizeof(struct rte_sched_queue_stats));
965 *qlen = q->qw - q->qr;
970 static inline uint32_t
971 rte_sched_port_qindex(struct rte_sched_port *port, uint32_t subport, uint32_t pipe, uint32_t traffic_class, uint32_t queue)
975 result = subport * port->n_pipes_per_subport + pipe;
976 result = result * RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE + traffic_class;
977 result = result * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS + queue;
982 static inline struct rte_mbuf **
983 rte_sched_port_qbase(struct rte_sched_port *port, uint32_t qindex)
985 uint32_t pindex = qindex >> 4;
986 uint32_t qpos = qindex & 0xF;
988 return (port->queue_array + pindex * port->qsize_sum + port->qsize_add[qpos]);
991 static inline uint16_t
992 rte_sched_port_qsize(struct rte_sched_port *port, uint32_t qindex)
994 uint32_t tc = (qindex >> 2) & 0x3;
996 return port->qsize[tc];
1002 rte_sched_port_queue_is_empty(struct rte_sched_port *port, uint32_t qindex)
1004 struct rte_sched_queue *queue = port->queue + qindex;
1006 return (queue->qr == queue->qw);
1010 rte_sched_port_queue_is_full(struct rte_sched_port *port, uint32_t qindex)
1012 struct rte_sched_queue *queue = port->queue + qindex;
1013 uint16_t qsize = rte_sched_port_qsize(port, qindex);
1014 uint16_t qlen = q->qw - q->qr;
1016 return (qlen >= qsize);
1019 #endif /* RTE_SCHED_DEBUG */
1021 #ifdef RTE_SCHED_COLLECT_STATS
1024 rte_sched_port_update_subport_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1026 struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1027 uint32_t tc_index = (qindex >> 2) & 0x3;
1028 uint32_t pkt_len = pkt->pkt.pkt_len;
1030 s->stats.n_pkts_tc[tc_index] += 1;
1031 s->stats.n_bytes_tc[tc_index] += pkt_len;
1035 rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1037 struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1038 uint32_t tc_index = (qindex >> 2) & 0x3;
1039 uint32_t pkt_len = pkt->pkt.pkt_len;
1041 s->stats.n_pkts_tc_dropped[tc_index] += 1;
1042 s->stats.n_bytes_tc_dropped[tc_index] += pkt_len;
1046 rte_sched_port_update_queue_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1048 struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1049 uint32_t pkt_len = pkt->pkt.pkt_len;
1051 qe->stats.n_pkts += 1;
1052 qe->stats.n_bytes += pkt_len;
1056 rte_sched_port_update_queue_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1058 struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1059 uint32_t pkt_len = pkt->pkt.pkt_len;
1061 qe->stats.n_pkts_dropped += 1;
1062 qe->stats.n_bytes_dropped += pkt_len;
1065 #endif /* RTE_SCHED_COLLECT_STATS */
1067 #ifdef RTE_SCHED_RED
1070 rte_sched_port_red_drop(struct rte_sched_port *port, struct rte_mbuf *pkt, uint32_t qindex, uint16_t qlen)
1072 struct rte_sched_queue_extra *qe;
1073 struct rte_red_config *red_cfg;
1074 struct rte_red *red;
1076 enum rte_meter_color color;
1078 tc_index = (qindex >> 2) & 0x3;
1079 color = rte_sched_port_pkt_read_color(pkt);
1080 red_cfg = &port->red_config[tc_index][color];
1082 qe = port->queue_extra + qindex;
1085 return rte_red_enqueue(red_cfg, red, qlen, port->time);
1089 rte_sched_port_set_queue_empty_timestamp(struct rte_sched_port *port, uint32_t qindex)
1091 struct rte_sched_queue_extra *qe;
1092 struct rte_red *red;
1094 qe = port->queue_extra + qindex;
1097 rte_red_mark_queue_empty(red, port->time);
1102 #define rte_sched_port_red_drop(port, pkt, qindex, qlen) 0
1104 #define rte_sched_port_set_queue_empty_timestamp(port, qindex)
1106 #endif /* RTE_SCHED_RED */
1111 debug_pipe_is_empty(struct rte_sched_port *port, uint32_t pindex)
1115 qindex = pindex << 4;
1117 for (i = 0; i < 16; i ++){
1118 uint32_t queue_empty = rte_sched_port_queue_is_empty(port, qindex + i);
1119 uint32_t bmp_bit_clear = (rte_bitmap_get(port->bmp, qindex + i) == 0);
1121 if (queue_empty != bmp_bit_clear){
1122 rte_panic("Queue status mismatch for queue %u of pipe %u\n", i, pindex);
1134 debug_check_queue_slab(struct rte_sched_port *port, uint32_t bmp_pos, uint64_t bmp_slab)
1140 rte_panic("Empty slab at position %u\n", bmp_pos);
1144 for (i = 0, mask = 1; i < 64; i ++, mask <<= 1) {
1145 if (mask & bmp_slab){
1146 if (rte_sched_port_queue_is_empty(port, bmp_pos + i)) {
1147 printf("Queue %u (slab offset %u) is empty\n", bmp_pos + i, i);
1154 rte_panic("Empty queues in slab 0x%" PRIx64 "starting at position %u\n",
1159 #endif /* RTE_SCHED_DEBUG */
1161 static inline uint32_t
1162 rte_sched_port_enqueue_qptrs_prefetch0(struct rte_sched_port *port, struct rte_mbuf *pkt)
1164 struct rte_sched_queue *q;
1165 #ifdef RTE_SCHED_COLLECT_STATS
1166 struct rte_sched_queue_extra *qe;
1168 uint32_t subport, pipe, traffic_class, queue, qindex;
1170 rte_sched_port_pkt_read_tree_path(pkt, &subport, &pipe, &traffic_class, &queue);
1172 qindex = rte_sched_port_qindex(port, subport, pipe, traffic_class, queue);
1173 q = port->queue + qindex;
1175 #ifdef RTE_SCHED_COLLECT_STATS
1176 qe = port->queue_extra + qindex;
1184 rte_sched_port_enqueue_qwa_prefetch0(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf **qbase)
1186 struct rte_sched_queue *q;
1187 struct rte_mbuf **q_qw;
1190 q = port->queue + qindex;
1191 qsize = rte_sched_port_qsize(port, qindex);
1192 q_qw = qbase + (q->qw & (qsize - 1));
1194 rte_prefetch0(q_qw);
1195 rte_bitmap_prefetch0(port->bmp, qindex);
1199 rte_sched_port_enqueue_qwa(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf **qbase, struct rte_mbuf *pkt)
1201 struct rte_sched_queue *q;
1205 q = port->queue + qindex;
1206 qsize = rte_sched_port_qsize(port, qindex);
1207 qlen = q->qw - q->qr;
1209 /* Drop the packet (and update drop stats) when queue is full */
1210 if (unlikely(rte_sched_port_red_drop(port, pkt, qindex, qlen) || (qlen >= qsize))) {
1211 rte_pktmbuf_free(pkt);
1212 #ifdef RTE_SCHED_COLLECT_STATS
1213 rte_sched_port_update_subport_stats_on_drop(port, qindex, pkt);
1214 rte_sched_port_update_queue_stats_on_drop(port, qindex, pkt);
1219 /* Enqueue packet */
1220 qbase[q->qw & (qsize - 1)] = pkt;
1223 /* Activate queue in the port bitmap */
1224 rte_bitmap_set(port->bmp, qindex);
1227 #ifdef RTE_SCHED_COLLECT_STATS
1228 rte_sched_port_update_subport_stats(port, qindex, pkt);
1229 rte_sched_port_update_queue_stats(port, qindex, pkt);
1235 #if RTE_SCHED_ENQUEUE == 0
1238 rte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
1244 for (i = 0; i < n_pkts; i ++) {
1245 struct rte_mbuf *pkt;
1246 struct rte_mbuf **q_base;
1247 uint32_t subport, pipe, traffic_class, queue, qindex;
1251 rte_sched_port_pkt_read_tree_path(pkt, &subport, &pipe, &traffic_class, &queue);
1253 qindex = rte_sched_port_qindex(port, subport, pipe, traffic_class, queue);
1255 q_base = rte_sched_port_qbase(port, qindex);
1257 result += rte_sched_port_enqueue_qwa(port, qindex, q_base, pkt);
1265 /* The enqueue function implements a 4-level pipeline with each stage processing
1266 * two different packets. The purpose of using a pipeline is to hide the latency
1267 * of prefetching the data structures. The naming convention is presented in the
1270 * p00 _______ p10 _______ p20 _______ p30 _______
1271 * ----->| |----->| |----->| |----->| |----->
1272 * | 0 | | 1 | | 2 | | 3 |
1273 * ----->|_______|----->|_______|----->|_______|----->|_______|----->
1278 rte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
1280 struct rte_mbuf *pkt00, *pkt01, *pkt10, *pkt11, *pkt20, *pkt21, *pkt30, *pkt31, *pkt_last;
1281 struct rte_mbuf **q00_base, **q01_base, **q10_base, **q11_base, **q20_base, **q21_base, **q30_base, **q31_base, **q_last_base;
1282 uint32_t q00, q01, q10, q11, q20, q21, q30, q31, q_last;
1283 uint32_t r00, r01, r10, r11, r20, r21, r30, r31, r_last;
1288 /* Less then 6 input packets available, which is not enough to feed the pipeline */
1289 if (unlikely(n_pkts < 6)) {
1290 struct rte_mbuf **q_base[5];
1293 /* Prefetch the mbuf structure of each packet */
1294 for (i = 0; i < n_pkts; i ++) {
1295 rte_prefetch0(pkts[i]);
1298 /* Prefetch the queue structure for each queue */
1299 for (i = 0; i < n_pkts; i ++) {
1300 q[i] = rte_sched_port_enqueue_qptrs_prefetch0(port, pkts[i]);
1303 /* Prefetch the write pointer location of each queue */
1304 for (i = 0; i < n_pkts; i ++) {
1305 q_base[i] = rte_sched_port_qbase(port, q[i]);
1306 rte_sched_port_enqueue_qwa_prefetch0(port, q[i], q_base[i]);
1309 /* Write each packet to its queue */
1310 for (i = 0; i < n_pkts; i ++) {
1311 result += rte_sched_port_enqueue_qwa(port, q[i], q_base[i], pkts[i]);
1317 /* Feed the first 3 stages of the pipeline (6 packets needed) */
1320 rte_prefetch0(pkt20);
1321 rte_prefetch0(pkt21);
1325 rte_prefetch0(pkt10);
1326 rte_prefetch0(pkt11);
1328 q20 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt20);
1329 q21 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt21);
1333 rte_prefetch0(pkt00);
1334 rte_prefetch0(pkt01);
1336 q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1337 q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1339 q20_base = rte_sched_port_qbase(port, q20);
1340 q21_base = rte_sched_port_qbase(port, q21);
1341 rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1342 rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1344 /* Run the pipeline */
1345 for (i = 6; i < (n_pkts & (~1)); i += 2) {
1346 /* Propagate stage inputs */
1357 q30_base = q20_base;
1358 q31_base = q21_base;
1360 /* Stage 0: Get packets in */
1362 pkt01 = pkts[i + 1];
1363 rte_prefetch0(pkt00);
1364 rte_prefetch0(pkt01);
1366 /* Stage 1: Prefetch queue structure storing queue pointers */
1367 q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1368 q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1370 /* Stage 2: Prefetch queue write location */
1371 q20_base = rte_sched_port_qbase(port, q20);
1372 q21_base = rte_sched_port_qbase(port, q21);
1373 rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1374 rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1376 /* Stage 3: Write packet to queue and activate queue */
1377 r30 = rte_sched_port_enqueue_qwa(port, q30, q30_base, pkt30);
1378 r31 = rte_sched_port_enqueue_qwa(port, q31, q31_base, pkt31);
1379 result += r30 + r31;
1382 /* Drain the pipeline (exactly 6 packets). Handle the last packet in the case
1383 of an odd number of input packets. */
1384 pkt_last = pkts[n_pkts - 1];
1385 rte_prefetch0(pkt_last);
1387 q00 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt00);
1388 q01 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt01);
1390 q10_base = rte_sched_port_qbase(port, q10);
1391 q11_base = rte_sched_port_qbase(port, q11);
1392 rte_sched_port_enqueue_qwa_prefetch0(port, q10, q10_base);
1393 rte_sched_port_enqueue_qwa_prefetch0(port, q11, q11_base);
1395 r20 = rte_sched_port_enqueue_qwa(port, q20, q20_base, pkt20);
1396 r21 = rte_sched_port_enqueue_qwa(port, q21, q21_base, pkt21);
1397 result += r20 + r21;
1399 q_last = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt_last);
1401 q00_base = rte_sched_port_qbase(port, q00);
1402 q01_base = rte_sched_port_qbase(port, q01);
1403 rte_sched_port_enqueue_qwa_prefetch0(port, q00, q00_base);
1404 rte_sched_port_enqueue_qwa_prefetch0(port, q01, q01_base);
1406 r10 = rte_sched_port_enqueue_qwa(port, q10, q10_base, pkt10);
1407 r11 = rte_sched_port_enqueue_qwa(port, q11, q11_base, pkt11);
1408 result += r10 + r11;
1410 q_last_base = rte_sched_port_qbase(port, q_last);
1411 rte_sched_port_enqueue_qwa_prefetch0(port, q_last, q_last_base);
1413 r00 = rte_sched_port_enqueue_qwa(port, q00, q00_base, pkt00);
1414 r01 = rte_sched_port_enqueue_qwa(port, q01, q01_base, pkt01);
1415 result += r00 + r01;
1418 r_last = rte_sched_port_enqueue_qwa(port, q_last, q_last_base, pkt_last);
1425 #endif /* RTE_SCHED_ENQUEUE */
1427 #if RTE_SCHED_TS_CREDITS_UPDATE == 0
1429 #define grinder_credits_update(port, pos)
1431 #elif !defined(RTE_SCHED_SUBPORT_TC_OV)
1434 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1436 struct rte_sched_grinder *grinder = port->grinder + pos;
1437 struct rte_sched_subport *subport = grinder->subport;
1438 struct rte_sched_pipe *pipe = grinder->pipe;
1439 struct rte_sched_pipe_profile *params = grinder->pipe_params;
1443 n_periods = (port->time - subport->tb_time) / subport->tb_period;
1444 subport->tb_credits += n_periods * subport->tb_credits_per_period;
1445 subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1446 subport->tb_time += n_periods * subport->tb_period;
1449 n_periods = (port->time - pipe->tb_time) / params->tb_period;
1450 pipe->tb_credits += n_periods * params->tb_credits_per_period;
1451 pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1452 pipe->tb_time += n_periods * params->tb_period;
1455 if (unlikely(port->time >= subport->tc_time)) {
1456 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1457 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1458 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1459 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1460 subport->tc_time = port->time + subport->tc_period;
1464 if (unlikely(port->time >= pipe->tc_time)) {
1465 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1466 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1467 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1468 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1469 pipe->tc_time = port->time + params->tc_period;
1476 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1478 struct rte_sched_grinder *grinder = port->grinder + pos;
1479 struct rte_sched_subport *subport = grinder->subport;
1480 struct rte_sched_pipe *pipe = grinder->pipe;
1481 struct rte_sched_pipe_profile *params = grinder->pipe_params;
1485 n_periods = (port->time - subport->tb_time) / subport->tb_period;
1486 subport->tb_credits += n_periods * subport->tb_credits_per_period;
1487 subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1488 subport->tb_time += n_periods * subport->tb_period;
1491 n_periods = (port->time - pipe->tb_time) / params->tb_period;
1492 pipe->tb_credits += n_periods * params->tb_credits_per_period;
1493 pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1494 pipe->tb_time += n_periods * params->tb_period;
1497 if (unlikely(port->time >= subport->tc_ov_time)) {
1498 uint64_t n_ov_periods;
1500 if (unlikely(port->time >= subport->tc_time)) {
1501 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1502 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1503 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1504 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1506 subport->tc_time = port->time + subport->tc_period;
1509 n_ov_periods = (subport->tc_time - port->time + subport->tc_ov_period - 1) / subport->tc_ov_period;
1511 subport->tc_ov_credits[0] = subport->tc_credits[0] / (n_ov_periods * subport->tc_ov_n[0]);
1512 subport->tc_ov_credits[1] = subport->tc_credits[1] / (n_ov_periods * subport->tc_ov_n[1]);
1513 subport->tc_ov_credits[2] = subport->tc_credits[2] / (n_ov_periods * subport->tc_ov_n[2]);
1514 subport->tc_ov_credits[3] = subport->tc_credits[3] / (n_ov_periods * subport->tc_ov_n[3]);
1516 subport->tc_ov_time = port->time + subport->tc_ov_period;
1517 subport->tc_ov_period_id ++;
1521 if (unlikely(port->time >= pipe->tc_time)) {
1522 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1523 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1524 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1525 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1526 pipe->tc_time = port->time + params->tc_period;
1528 if (unlikely(pipe->tc_ov_period_id != subport->tc_ov_period_id)) {
1529 uint32_t pipe_tc_ov_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
1530 uint32_t tc_mask[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
1531 uint32_t mask[] = {UINT32_MAX, 0};
1533 tc_mask[0] = mask[subport->tc_ov[0]];
1534 tc_mask[1] = mask[subport->tc_ov[1]];
1535 tc_mask[2] = mask[subport->tc_ov[2]];
1536 tc_mask[3] = mask[subport->tc_ov[3]];
1538 pipe_tc_ov_credits[0] = subport->tc_ov_credits[0] * params->tc_ov_weight[0];
1539 pipe_tc_ov_credits[1] = subport->tc_ov_credits[1] * params->tc_ov_weight[1];
1540 pipe_tc_ov_credits[2] = subport->tc_ov_credits[2] * params->tc_ov_weight[2];
1541 pipe_tc_ov_credits[3] = subport->tc_ov_credits[3] * params->tc_ov_weight[3];
1543 pipe->tc_ov_credits[0] = (tc_mask[0] & pipe->tc_credits[0]) | ((~ tc_mask[0]) & pipe_tc_ov_credits[0]);
1544 pipe->tc_ov_credits[1] = (tc_mask[1] & pipe->tc_credits[1]) | ((~ tc_mask[1]) & pipe_tc_ov_credits[1]);
1545 pipe->tc_ov_credits[2] = (tc_mask[2] & pipe->tc_credits[2]) | ((~ tc_mask[2]) & pipe_tc_ov_credits[2]);
1546 pipe->tc_ov_credits[3] = (tc_mask[3] & pipe->tc_credits[3]) | ((~ tc_mask[3]) & pipe_tc_ov_credits[3]);
1548 pipe->tc_ov_period_id = subport->tc_ov_period_id;
1552 #endif /* RTE_SCHED_TS_CREDITS_UPDATE, RTE_SCHED_SUBPORT_TC_OV */
1554 #ifndef RTE_SCHED_SUBPORT_TC_OV
1557 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1559 struct rte_sched_grinder *grinder = port->grinder + pos;
1560 struct rte_sched_subport *subport = grinder->subport;
1561 struct rte_sched_pipe *pipe = grinder->pipe;
1562 struct rte_mbuf *pkt = grinder->pkt;
1563 uint32_t tc_index = grinder->tc_index;
1564 uint32_t pkt_len = pkt->pkt.pkt_len + port->frame_overhead;
1567 /* Check queue credits */
1568 enough_credits = (pkt_len <= subport->tb_credits) &&
1569 (pkt_len <= subport->tc_credits[tc_index]) &&
1570 (pkt_len <= pipe->tb_credits) &&
1571 (pkt_len <= pipe->tc_credits[tc_index]);
1573 if (!enough_credits) {
1577 /* Update port credits */
1578 subport->tb_credits -= pkt_len;
1579 subport->tc_credits[tc_index] -= pkt_len;
1580 pipe->tb_credits -= pkt_len;
1581 pipe->tc_credits[tc_index] -= pkt_len;
1589 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1591 struct rte_sched_grinder *grinder = port->grinder + pos;
1592 struct rte_sched_subport *subport = grinder->subport;
1593 struct rte_sched_pipe *pipe = grinder->pipe;
1594 struct rte_mbuf *pkt = grinder->pkt;
1595 uint32_t tc_index = grinder->tc_index;
1596 uint32_t pkt_len = pkt->pkt.pkt_len + port->frame_overhead;
1597 uint32_t subport_tb_credits = subport->tb_credits;
1598 uint32_t subport_tc_credits = subport->tc_credits[tc_index];
1599 uint32_t pipe_tb_credits = pipe->tb_credits;
1600 uint32_t pipe_tc_credits = pipe->tc_credits[tc_index];
1601 uint32_t pipe_tc_ov_credits = pipe->tc_ov_credits[tc_index];
1604 /* Check pipe and subport credits */
1605 enough_credits = (pkt_len <= subport_tb_credits) &&
1606 (pkt_len <= subport_tc_credits) &&
1607 (pkt_len <= pipe_tb_credits) &&
1608 (pkt_len <= pipe_tc_credits) &&
1609 (pkt_len <= pipe_tc_ov_credits);
1611 if (!enough_credits) {
1615 /* Update pipe and subport credits */
1616 subport->tb_credits -= pkt_len;
1617 subport->tc_credits[tc_index] -= pkt_len;
1618 pipe->tb_credits -= pkt_len;
1619 pipe->tc_credits[tc_index] -= pkt_len;
1620 pipe->tc_ov_credits[tc_index] -= pkt_len;
1625 #endif /* RTE_SCHED_SUBPORT_TC_OV */
1628 grinder_schedule(struct rte_sched_port *port, uint32_t pos)
1630 struct rte_sched_grinder *grinder = port->grinder + pos;
1631 struct rte_sched_queue *queue = grinder->queue[grinder->qpos];
1632 struct rte_mbuf *pkt = grinder->pkt;
1633 uint32_t pkt_len = pkt->pkt.pkt_len + port->frame_overhead;
1635 #if RTE_SCHED_TS_CREDITS_CHECK
1636 if (!grinder_credits_check(port, pos)) {
1641 /* Advance port time */
1642 port->time += pkt_len;
1645 port->pkts_out[port->n_pkts_out ++] = pkt;
1647 grinder->wrr_tokens[grinder->qpos] += pkt_len * grinder->wrr_cost[grinder->qpos];
1648 if (queue->qr == queue->qw) {
1649 uint32_t qindex = grinder->qindex[grinder->qpos];
1651 rte_bitmap_clear(port->bmp, qindex);
1652 grinder->qmask &= ~(1 << grinder->qpos);
1653 grinder->wrr_mask[grinder->qpos] = 0;
1654 rte_sched_port_set_queue_empty_timestamp(port, qindex);
1657 /* Reset pipe loop detection */
1658 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1659 grinder->productive = 1;
1664 #if RTE_SCHED_OPTIMIZATIONS
1667 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1669 __m128i index = _mm_set1_epi32 (base_pipe);
1670 __m128i pipes = _mm_load_si128((__m128i *)port->grinder_base_bmp_pos);
1671 __m128i res = _mm_cmpeq_epi32(pipes, index);
1672 pipes = _mm_load_si128((__m128i *)(port->grinder_base_bmp_pos + 4));
1673 pipes = _mm_cmpeq_epi32(pipes, index);
1674 res = _mm_or_si128(res, pipes);
1676 if (_mm_testz_si128(res, res))
1685 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1689 for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i ++) {
1690 if (port->grinder_base_bmp_pos[i] == base_pipe) {
1698 #endif /* RTE_SCHED_OPTIMIZATIONS */
1701 grinder_pcache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t bmp_pos, uint64_t bmp_slab)
1703 struct rte_sched_grinder *grinder = port->grinder + pos;
1706 grinder->pcache_w = 0;
1707 grinder->pcache_r = 0;
1709 w[0] = (uint16_t) bmp_slab;
1710 w[1] = (uint16_t) (bmp_slab >> 16);
1711 w[2] = (uint16_t) (bmp_slab >> 32);
1712 w[3] = (uint16_t) (bmp_slab >> 48);
1714 grinder->pcache_qmask[grinder->pcache_w] = w[0];
1715 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos;
1716 grinder->pcache_w += (w[0] != 0);
1718 grinder->pcache_qmask[grinder->pcache_w] = w[1];
1719 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 16;
1720 grinder->pcache_w += (w[1] != 0);
1722 grinder->pcache_qmask[grinder->pcache_w] = w[2];
1723 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 32;
1724 grinder->pcache_w += (w[2] != 0);
1726 grinder->pcache_qmask[grinder->pcache_w] = w[3];
1727 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 48;
1728 grinder->pcache_w += (w[3] != 0);
1732 grinder_tccache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t qindex, uint16_t qmask)
1734 struct rte_sched_grinder *grinder = port->grinder + pos;
1737 grinder->tccache_w = 0;
1738 grinder->tccache_r = 0;
1740 b[0] = (uint8_t) (qmask & 0xF);
1741 b[1] = (uint8_t) ((qmask >> 4) & 0xF);
1742 b[2] = (uint8_t) ((qmask >> 8) & 0xF);
1743 b[3] = (uint8_t) ((qmask >> 12) & 0xF);
1745 grinder->tccache_qmask[grinder->tccache_w] = b[0];
1746 grinder->tccache_qindex[grinder->tccache_w] = qindex;
1747 grinder->tccache_w += (b[0] != 0);
1749 grinder->tccache_qmask[grinder->tccache_w] = b[1];
1750 grinder->tccache_qindex[grinder->tccache_w] = qindex + 4;
1751 grinder->tccache_w += (b[1] != 0);
1753 grinder->tccache_qmask[grinder->tccache_w] = b[2];
1754 grinder->tccache_qindex[grinder->tccache_w] = qindex + 8;
1755 grinder->tccache_w += (b[2] != 0);
1757 grinder->tccache_qmask[grinder->tccache_w] = b[3];
1758 grinder->tccache_qindex[grinder->tccache_w] = qindex + 12;
1759 grinder->tccache_w += (b[3] != 0);
1763 grinder_next_tc(struct rte_sched_port *port, uint32_t pos)
1765 struct rte_sched_grinder *grinder = port->grinder + pos;
1766 struct rte_mbuf **qbase;
1770 if (grinder->tccache_r == grinder->tccache_w) {
1774 qindex = grinder->tccache_qindex[grinder->tccache_r];
1775 qbase = rte_sched_port_qbase(port, qindex);
1776 qsize = rte_sched_port_qsize(port, qindex);
1778 grinder->tc_index = (qindex >> 2) & 0x3;
1779 grinder->qmask = grinder->tccache_qmask[grinder->tccache_r];
1780 grinder->qsize = qsize;
1782 grinder->qindex[0] = qindex;
1783 grinder->qindex[1] = qindex + 1;
1784 grinder->qindex[2] = qindex + 2;
1785 grinder->qindex[3] = qindex + 3;
1787 grinder->queue[0] = port->queue + qindex;
1788 grinder->queue[1] = port->queue + qindex + 1;
1789 grinder->queue[2] = port->queue + qindex + 2;
1790 grinder->queue[3] = port->queue + qindex + 3;
1792 grinder->qbase[0] = qbase;
1793 grinder->qbase[1] = qbase + qsize;
1794 grinder->qbase[2] = qbase + 2 * qsize;
1795 grinder->qbase[3] = qbase + 3 * qsize;
1797 grinder->tccache_r ++;
1802 grinder_next_pipe(struct rte_sched_port *port, uint32_t pos)
1804 struct rte_sched_grinder *grinder = port->grinder + pos;
1805 uint32_t pipe_qindex;
1806 uint16_t pipe_qmask;
1808 if (grinder->pcache_r < grinder->pcache_w) {
1809 pipe_qmask = grinder->pcache_qmask[grinder->pcache_r];
1810 pipe_qindex = grinder->pcache_qindex[grinder->pcache_r];
1811 grinder->pcache_r ++;
1813 uint64_t bmp_slab = 0;
1814 uint32_t bmp_pos = 0;
1816 /* Get another non-empty pipe group */
1817 if (unlikely(rte_bitmap_scan(port->bmp, &bmp_pos, &bmp_slab) <= 0)) {
1822 debug_check_queue_slab(port, bmp_pos, bmp_slab);
1825 /* Return if pipe group already in one of the other grinders */
1826 port->grinder_base_bmp_pos[pos] = RTE_SCHED_BMP_POS_INVALID;
1827 if (unlikely(grinder_pipe_exists(port, bmp_pos))) {
1830 port->grinder_base_bmp_pos[pos] = bmp_pos;
1832 /* Install new pipe group into grinder's pipe cache */
1833 grinder_pcache_populate(port, pos, bmp_pos, bmp_slab);
1835 pipe_qmask = grinder->pcache_qmask[0];
1836 pipe_qindex = grinder->pcache_qindex[0];
1837 grinder->pcache_r = 1;
1840 /* Install new pipe in the grinder */
1841 grinder->pindex = pipe_qindex >> 4;
1842 grinder->subport = port->subport + (grinder->pindex / port->n_pipes_per_subport);
1843 grinder->pipe = port->pipe + grinder->pindex;
1844 grinder->pipe_params = NULL; /* to be set after the pipe structure is prefetched */
1845 grinder->productive = 0;
1847 grinder_tccache_populate(port, pos, pipe_qindex, pipe_qmask);
1848 grinder_next_tc(port, pos);
1850 /* Check for pipe exhaustion */
1851 if (grinder->pindex == port->pipe_loop) {
1852 port->pipe_exhaustion = 1;
1853 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1859 #if RTE_SCHED_WRR == 0
1861 #define grinder_wrr_load(a,b)
1863 #define grinder_wrr_store(a,b)
1866 grinder_wrr(struct rte_sched_port *port, uint32_t pos)
1868 struct rte_sched_grinder *grinder = port->grinder + pos;
1869 uint64_t slab = grinder->qmask;
1871 if (rte_bsf64(slab, &grinder->qpos) == 0) {
1872 rte_panic("grinder wrr\n");
1876 #elif RTE_SCHED_WRR == 1
1879 grinder_wrr_load(struct rte_sched_port *port, uint32_t pos)
1881 struct rte_sched_grinder *grinder = port->grinder + pos;
1882 struct rte_sched_pipe *pipe = grinder->pipe;
1883 struct rte_sched_pipe_profile *pipe_params = grinder->pipe_params;
1884 uint32_t tc_index = grinder->tc_index;
1885 uint32_t qmask = grinder->qmask;
1888 qindex = tc_index * 4;
1890 grinder->wrr_tokens[0] = ((uint16_t) pipe->wrr_tokens[qindex]) << RTE_SCHED_WRR_SHIFT;
1891 grinder->wrr_tokens[1] = ((uint16_t) pipe->wrr_tokens[qindex + 1]) << RTE_SCHED_WRR_SHIFT;
1892 grinder->wrr_tokens[2] = ((uint16_t) pipe->wrr_tokens[qindex + 2]) << RTE_SCHED_WRR_SHIFT;
1893 grinder->wrr_tokens[3] = ((uint16_t) pipe->wrr_tokens[qindex + 3]) << RTE_SCHED_WRR_SHIFT;
1895 grinder->wrr_mask[0] = (qmask & 0x1) * 0xFFFF;
1896 grinder->wrr_mask[1] = ((qmask >> 1) & 0x1) * 0xFFFF;
1897 grinder->wrr_mask[2] = ((qmask >> 2) & 0x1) * 0xFFFF;
1898 grinder->wrr_mask[3] = ((qmask >> 3) & 0x1) * 0xFFFF;
1900 grinder->wrr_cost[0] = pipe_params->wrr_cost[qindex];
1901 grinder->wrr_cost[1] = pipe_params->wrr_cost[qindex + 1];
1902 grinder->wrr_cost[2] = pipe_params->wrr_cost[qindex + 2];
1903 grinder->wrr_cost[3] = pipe_params->wrr_cost[qindex + 3];
1907 grinder_wrr_store(struct rte_sched_port *port, uint32_t pos)
1909 struct rte_sched_grinder *grinder = port->grinder + pos;
1910 struct rte_sched_pipe *pipe = grinder->pipe;
1911 uint32_t tc_index = grinder->tc_index;
1914 qindex = tc_index * 4;
1916 pipe->wrr_tokens[qindex] = (uint8_t) ((grinder->wrr_tokens[0] & grinder->wrr_mask[0]) >> RTE_SCHED_WRR_SHIFT);
1917 pipe->wrr_tokens[qindex + 1] = (uint8_t) ((grinder->wrr_tokens[1] & grinder->wrr_mask[1]) >> RTE_SCHED_WRR_SHIFT);
1918 pipe->wrr_tokens[qindex + 2] = (uint8_t) ((grinder->wrr_tokens[2] & grinder->wrr_mask[2]) >> RTE_SCHED_WRR_SHIFT);
1919 pipe->wrr_tokens[qindex + 3] = (uint8_t) ((grinder->wrr_tokens[3] & grinder->wrr_mask[3]) >> RTE_SCHED_WRR_SHIFT);
1923 grinder_wrr(struct rte_sched_port *port, uint32_t pos)
1925 struct rte_sched_grinder *grinder = port->grinder + pos;
1926 uint16_t wrr_tokens_min;
1928 grinder->wrr_tokens[0] |= ~grinder->wrr_mask[0];
1929 grinder->wrr_tokens[1] |= ~grinder->wrr_mask[1];
1930 grinder->wrr_tokens[2] |= ~grinder->wrr_mask[2];
1931 grinder->wrr_tokens[3] |= ~grinder->wrr_mask[3];
1933 grinder->qpos = rte_min_pos_4_u16(grinder->wrr_tokens);
1934 wrr_tokens_min = grinder->wrr_tokens[grinder->qpos];
1936 grinder->wrr_tokens[0] -= wrr_tokens_min;
1937 grinder->wrr_tokens[1] -= wrr_tokens_min;
1938 grinder->wrr_tokens[2] -= wrr_tokens_min;
1939 grinder->wrr_tokens[3] -= wrr_tokens_min;
1944 #error Invalid value for RTE_SCHED_WRR
1946 #endif /* RTE_SCHED_WRR */
1948 #define grinder_evict(port, pos)
1951 grinder_prefetch_pipe(struct rte_sched_port *port, uint32_t pos)
1953 struct rte_sched_grinder *grinder = port->grinder + pos;
1955 rte_prefetch0(grinder->pipe);
1956 rte_prefetch0(grinder->queue[0]);
1960 grinder_prefetch_tc_queue_arrays(struct rte_sched_port *port, uint32_t pos)
1962 struct rte_sched_grinder *grinder = port->grinder + pos;
1963 uint16_t qsize, qr[4];
1965 qsize = grinder->qsize;
1966 qr[0] = grinder->queue[0]->qr & (qsize - 1);
1967 qr[1] = grinder->queue[1]->qr & (qsize - 1);
1968 qr[2] = grinder->queue[2]->qr & (qsize - 1);
1969 qr[3] = grinder->queue[3]->qr & (qsize - 1);
1971 rte_prefetch0(grinder->qbase[0] + qr[0]);
1972 rte_prefetch0(grinder->qbase[1] + qr[1]);
1974 grinder_wrr_load(port, pos);
1975 grinder_wrr(port, pos);
1977 rte_prefetch0(grinder->qbase[2] + qr[2]);
1978 rte_prefetch0(grinder->qbase[3] + qr[3]);
1982 grinder_prefetch_mbuf(struct rte_sched_port *port, uint32_t pos)
1984 struct rte_sched_grinder *grinder = port->grinder + pos;
1985 uint32_t qpos = grinder->qpos;
1986 struct rte_mbuf **qbase = grinder->qbase[qpos];
1987 uint16_t qsize = grinder->qsize;
1988 uint16_t qr = grinder->queue[qpos]->qr & (qsize - 1);
1990 grinder->pkt = qbase[qr];
1991 rte_prefetch0(grinder->pkt);
1993 if (unlikely((qr & 0x7) == 7)) {
1994 uint16_t qr_next = (grinder->queue[qpos]->qr + 1) & (qsize - 1);
1996 rte_prefetch0(qbase + qr_next);
2000 static inline uint32_t
2001 grinder_handle(struct rte_sched_port *port, uint32_t pos)
2003 struct rte_sched_grinder *grinder = port->grinder + pos;
2005 switch (grinder->state) {
2006 case e_GRINDER_PREFETCH_PIPE:
2008 if (grinder_next_pipe(port, pos)) {
2009 grinder_prefetch_pipe(port, pos);
2010 port->busy_grinders ++;
2012 grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2019 case e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS:
2021 struct rte_sched_pipe *pipe = grinder->pipe;
2023 grinder->pipe_params = port->pipe_profiles + pipe->profile;
2024 grinder_prefetch_tc_queue_arrays(port, pos);
2025 grinder_credits_update(port, pos);
2027 grinder->state = e_GRINDER_PREFETCH_MBUF;
2031 case e_GRINDER_PREFETCH_MBUF:
2033 grinder_prefetch_mbuf(port, pos);
2035 grinder->state = e_GRINDER_READ_MBUF;
2039 case e_GRINDER_READ_MBUF:
2041 uint32_t result = 0;
2043 result = grinder_schedule(port, pos);
2045 /* Look for next packet within the same TC */
2046 if (result && grinder->qmask) {
2047 grinder_wrr(port, pos);
2048 grinder_prefetch_mbuf(port, pos);
2052 grinder_wrr_store(port, pos);
2054 /* Look for another active TC within same pipe */
2055 if (grinder_next_tc(port, pos)) {
2056 grinder_prefetch_tc_queue_arrays(port, pos);
2058 grinder->state = e_GRINDER_PREFETCH_MBUF;
2061 if ((grinder->productive == 0) && (port->pipe_loop == RTE_SCHED_PIPE_INVALID)) {
2062 port->pipe_loop = grinder->pindex;
2064 grinder_evict(port, pos);
2066 /* Look for another active pipe */
2067 if (grinder_next_pipe(port, pos)) {
2068 grinder_prefetch_pipe(port, pos);
2070 grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2074 /* No active pipe found */
2075 port->busy_grinders --;
2077 grinder->state = e_GRINDER_PREFETCH_PIPE;
2082 rte_panic("Algorithmic error (invalid state)\n");
2088 rte_sched_port_time_resync(struct rte_sched_port *port)
2090 uint64_t cycles = rte_get_tsc_cycles();
2091 uint64_t cycles_diff = cycles - port->time_cpu_cycles;
2092 double bytes_diff = ((double) cycles_diff) / port->cycles_per_byte;
2094 /* Advance port time */
2095 port->time_cpu_cycles = cycles;
2096 port->time_cpu_bytes += (uint64_t) bytes_diff;
2097 if (port->time < port->time_cpu_bytes) {
2098 port->time = port->time_cpu_bytes;
2101 /* Reset pipe loop detection */
2102 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
2106 rte_sched_port_exceptions(struct rte_sched_port *port)
2110 /* Check if any exception flag is set */
2111 exceptions = (port->busy_grinders == 0) ||
2112 (port->pipe_exhaustion == 1);
2114 /* Clear exception flags */
2115 port->pipe_exhaustion = 0;
2121 rte_sched_port_dequeue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
2125 port->pkts_out = pkts;
2126 port->n_pkts_out = 0;
2128 rte_sched_port_time_resync(port);
2130 /* Take each queue in the grinder one step further */
2131 for (i = 0, count = 0; ; i ++) {
2132 count += grinder_handle(port, i & (RTE_SCHED_PORT_N_GRINDERS - 1));
2133 if ((count == n_pkts) || rte_sched_port_exceptions(port)) {