4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <rte_common.h>
39 #include <rte_memory.h>
40 #include <rte_malloc.h>
41 #include <rte_cycles.h>
42 #include <rte_prefetch.h>
43 #include <rte_branch_prediction.h>
46 #include "rte_sched.h"
47 #include "rte_bitmap.h"
48 #include "rte_sched_common.h"
49 #include "rte_approx.h"
51 #ifdef __INTEL_COMPILER
52 #pragma warning(disable:2259) /* conversion may lose significant bits */
55 #ifdef RTE_SCHED_VECTOR
59 #define SCHED_VECTOR_SSE4
64 #define RTE_SCHED_TB_RATE_CONFIG_ERR (1e-7)
65 #define RTE_SCHED_WRR_SHIFT 3
66 #define RTE_SCHED_GRINDER_PCACHE_SIZE (64 / RTE_SCHED_QUEUES_PER_PIPE)
67 #define RTE_SCHED_PIPE_INVALID UINT32_MAX
68 #define RTE_SCHED_BMP_POS_INVALID UINT32_MAX
70 struct rte_sched_subport {
71 /* Token bucket (TB) */
72 uint64_t tb_time; /* time of last update */
74 uint32_t tb_credits_per_period;
78 /* Traffic classes (TCs) */
79 uint64_t tc_time; /* time of next update */
80 uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
81 uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
84 /* TC oversubscription */
86 uint32_t tc_ov_wm_min;
87 uint32_t tc_ov_wm_max;
88 uint8_t tc_ov_period_id;
94 struct rte_sched_subport_stats stats;
97 struct rte_sched_pipe_profile {
98 /* Token bucket (TB) */
100 uint32_t tb_credits_per_period;
103 /* Pipe traffic classes */
105 uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
106 uint8_t tc_ov_weight;
109 uint8_t wrr_cost[RTE_SCHED_QUEUES_PER_PIPE];
112 struct rte_sched_pipe {
113 /* Token bucket (TB) */
114 uint64_t tb_time; /* time of last update */
117 /* Pipe profile and flags */
120 /* Traffic classes (TCs) */
121 uint64_t tc_time; /* time of next update */
122 uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
124 /* Weighted Round Robin (WRR) */
125 uint8_t wrr_tokens[RTE_SCHED_QUEUES_PER_PIPE];
127 /* TC oversubscription */
128 uint32_t tc_ov_credits;
129 uint8_t tc_ov_period_id;
131 } __rte_cache_aligned;
133 struct rte_sched_queue {
138 struct rte_sched_queue_extra {
139 struct rte_sched_queue_stats stats;
146 e_GRINDER_PREFETCH_PIPE = 0,
147 e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS,
148 e_GRINDER_PREFETCH_MBUF,
153 * Path through the scheduler hierarchy used by the scheduler enqueue
154 * operation to identify the destination queue for the current
155 * packet. Stored in the field pkt.hash.sched of struct rte_mbuf of
156 * each packet, typically written by the classification stage and read
157 * by scheduler enqueue.
159 struct rte_sched_port_hierarchy {
160 uint16_t queue:2; /**< Queue ID (0 .. 3) */
161 uint16_t traffic_class:2; /**< Traffic class ID (0 .. 3)*/
162 uint32_t color:2; /**< Color */
164 uint16_t subport; /**< Subport ID */
165 uint32_t pipe; /**< Pipe ID */
168 struct rte_sched_grinder {
170 uint16_t pcache_qmask[RTE_SCHED_GRINDER_PCACHE_SIZE];
171 uint32_t pcache_qindex[RTE_SCHED_GRINDER_PCACHE_SIZE];
176 enum grinder_state state;
179 struct rte_sched_subport *subport;
180 struct rte_sched_pipe *pipe;
181 struct rte_sched_pipe_profile *pipe_params;
184 uint8_t tccache_qmask[4];
185 uint32_t tccache_qindex[4];
191 struct rte_sched_queue *queue[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
192 struct rte_mbuf **qbase[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
193 uint32_t qindex[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
197 struct rte_mbuf *pkt;
200 uint16_t wrr_tokens[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
201 uint16_t wrr_mask[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
202 uint8_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
205 struct rte_sched_port {
206 /* User parameters */
207 uint32_t n_subports_per_port;
208 uint32_t n_pipes_per_subport;
211 uint32_t frame_overhead;
212 uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
213 uint32_t n_pipe_profiles;
214 uint32_t pipe_tc3_rate_max;
216 struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][e_RTE_METER_COLORS];
220 uint64_t time_cpu_cycles; /* Current CPU time measured in CPU cyles */
221 uint64_t time_cpu_bytes; /* Current CPU time measured in bytes */
222 uint64_t time; /* Current NIC TX time measured in bytes */
223 double cycles_per_byte; /* CPU cycles per byte */
225 /* Scheduling loop detection */
227 uint32_t pipe_exhaustion;
230 struct rte_bitmap *bmp;
231 uint32_t grinder_base_bmp_pos[RTE_SCHED_PORT_N_GRINDERS] __rte_aligned_16;
234 struct rte_sched_grinder grinder[RTE_SCHED_PORT_N_GRINDERS];
235 uint32_t busy_grinders;
236 struct rte_mbuf **pkts_out;
239 /* Queue base calculation */
240 uint32_t qsize_add[RTE_SCHED_QUEUES_PER_PIPE];
243 /* Large data structures */
244 struct rte_sched_subport *subport;
245 struct rte_sched_pipe *pipe;
246 struct rte_sched_queue *queue;
247 struct rte_sched_queue_extra *queue_extra;
248 struct rte_sched_pipe_profile *pipe_profiles;
250 struct rte_mbuf **queue_array;
251 uint8_t memory[0] __rte_cache_aligned;
252 } __rte_cache_aligned;
254 enum rte_sched_port_array {
255 e_RTE_SCHED_PORT_ARRAY_SUBPORT = 0,
256 e_RTE_SCHED_PORT_ARRAY_PIPE,
257 e_RTE_SCHED_PORT_ARRAY_QUEUE,
258 e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA,
259 e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES,
260 e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY,
261 e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY,
262 e_RTE_SCHED_PORT_ARRAY_TOTAL,
265 #ifdef RTE_SCHED_COLLECT_STATS
267 static inline uint32_t
268 rte_sched_port_queues_per_subport(struct rte_sched_port *port)
270 return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport;
275 static inline uint32_t
276 rte_sched_port_queues_per_port(struct rte_sched_port *port)
278 return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport * port->n_subports_per_port;
281 static inline struct rte_mbuf **
282 rte_sched_port_qbase(struct rte_sched_port *port, uint32_t qindex)
284 uint32_t pindex = qindex >> 4;
285 uint32_t qpos = qindex & 0xF;
287 return (port->queue_array + pindex *
288 port->qsize_sum + port->qsize_add[qpos]);
291 static inline uint16_t
292 rte_sched_port_qsize(struct rte_sched_port *port, uint32_t qindex)
294 uint32_t tc = (qindex >> 2) & 0x3;
296 return port->qsize[tc];
300 rte_sched_port_check_params(struct rte_sched_port_params *params)
308 if ((params->socket < 0) || (params->socket >= RTE_MAX_NUMA_NODES))
312 if (params->rate == 0)
316 if (params->mtu == 0)
319 /* n_subports_per_port: non-zero, limited to 16 bits, power of 2 */
320 if (params->n_subports_per_port == 0 ||
321 params->n_subports_per_port > 1u << 16 ||
322 !rte_is_power_of_2(params->n_subports_per_port))
325 /* n_pipes_per_subport: non-zero, power of 2 */
326 if (params->n_pipes_per_subport == 0 ||
327 !rte_is_power_of_2(params->n_pipes_per_subport))
330 /* qsize: non-zero, power of 2,
331 * no bigger than 32K (due to 16-bit read/write pointers)
333 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
334 uint16_t qsize = params->qsize[i];
336 if (qsize == 0 || !rte_is_power_of_2(qsize))
340 /* pipe_profiles and n_pipe_profiles */
341 if (params->pipe_profiles == NULL ||
342 params->n_pipe_profiles == 0 ||
343 params->n_pipe_profiles > RTE_SCHED_PIPE_PROFILES_PER_PORT)
346 for (i = 0; i < params->n_pipe_profiles; i++) {
347 struct rte_sched_pipe_params *p = params->pipe_profiles + i;
349 /* TB rate: non-zero, not greater than port rate */
350 if (p->tb_rate == 0 || p->tb_rate > params->rate)
353 /* TB size: non-zero */
357 /* TC rate: non-zero, less than pipe rate */
358 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
359 if (p->tc_rate[j] == 0 || p->tc_rate[j] > p->tb_rate)
363 /* TC period: non-zero */
364 if (p->tc_period == 0)
367 #ifdef RTE_SCHED_SUBPORT_TC_OV
368 /* TC3 oversubscription weight: non-zero */
369 if (p->tc_ov_weight == 0)
373 /* Queue WRR weights: non-zero */
374 for (j = 0; j < RTE_SCHED_QUEUES_PER_PIPE; j++) {
375 if (p->wrr_weights[j] == 0)
384 rte_sched_port_get_array_base(struct rte_sched_port_params *params, enum rte_sched_port_array array)
386 uint32_t n_subports_per_port = params->n_subports_per_port;
387 uint32_t n_pipes_per_subport = params->n_pipes_per_subport;
388 uint32_t n_pipes_per_port = n_pipes_per_subport * n_subports_per_port;
389 uint32_t n_queues_per_port = RTE_SCHED_QUEUES_PER_PIPE * n_pipes_per_subport * n_subports_per_port;
391 uint32_t size_subport = n_subports_per_port * sizeof(struct rte_sched_subport);
392 uint32_t size_pipe = n_pipes_per_port * sizeof(struct rte_sched_pipe);
393 uint32_t size_queue = n_queues_per_port * sizeof(struct rte_sched_queue);
394 uint32_t size_queue_extra
395 = n_queues_per_port * sizeof(struct rte_sched_queue_extra);
396 uint32_t size_pipe_profiles
397 = RTE_SCHED_PIPE_PROFILES_PER_PORT * sizeof(struct rte_sched_pipe_profile);
398 uint32_t size_bmp_array = rte_bitmap_get_memory_footprint(n_queues_per_port);
399 uint32_t size_per_pipe_queue_array, size_queue_array;
403 size_per_pipe_queue_array = 0;
404 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
405 size_per_pipe_queue_array += RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS
406 * params->qsize[i] * sizeof(struct rte_mbuf *);
408 size_queue_array = n_pipes_per_port * size_per_pipe_queue_array;
412 if (array == e_RTE_SCHED_PORT_ARRAY_SUBPORT)
414 base += RTE_CACHE_LINE_ROUNDUP(size_subport);
416 if (array == e_RTE_SCHED_PORT_ARRAY_PIPE)
418 base += RTE_CACHE_LINE_ROUNDUP(size_pipe);
420 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE)
422 base += RTE_CACHE_LINE_ROUNDUP(size_queue);
424 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA)
426 base += RTE_CACHE_LINE_ROUNDUP(size_queue_extra);
428 if (array == e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES)
430 base += RTE_CACHE_LINE_ROUNDUP(size_pipe_profiles);
432 if (array == e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY)
434 base += RTE_CACHE_LINE_ROUNDUP(size_bmp_array);
436 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY)
438 base += RTE_CACHE_LINE_ROUNDUP(size_queue_array);
444 rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)
446 uint32_t size0, size1;
449 status = rte_sched_port_check_params(params);
451 RTE_LOG(NOTICE, SCHED,
452 "Port scheduler params check failed (%d)\n", status);
457 size0 = sizeof(struct rte_sched_port);
458 size1 = rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_TOTAL);
460 return size0 + size1;
464 rte_sched_port_config_qsize(struct rte_sched_port *port)
467 port->qsize_add[0] = 0;
468 port->qsize_add[1] = port->qsize_add[0] + port->qsize[0];
469 port->qsize_add[2] = port->qsize_add[1] + port->qsize[0];
470 port->qsize_add[3] = port->qsize_add[2] + port->qsize[0];
473 port->qsize_add[4] = port->qsize_add[3] + port->qsize[0];
474 port->qsize_add[5] = port->qsize_add[4] + port->qsize[1];
475 port->qsize_add[6] = port->qsize_add[5] + port->qsize[1];
476 port->qsize_add[7] = port->qsize_add[6] + port->qsize[1];
479 port->qsize_add[8] = port->qsize_add[7] + port->qsize[1];
480 port->qsize_add[9] = port->qsize_add[8] + port->qsize[2];
481 port->qsize_add[10] = port->qsize_add[9] + port->qsize[2];
482 port->qsize_add[11] = port->qsize_add[10] + port->qsize[2];
485 port->qsize_add[12] = port->qsize_add[11] + port->qsize[2];
486 port->qsize_add[13] = port->qsize_add[12] + port->qsize[3];
487 port->qsize_add[14] = port->qsize_add[13] + port->qsize[3];
488 port->qsize_add[15] = port->qsize_add[14] + port->qsize[3];
490 port->qsize_sum = port->qsize_add[15] + port->qsize[3];
494 rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)
496 struct rte_sched_pipe_profile *p = port->pipe_profiles + i;
498 RTE_LOG(DEBUG, SCHED, "Low level config for pipe profile %u:\n"
499 " Token bucket: period = %u, credits per period = %u, size = %u\n"
500 " Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\n"
501 " Traffic class 3 oversubscription: weight = %hhu\n"
502 " WRR cost: [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu]\n",
507 p->tb_credits_per_period,
510 /* Traffic classes */
512 p->tc_credits_per_period[0],
513 p->tc_credits_per_period[1],
514 p->tc_credits_per_period[2],
515 p->tc_credits_per_period[3],
517 /* Traffic class 3 oversubscription */
521 p->wrr_cost[ 0], p->wrr_cost[ 1], p->wrr_cost[ 2], p->wrr_cost[ 3],
522 p->wrr_cost[ 4], p->wrr_cost[ 5], p->wrr_cost[ 6], p->wrr_cost[ 7],
523 p->wrr_cost[ 8], p->wrr_cost[ 9], p->wrr_cost[10], p->wrr_cost[11],
524 p->wrr_cost[12], p->wrr_cost[13], p->wrr_cost[14], p->wrr_cost[15]);
527 static inline uint64_t
528 rte_sched_time_ms_to_bytes(uint32_t time_ms, uint32_t rate)
530 uint64_t time = time_ms;
532 time = (time * rate) / 1000;
538 rte_sched_port_config_pipe_profile_table(struct rte_sched_port *port, struct rte_sched_port_params *params)
542 for (i = 0; i < port->n_pipe_profiles; i++) {
543 struct rte_sched_pipe_params *src = params->pipe_profiles + i;
544 struct rte_sched_pipe_profile *dst = port->pipe_profiles + i;
547 if (src->tb_rate == params->rate) {
548 dst->tb_credits_per_period = 1;
551 double tb_rate = (double) src->tb_rate
552 / (double) params->rate;
553 double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
555 rte_approx(tb_rate, d,
556 &dst->tb_credits_per_period, &dst->tb_period);
558 dst->tb_size = src->tb_size;
560 /* Traffic Classes */
561 dst->tc_period = rte_sched_time_ms_to_bytes(src->tc_period,
564 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++)
565 dst->tc_credits_per_period[j]
566 = rte_sched_time_ms_to_bytes(src->tc_period,
569 #ifdef RTE_SCHED_SUBPORT_TC_OV
570 dst->tc_ov_weight = src->tc_ov_weight;
574 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
575 uint32_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
576 uint32_t lcd, lcd1, lcd2;
579 qindex = j * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS;
581 wrr_cost[0] = src->wrr_weights[qindex];
582 wrr_cost[1] = src->wrr_weights[qindex + 1];
583 wrr_cost[2] = src->wrr_weights[qindex + 2];
584 wrr_cost[3] = src->wrr_weights[qindex + 3];
586 lcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]);
587 lcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]);
588 lcd = rte_get_lcd(lcd1, lcd2);
590 wrr_cost[0] = lcd / wrr_cost[0];
591 wrr_cost[1] = lcd / wrr_cost[1];
592 wrr_cost[2] = lcd / wrr_cost[2];
593 wrr_cost[3] = lcd / wrr_cost[3];
595 dst->wrr_cost[qindex] = (uint8_t) wrr_cost[0];
596 dst->wrr_cost[qindex + 1] = (uint8_t) wrr_cost[1];
597 dst->wrr_cost[qindex + 2] = (uint8_t) wrr_cost[2];
598 dst->wrr_cost[qindex + 3] = (uint8_t) wrr_cost[3];
601 rte_sched_port_log_pipe_profile(port, i);
604 port->pipe_tc3_rate_max = 0;
605 for (i = 0; i < port->n_pipe_profiles; i++) {
606 struct rte_sched_pipe_params *src = params->pipe_profiles + i;
607 uint32_t pipe_tc3_rate = src->tc_rate[3];
609 if (port->pipe_tc3_rate_max < pipe_tc3_rate)
610 port->pipe_tc3_rate_max = pipe_tc3_rate;
614 struct rte_sched_port *
615 rte_sched_port_config(struct rte_sched_port_params *params)
617 struct rte_sched_port *port = NULL;
618 uint32_t mem_size, bmp_mem_size, n_queues_per_port, i;
620 /* Check user parameters. Determine the amount of memory to allocate */
621 mem_size = rte_sched_port_get_memory_footprint(params);
625 /* Allocate memory to store the data structures */
626 port = rte_zmalloc("qos_params", mem_size, RTE_CACHE_LINE_SIZE);
630 /* compile time checks */
631 RTE_BUILD_BUG_ON(RTE_SCHED_PORT_N_GRINDERS == 0);
632 RTE_BUILD_BUG_ON(RTE_SCHED_PORT_N_GRINDERS & (RTE_SCHED_PORT_N_GRINDERS - 1));
634 /* User parameters */
635 port->n_subports_per_port = params->n_subports_per_port;
636 port->n_pipes_per_subport = params->n_pipes_per_subport;
637 port->rate = params->rate;
638 port->mtu = params->mtu + params->frame_overhead;
639 port->frame_overhead = params->frame_overhead;
640 memcpy(port->qsize, params->qsize, sizeof(params->qsize));
641 port->n_pipe_profiles = params->n_pipe_profiles;
644 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
647 for (j = 0; j < e_RTE_METER_COLORS; j++) {
648 /* if min/max are both zero, then RED is disabled */
649 if ((params->red_params[i][j].min_th |
650 params->red_params[i][j].max_th) == 0) {
654 if (rte_red_config_init(&port->red_config[i][j],
655 params->red_params[i][j].wq_log2,
656 params->red_params[i][j].min_th,
657 params->red_params[i][j].max_th,
658 params->red_params[i][j].maxp_inv) != 0) {
666 port->time_cpu_cycles = rte_get_tsc_cycles();
667 port->time_cpu_bytes = 0;
669 port->cycles_per_byte = ((double) rte_get_tsc_hz()) / ((double) params->rate);
671 /* Scheduling loop detection */
672 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
673 port->pipe_exhaustion = 0;
676 port->busy_grinders = 0;
677 port->pkts_out = NULL;
678 port->n_pkts_out = 0;
680 /* Queue base calculation */
681 rte_sched_port_config_qsize(port);
683 /* Large data structures */
684 port->subport = (struct rte_sched_subport *)
685 (port->memory + rte_sched_port_get_array_base(params,
686 e_RTE_SCHED_PORT_ARRAY_SUBPORT));
687 port->pipe = (struct rte_sched_pipe *)
688 (port->memory + rte_sched_port_get_array_base(params,
689 e_RTE_SCHED_PORT_ARRAY_PIPE));
690 port->queue = (struct rte_sched_queue *)
691 (port->memory + rte_sched_port_get_array_base(params,
692 e_RTE_SCHED_PORT_ARRAY_QUEUE));
693 port->queue_extra = (struct rte_sched_queue_extra *)
694 (port->memory + rte_sched_port_get_array_base(params,
695 e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA));
696 port->pipe_profiles = (struct rte_sched_pipe_profile *)
697 (port->memory + rte_sched_port_get_array_base(params,
698 e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES));
699 port->bmp_array = port->memory
700 + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY);
701 port->queue_array = (struct rte_mbuf **)
702 (port->memory + rte_sched_port_get_array_base(params,
703 e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY));
705 /* Pipe profile table */
706 rte_sched_port_config_pipe_profile_table(port, params);
709 n_queues_per_port = rte_sched_port_queues_per_port(port);
710 bmp_mem_size = rte_bitmap_get_memory_footprint(n_queues_per_port);
711 port->bmp = rte_bitmap_init(n_queues_per_port, port->bmp_array,
713 if (port->bmp == NULL) {
714 RTE_LOG(ERR, SCHED, "Bitmap init error\n");
718 for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i++)
719 port->grinder_base_bmp_pos[i] = RTE_SCHED_PIPE_INVALID;
726 rte_sched_port_free(struct rte_sched_port *port)
730 /* Check user parameters */
734 /* Free enqueued mbufs */
735 for (queue = 0; queue < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; queue++) {
736 struct rte_mbuf **mbufs = rte_sched_port_qbase(port, queue);
739 for (i = 0; i < rte_sched_port_qsize(port, queue); i++)
740 rte_pktmbuf_free(mbufs[i]);
743 rte_bitmap_free(port->bmp);
748 rte_sched_port_log_subport_config(struct rte_sched_port *port, uint32_t i)
750 struct rte_sched_subport *s = port->subport + i;
752 RTE_LOG(DEBUG, SCHED, "Low level config for subport %u:\n"
753 " Token bucket: period = %u, credits per period = %u, size = %u\n"
754 " Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\n"
755 " Traffic class 3 oversubscription: wm min = %u, wm max = %u\n",
760 s->tb_credits_per_period,
763 /* Traffic classes */
765 s->tc_credits_per_period[0],
766 s->tc_credits_per_period[1],
767 s->tc_credits_per_period[2],
768 s->tc_credits_per_period[3],
770 /* Traffic class 3 oversubscription */
776 rte_sched_subport_config(struct rte_sched_port *port,
778 struct rte_sched_subport_params *params)
780 struct rte_sched_subport *s;
783 /* Check user parameters */
785 subport_id >= port->n_subports_per_port ||
789 if (params->tb_rate == 0 || params->tb_rate > port->rate)
792 if (params->tb_size == 0)
795 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
796 if (params->tc_rate[i] == 0 ||
797 params->tc_rate[i] > params->tb_rate)
801 if (params->tc_period == 0)
804 s = port->subport + subport_id;
806 /* Token Bucket (TB) */
807 if (params->tb_rate == port->rate) {
808 s->tb_credits_per_period = 1;
811 double tb_rate = ((double) params->tb_rate) / ((double) port->rate);
812 double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
814 rte_approx(tb_rate, d, &s->tb_credits_per_period, &s->tb_period);
817 s->tb_size = params->tb_size;
818 s->tb_time = port->time;
819 s->tb_credits = s->tb_size / 2;
821 /* Traffic Classes (TCs) */
822 s->tc_period = rte_sched_time_ms_to_bytes(params->tc_period, port->rate);
823 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
824 s->tc_credits_per_period[i]
825 = rte_sched_time_ms_to_bytes(params->tc_period,
828 s->tc_time = port->time + s->tc_period;
829 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)
830 s->tc_credits[i] = s->tc_credits_per_period[i];
832 #ifdef RTE_SCHED_SUBPORT_TC_OV
833 /* TC oversubscription */
834 s->tc_ov_wm_min = port->mtu;
835 s->tc_ov_wm_max = rte_sched_time_ms_to_bytes(params->tc_period,
836 port->pipe_tc3_rate_max);
837 s->tc_ov_wm = s->tc_ov_wm_max;
838 s->tc_ov_period_id = 0;
844 rte_sched_port_log_subport_config(port, subport_id);
850 rte_sched_pipe_config(struct rte_sched_port *port,
853 int32_t pipe_profile)
855 struct rte_sched_subport *s;
856 struct rte_sched_pipe *p;
857 struct rte_sched_pipe_profile *params;
858 uint32_t deactivate, profile, i;
860 /* Check user parameters */
861 profile = (uint32_t) pipe_profile;
862 deactivate = (pipe_profile < 0);
865 subport_id >= port->n_subports_per_port ||
866 pipe_id >= port->n_pipes_per_subport ||
867 (!deactivate && profile >= port->n_pipe_profiles))
871 /* Check that subport configuration is valid */
872 s = port->subport + subport_id;
873 if (s->tb_period == 0)
876 p = port->pipe + (subport_id * port->n_pipes_per_subport + pipe_id);
878 /* Handle the case when pipe already has a valid configuration */
880 params = port->pipe_profiles + p->profile;
882 #ifdef RTE_SCHED_SUBPORT_TC_OV
883 double subport_tc3_rate = (double) s->tc_credits_per_period[3]
884 / (double) s->tc_period;
885 double pipe_tc3_rate = (double) params->tc_credits_per_period[3]
886 / (double) params->tc_period;
887 uint32_t tc3_ov = s->tc_ov;
889 /* Unplug pipe from its subport */
890 s->tc_ov_n -= params->tc_ov_weight;
891 s->tc_ov_rate -= pipe_tc3_rate;
892 s->tc_ov = s->tc_ov_rate > subport_tc3_rate;
894 if (s->tc_ov != tc3_ov) {
895 RTE_LOG(DEBUG, SCHED,
896 "Subport %u TC3 oversubscription is OFF (%.4lf >= %.4lf)\n",
897 subport_id, subport_tc3_rate, s->tc_ov_rate);
902 memset(p, 0, sizeof(struct rte_sched_pipe));
908 /* Apply the new pipe configuration */
909 p->profile = profile;
910 params = port->pipe_profiles + p->profile;
912 /* Token Bucket (TB) */
913 p->tb_time = port->time;
914 p->tb_credits = params->tb_size / 2;
916 /* Traffic Classes (TCs) */
917 p->tc_time = port->time + params->tc_period;
918 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)
919 p->tc_credits[i] = params->tc_credits_per_period[i];
921 #ifdef RTE_SCHED_SUBPORT_TC_OV
923 /* Subport TC3 oversubscription */
924 double subport_tc3_rate = (double) s->tc_credits_per_period[3]
925 / (double) s->tc_period;
926 double pipe_tc3_rate = (double) params->tc_credits_per_period[3]
927 / (double) params->tc_period;
928 uint32_t tc3_ov = s->tc_ov;
930 s->tc_ov_n += params->tc_ov_weight;
931 s->tc_ov_rate += pipe_tc3_rate;
932 s->tc_ov = s->tc_ov_rate > subport_tc3_rate;
934 if (s->tc_ov != tc3_ov) {
935 RTE_LOG(DEBUG, SCHED,
936 "Subport %u TC3 oversubscription is ON (%.4lf < %.4lf)\n",
937 subport_id, subport_tc3_rate, s->tc_ov_rate);
939 p->tc_ov_period_id = s->tc_ov_period_id;
940 p->tc_ov_credits = s->tc_ov_wm;
948 rte_sched_port_pkt_write(struct rte_mbuf *pkt,
949 uint32_t subport, uint32_t pipe, uint32_t traffic_class,
950 uint32_t queue, enum rte_meter_color color)
952 struct rte_sched_port_hierarchy *sched
953 = (struct rte_sched_port_hierarchy *) &pkt->hash.sched;
955 RTE_BUILD_BUG_ON(sizeof(*sched) > sizeof(pkt->hash.sched));
957 sched->color = (uint32_t) color;
958 sched->subport = subport;
960 sched->traffic_class = traffic_class;
961 sched->queue = queue;
965 rte_sched_port_pkt_read_tree_path(const struct rte_mbuf *pkt,
966 uint32_t *subport, uint32_t *pipe,
967 uint32_t *traffic_class, uint32_t *queue)
969 const struct rte_sched_port_hierarchy *sched
970 = (const struct rte_sched_port_hierarchy *) &pkt->hash.sched;
972 *subport = sched->subport;
974 *traffic_class = sched->traffic_class;
975 *queue = sched->queue;
979 rte_sched_port_pkt_read_color(const struct rte_mbuf *pkt)
981 const struct rte_sched_port_hierarchy *sched
982 = (const struct rte_sched_port_hierarchy *) &pkt->hash.sched;
984 return (enum rte_meter_color) sched->color;
988 rte_sched_subport_read_stats(struct rte_sched_port *port,
990 struct rte_sched_subport_stats *stats,
993 struct rte_sched_subport *s;
995 /* Check user parameters */
996 if (port == NULL || subport_id >= port->n_subports_per_port ||
997 stats == NULL || tc_ov == NULL)
1000 s = port->subport + subport_id;
1002 /* Copy subport stats and clear */
1003 memcpy(stats, &s->stats, sizeof(struct rte_sched_subport_stats));
1004 memset(&s->stats, 0, sizeof(struct rte_sched_subport_stats));
1006 /* Subport TC ovesubscription status */
1013 rte_sched_queue_read_stats(struct rte_sched_port *port,
1015 struct rte_sched_queue_stats *stats,
1018 struct rte_sched_queue *q;
1019 struct rte_sched_queue_extra *qe;
1021 /* Check user parameters */
1022 if ((port == NULL) ||
1023 (queue_id >= rte_sched_port_queues_per_port(port)) ||
1028 q = port->queue + queue_id;
1029 qe = port->queue_extra + queue_id;
1031 /* Copy queue stats and clear */
1032 memcpy(stats, &qe->stats, sizeof(struct rte_sched_queue_stats));
1033 memset(&qe->stats, 0, sizeof(struct rte_sched_queue_stats));
1036 *qlen = q->qw - q->qr;
1041 static inline uint32_t
1042 rte_sched_port_qindex(struct rte_sched_port *port, uint32_t subport, uint32_t pipe, uint32_t traffic_class, uint32_t queue)
1046 result = subport * port->n_pipes_per_subport + pipe;
1047 result = result * RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE + traffic_class;
1048 result = result * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS + queue;
1053 #ifdef RTE_SCHED_DEBUG
1056 rte_sched_port_queue_is_empty(struct rte_sched_port *port, uint32_t qindex)
1058 struct rte_sched_queue *queue = port->queue + qindex;
1060 return queue->qr == queue->qw;
1063 #endif /* RTE_SCHED_DEBUG */
1065 #ifdef RTE_SCHED_COLLECT_STATS
1068 rte_sched_port_update_subport_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1070 struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1071 uint32_t tc_index = (qindex >> 2) & 0x3;
1072 uint32_t pkt_len = pkt->pkt_len;
1074 s->stats.n_pkts_tc[tc_index] += 1;
1075 s->stats.n_bytes_tc[tc_index] += pkt_len;
1079 rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1081 struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1082 uint32_t tc_index = (qindex >> 2) & 0x3;
1083 uint32_t pkt_len = pkt->pkt_len;
1085 s->stats.n_pkts_tc_dropped[tc_index] += 1;
1086 s->stats.n_bytes_tc_dropped[tc_index] += pkt_len;
1090 rte_sched_port_update_queue_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1092 struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1093 uint32_t pkt_len = pkt->pkt_len;
1095 qe->stats.n_pkts += 1;
1096 qe->stats.n_bytes += pkt_len;
1100 rte_sched_port_update_queue_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1102 struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1103 uint32_t pkt_len = pkt->pkt_len;
1105 qe->stats.n_pkts_dropped += 1;
1106 qe->stats.n_bytes_dropped += pkt_len;
1109 #endif /* RTE_SCHED_COLLECT_STATS */
1111 #ifdef RTE_SCHED_RED
1114 rte_sched_port_red_drop(struct rte_sched_port *port, struct rte_mbuf *pkt, uint32_t qindex, uint16_t qlen)
1116 struct rte_sched_queue_extra *qe;
1117 struct rte_red_config *red_cfg;
1118 struct rte_red *red;
1120 enum rte_meter_color color;
1122 tc_index = (qindex >> 2) & 0x3;
1123 color = rte_sched_port_pkt_read_color(pkt);
1124 red_cfg = &port->red_config[tc_index][color];
1126 if ((red_cfg->min_th | red_cfg->max_th) == 0)
1129 qe = port->queue_extra + qindex;
1132 return rte_red_enqueue(red_cfg, red, qlen, port->time);
1136 rte_sched_port_set_queue_empty_timestamp(struct rte_sched_port *port, uint32_t qindex)
1138 struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1139 struct rte_red *red = &qe->red;
1141 rte_red_mark_queue_empty(red, port->time);
1146 #define rte_sched_port_red_drop(port, pkt, qindex, qlen) 0
1148 #define rte_sched_port_set_queue_empty_timestamp(port, qindex)
1150 #endif /* RTE_SCHED_RED */
1152 #ifdef RTE_SCHED_DEBUG
1155 debug_check_queue_slab(struct rte_sched_port *port, uint32_t bmp_pos,
1162 rte_panic("Empty slab at position %u\n", bmp_pos);
1165 for (i = 0, mask = 1; i < 64; i++, mask <<= 1) {
1166 if (mask & bmp_slab) {
1167 if (rte_sched_port_queue_is_empty(port, bmp_pos + i)) {
1168 printf("Queue %u (slab offset %u) is empty\n", bmp_pos + i, i);
1175 rte_panic("Empty queues in slab 0x%" PRIx64 "starting at position %u\n",
1179 #endif /* RTE_SCHED_DEBUG */
1181 static inline uint32_t
1182 rte_sched_port_enqueue_qptrs_prefetch0(struct rte_sched_port *port,
1183 struct rte_mbuf *pkt)
1185 struct rte_sched_queue *q;
1186 #ifdef RTE_SCHED_COLLECT_STATS
1187 struct rte_sched_queue_extra *qe;
1189 uint32_t subport, pipe, traffic_class, queue, qindex;
1191 rte_sched_port_pkt_read_tree_path(pkt, &subport, &pipe, &traffic_class, &queue);
1193 qindex = rte_sched_port_qindex(port, subport, pipe, traffic_class, queue);
1194 q = port->queue + qindex;
1196 #ifdef RTE_SCHED_COLLECT_STATS
1197 qe = port->queue_extra + qindex;
1205 rte_sched_port_enqueue_qwa_prefetch0(struct rte_sched_port *port,
1206 uint32_t qindex, struct rte_mbuf **qbase)
1208 struct rte_sched_queue *q;
1209 struct rte_mbuf **q_qw;
1212 q = port->queue + qindex;
1213 qsize = rte_sched_port_qsize(port, qindex);
1214 q_qw = qbase + (q->qw & (qsize - 1));
1216 rte_prefetch0(q_qw);
1217 rte_bitmap_prefetch0(port->bmp, qindex);
1221 rte_sched_port_enqueue_qwa(struct rte_sched_port *port, uint32_t qindex,
1222 struct rte_mbuf **qbase, struct rte_mbuf *pkt)
1224 struct rte_sched_queue *q;
1228 q = port->queue + qindex;
1229 qsize = rte_sched_port_qsize(port, qindex);
1230 qlen = q->qw - q->qr;
1232 /* Drop the packet (and update drop stats) when queue is full */
1233 if (unlikely(rte_sched_port_red_drop(port, pkt, qindex, qlen) ||
1235 rte_pktmbuf_free(pkt);
1236 #ifdef RTE_SCHED_COLLECT_STATS
1237 rte_sched_port_update_subport_stats_on_drop(port, qindex, pkt);
1238 rte_sched_port_update_queue_stats_on_drop(port, qindex, pkt);
1243 /* Enqueue packet */
1244 qbase[q->qw & (qsize - 1)] = pkt;
1247 /* Activate queue in the port bitmap */
1248 rte_bitmap_set(port->bmp, qindex);
1251 #ifdef RTE_SCHED_COLLECT_STATS
1252 rte_sched_port_update_subport_stats(port, qindex, pkt);
1253 rte_sched_port_update_queue_stats(port, qindex, pkt);
1261 * The enqueue function implements a 4-level pipeline with each stage
1262 * processing two different packets. The purpose of using a pipeline
1263 * is to hide the latency of prefetching the data structures. The
1264 * naming convention is presented in the diagram below:
1266 * p00 _______ p10 _______ p20 _______ p30 _______
1267 * ----->| |----->| |----->| |----->| |----->
1268 * | 0 | | 1 | | 2 | | 3 |
1269 * ----->|_______|----->|_______|----->|_______|----->|_______|----->
1274 rte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts,
1277 struct rte_mbuf *pkt00, *pkt01, *pkt10, *pkt11, *pkt20, *pkt21,
1278 *pkt30, *pkt31, *pkt_last;
1279 struct rte_mbuf **q00_base, **q01_base, **q10_base, **q11_base,
1280 **q20_base, **q21_base, **q30_base, **q31_base, **q_last_base;
1281 uint32_t q00, q01, q10, q11, q20, q21, q30, q31, q_last;
1282 uint32_t r00, r01, r10, r11, r20, r21, r30, r31, r_last;
1288 * Less then 6 input packets available, which is not enough to
1291 if (unlikely(n_pkts < 6)) {
1292 struct rte_mbuf **q_base[5];
1295 /* Prefetch the mbuf structure of each packet */
1296 for (i = 0; i < n_pkts; i++)
1297 rte_prefetch0(pkts[i]);
1299 /* Prefetch the queue structure for each queue */
1300 for (i = 0; i < n_pkts; i++)
1301 q[i] = rte_sched_port_enqueue_qptrs_prefetch0(port,
1304 /* Prefetch the write pointer location of each queue */
1305 for (i = 0; i < n_pkts; i++) {
1306 q_base[i] = rte_sched_port_qbase(port, q[i]);
1307 rte_sched_port_enqueue_qwa_prefetch0(port, q[i],
1311 /* Write each packet to its queue */
1312 for (i = 0; i < n_pkts; i++)
1313 result += rte_sched_port_enqueue_qwa(port, q[i],
1314 q_base[i], pkts[i]);
1319 /* Feed the first 3 stages of the pipeline (6 packets needed) */
1322 rte_prefetch0(pkt20);
1323 rte_prefetch0(pkt21);
1327 rte_prefetch0(pkt10);
1328 rte_prefetch0(pkt11);
1330 q20 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt20);
1331 q21 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt21);
1335 rte_prefetch0(pkt00);
1336 rte_prefetch0(pkt01);
1338 q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1339 q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1341 q20_base = rte_sched_port_qbase(port, q20);
1342 q21_base = rte_sched_port_qbase(port, q21);
1343 rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1344 rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1346 /* Run the pipeline */
1347 for (i = 6; i < (n_pkts & (~1)); i += 2) {
1348 /* Propagate stage inputs */
1359 q30_base = q20_base;
1360 q31_base = q21_base;
1362 /* Stage 0: Get packets in */
1364 pkt01 = pkts[i + 1];
1365 rte_prefetch0(pkt00);
1366 rte_prefetch0(pkt01);
1368 /* Stage 1: Prefetch queue structure storing queue pointers */
1369 q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1370 q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1372 /* Stage 2: Prefetch queue write location */
1373 q20_base = rte_sched_port_qbase(port, q20);
1374 q21_base = rte_sched_port_qbase(port, q21);
1375 rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1376 rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1378 /* Stage 3: Write packet to queue and activate queue */
1379 r30 = rte_sched_port_enqueue_qwa(port, q30, q30_base, pkt30);
1380 r31 = rte_sched_port_enqueue_qwa(port, q31, q31_base, pkt31);
1381 result += r30 + r31;
1385 * Drain the pipeline (exactly 6 packets).
1386 * Handle the last packet in the case
1387 * of an odd number of input packets.
1389 pkt_last = pkts[n_pkts - 1];
1390 rte_prefetch0(pkt_last);
1392 q00 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt00);
1393 q01 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt01);
1395 q10_base = rte_sched_port_qbase(port, q10);
1396 q11_base = rte_sched_port_qbase(port, q11);
1397 rte_sched_port_enqueue_qwa_prefetch0(port, q10, q10_base);
1398 rte_sched_port_enqueue_qwa_prefetch0(port, q11, q11_base);
1400 r20 = rte_sched_port_enqueue_qwa(port, q20, q20_base, pkt20);
1401 r21 = rte_sched_port_enqueue_qwa(port, q21, q21_base, pkt21);
1402 result += r20 + r21;
1404 q_last = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt_last);
1406 q00_base = rte_sched_port_qbase(port, q00);
1407 q01_base = rte_sched_port_qbase(port, q01);
1408 rte_sched_port_enqueue_qwa_prefetch0(port, q00, q00_base);
1409 rte_sched_port_enqueue_qwa_prefetch0(port, q01, q01_base);
1411 r10 = rte_sched_port_enqueue_qwa(port, q10, q10_base, pkt10);
1412 r11 = rte_sched_port_enqueue_qwa(port, q11, q11_base, pkt11);
1413 result += r10 + r11;
1415 q_last_base = rte_sched_port_qbase(port, q_last);
1416 rte_sched_port_enqueue_qwa_prefetch0(port, q_last, q_last_base);
1418 r00 = rte_sched_port_enqueue_qwa(port, q00, q00_base, pkt00);
1419 r01 = rte_sched_port_enqueue_qwa(port, q01, q01_base, pkt01);
1420 result += r00 + r01;
1423 r_last = rte_sched_port_enqueue_qwa(port, q_last, q_last_base, pkt_last);
1430 #ifndef RTE_SCHED_SUBPORT_TC_OV
1433 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1435 struct rte_sched_grinder *grinder = port->grinder + pos;
1436 struct rte_sched_subport *subport = grinder->subport;
1437 struct rte_sched_pipe *pipe = grinder->pipe;
1438 struct rte_sched_pipe_profile *params = grinder->pipe_params;
1442 n_periods = (port->time - subport->tb_time) / subport->tb_period;
1443 subport->tb_credits += n_periods * subport->tb_credits_per_period;
1444 subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1445 subport->tb_time += n_periods * subport->tb_period;
1448 n_periods = (port->time - pipe->tb_time) / params->tb_period;
1449 pipe->tb_credits += n_periods * params->tb_credits_per_period;
1450 pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1451 pipe->tb_time += n_periods * params->tb_period;
1454 if (unlikely(port->time >= subport->tc_time)) {
1455 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1456 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1457 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1458 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1459 subport->tc_time = port->time + subport->tc_period;
1463 if (unlikely(port->time >= pipe->tc_time)) {
1464 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1465 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1466 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1467 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1468 pipe->tc_time = port->time + params->tc_period;
1474 static inline uint32_t
1475 grinder_tc_ov_credits_update(struct rte_sched_port *port, uint32_t pos)
1477 struct rte_sched_grinder *grinder = port->grinder + pos;
1478 struct rte_sched_subport *subport = grinder->subport;
1479 uint32_t tc_ov_consumption[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
1480 uint32_t tc_ov_consumption_max;
1481 uint32_t tc_ov_wm = subport->tc_ov_wm;
1483 if (subport->tc_ov == 0)
1484 return subport->tc_ov_wm_max;
1486 tc_ov_consumption[0] = subport->tc_credits_per_period[0] - subport->tc_credits[0];
1487 tc_ov_consumption[1] = subport->tc_credits_per_period[1] - subport->tc_credits[1];
1488 tc_ov_consumption[2] = subport->tc_credits_per_period[2] - subport->tc_credits[2];
1489 tc_ov_consumption[3] = subport->tc_credits_per_period[3] - subport->tc_credits[3];
1491 tc_ov_consumption_max = subport->tc_credits_per_period[3] -
1492 (tc_ov_consumption[0] + tc_ov_consumption[1] + tc_ov_consumption[2]);
1494 if (tc_ov_consumption[3] > (tc_ov_consumption_max - port->mtu)) {
1495 tc_ov_wm -= tc_ov_wm >> 7;
1496 if (tc_ov_wm < subport->tc_ov_wm_min)
1497 tc_ov_wm = subport->tc_ov_wm_min;
1502 tc_ov_wm += (tc_ov_wm >> 7) + 1;
1503 if (tc_ov_wm > subport->tc_ov_wm_max)
1504 tc_ov_wm = subport->tc_ov_wm_max;
1510 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1512 struct rte_sched_grinder *grinder = port->grinder + pos;
1513 struct rte_sched_subport *subport = grinder->subport;
1514 struct rte_sched_pipe *pipe = grinder->pipe;
1515 struct rte_sched_pipe_profile *params = grinder->pipe_params;
1519 n_periods = (port->time - subport->tb_time) / subport->tb_period;
1520 subport->tb_credits += n_periods * subport->tb_credits_per_period;
1521 subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1522 subport->tb_time += n_periods * subport->tb_period;
1525 n_periods = (port->time - pipe->tb_time) / params->tb_period;
1526 pipe->tb_credits += n_periods * params->tb_credits_per_period;
1527 pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1528 pipe->tb_time += n_periods * params->tb_period;
1531 if (unlikely(port->time >= subport->tc_time)) {
1532 subport->tc_ov_wm = grinder_tc_ov_credits_update(port, pos);
1534 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1535 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1536 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1537 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1539 subport->tc_time = port->time + subport->tc_period;
1540 subport->tc_ov_period_id++;
1544 if (unlikely(port->time >= pipe->tc_time)) {
1545 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1546 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1547 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1548 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1549 pipe->tc_time = port->time + params->tc_period;
1552 /* Pipe TCs - Oversubscription */
1553 if (unlikely(pipe->tc_ov_period_id != subport->tc_ov_period_id)) {
1554 pipe->tc_ov_credits = subport->tc_ov_wm * params->tc_ov_weight;
1556 pipe->tc_ov_period_id = subport->tc_ov_period_id;
1560 #endif /* RTE_SCHED_TS_CREDITS_UPDATE, RTE_SCHED_SUBPORT_TC_OV */
1563 #ifndef RTE_SCHED_SUBPORT_TC_OV
1566 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1568 struct rte_sched_grinder *grinder = port->grinder + pos;
1569 struct rte_sched_subport *subport = grinder->subport;
1570 struct rte_sched_pipe *pipe = grinder->pipe;
1571 struct rte_mbuf *pkt = grinder->pkt;
1572 uint32_t tc_index = grinder->tc_index;
1573 uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1574 uint32_t subport_tb_credits = subport->tb_credits;
1575 uint32_t subport_tc_credits = subport->tc_credits[tc_index];
1576 uint32_t pipe_tb_credits = pipe->tb_credits;
1577 uint32_t pipe_tc_credits = pipe->tc_credits[tc_index];
1580 /* Check queue credits */
1581 enough_credits = (pkt_len <= subport_tb_credits) &&
1582 (pkt_len <= subport_tc_credits) &&
1583 (pkt_len <= pipe_tb_credits) &&
1584 (pkt_len <= pipe_tc_credits);
1586 if (!enough_credits)
1589 /* Update port credits */
1590 subport->tb_credits -= pkt_len;
1591 subport->tc_credits[tc_index] -= pkt_len;
1592 pipe->tb_credits -= pkt_len;
1593 pipe->tc_credits[tc_index] -= pkt_len;
1601 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1603 struct rte_sched_grinder *grinder = port->grinder + pos;
1604 struct rte_sched_subport *subport = grinder->subport;
1605 struct rte_sched_pipe *pipe = grinder->pipe;
1606 struct rte_mbuf *pkt = grinder->pkt;
1607 uint32_t tc_index = grinder->tc_index;
1608 uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1609 uint32_t subport_tb_credits = subport->tb_credits;
1610 uint32_t subport_tc_credits = subport->tc_credits[tc_index];
1611 uint32_t pipe_tb_credits = pipe->tb_credits;
1612 uint32_t pipe_tc_credits = pipe->tc_credits[tc_index];
1613 uint32_t pipe_tc_ov_mask1[] = {UINT32_MAX, UINT32_MAX, UINT32_MAX, pipe->tc_ov_credits};
1614 uint32_t pipe_tc_ov_mask2[] = {0, 0, 0, UINT32_MAX};
1615 uint32_t pipe_tc_ov_credits = pipe_tc_ov_mask1[tc_index];
1618 /* Check pipe and subport credits */
1619 enough_credits = (pkt_len <= subport_tb_credits) &&
1620 (pkt_len <= subport_tc_credits) &&
1621 (pkt_len <= pipe_tb_credits) &&
1622 (pkt_len <= pipe_tc_credits) &&
1623 (pkt_len <= pipe_tc_ov_credits);
1625 if (!enough_credits)
1628 /* Update pipe and subport credits */
1629 subport->tb_credits -= pkt_len;
1630 subport->tc_credits[tc_index] -= pkt_len;
1631 pipe->tb_credits -= pkt_len;
1632 pipe->tc_credits[tc_index] -= pkt_len;
1633 pipe->tc_ov_credits -= pipe_tc_ov_mask2[tc_index] & pkt_len;
1638 #endif /* RTE_SCHED_SUBPORT_TC_OV */
1642 grinder_schedule(struct rte_sched_port *port, uint32_t pos)
1644 struct rte_sched_grinder *grinder = port->grinder + pos;
1645 struct rte_sched_queue *queue = grinder->queue[grinder->qpos];
1646 struct rte_mbuf *pkt = grinder->pkt;
1647 uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1649 if (!grinder_credits_check(port, pos))
1652 /* Advance port time */
1653 port->time += pkt_len;
1656 port->pkts_out[port->n_pkts_out++] = pkt;
1658 grinder->wrr_tokens[grinder->qpos] += pkt_len * grinder->wrr_cost[grinder->qpos];
1659 if (queue->qr == queue->qw) {
1660 uint32_t qindex = grinder->qindex[grinder->qpos];
1662 rte_bitmap_clear(port->bmp, qindex);
1663 grinder->qmask &= ~(1 << grinder->qpos);
1664 grinder->wrr_mask[grinder->qpos] = 0;
1665 rte_sched_port_set_queue_empty_timestamp(port, qindex);
1668 /* Reset pipe loop detection */
1669 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1670 grinder->productive = 1;
1675 #ifdef SCHED_VECTOR_SSE4
1678 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1680 __m128i index = _mm_set1_epi32(base_pipe);
1681 __m128i pipes = _mm_load_si128((__m128i *)port->grinder_base_bmp_pos);
1682 __m128i res = _mm_cmpeq_epi32(pipes, index);
1684 pipes = _mm_load_si128((__m128i *)(port->grinder_base_bmp_pos + 4));
1685 pipes = _mm_cmpeq_epi32(pipes, index);
1686 res = _mm_or_si128(res, pipes);
1688 if (_mm_testz_si128(res, res))
1697 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1701 for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i++) {
1702 if (port->grinder_base_bmp_pos[i] == base_pipe)
1709 #endif /* RTE_SCHED_OPTIMIZATIONS */
1712 grinder_pcache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t bmp_pos, uint64_t bmp_slab)
1714 struct rte_sched_grinder *grinder = port->grinder + pos;
1717 grinder->pcache_w = 0;
1718 grinder->pcache_r = 0;
1720 w[0] = (uint16_t) bmp_slab;
1721 w[1] = (uint16_t) (bmp_slab >> 16);
1722 w[2] = (uint16_t) (bmp_slab >> 32);
1723 w[3] = (uint16_t) (bmp_slab >> 48);
1725 grinder->pcache_qmask[grinder->pcache_w] = w[0];
1726 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos;
1727 grinder->pcache_w += (w[0] != 0);
1729 grinder->pcache_qmask[grinder->pcache_w] = w[1];
1730 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 16;
1731 grinder->pcache_w += (w[1] != 0);
1733 grinder->pcache_qmask[grinder->pcache_w] = w[2];
1734 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 32;
1735 grinder->pcache_w += (w[2] != 0);
1737 grinder->pcache_qmask[grinder->pcache_w] = w[3];
1738 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 48;
1739 grinder->pcache_w += (w[3] != 0);
1743 grinder_tccache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t qindex, uint16_t qmask)
1745 struct rte_sched_grinder *grinder = port->grinder + pos;
1748 grinder->tccache_w = 0;
1749 grinder->tccache_r = 0;
1751 b[0] = (uint8_t) (qmask & 0xF);
1752 b[1] = (uint8_t) ((qmask >> 4) & 0xF);
1753 b[2] = (uint8_t) ((qmask >> 8) & 0xF);
1754 b[3] = (uint8_t) ((qmask >> 12) & 0xF);
1756 grinder->tccache_qmask[grinder->tccache_w] = b[0];
1757 grinder->tccache_qindex[grinder->tccache_w] = qindex;
1758 grinder->tccache_w += (b[0] != 0);
1760 grinder->tccache_qmask[grinder->tccache_w] = b[1];
1761 grinder->tccache_qindex[grinder->tccache_w] = qindex + 4;
1762 grinder->tccache_w += (b[1] != 0);
1764 grinder->tccache_qmask[grinder->tccache_w] = b[2];
1765 grinder->tccache_qindex[grinder->tccache_w] = qindex + 8;
1766 grinder->tccache_w += (b[2] != 0);
1768 grinder->tccache_qmask[grinder->tccache_w] = b[3];
1769 grinder->tccache_qindex[grinder->tccache_w] = qindex + 12;
1770 grinder->tccache_w += (b[3] != 0);
1774 grinder_next_tc(struct rte_sched_port *port, uint32_t pos)
1776 struct rte_sched_grinder *grinder = port->grinder + pos;
1777 struct rte_mbuf **qbase;
1781 if (grinder->tccache_r == grinder->tccache_w)
1784 qindex = grinder->tccache_qindex[grinder->tccache_r];
1785 qbase = rte_sched_port_qbase(port, qindex);
1786 qsize = rte_sched_port_qsize(port, qindex);
1788 grinder->tc_index = (qindex >> 2) & 0x3;
1789 grinder->qmask = grinder->tccache_qmask[grinder->tccache_r];
1790 grinder->qsize = qsize;
1792 grinder->qindex[0] = qindex;
1793 grinder->qindex[1] = qindex + 1;
1794 grinder->qindex[2] = qindex + 2;
1795 grinder->qindex[3] = qindex + 3;
1797 grinder->queue[0] = port->queue + qindex;
1798 grinder->queue[1] = port->queue + qindex + 1;
1799 grinder->queue[2] = port->queue + qindex + 2;
1800 grinder->queue[3] = port->queue + qindex + 3;
1802 grinder->qbase[0] = qbase;
1803 grinder->qbase[1] = qbase + qsize;
1804 grinder->qbase[2] = qbase + 2 * qsize;
1805 grinder->qbase[3] = qbase + 3 * qsize;
1807 grinder->tccache_r++;
1812 grinder_next_pipe(struct rte_sched_port *port, uint32_t pos)
1814 struct rte_sched_grinder *grinder = port->grinder + pos;
1815 uint32_t pipe_qindex;
1816 uint16_t pipe_qmask;
1818 if (grinder->pcache_r < grinder->pcache_w) {
1819 pipe_qmask = grinder->pcache_qmask[grinder->pcache_r];
1820 pipe_qindex = grinder->pcache_qindex[grinder->pcache_r];
1821 grinder->pcache_r++;
1823 uint64_t bmp_slab = 0;
1824 uint32_t bmp_pos = 0;
1826 /* Get another non-empty pipe group */
1827 if (unlikely(rte_bitmap_scan(port->bmp, &bmp_pos, &bmp_slab) <= 0))
1830 #ifdef RTE_SCHED_DEBUG
1831 debug_check_queue_slab(port, bmp_pos, bmp_slab);
1834 /* Return if pipe group already in one of the other grinders */
1835 port->grinder_base_bmp_pos[pos] = RTE_SCHED_BMP_POS_INVALID;
1836 if (unlikely(grinder_pipe_exists(port, bmp_pos)))
1839 port->grinder_base_bmp_pos[pos] = bmp_pos;
1841 /* Install new pipe group into grinder's pipe cache */
1842 grinder_pcache_populate(port, pos, bmp_pos, bmp_slab);
1844 pipe_qmask = grinder->pcache_qmask[0];
1845 pipe_qindex = grinder->pcache_qindex[0];
1846 grinder->pcache_r = 1;
1849 /* Install new pipe in the grinder */
1850 grinder->pindex = pipe_qindex >> 4;
1851 grinder->subport = port->subport + (grinder->pindex / port->n_pipes_per_subport);
1852 grinder->pipe = port->pipe + grinder->pindex;
1853 grinder->pipe_params = NULL; /* to be set after the pipe structure is prefetched */
1854 grinder->productive = 0;
1856 grinder_tccache_populate(port, pos, pipe_qindex, pipe_qmask);
1857 grinder_next_tc(port, pos);
1859 /* Check for pipe exhaustion */
1860 if (grinder->pindex == port->pipe_loop) {
1861 port->pipe_exhaustion = 1;
1862 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1870 grinder_wrr_load(struct rte_sched_port *port, uint32_t pos)
1872 struct rte_sched_grinder *grinder = port->grinder + pos;
1873 struct rte_sched_pipe *pipe = grinder->pipe;
1874 struct rte_sched_pipe_profile *pipe_params = grinder->pipe_params;
1875 uint32_t tc_index = grinder->tc_index;
1876 uint32_t qmask = grinder->qmask;
1879 qindex = tc_index * 4;
1881 grinder->wrr_tokens[0] = ((uint16_t) pipe->wrr_tokens[qindex]) << RTE_SCHED_WRR_SHIFT;
1882 grinder->wrr_tokens[1] = ((uint16_t) pipe->wrr_tokens[qindex + 1]) << RTE_SCHED_WRR_SHIFT;
1883 grinder->wrr_tokens[2] = ((uint16_t) pipe->wrr_tokens[qindex + 2]) << RTE_SCHED_WRR_SHIFT;
1884 grinder->wrr_tokens[3] = ((uint16_t) pipe->wrr_tokens[qindex + 3]) << RTE_SCHED_WRR_SHIFT;
1886 grinder->wrr_mask[0] = (qmask & 0x1) * 0xFFFF;
1887 grinder->wrr_mask[1] = ((qmask >> 1) & 0x1) * 0xFFFF;
1888 grinder->wrr_mask[2] = ((qmask >> 2) & 0x1) * 0xFFFF;
1889 grinder->wrr_mask[3] = ((qmask >> 3) & 0x1) * 0xFFFF;
1891 grinder->wrr_cost[0] = pipe_params->wrr_cost[qindex];
1892 grinder->wrr_cost[1] = pipe_params->wrr_cost[qindex + 1];
1893 grinder->wrr_cost[2] = pipe_params->wrr_cost[qindex + 2];
1894 grinder->wrr_cost[3] = pipe_params->wrr_cost[qindex + 3];
1898 grinder_wrr_store(struct rte_sched_port *port, uint32_t pos)
1900 struct rte_sched_grinder *grinder = port->grinder + pos;
1901 struct rte_sched_pipe *pipe = grinder->pipe;
1902 uint32_t tc_index = grinder->tc_index;
1905 qindex = tc_index * 4;
1907 pipe->wrr_tokens[qindex] = (grinder->wrr_tokens[0] & grinder->wrr_mask[0])
1908 >> RTE_SCHED_WRR_SHIFT;
1909 pipe->wrr_tokens[qindex + 1] = (grinder->wrr_tokens[1] & grinder->wrr_mask[1])
1910 >> RTE_SCHED_WRR_SHIFT;
1911 pipe->wrr_tokens[qindex + 2] = (grinder->wrr_tokens[2] & grinder->wrr_mask[2])
1912 >> RTE_SCHED_WRR_SHIFT;
1913 pipe->wrr_tokens[qindex + 3] = (grinder->wrr_tokens[3] & grinder->wrr_mask[3])
1914 >> RTE_SCHED_WRR_SHIFT;
1918 grinder_wrr(struct rte_sched_port *port, uint32_t pos)
1920 struct rte_sched_grinder *grinder = port->grinder + pos;
1921 uint16_t wrr_tokens_min;
1923 grinder->wrr_tokens[0] |= ~grinder->wrr_mask[0];
1924 grinder->wrr_tokens[1] |= ~grinder->wrr_mask[1];
1925 grinder->wrr_tokens[2] |= ~grinder->wrr_mask[2];
1926 grinder->wrr_tokens[3] |= ~grinder->wrr_mask[3];
1928 grinder->qpos = rte_min_pos_4_u16(grinder->wrr_tokens);
1929 wrr_tokens_min = grinder->wrr_tokens[grinder->qpos];
1931 grinder->wrr_tokens[0] -= wrr_tokens_min;
1932 grinder->wrr_tokens[1] -= wrr_tokens_min;
1933 grinder->wrr_tokens[2] -= wrr_tokens_min;
1934 grinder->wrr_tokens[3] -= wrr_tokens_min;
1938 #define grinder_evict(port, pos)
1941 grinder_prefetch_pipe(struct rte_sched_port *port, uint32_t pos)
1943 struct rte_sched_grinder *grinder = port->grinder + pos;
1945 rte_prefetch0(grinder->pipe);
1946 rte_prefetch0(grinder->queue[0]);
1950 grinder_prefetch_tc_queue_arrays(struct rte_sched_port *port, uint32_t pos)
1952 struct rte_sched_grinder *grinder = port->grinder + pos;
1953 uint16_t qsize, qr[4];
1955 qsize = grinder->qsize;
1956 qr[0] = grinder->queue[0]->qr & (qsize - 1);
1957 qr[1] = grinder->queue[1]->qr & (qsize - 1);
1958 qr[2] = grinder->queue[2]->qr & (qsize - 1);
1959 qr[3] = grinder->queue[3]->qr & (qsize - 1);
1961 rte_prefetch0(grinder->qbase[0] + qr[0]);
1962 rte_prefetch0(grinder->qbase[1] + qr[1]);
1964 grinder_wrr_load(port, pos);
1965 grinder_wrr(port, pos);
1967 rte_prefetch0(grinder->qbase[2] + qr[2]);
1968 rte_prefetch0(grinder->qbase[3] + qr[3]);
1972 grinder_prefetch_mbuf(struct rte_sched_port *port, uint32_t pos)
1974 struct rte_sched_grinder *grinder = port->grinder + pos;
1975 uint32_t qpos = grinder->qpos;
1976 struct rte_mbuf **qbase = grinder->qbase[qpos];
1977 uint16_t qsize = grinder->qsize;
1978 uint16_t qr = grinder->queue[qpos]->qr & (qsize - 1);
1980 grinder->pkt = qbase[qr];
1981 rte_prefetch0(grinder->pkt);
1983 if (unlikely((qr & 0x7) == 7)) {
1984 uint16_t qr_next = (grinder->queue[qpos]->qr + 1) & (qsize - 1);
1986 rte_prefetch0(qbase + qr_next);
1990 static inline uint32_t
1991 grinder_handle(struct rte_sched_port *port, uint32_t pos)
1993 struct rte_sched_grinder *grinder = port->grinder + pos;
1995 switch (grinder->state) {
1996 case e_GRINDER_PREFETCH_PIPE:
1998 if (grinder_next_pipe(port, pos)) {
1999 grinder_prefetch_pipe(port, pos);
2000 port->busy_grinders++;
2002 grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2009 case e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS:
2011 struct rte_sched_pipe *pipe = grinder->pipe;
2013 grinder->pipe_params = port->pipe_profiles + pipe->profile;
2014 grinder_prefetch_tc_queue_arrays(port, pos);
2015 grinder_credits_update(port, pos);
2017 grinder->state = e_GRINDER_PREFETCH_MBUF;
2021 case e_GRINDER_PREFETCH_MBUF:
2023 grinder_prefetch_mbuf(port, pos);
2025 grinder->state = e_GRINDER_READ_MBUF;
2029 case e_GRINDER_READ_MBUF:
2031 uint32_t result = 0;
2033 result = grinder_schedule(port, pos);
2035 /* Look for next packet within the same TC */
2036 if (result && grinder->qmask) {
2037 grinder_wrr(port, pos);
2038 grinder_prefetch_mbuf(port, pos);
2042 grinder_wrr_store(port, pos);
2044 /* Look for another active TC within same pipe */
2045 if (grinder_next_tc(port, pos)) {
2046 grinder_prefetch_tc_queue_arrays(port, pos);
2048 grinder->state = e_GRINDER_PREFETCH_MBUF;
2052 if (grinder->productive == 0 &&
2053 port->pipe_loop == RTE_SCHED_PIPE_INVALID)
2054 port->pipe_loop = grinder->pindex;
2056 grinder_evict(port, pos);
2058 /* Look for another active pipe */
2059 if (grinder_next_pipe(port, pos)) {
2060 grinder_prefetch_pipe(port, pos);
2062 grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2066 /* No active pipe found */
2067 port->busy_grinders--;
2069 grinder->state = e_GRINDER_PREFETCH_PIPE;
2074 rte_panic("Algorithmic error (invalid state)\n");
2080 rte_sched_port_time_resync(struct rte_sched_port *port)
2082 uint64_t cycles = rte_get_tsc_cycles();
2083 uint64_t cycles_diff = cycles - port->time_cpu_cycles;
2084 double bytes_diff = ((double) cycles_diff) / port->cycles_per_byte;
2086 /* Advance port time */
2087 port->time_cpu_cycles = cycles;
2088 port->time_cpu_bytes += (uint64_t) bytes_diff;
2089 if (port->time < port->time_cpu_bytes)
2090 port->time = port->time_cpu_bytes;
2092 /* Reset pipe loop detection */
2093 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
2097 rte_sched_port_exceptions(struct rte_sched_port *port, int second_pass)
2101 /* Check if any exception flag is set */
2102 exceptions = (second_pass && port->busy_grinders == 0) ||
2103 (port->pipe_exhaustion == 1);
2105 /* Clear exception flags */
2106 port->pipe_exhaustion = 0;
2112 rte_sched_port_dequeue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
2116 port->pkts_out = pkts;
2117 port->n_pkts_out = 0;
2119 rte_sched_port_time_resync(port);
2121 /* Take each queue in the grinder one step further */
2122 for (i = 0, count = 0; ; i++) {
2123 count += grinder_handle(port, i & (RTE_SCHED_PORT_N_GRINDERS - 1));
2124 if ((count == n_pkts) ||
2125 rte_sched_port_exceptions(port, i >= RTE_SCHED_PORT_N_GRINDERS)) {