4 * Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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38 #include <rte_common.h>
40 #include <rte_memory.h>
41 #include <rte_memzone.h>
42 #include <rte_cycles.h>
43 #include <rte_prefetch.h>
44 #include <rte_branch_prediction.h>
47 #include "rte_sched.h"
48 #include "rte_bitmap.h"
49 #include "rte_sched_common.h"
50 #include "rte_approx.h"
52 #ifdef __INTEL_COMPILER
53 #pragma warning(disable:2259) /* conversion may lose significant bits */
56 #ifndef RTE_SCHED_DEBUG
57 #define RTE_SCHED_DEBUG 0
60 #ifndef RTE_SCHED_OPTIMIZATIONS
61 #define RTE_SCHED_OPTIMIZATIONS 0
64 #if RTE_SCHED_OPTIMIZATIONS
65 #include <immintrin.h>
68 #define RTE_SCHED_ENQUEUE 1
70 #define RTE_SCHED_TS 1
72 #if RTE_SCHED_TS == 0 /* Infinite credits. Traffic shaping disabled. */
73 #define RTE_SCHED_TS_CREDITS_UPDATE 0
74 #define RTE_SCHED_TS_CREDITS_CHECK 0
75 #else /* Real Credits. Full traffic shaping implemented. */
76 #define RTE_SCHED_TS_CREDITS_UPDATE 1
77 #define RTE_SCHED_TS_CREDITS_CHECK 1
80 #ifndef RTE_SCHED_TB_RATE_CONFIG_ERR
81 #define RTE_SCHED_TB_RATE_CONFIG_ERR (1e-7)
84 #define RTE_SCHED_WRR 1
86 #ifndef RTE_SCHED_WRR_SHIFT
87 #define RTE_SCHED_WRR_SHIFT 3
90 #ifndef RTE_SCHED_PORT_N_GRINDERS
91 #define RTE_SCHED_PORT_N_GRINDERS 8
93 #if (RTE_SCHED_PORT_N_GRINDERS == 0) || (RTE_SCHED_PORT_N_GRINDERS & (RTE_SCHED_PORT_N_GRINDERS - 1))
94 #error Number of grinders must be non-zero and a power of 2
96 #if (RTE_SCHED_OPTIMIZATIONS && (RTE_SCHED_PORT_N_GRINDERS != 8))
97 #error Number of grinders must be 8 when RTE_SCHED_OPTIMIZATIONS is set
100 #define RTE_SCHED_GRINDER_PCACHE_SIZE (64 / RTE_SCHED_QUEUES_PER_PIPE)
102 #define RTE_SCHED_PIPE_INVALID UINT32_MAX
104 #define RTE_SCHED_BMP_POS_INVALID UINT32_MAX
106 struct rte_sched_subport {
107 /* Token bucket (TB) */
108 uint64_t tb_time; /* time of last update */
110 uint32_t tb_credits_per_period;
114 /* Traffic classes (TCs) */
115 uint64_t tc_time; /* time of next update */
116 uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
117 uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
120 /* TC oversubscription */
121 uint32_t tc_ov_period;
123 uint32_t tc_ov_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
124 uint8_t tc_ov_period_id;
125 uint8_t tc_ov[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
126 uint32_t tc_ov_n[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
127 double tc_ov_rate[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
130 struct rte_sched_subport_stats stats;
133 struct rte_sched_pipe_profile {
134 /* Token bucket (TB) */
136 uint32_t tb_credits_per_period;
139 /* Pipe traffic classes */
141 uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
142 uint8_t tc_ov_weight[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
145 uint8_t wrr_cost[RTE_SCHED_QUEUES_PER_PIPE];
148 struct rte_sched_pipe {
149 /* Token bucket (TB) */
150 uint64_t tb_time; /* time of last update */
153 /* Pipe profile and flags */
156 /* Traffic classes (TCs) */
157 uint64_t tc_time; /* time of next update */
158 uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
160 /* Weighted Round Robin (WRR) */
161 uint8_t wrr_tokens[RTE_SCHED_QUEUES_PER_PIPE];
163 /* TC oversubscription */
164 #ifdef RTE_SCHED_SUBPORT_TC_OV
165 uint32_t tc_ov_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
166 uint8_t tc_ov_period_id;
170 } __rte_cache_aligned;
172 struct rte_sched_queue {
177 struct rte_sched_queue_extra {
178 struct rte_sched_queue_stats stats;
185 e_GRINDER_PREFETCH_PIPE = 0,
186 e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS,
187 e_GRINDER_PREFETCH_MBUF,
191 struct rte_sched_grinder {
193 uint16_t pcache_qmask[RTE_SCHED_GRINDER_PCACHE_SIZE];
194 uint32_t pcache_qindex[RTE_SCHED_GRINDER_PCACHE_SIZE];
199 enum grinder_state state;
202 struct rte_sched_subport *subport;
203 struct rte_sched_pipe *pipe;
204 struct rte_sched_pipe_profile *pipe_params;
207 uint8_t tccache_qmask[4];
208 uint32_t tccache_qindex[4];
214 struct rte_sched_queue *queue[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
215 struct rte_mbuf **qbase[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
216 uint32_t qindex[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
220 struct rte_mbuf *pkt;
224 uint16_t wrr_tokens[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
225 uint16_t wrr_mask[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
226 uint8_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
229 struct rte_sched_port {
230 /* User parameters */
231 uint32_t n_subports_per_port;
232 uint32_t n_pipes_per_subport;
234 uint32_t frame_overhead;
235 uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
236 uint32_t n_pipe_profiles;
238 struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][e_RTE_METER_COLORS];
242 uint64_t time_cpu_cycles; /* Current CPU time measured in CPU cyles */
243 uint64_t time_cpu_bytes; /* Current CPU time measured in bytes */
244 uint64_t time; /* Current NIC TX time measured in bytes */
245 double cycles_per_byte; /* CPU cycles per byte */
247 /* Scheduling loop detection */
249 uint32_t pipe_exhaustion;
252 struct rte_bitmap *bmp;
253 uint32_t grinder_base_bmp_pos[RTE_SCHED_PORT_N_GRINDERS] __rte_aligned_16;
256 struct rte_sched_grinder grinder[RTE_SCHED_PORT_N_GRINDERS];
257 uint32_t busy_grinders;
258 struct rte_mbuf **pkts_out;
261 /* Queue base calculation */
262 uint32_t qsize_add[RTE_SCHED_QUEUES_PER_PIPE];
265 /* Large data structures */
266 struct rte_sched_subport *subport;
267 struct rte_sched_pipe *pipe;
268 struct rte_sched_queue *queue;
269 struct rte_sched_queue_extra *queue_extra;
270 struct rte_sched_pipe_profile *pipe_profiles;
272 struct rte_mbuf **queue_array;
273 uint8_t memory[0] __rte_cache_aligned;
274 } __rte_cache_aligned;
276 enum rte_sched_port_array {
277 e_RTE_SCHED_PORT_ARRAY_SUBPORT = 0,
278 e_RTE_SCHED_PORT_ARRAY_PIPE,
279 e_RTE_SCHED_PORT_ARRAY_QUEUE,
280 e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA,
281 e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES,
282 e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY,
283 e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY,
284 e_RTE_SCHED_PORT_ARRAY_TOTAL,
287 #ifdef RTE_SCHED_COLLECT_STATS
289 static inline uint32_t
290 rte_sched_port_queues_per_subport(struct rte_sched_port *port)
292 return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport;
297 static inline uint32_t
298 rte_sched_port_queues_per_port(struct rte_sched_port *port)
300 return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport * port->n_subports_per_port;
304 rte_sched_port_check_params(struct rte_sched_port_params *params)
308 if (params == NULL) {
313 if (params->name == NULL) {
318 if ((params->socket < 0) || (params->socket >= RTE_MAX_NUMA_NODES)) {
323 if (params->rate == 0) {
327 /* n_subports_per_port: non-zero, power of 2 */
328 if ((params->n_subports_per_port == 0) || (!rte_is_power_of_2(params->n_subports_per_port))) {
332 /* n_pipes_per_subport: non-zero, power of 2 */
333 if ((params->n_pipes_per_subport == 0) || (!rte_is_power_of_2(params->n_pipes_per_subport))) {
337 /* qsize: non-zero, power of 2, no bigger than 32K (due to 16-bit read/write pointers) */
338 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
339 uint16_t qsize = params->qsize[i];
341 if ((qsize == 0) || (!rte_is_power_of_2(qsize))) {
346 /* pipe_profiles and n_pipe_profiles */
347 if ((params->pipe_profiles == NULL) ||
348 (params->n_pipe_profiles == 0) ||
349 (params->n_pipe_profiles > RTE_SCHED_PIPE_PROFILES_PER_PORT)) {
353 for (i = 0; i < params->n_pipe_profiles; i ++) {
354 struct rte_sched_pipe_params *p = params->pipe_profiles + i;
356 /* TB rate: non-zero, not greater than port rate */
357 if ((p->tb_rate == 0) || (p->tb_rate > params->rate)) {
361 /* TB size: non-zero */
362 if (p->tb_size == 0) {
366 /* TC rate: non-zero, less than pipe rate */
367 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
368 if ((p->tc_rate[j] == 0) || (p->tc_rate[j] > p->tb_rate)) {
373 /* TC period: non-zero */
374 if (p->tc_period == 0) {
378 #ifdef RTE_SCHED_SUBPORT_TC_OV
379 /* TC oversubscription weights: non-zero */
380 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
381 if (p->tc_ov_weight[j] == 0) {
387 /* Queue WRR weights: non-zero */
388 for (j = 0; j < RTE_SCHED_QUEUES_PER_PIPE; j ++) {
389 if (p->wrr_weights[j] == 0) {
399 rte_sched_port_get_array_base(struct rte_sched_port_params *params, enum rte_sched_port_array array)
401 uint32_t n_subports_per_port = params->n_subports_per_port;
402 uint32_t n_pipes_per_subport = params->n_pipes_per_subport;
403 uint32_t n_pipes_per_port = n_pipes_per_subport * n_subports_per_port;
404 uint32_t n_queues_per_port = RTE_SCHED_QUEUES_PER_PIPE * n_pipes_per_subport * n_subports_per_port;
406 uint32_t size_subport = n_subports_per_port * sizeof(struct rte_sched_subport);
407 uint32_t size_pipe = n_pipes_per_port * sizeof(struct rte_sched_pipe);
408 uint32_t size_queue = n_queues_per_port * sizeof(struct rte_sched_queue);
409 uint32_t size_queue_extra = n_queues_per_port * sizeof(struct rte_sched_queue_extra);
410 uint32_t size_pipe_profiles = RTE_SCHED_PIPE_PROFILES_PER_PORT * sizeof(struct rte_sched_pipe_profile);
411 uint32_t size_bmp_array = rte_bitmap_get_memory_footprint(n_queues_per_port);
412 uint32_t size_per_pipe_queue_array, size_queue_array;
416 size_per_pipe_queue_array = 0;
417 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
418 size_per_pipe_queue_array += RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS * params->qsize[i] * sizeof(struct rte_mbuf *);
420 size_queue_array = n_pipes_per_port * size_per_pipe_queue_array;
424 if (array == e_RTE_SCHED_PORT_ARRAY_SUBPORT) return base;
425 base += CACHE_LINE_ROUNDUP(size_subport);
427 if (array == e_RTE_SCHED_PORT_ARRAY_PIPE) return base;
428 base += CACHE_LINE_ROUNDUP(size_pipe);
430 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE) return base;
431 base += CACHE_LINE_ROUNDUP(size_queue);
433 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA) return base;
434 base += CACHE_LINE_ROUNDUP(size_queue_extra);
436 if (array == e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES) return base;
437 base += CACHE_LINE_ROUNDUP(size_pipe_profiles);
439 if (array == e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY) return base;
440 base += CACHE_LINE_ROUNDUP(size_bmp_array);
442 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY) return base;
443 base += CACHE_LINE_ROUNDUP(size_queue_array);
449 rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)
451 uint32_t size0, size1;
454 status = rte_sched_port_check_params(params);
456 RTE_LOG(INFO, SCHED, "Port scheduler params check failed (%d)\n", status);
461 size0 = sizeof(struct rte_sched_port);
462 size1 = rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_TOTAL);
464 return (size0 + size1);
468 rte_sched_port_config_qsize(struct rte_sched_port *port)
471 port->qsize_add[0] = 0;
472 port->qsize_add[1] = port->qsize_add[0] + port->qsize[0];
473 port->qsize_add[2] = port->qsize_add[1] + port->qsize[0];
474 port->qsize_add[3] = port->qsize_add[2] + port->qsize[0];
477 port->qsize_add[4] = port->qsize_add[3] + port->qsize[0];
478 port->qsize_add[5] = port->qsize_add[4] + port->qsize[1];
479 port->qsize_add[6] = port->qsize_add[5] + port->qsize[1];
480 port->qsize_add[7] = port->qsize_add[6] + port->qsize[1];
483 port->qsize_add[8] = port->qsize_add[7] + port->qsize[1];
484 port->qsize_add[9] = port->qsize_add[8] + port->qsize[2];
485 port->qsize_add[10] = port->qsize_add[9] + port->qsize[2];
486 port->qsize_add[11] = port->qsize_add[10] + port->qsize[2];
489 port->qsize_add[12] = port->qsize_add[11] + port->qsize[2];
490 port->qsize_add[13] = port->qsize_add[12] + port->qsize[3];
491 port->qsize_add[14] = port->qsize_add[13] + port->qsize[3];
492 port->qsize_add[15] = port->qsize_add[14] + port->qsize[3];
494 port->qsize_sum = port->qsize_add[15] + port->qsize[3];
498 rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)
500 struct rte_sched_pipe_profile *p = port->pipe_profiles + i;
502 RTE_LOG(INFO, SCHED, "Low level config for pipe profile %u:\n"
503 "\tToken bucket: period = %u, credits per period = %u, size = %u\n"
504 "\tTraffic classes: period = %u, credits per period = [%u, %u, %u, %u], ov weights = [%hhu, %hhu, %hhu, %hhu]\n"
505 "\tWRR cost: [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu]\n",
510 p->tb_credits_per_period,
513 /* Traffic classes */
515 p->tc_credits_per_period[0],
516 p->tc_credits_per_period[1],
517 p->tc_credits_per_period[2],
518 p->tc_credits_per_period[3],
525 p->wrr_cost[ 0], p->wrr_cost[ 1], p->wrr_cost[ 2], p->wrr_cost[ 3],
526 p->wrr_cost[ 4], p->wrr_cost[ 5], p->wrr_cost[ 6], p->wrr_cost[ 7],
527 p->wrr_cost[ 8], p->wrr_cost[ 9], p->wrr_cost[10], p->wrr_cost[11],
528 p->wrr_cost[12], p->wrr_cost[13], p->wrr_cost[14], p->wrr_cost[15]);
531 static inline uint64_t
532 rte_sched_time_ms_to_bytes(uint32_t time_ms, uint32_t rate)
534 uint64_t time = time_ms;
535 time = (time * rate) / 1000;
541 rte_sched_port_config_pipe_profile_table(struct rte_sched_port *port, struct rte_sched_port_params *params)
545 for (i = 0; i < port->n_pipe_profiles; i ++) {
546 struct rte_sched_pipe_params *src = params->pipe_profiles + i;
547 struct rte_sched_pipe_profile *dst = port->pipe_profiles + i;
550 if (src->tb_rate == params->rate) {
551 dst->tb_credits_per_period = 1;
554 double tb_rate = ((double) src->tb_rate) / ((double) params->rate);
555 double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
557 rte_approx(tb_rate, d, &dst->tb_credits_per_period, &dst->tb_period);
559 dst->tb_size = src->tb_size;
561 /* Traffic Classes */
562 dst->tc_period = (uint32_t) rte_sched_time_ms_to_bytes(src->tc_period, params->rate);
563 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
564 dst->tc_credits_per_period[j] = (uint32_t) rte_sched_time_ms_to_bytes(src->tc_period, src->tc_rate[j]);
566 #ifdef RTE_SCHED_SUBPORT_TC_OV
567 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
568 dst->tc_ov_weight[j] = src->tc_ov_weight[j];
573 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
574 uint32_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
575 uint32_t lcd, lcd1, lcd2;
578 qindex = j * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS;
580 wrr_cost[0] = src->wrr_weights[qindex];
581 wrr_cost[1] = src->wrr_weights[qindex + 1];
582 wrr_cost[2] = src->wrr_weights[qindex + 2];
583 wrr_cost[3] = src->wrr_weights[qindex + 3];
585 lcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]);
586 lcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]);
587 lcd = rte_get_lcd(lcd1, lcd2);
589 wrr_cost[0] = lcd / wrr_cost[0];
590 wrr_cost[1] = lcd / wrr_cost[1];
591 wrr_cost[2] = lcd / wrr_cost[2];
592 wrr_cost[3] = lcd / wrr_cost[3];
594 dst->wrr_cost[qindex] = (uint8_t) wrr_cost[0];
595 dst->wrr_cost[qindex + 1] = (uint8_t) wrr_cost[1];
596 dst->wrr_cost[qindex + 2] = (uint8_t) wrr_cost[2];
597 dst->wrr_cost[qindex + 3] = (uint8_t) wrr_cost[3];
600 rte_sched_port_log_pipe_profile(port, i);
604 struct rte_sched_port *
605 rte_sched_port_config(struct rte_sched_port_params *params)
607 struct rte_sched_port *port = NULL;
608 const struct rte_memzone *mz = NULL;
609 uint32_t mem_size, bmp_mem_size, n_queues_per_port, i;
611 /* Check user parameters. Determine the amount of memory to allocate */
612 mem_size = rte_sched_port_get_memory_footprint(params);
617 /* Allocate memory to store the data structures */
618 mz = rte_memzone_lookup(params->name);
620 /* Use existing memzone, provided that its size is big enough */
621 if (mz->len < mem_size) {
625 /* Create new memzone */
626 mz = rte_memzone_reserve(params->name, mem_size, params->socket, 0);
631 memset(mz->addr, 0, mem_size);
632 port = (struct rte_sched_port *) mz->addr;
634 /* User parameters */
635 port->n_subports_per_port = params->n_subports_per_port;
636 port->n_pipes_per_subport = params->n_pipes_per_subport;
637 port->rate = params->rate;
638 port->frame_overhead = params->frame_overhead;
639 memcpy(port->qsize, params->qsize, sizeof(params->qsize));
640 port->n_pipe_profiles = params->n_pipe_profiles;
643 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
646 for (j = 0; j < e_RTE_METER_COLORS; j++) {
647 if (rte_red_config_init(&port->red_config[i][j],
648 params->red_params[i][j].wq_log2,
649 params->red_params[i][j].min_th,
650 params->red_params[i][j].max_th,
651 params->red_params[i][j].maxp_inv) != 0) {
659 port->time_cpu_cycles = rte_get_tsc_cycles();
660 port->time_cpu_bytes = 0;
662 port->cycles_per_byte = ((double) rte_get_tsc_hz()) / ((double) params->rate);
664 /* Scheduling loop detection */
665 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
666 port->pipe_exhaustion = 0;
669 port->busy_grinders = 0;
670 port->pkts_out = NULL;
671 port->n_pkts_out = 0;
673 /* Queue base calculation */
674 rte_sched_port_config_qsize(port);
676 /* Large data structures */
677 port->subport = (struct rte_sched_subport *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_SUBPORT));
678 port->pipe = (struct rte_sched_pipe *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_PIPE));
679 port->queue = (struct rte_sched_queue *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE));
680 port->queue_extra = (struct rte_sched_queue_extra *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA));
681 port->pipe_profiles = (struct rte_sched_pipe_profile *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES));
682 port->bmp_array = port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY);
683 port->queue_array = (struct rte_mbuf **) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY));
685 /* Pipe profile table */
686 rte_sched_port_config_pipe_profile_table(port, params);
689 n_queues_per_port = rte_sched_port_queues_per_port(port);
690 bmp_mem_size = rte_bitmap_get_memory_footprint(n_queues_per_port);
691 port->bmp = rte_bitmap_init(n_queues_per_port, port->bmp_array, bmp_mem_size);
692 if (port->bmp == NULL) {
693 RTE_LOG(INFO, SCHED, "Bitmap init error\n");
696 for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i ++) {
697 port->grinder_base_bmp_pos[i] = RTE_SCHED_PIPE_INVALID;
704 rte_sched_port_free(struct rte_sched_port *port)
706 /* Check user parameters */
710 rte_bitmap_free(port->bmp);
716 rte_sched_port_log_subport_config(struct rte_sched_port *port, uint32_t i)
718 struct rte_sched_subport *s = port->subport + i;
720 RTE_LOG(INFO, SCHED, "Low level config for subport %u:\n"
721 "\tToken bucket: period = %u, credits per period = %u, size = %u\n"
722 "\tTraffic classes: period = %u, credits per period = [%u, %u, %u, %u], ov period = %u\n",
727 s->tb_credits_per_period,
730 /* Traffic classes */
732 s->tc_credits_per_period[0],
733 s->tc_credits_per_period[1],
734 s->tc_credits_per_period[2],
735 s->tc_credits_per_period[3],
740 rte_sched_subport_config(struct rte_sched_port *port,
742 struct rte_sched_subport_params *params)
744 struct rte_sched_subport *s;
747 /* Check user parameters */
748 if ((port == NULL) ||
749 (subport_id >= port->n_subports_per_port) ||
754 if ((params->tb_rate == 0) || (params->tb_rate > port->rate)) {
758 if (params->tb_size == 0) {
762 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
763 if ((params->tc_rate[i] == 0) || (params->tc_rate[i] > params->tb_rate)) {
768 if (params->tc_period == 0) {
772 #ifdef RTE_SCHED_SUBPORT_TC_OV
773 if ((params->tc_ov_period == 0) || (params->tc_ov_period > params->tc_period)) {
778 s = port->subport + subport_id;
780 /* Token Bucket (TB) */
781 if (params->tb_rate == port->rate) {
782 s->tb_credits_per_period = 1;
785 double tb_rate = ((double) params->tb_rate) / ((double) port->rate);
786 double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
788 rte_approx(tb_rate, d, &s->tb_credits_per_period, &s->tb_period);
790 s->tb_size = params->tb_size;
791 s->tb_time = port->time;
792 s->tb_credits = s->tb_size / 2;
794 /* Traffic Classes (TCs) */
795 s->tc_period = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, port->rate);
796 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
797 s->tc_credits_per_period[i] = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, params->tc_rate[i]);
799 s->tc_time = port->time + s->tc_period;
800 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
801 s->tc_credits[i] = s->tc_credits_per_period[i];
804 #ifdef RTE_SCHED_SUBPORT_TC_OV
805 /* TC oversubscription */
806 s->tc_ov_period = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_ov_period, port->rate);
807 s->tc_ov_time = port->time + s->tc_ov_period;
808 s->tc_ov_period_id = 0;
809 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
812 s->tc_ov_rate[i] = 0;
813 s->tc_ov_credits[i] = 0;
817 rte_sched_port_log_subport_config(port, subport_id);
823 rte_sched_pipe_config(struct rte_sched_port *port,
826 int32_t pipe_profile)
828 struct rte_sched_subport *s;
829 struct rte_sched_pipe *p;
830 struct rte_sched_pipe_profile *params;
831 uint32_t deactivate, profile, i;
833 /* Check user parameters */
834 profile = (uint32_t) pipe_profile;
835 deactivate = (pipe_profile < 0);
836 if ((port == NULL) ||
837 (subport_id >= port->n_subports_per_port) ||
838 (pipe_id >= port->n_pipes_per_subport) ||
839 ((!deactivate) && (profile >= port->n_pipe_profiles))) {
843 /* Check that subport configuration is valid */
844 s = port->subport + subport_id;
845 if (s->tb_period == 0) {
849 p = port->pipe + (subport_id * port->n_pipes_per_subport + pipe_id);
851 /* Handle the case when pipe already has a valid configuration */
853 params = port->pipe_profiles + p->profile;
855 #ifdef RTE_SCHED_SUBPORT_TC_OV
856 /* Unplug pipe from its subport */
857 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
858 s->tc_ov_n[i] -= params->tc_ov_weight[i];
859 s->tc_ov_rate[i] -= ((double) params->tc_credits_per_period[i]) / ((double) params->tc_period);
860 s->tc_ov[i] = s->tc_ov_rate[i] > (((double) s->tc_credits_per_period[i]) / ((double) s->tc_period));
865 memset(p, 0, sizeof(struct rte_sched_pipe));
872 /* Apply the new pipe configuration */
873 p->profile = profile;
874 params = port->pipe_profiles + p->profile;
876 /* Token Bucket (TB) */
877 p->tb_time = port->time;
878 p->tb_credits = params->tb_size / 2;
880 /* Traffic Classes (TCs) */
881 p->tc_time = port->time + params->tc_period;
882 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
883 p->tc_credits[i] = params->tc_credits_per_period[i];
886 #ifdef RTE_SCHED_SUBPORT_TC_OV
887 /* Subport TC oversubscription */
888 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
889 s->tc_ov_n[i] += params->tc_ov_weight[i];
890 s->tc_ov_rate[i] += ((double) params->tc_credits_per_period[i]) / ((double) params->tc_period);
891 s->tc_ov[i] = s->tc_ov_rate[i] > (((double) s->tc_credits_per_period[i]) / ((double) s->tc_period));
893 p->tc_ov_period_id = s->tc_ov_period_id;
894 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
895 p->tc_ov_credits[i] = 0;
903 rte_sched_subport_read_stats(struct rte_sched_port *port,
905 struct rte_sched_subport_stats *stats,
908 struct rte_sched_subport *s;
911 /* Check user parameters */
912 if ((port == NULL) ||
913 (subport_id >= port->n_subports_per_port) ||
918 s = port->subport + subport_id;
920 /* Copy subport stats and clear */
921 memcpy(stats, &s->stats, sizeof(struct rte_sched_subport_stats));
922 memset(&s->stats, 0, sizeof(struct rte_sched_subport_stats));
924 /* Subport TC ovesubscription status */
926 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
927 mask |= ((uint32_t) s->tc_ov[i]) << i;
935 rte_sched_queue_read_stats(struct rte_sched_port *port,
937 struct rte_sched_queue_stats *stats,
940 struct rte_sched_queue *q;
941 struct rte_sched_queue_extra *qe;
943 /* Check user parameters */
944 if ((port == NULL) ||
945 (queue_id >= rte_sched_port_queues_per_port(port)) ||
950 q = port->queue + queue_id;
951 qe = port->queue_extra + queue_id;
953 /* Copy queue stats and clear */
954 memcpy(stats, &qe->stats, sizeof(struct rte_sched_queue_stats));
955 memset(&qe->stats, 0, sizeof(struct rte_sched_queue_stats));
958 *qlen = q->qw - q->qr;
963 static inline uint32_t
964 rte_sched_port_qindex(struct rte_sched_port *port, uint32_t subport, uint32_t pipe, uint32_t traffic_class, uint32_t queue)
968 result = subport * port->n_pipes_per_subport + pipe;
969 result = result * RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE + traffic_class;
970 result = result * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS + queue;
975 static inline struct rte_mbuf **
976 rte_sched_port_qbase(struct rte_sched_port *port, uint32_t qindex)
978 uint32_t pindex = qindex >> 4;
979 uint32_t qpos = qindex & 0xF;
981 return (port->queue_array + pindex * port->qsize_sum + port->qsize_add[qpos]);
984 static inline uint16_t
985 rte_sched_port_qsize(struct rte_sched_port *port, uint32_t qindex)
987 uint32_t tc = (qindex >> 2) & 0x3;
989 return port->qsize[tc];
995 rte_sched_port_queue_is_empty(struct rte_sched_port *port, uint32_t qindex)
997 struct rte_sched_queue *queue = port->queue + qindex;
999 return (queue->qr == queue->qw);
1003 rte_sched_port_queue_is_full(struct rte_sched_port *port, uint32_t qindex)
1005 struct rte_sched_queue *queue = port->queue + qindex;
1006 uint16_t qsize = rte_sched_port_qsize(port, qindex);
1007 uint16_t qlen = q->qw - q->qr;
1009 return (qlen >= qsize);
1012 #endif /* RTE_SCHED_DEBUG */
1014 #ifdef RTE_SCHED_COLLECT_STATS
1017 rte_sched_port_update_subport_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1019 struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1020 uint32_t tc_index = (qindex >> 2) & 0x3;
1021 uint32_t pkt_len = pkt->pkt.pkt_len;
1023 s->stats.n_pkts_tc[tc_index] += 1;
1024 s->stats.n_bytes_tc[tc_index] += pkt_len;
1028 rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1030 struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1031 uint32_t tc_index = (qindex >> 2) & 0x3;
1032 uint32_t pkt_len = pkt->pkt.pkt_len;
1034 s->stats.n_pkts_tc_dropped[tc_index] += 1;
1035 s->stats.n_bytes_tc_dropped[tc_index] += pkt_len;
1039 rte_sched_port_update_queue_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1041 struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1042 uint32_t pkt_len = pkt->pkt.pkt_len;
1044 qe->stats.n_pkts += 1;
1045 qe->stats.n_bytes += pkt_len;
1049 rte_sched_port_update_queue_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1051 struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1052 uint32_t pkt_len = pkt->pkt.pkt_len;
1054 qe->stats.n_pkts_dropped += 1;
1055 qe->stats.n_bytes_dropped += pkt_len;
1058 #endif /* RTE_SCHED_COLLECT_STATS */
1060 #ifdef RTE_SCHED_RED
1063 rte_sched_port_red_drop(struct rte_sched_port *port, struct rte_mbuf *pkt, uint32_t qindex, uint16_t qlen)
1065 struct rte_sched_queue_extra *qe;
1066 struct rte_red_config *red_cfg;
1067 struct rte_red *red;
1069 enum rte_meter_color color;
1071 tc_index = (qindex >> 2) & 0x3;
1072 color = rte_sched_port_pkt_read_color(pkt);
1073 red_cfg = &port->red_config[tc_index][color];
1075 qe = port->queue_extra + qindex;
1078 return rte_red_enqueue(red_cfg, red, qlen, port->time);
1082 rte_sched_port_set_queue_empty_timestamp(struct rte_sched_port *port, uint32_t qindex)
1084 struct rte_sched_queue_extra *qe;
1085 struct rte_red *red;
1087 qe = port->queue_extra + qindex;
1090 rte_red_mark_queue_empty(red, port->time);
1095 #define rte_sched_port_red_drop(port, pkt, qindex, qlen) 0
1097 #define rte_sched_port_set_queue_empty_timestamp(port, qindex)
1099 #endif /* RTE_SCHED_RED */
1104 debug_pipe_is_empty(struct rte_sched_port *port, uint32_t pindex)
1108 qindex = pindex << 4;
1110 for (i = 0; i < 16; i ++){
1111 uint32_t queue_empty = rte_sched_port_queue_is_empty(port, qindex + i);
1112 uint32_t bmp_bit_clear = (rte_bitmap_get(port->bmp, qindex + i) == 0);
1114 if (queue_empty != bmp_bit_clear){
1115 rte_panic("Queue status mismatch for queue %u of pipe %u\n", i, pindex);
1127 debug_check_queue_slab(struct rte_sched_port *port, uint32_t bmp_pos, uint64_t bmp_slab)
1133 rte_panic("Empty slab at position %u\n", bmp_pos);
1137 for (i = 0, mask = 1; i < 64; i ++, mask <<= 1) {
1138 if (mask & bmp_slab){
1139 if (rte_sched_port_queue_is_empty(port, bmp_pos + i)) {
1140 printf("Queue %u (slab offset %u) is empty\n", bmp_pos + i, i);
1147 rte_panic("Empty queues in slab 0x%" PRIx64 "starting at position %u\n",
1152 #endif /* RTE_SCHED_DEBUG */
1154 static inline uint32_t
1155 rte_sched_port_enqueue_qptrs_prefetch0(struct rte_sched_port *port, struct rte_mbuf *pkt)
1157 struct rte_sched_queue *q;
1158 #ifdef RTE_SCHED_COLLECT_STATS
1159 struct rte_sched_queue_extra *qe;
1161 uint32_t subport, pipe, traffic_class, queue, qindex;
1163 rte_sched_port_pkt_read_tree_path(pkt, &subport, &pipe, &traffic_class, &queue);
1165 qindex = rte_sched_port_qindex(port, subport, pipe, traffic_class, queue);
1166 q = port->queue + qindex;
1168 #ifdef RTE_SCHED_COLLECT_STATS
1169 qe = port->queue_extra + qindex;
1177 rte_sched_port_enqueue_qwa_prefetch0(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf **qbase)
1179 struct rte_sched_queue *q;
1180 struct rte_mbuf **q_qw;
1183 q = port->queue + qindex;
1184 qsize = rte_sched_port_qsize(port, qindex);
1185 q_qw = qbase + (q->qw & (qsize - 1));
1187 rte_prefetch0(q_qw);
1188 rte_bitmap_prefetch0(port->bmp, qindex);
1192 rte_sched_port_enqueue_qwa(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf **qbase, struct rte_mbuf *pkt)
1194 struct rte_sched_queue *q;
1198 q = port->queue + qindex;
1199 qsize = rte_sched_port_qsize(port, qindex);
1200 qlen = q->qw - q->qr;
1202 /* Drop the packet (and update drop stats) when queue is full */
1203 if (unlikely(rte_sched_port_red_drop(port, pkt, qindex, qlen) || (qlen >= qsize))) {
1204 rte_pktmbuf_free(pkt);
1205 #ifdef RTE_SCHED_COLLECT_STATS
1206 rte_sched_port_update_subport_stats_on_drop(port, qindex, pkt);
1207 rte_sched_port_update_queue_stats_on_drop(port, qindex, pkt);
1212 /* Enqueue packet */
1213 qbase[q->qw & (qsize - 1)] = pkt;
1216 /* Activate queue in the port bitmap */
1217 rte_bitmap_set(port->bmp, qindex);
1220 #ifdef RTE_SCHED_COLLECT_STATS
1221 rte_sched_port_update_subport_stats(port, qindex, pkt);
1222 rte_sched_port_update_queue_stats(port, qindex, pkt);
1228 #if RTE_SCHED_ENQUEUE == 0
1231 rte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
1237 for (i = 0; i < n_pkts; i ++) {
1238 struct rte_mbuf *pkt;
1239 struct rte_mbuf **q_base;
1240 uint32_t subport, pipe, traffic_class, queue, qindex;
1244 rte_sched_port_pkt_read_tree_path(pkt, &subport, &pipe, &traffic_class, &queue);
1246 qindex = rte_sched_port_qindex(port, subport, pipe, traffic_class, queue);
1248 q_base = rte_sched_port_qbase(port, qindex);
1250 result += rte_sched_port_enqueue_qwa(port, qindex, q_base, pkt);
1258 /* The enqueue function implements a 4-level pipeline with each stage processing
1259 * two different packets. The purpose of using a pipeline is to hide the latency
1260 * of prefetching the data structures. The naming convention is presented in the
1263 * p00 _______ p10 _______ p20 _______ p30 _______
1264 * ----->| |----->| |----->| |----->| |----->
1265 * | 0 | | 1 | | 2 | | 3 |
1266 * ----->|_______|----->|_______|----->|_______|----->|_______|----->
1271 rte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
1273 struct rte_mbuf *pkt00, *pkt01, *pkt10, *pkt11, *pkt20, *pkt21, *pkt30, *pkt31, *pkt_last;
1274 struct rte_mbuf **q00_base, **q01_base, **q10_base, **q11_base, **q20_base, **q21_base, **q30_base, **q31_base, **q_last_base;
1275 uint32_t q00, q01, q10, q11, q20, q21, q30, q31, q_last;
1276 uint32_t r00, r01, r10, r11, r20, r21, r30, r31, r_last;
1281 /* Less then 6 input packets available, which is not enough to feed the pipeline */
1282 if (unlikely(n_pkts < 6)) {
1283 struct rte_mbuf **q_base[5];
1286 /* Prefetch the mbuf structure of each packet */
1287 for (i = 0; i < n_pkts; i ++) {
1288 rte_prefetch0(pkts[i]);
1291 /* Prefetch the queue structure for each queue */
1292 for (i = 0; i < n_pkts; i ++) {
1293 q[i] = rte_sched_port_enqueue_qptrs_prefetch0(port, pkts[i]);
1296 /* Prefetch the write pointer location of each queue */
1297 for (i = 0; i < n_pkts; i ++) {
1298 q_base[i] = rte_sched_port_qbase(port, q[i]);
1299 rte_sched_port_enqueue_qwa_prefetch0(port, q[i], q_base[i]);
1302 /* Write each packet to its queue */
1303 for (i = 0; i < n_pkts; i ++) {
1304 result += rte_sched_port_enqueue_qwa(port, q[i], q_base[i], pkts[i]);
1310 /* Feed the first 3 stages of the pipeline (6 packets needed) */
1313 rte_prefetch0(pkt20);
1314 rte_prefetch0(pkt21);
1318 rte_prefetch0(pkt10);
1319 rte_prefetch0(pkt11);
1321 q20 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt20);
1322 q21 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt21);
1326 rte_prefetch0(pkt00);
1327 rte_prefetch0(pkt01);
1329 q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1330 q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1332 q20_base = rte_sched_port_qbase(port, q20);
1333 q21_base = rte_sched_port_qbase(port, q21);
1334 rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1335 rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1337 /* Run the pipeline */
1338 for (i = 6; i < (n_pkts & (~1)); i += 2) {
1339 /* Propagate stage inputs */
1350 q30_base = q20_base;
1351 q31_base = q21_base;
1353 /* Stage 0: Get packets in */
1355 pkt01 = pkts[i + 1];
1356 rte_prefetch0(pkt00);
1357 rte_prefetch0(pkt01);
1359 /* Stage 1: Prefetch queue structure storing queue pointers */
1360 q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1361 q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1363 /* Stage 2: Prefetch queue write location */
1364 q20_base = rte_sched_port_qbase(port, q20);
1365 q21_base = rte_sched_port_qbase(port, q21);
1366 rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1367 rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1369 /* Stage 3: Write packet to queue and activate queue */
1370 r30 = rte_sched_port_enqueue_qwa(port, q30, q30_base, pkt30);
1371 r31 = rte_sched_port_enqueue_qwa(port, q31, q31_base, pkt31);
1372 result += r30 + r31;
1375 /* Drain the pipeline (exactly 6 packets). Handle the last packet in the case
1376 of an odd number of input packets. */
1377 pkt_last = pkts[n_pkts - 1];
1378 rte_prefetch0(pkt_last);
1380 q00 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt00);
1381 q01 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt01);
1383 q10_base = rte_sched_port_qbase(port, q10);
1384 q11_base = rte_sched_port_qbase(port, q11);
1385 rte_sched_port_enqueue_qwa_prefetch0(port, q10, q10_base);
1386 rte_sched_port_enqueue_qwa_prefetch0(port, q11, q11_base);
1388 r20 = rte_sched_port_enqueue_qwa(port, q20, q20_base, pkt20);
1389 r21 = rte_sched_port_enqueue_qwa(port, q21, q21_base, pkt21);
1390 result += r20 + r21;
1392 q_last = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt_last);
1394 q00_base = rte_sched_port_qbase(port, q00);
1395 q01_base = rte_sched_port_qbase(port, q01);
1396 rte_sched_port_enqueue_qwa_prefetch0(port, q00, q00_base);
1397 rte_sched_port_enqueue_qwa_prefetch0(port, q01, q01_base);
1399 r10 = rte_sched_port_enqueue_qwa(port, q10, q10_base, pkt10);
1400 r11 = rte_sched_port_enqueue_qwa(port, q11, q11_base, pkt11);
1401 result += r10 + r11;
1403 q_last_base = rte_sched_port_qbase(port, q_last);
1404 rte_sched_port_enqueue_qwa_prefetch0(port, q_last, q_last_base);
1406 r00 = rte_sched_port_enqueue_qwa(port, q00, q00_base, pkt00);
1407 r01 = rte_sched_port_enqueue_qwa(port, q01, q01_base, pkt01);
1408 result += r00 + r01;
1411 r_last = rte_sched_port_enqueue_qwa(port, q_last, q_last_base, pkt_last);
1418 #endif /* RTE_SCHED_ENQUEUE */
1420 #if RTE_SCHED_TS_CREDITS_UPDATE == 0
1422 #define grinder_credits_update(port, pos)
1424 #elif !defined(RTE_SCHED_SUBPORT_TC_OV)
1427 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1429 struct rte_sched_grinder *grinder = port->grinder + pos;
1430 struct rte_sched_subport *subport = grinder->subport;
1431 struct rte_sched_pipe *pipe = grinder->pipe;
1432 struct rte_sched_pipe_profile *params = grinder->pipe_params;
1436 n_periods = (port->time - subport->tb_time) / subport->tb_period;
1437 subport->tb_credits += n_periods * subport->tb_credits_per_period;
1438 subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1439 subport->tb_time += n_periods * subport->tb_period;
1442 n_periods = (port->time - pipe->tb_time) / params->tb_period;
1443 pipe->tb_credits += n_periods * params->tb_credits_per_period;
1444 pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1445 pipe->tb_time += n_periods * params->tb_period;
1448 if (unlikely(port->time >= subport->tc_time)) {
1449 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1450 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1451 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1452 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1453 subport->tc_time = port->time + subport->tc_period;
1457 if (unlikely(port->time >= pipe->tc_time)) {
1458 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1459 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1460 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1461 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1462 pipe->tc_time = port->time + params->tc_period;
1469 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1471 struct rte_sched_grinder *grinder = port->grinder + pos;
1472 struct rte_sched_subport *subport = grinder->subport;
1473 struct rte_sched_pipe *pipe = grinder->pipe;
1474 struct rte_sched_pipe_profile *params = grinder->pipe_params;
1478 n_periods = (port->time - subport->tb_time) / subport->tb_period;
1479 subport->tb_credits += n_periods * subport->tb_credits_per_period;
1480 subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1481 subport->tb_time += n_periods * subport->tb_period;
1484 n_periods = (port->time - pipe->tb_time) / params->tb_period;
1485 pipe->tb_credits += n_periods * params->tb_credits_per_period;
1486 pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1487 pipe->tb_time += n_periods * params->tb_period;
1490 if (unlikely(port->time >= subport->tc_ov_time)) {
1491 uint64_t n_ov_periods;
1493 if (unlikely(port->time >= subport->tc_time)) {
1494 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1495 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1496 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1497 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1499 subport->tc_time = port->time + subport->tc_period;
1502 n_ov_periods = (subport->tc_time - port->time + subport->tc_ov_period - 1) / subport->tc_ov_period;
1504 subport->tc_ov_credits[0] = subport->tc_credits[0] / (n_ov_periods * subport->tc_ov_n[0]);
1505 subport->tc_ov_credits[1] = subport->tc_credits[1] / (n_ov_periods * subport->tc_ov_n[1]);
1506 subport->tc_ov_credits[2] = subport->tc_credits[2] / (n_ov_periods * subport->tc_ov_n[2]);
1507 subport->tc_ov_credits[3] = subport->tc_credits[3] / (n_ov_periods * subport->tc_ov_n[3]);
1509 subport->tc_ov_time = port->time + subport->tc_ov_period;
1510 subport->tc_ov_period_id ++;
1514 if (unlikely(port->time >= pipe->tc_time)) {
1515 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1516 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1517 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1518 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1519 pipe->tc_time = port->time + params->tc_period;
1521 if (unlikely(pipe->tc_ov_period_id != subport->tc_ov_period_id)) {
1522 uint32_t pipe_tc_ov_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
1523 uint32_t tc_mask[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
1524 uint32_t mask[] = {UINT32_MAX, 0};
1526 tc_mask[0] = mask[subport->tc_ov[0]];
1527 tc_mask[1] = mask[subport->tc_ov[1]];
1528 tc_mask[2] = mask[subport->tc_ov[2]];
1529 tc_mask[3] = mask[subport->tc_ov[3]];
1531 pipe_tc_ov_credits[0] = subport->tc_ov_credits[0] * params->tc_ov_weight[0];
1532 pipe_tc_ov_credits[1] = subport->tc_ov_credits[1] * params->tc_ov_weight[1];
1533 pipe_tc_ov_credits[2] = subport->tc_ov_credits[2] * params->tc_ov_weight[2];
1534 pipe_tc_ov_credits[3] = subport->tc_ov_credits[3] * params->tc_ov_weight[3];
1536 pipe->tc_ov_credits[0] = (tc_mask[0] & pipe->tc_credits[0]) | ((~ tc_mask[0]) & pipe_tc_ov_credits[0]);
1537 pipe->tc_ov_credits[1] = (tc_mask[1] & pipe->tc_credits[1]) | ((~ tc_mask[1]) & pipe_tc_ov_credits[1]);
1538 pipe->tc_ov_credits[2] = (tc_mask[2] & pipe->tc_credits[2]) | ((~ tc_mask[2]) & pipe_tc_ov_credits[2]);
1539 pipe->tc_ov_credits[3] = (tc_mask[3] & pipe->tc_credits[3]) | ((~ tc_mask[3]) & pipe_tc_ov_credits[3]);
1541 pipe->tc_ov_period_id = subport->tc_ov_period_id;
1545 #endif /* RTE_SCHED_TS_CREDITS_UPDATE, RTE_SCHED_SUBPORT_TC_OV */
1547 #ifndef RTE_SCHED_SUBPORT_TC_OV
1550 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1552 struct rte_sched_grinder *grinder = port->grinder + pos;
1553 struct rte_sched_subport *subport = grinder->subport;
1554 struct rte_sched_pipe *pipe = grinder->pipe;
1555 struct rte_mbuf *pkt = grinder->pkt;
1556 uint32_t tc_index = grinder->tc_index;
1557 uint32_t pkt_len = pkt->pkt.pkt_len + port->frame_overhead;
1560 /* Check queue credits */
1561 enough_credits = (pkt_len <= subport->tb_credits) &&
1562 (pkt_len <= subport->tc_credits[tc_index]) &&
1563 (pkt_len <= pipe->tb_credits) &&
1564 (pkt_len <= pipe->tc_credits[tc_index]);
1566 if (!enough_credits) {
1570 /* Update port credits */
1571 subport->tb_credits -= pkt_len;
1572 subport->tc_credits[tc_index] -= pkt_len;
1573 pipe->tb_credits -= pkt_len;
1574 pipe->tc_credits[tc_index] -= pkt_len;
1582 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1584 struct rte_sched_grinder *grinder = port->grinder + pos;
1585 struct rte_sched_subport *subport = grinder->subport;
1586 struct rte_sched_pipe *pipe = grinder->pipe;
1587 struct rte_mbuf *pkt = grinder->pkt;
1588 uint32_t tc_index = grinder->tc_index;
1589 uint32_t pkt_len = pkt->pkt.pkt_len + port->frame_overhead;
1590 uint32_t subport_tb_credits = subport->tb_credits;
1591 uint32_t subport_tc_credits = subport->tc_credits[tc_index];
1592 uint32_t pipe_tb_credits = pipe->tb_credits;
1593 uint32_t pipe_tc_credits = pipe->tc_credits[tc_index];
1594 uint32_t pipe_tc_ov_credits = pipe->tc_ov_credits[tc_index];
1597 /* Check pipe and subport credits */
1598 enough_credits = (pkt_len <= subport_tb_credits) &&
1599 (pkt_len <= subport_tc_credits) &&
1600 (pkt_len <= pipe_tb_credits) &&
1601 (pkt_len <= pipe_tc_credits) &&
1602 (pkt_len <= pipe_tc_ov_credits);
1604 if (!enough_credits) {
1608 /* Update pipe and subport credits */
1609 subport->tb_credits -= pkt_len;
1610 subport->tc_credits[tc_index] -= pkt_len;
1611 pipe->tb_credits -= pkt_len;
1612 pipe->tc_credits[tc_index] -= pkt_len;
1613 pipe->tc_ov_credits[tc_index] -= pkt_len;
1618 #endif /* RTE_SCHED_SUBPORT_TC_OV */
1621 grinder_schedule(struct rte_sched_port *port, uint32_t pos)
1623 struct rte_sched_grinder *grinder = port->grinder + pos;
1624 struct rte_sched_queue *queue = grinder->queue[grinder->qpos];
1625 struct rte_mbuf *pkt = grinder->pkt;
1626 uint32_t pkt_len = pkt->pkt.pkt_len + port->frame_overhead;
1628 #if RTE_SCHED_TS_CREDITS_CHECK
1629 if (!grinder_credits_check(port, pos)) {
1634 /* Advance port time */
1635 port->time += pkt_len;
1638 port->pkts_out[port->n_pkts_out ++] = pkt;
1640 grinder->wrr_tokens[grinder->qpos] += pkt_len * grinder->wrr_cost[grinder->qpos];
1641 if (queue->qr == queue->qw) {
1642 uint32_t qindex = grinder->qindex[grinder->qpos];
1644 rte_bitmap_clear(port->bmp, qindex);
1645 grinder->qmask &= ~(1 << grinder->qpos);
1646 grinder->wrr_mask[grinder->qpos] = 0;
1647 rte_sched_port_set_queue_empty_timestamp(port, qindex);
1650 /* Reset pipe loop detection */
1651 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1652 grinder->productive = 1;
1657 #if RTE_SCHED_OPTIMIZATIONS
1660 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1662 __m128i index = _mm_set1_epi32 (base_pipe);
1663 __m128i pipes = _mm_load_si128((__m128i *)port->grinder_base_bmp_pos);
1664 __m128i res = _mm_cmpeq_epi32(pipes, index);
1665 pipes = _mm_load_si128((__m128i *)(port->grinder_base_bmp_pos + 4));
1666 pipes = _mm_cmpeq_epi32(pipes, index);
1667 res = _mm_or_si128(res, pipes);
1669 if (_mm_testz_si128(res, res))
1678 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1682 for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i ++) {
1683 if (port->grinder_base_bmp_pos[i] == base_pipe) {
1691 #endif /* RTE_SCHED_OPTIMIZATIONS */
1694 grinder_pcache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t bmp_pos, uint64_t bmp_slab)
1696 struct rte_sched_grinder *grinder = port->grinder + pos;
1699 grinder->pcache_w = 0;
1700 grinder->pcache_r = 0;
1702 w[0] = (uint16_t) bmp_slab;
1703 w[1] = (uint16_t) (bmp_slab >> 16);
1704 w[2] = (uint16_t) (bmp_slab >> 32);
1705 w[3] = (uint16_t) (bmp_slab >> 48);
1707 grinder->pcache_qmask[grinder->pcache_w] = w[0];
1708 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos;
1709 grinder->pcache_w += (w[0] != 0);
1711 grinder->pcache_qmask[grinder->pcache_w] = w[1];
1712 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 16;
1713 grinder->pcache_w += (w[1] != 0);
1715 grinder->pcache_qmask[grinder->pcache_w] = w[2];
1716 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 32;
1717 grinder->pcache_w += (w[2] != 0);
1719 grinder->pcache_qmask[grinder->pcache_w] = w[3];
1720 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 48;
1721 grinder->pcache_w += (w[3] != 0);
1725 grinder_tccache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t qindex, uint16_t qmask)
1727 struct rte_sched_grinder *grinder = port->grinder + pos;
1730 grinder->tccache_w = 0;
1731 grinder->tccache_r = 0;
1733 b[0] = (uint8_t) (qmask & 0xF);
1734 b[1] = (uint8_t) ((qmask >> 4) & 0xF);
1735 b[2] = (uint8_t) ((qmask >> 8) & 0xF);
1736 b[3] = (uint8_t) ((qmask >> 12) & 0xF);
1738 grinder->tccache_qmask[grinder->tccache_w] = b[0];
1739 grinder->tccache_qindex[grinder->tccache_w] = qindex;
1740 grinder->tccache_w += (b[0] != 0);
1742 grinder->tccache_qmask[grinder->tccache_w] = b[1];
1743 grinder->tccache_qindex[grinder->tccache_w] = qindex + 4;
1744 grinder->tccache_w += (b[1] != 0);
1746 grinder->tccache_qmask[grinder->tccache_w] = b[2];
1747 grinder->tccache_qindex[grinder->tccache_w] = qindex + 8;
1748 grinder->tccache_w += (b[2] != 0);
1750 grinder->tccache_qmask[grinder->tccache_w] = b[3];
1751 grinder->tccache_qindex[grinder->tccache_w] = qindex + 12;
1752 grinder->tccache_w += (b[3] != 0);
1756 grinder_next_tc(struct rte_sched_port *port, uint32_t pos)
1758 struct rte_sched_grinder *grinder = port->grinder + pos;
1759 struct rte_mbuf **qbase;
1763 if (grinder->tccache_r == grinder->tccache_w) {
1767 qindex = grinder->tccache_qindex[grinder->tccache_r];
1768 qbase = rte_sched_port_qbase(port, qindex);
1769 qsize = rte_sched_port_qsize(port, qindex);
1771 grinder->tc_index = (qindex >> 2) & 0x3;
1772 grinder->qmask = grinder->tccache_qmask[grinder->tccache_r];
1773 grinder->qsize = qsize;
1775 grinder->qindex[0] = qindex;
1776 grinder->qindex[1] = qindex + 1;
1777 grinder->qindex[2] = qindex + 2;
1778 grinder->qindex[3] = qindex + 3;
1780 grinder->queue[0] = port->queue + qindex;
1781 grinder->queue[1] = port->queue + qindex + 1;
1782 grinder->queue[2] = port->queue + qindex + 2;
1783 grinder->queue[3] = port->queue + qindex + 3;
1785 grinder->qbase[0] = qbase;
1786 grinder->qbase[1] = qbase + qsize;
1787 grinder->qbase[2] = qbase + 2 * qsize;
1788 grinder->qbase[3] = qbase + 3 * qsize;
1790 grinder->tccache_r ++;
1795 grinder_next_pipe(struct rte_sched_port *port, uint32_t pos)
1797 struct rte_sched_grinder *grinder = port->grinder + pos;
1798 uint32_t pipe_qindex;
1799 uint16_t pipe_qmask;
1801 if (grinder->pcache_r < grinder->pcache_w) {
1802 pipe_qmask = grinder->pcache_qmask[grinder->pcache_r];
1803 pipe_qindex = grinder->pcache_qindex[grinder->pcache_r];
1804 grinder->pcache_r ++;
1806 uint64_t bmp_slab = 0;
1807 uint32_t bmp_pos = 0;
1809 /* Get another non-empty pipe group */
1810 if (unlikely(rte_bitmap_scan(port->bmp, &bmp_pos, &bmp_slab) <= 0)) {
1815 debug_check_queue_slab(port, bmp_pos, bmp_slab);
1818 /* Return if pipe group already in one of the other grinders */
1819 port->grinder_base_bmp_pos[pos] = RTE_SCHED_BMP_POS_INVALID;
1820 if (unlikely(grinder_pipe_exists(port, bmp_pos))) {
1823 port->grinder_base_bmp_pos[pos] = bmp_pos;
1825 /* Install new pipe group into grinder's pipe cache */
1826 grinder_pcache_populate(port, pos, bmp_pos, bmp_slab);
1828 pipe_qmask = grinder->pcache_qmask[0];
1829 pipe_qindex = grinder->pcache_qindex[0];
1830 grinder->pcache_r = 1;
1833 /* Install new pipe in the grinder */
1834 grinder->pindex = pipe_qindex >> 4;
1835 grinder->subport = port->subport + (grinder->pindex / port->n_pipes_per_subport);
1836 grinder->pipe = port->pipe + grinder->pindex;
1837 grinder->pipe_params = NULL; /* to be set after the pipe structure is prefetched */
1838 grinder->productive = 0;
1840 grinder_tccache_populate(port, pos, pipe_qindex, pipe_qmask);
1841 grinder_next_tc(port, pos);
1843 /* Check for pipe exhaustion */
1844 if (grinder->pindex == port->pipe_loop) {
1845 port->pipe_exhaustion = 1;
1846 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1852 #if RTE_SCHED_WRR == 0
1854 #define grinder_wrr_load(a,b)
1856 #define grinder_wrr_store(a,b)
1859 grinder_wrr(struct rte_sched_port *port, uint32_t pos)
1861 struct rte_sched_grinder *grinder = port->grinder + pos;
1862 uint64_t slab = grinder->qmask;
1864 if (rte_bsf64(slab, &grinder->qpos) == 0) {
1865 rte_panic("grinder wrr\n");
1869 #elif RTE_SCHED_WRR == 1
1872 grinder_wrr_load(struct rte_sched_port *port, uint32_t pos)
1874 struct rte_sched_grinder *grinder = port->grinder + pos;
1875 struct rte_sched_pipe *pipe = grinder->pipe;
1876 struct rte_sched_pipe_profile *pipe_params = grinder->pipe_params;
1877 uint32_t tc_index = grinder->tc_index;
1878 uint32_t qmask = grinder->qmask;
1881 qindex = tc_index * 4;
1883 grinder->wrr_tokens[0] = ((uint16_t) pipe->wrr_tokens[qindex]) << RTE_SCHED_WRR_SHIFT;
1884 grinder->wrr_tokens[1] = ((uint16_t) pipe->wrr_tokens[qindex + 1]) << RTE_SCHED_WRR_SHIFT;
1885 grinder->wrr_tokens[2] = ((uint16_t) pipe->wrr_tokens[qindex + 2]) << RTE_SCHED_WRR_SHIFT;
1886 grinder->wrr_tokens[3] = ((uint16_t) pipe->wrr_tokens[qindex + 3]) << RTE_SCHED_WRR_SHIFT;
1888 grinder->wrr_mask[0] = (qmask & 0x1) * 0xFFFF;
1889 grinder->wrr_mask[1] = ((qmask >> 1) & 0x1) * 0xFFFF;
1890 grinder->wrr_mask[2] = ((qmask >> 2) & 0x1) * 0xFFFF;
1891 grinder->wrr_mask[3] = ((qmask >> 3) & 0x1) * 0xFFFF;
1893 grinder->wrr_cost[0] = pipe_params->wrr_cost[qindex];
1894 grinder->wrr_cost[1] = pipe_params->wrr_cost[qindex + 1];
1895 grinder->wrr_cost[2] = pipe_params->wrr_cost[qindex + 2];
1896 grinder->wrr_cost[3] = pipe_params->wrr_cost[qindex + 3];
1900 grinder_wrr_store(struct rte_sched_port *port, uint32_t pos)
1902 struct rte_sched_grinder *grinder = port->grinder + pos;
1903 struct rte_sched_pipe *pipe = grinder->pipe;
1904 uint32_t tc_index = grinder->tc_index;
1907 qindex = tc_index * 4;
1909 pipe->wrr_tokens[qindex] = (uint8_t) ((grinder->wrr_tokens[0] & grinder->wrr_mask[0]) >> RTE_SCHED_WRR_SHIFT);
1910 pipe->wrr_tokens[qindex + 1] = (uint8_t) ((grinder->wrr_tokens[1] & grinder->wrr_mask[1]) >> RTE_SCHED_WRR_SHIFT);
1911 pipe->wrr_tokens[qindex + 2] = (uint8_t) ((grinder->wrr_tokens[2] & grinder->wrr_mask[2]) >> RTE_SCHED_WRR_SHIFT);
1912 pipe->wrr_tokens[qindex + 3] = (uint8_t) ((grinder->wrr_tokens[3] & grinder->wrr_mask[3]) >> RTE_SCHED_WRR_SHIFT);
1916 grinder_wrr(struct rte_sched_port *port, uint32_t pos)
1918 struct rte_sched_grinder *grinder = port->grinder + pos;
1919 uint16_t wrr_tokens_min;
1921 grinder->wrr_tokens[0] |= ~grinder->wrr_mask[0];
1922 grinder->wrr_tokens[1] |= ~grinder->wrr_mask[1];
1923 grinder->wrr_tokens[2] |= ~grinder->wrr_mask[2];
1924 grinder->wrr_tokens[3] |= ~grinder->wrr_mask[3];
1926 grinder->qpos = rte_min_pos_4_u16(grinder->wrr_tokens);
1927 wrr_tokens_min = grinder->wrr_tokens[grinder->qpos];
1929 grinder->wrr_tokens[0] -= wrr_tokens_min;
1930 grinder->wrr_tokens[1] -= wrr_tokens_min;
1931 grinder->wrr_tokens[2] -= wrr_tokens_min;
1932 grinder->wrr_tokens[3] -= wrr_tokens_min;
1937 #error Invalid value for RTE_SCHED_WRR
1939 #endif /* RTE_SCHED_WRR */
1941 #define grinder_evict(port, pos)
1944 grinder_prefetch_pipe(struct rte_sched_port *port, uint32_t pos)
1946 struct rte_sched_grinder *grinder = port->grinder + pos;
1948 rte_prefetch0(grinder->pipe);
1949 rte_prefetch0(grinder->queue[0]);
1953 grinder_prefetch_tc_queue_arrays(struct rte_sched_port *port, uint32_t pos)
1955 struct rte_sched_grinder *grinder = port->grinder + pos;
1956 uint16_t qsize, qr[4];
1958 qsize = grinder->qsize;
1959 qr[0] = grinder->queue[0]->qr & (qsize - 1);
1960 qr[1] = grinder->queue[1]->qr & (qsize - 1);
1961 qr[2] = grinder->queue[2]->qr & (qsize - 1);
1962 qr[3] = grinder->queue[3]->qr & (qsize - 1);
1964 rte_prefetch0(grinder->qbase[0] + qr[0]);
1965 rte_prefetch0(grinder->qbase[1] + qr[1]);
1967 grinder_wrr_load(port, pos);
1968 grinder_wrr(port, pos);
1970 rte_prefetch0(grinder->qbase[2] + qr[2]);
1971 rte_prefetch0(grinder->qbase[3] + qr[3]);
1975 grinder_prefetch_mbuf(struct rte_sched_port *port, uint32_t pos)
1977 struct rte_sched_grinder *grinder = port->grinder + pos;
1978 uint32_t qpos = grinder->qpos;
1979 struct rte_mbuf **qbase = grinder->qbase[qpos];
1980 uint16_t qsize = grinder->qsize;
1981 uint16_t qr = grinder->queue[qpos]->qr & (qsize - 1);
1983 grinder->pkt = qbase[qr];
1984 rte_prefetch0(grinder->pkt);
1986 if (unlikely((qr & 0x7) == 7)) {
1987 uint16_t qr_next = (grinder->queue[qpos]->qr + 1) & (qsize - 1);
1989 rte_prefetch0(qbase + qr_next);
1993 static inline uint32_t
1994 grinder_handle(struct rte_sched_port *port, uint32_t pos)
1996 struct rte_sched_grinder *grinder = port->grinder + pos;
1998 switch (grinder->state) {
1999 case e_GRINDER_PREFETCH_PIPE:
2001 if (grinder_next_pipe(port, pos)) {
2002 grinder_prefetch_pipe(port, pos);
2003 port->busy_grinders ++;
2005 grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2012 case e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS:
2014 struct rte_sched_pipe *pipe = grinder->pipe;
2016 grinder->pipe_params = port->pipe_profiles + pipe->profile;
2017 grinder_prefetch_tc_queue_arrays(port, pos);
2018 grinder_credits_update(port, pos);
2020 grinder->state = e_GRINDER_PREFETCH_MBUF;
2024 case e_GRINDER_PREFETCH_MBUF:
2026 grinder_prefetch_mbuf(port, pos);
2028 grinder->state = e_GRINDER_READ_MBUF;
2032 case e_GRINDER_READ_MBUF:
2034 uint32_t result = 0;
2036 result = grinder_schedule(port, pos);
2038 /* Look for next packet within the same TC */
2039 if (result && grinder->qmask) {
2040 grinder_wrr(port, pos);
2041 grinder_prefetch_mbuf(port, pos);
2045 grinder_wrr_store(port, pos);
2047 /* Look for another active TC within same pipe */
2048 if (grinder_next_tc(port, pos)) {
2049 grinder_prefetch_tc_queue_arrays(port, pos);
2051 grinder->state = e_GRINDER_PREFETCH_MBUF;
2054 if ((grinder->productive == 0) && (port->pipe_loop == RTE_SCHED_PIPE_INVALID)) {
2055 port->pipe_loop = grinder->pindex;
2057 grinder_evict(port, pos);
2059 /* Look for another active pipe */
2060 if (grinder_next_pipe(port, pos)) {
2061 grinder_prefetch_pipe(port, pos);
2063 grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2067 /* No active pipe found */
2068 port->busy_grinders --;
2070 grinder->state = e_GRINDER_PREFETCH_PIPE;
2075 rte_panic("Algorithmic error (invalid state)\n");
2081 rte_sched_port_time_resync(struct rte_sched_port *port)
2083 uint64_t cycles = rte_get_tsc_cycles();
2084 uint64_t cycles_diff = cycles - port->time_cpu_cycles;
2085 double bytes_diff = ((double) cycles_diff) / port->cycles_per_byte;
2087 /* Advance port time */
2088 port->time_cpu_cycles = cycles;
2089 port->time_cpu_bytes += (uint64_t) bytes_diff;
2090 if (port->time < port->time_cpu_bytes) {
2091 port->time = port->time_cpu_bytes;
2094 /* Reset pipe loop detection */
2095 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
2099 rte_sched_port_exceptions(struct rte_sched_port *port)
2103 /* Check if any exception flag is set */
2104 exceptions = (port->busy_grinders == 0) ||
2105 (port->pipe_exhaustion == 1);
2107 /* Clear exception flags */
2108 port->pipe_exhaustion = 0;
2114 rte_sched_port_dequeue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
2118 port->pkts_out = pkts;
2119 port->n_pkts_out = 0;
2121 rte_sched_port_time_resync(port);
2123 /* Take each queue in the grinder one step further */
2124 for (i = 0, count = 0; ; i ++) {
2125 count += grinder_handle(port, i & (RTE_SCHED_PORT_N_GRINDERS - 1));
2126 if ((count == n_pkts) || rte_sched_port_exceptions(port)) {