4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef __INCLUDE_RTE_LRU_X86_H__
35 #define __INCLUDE_RTE_LRU_X86_H__
43 #ifdef __INTEL_COMPILER
44 #define GCC_VERSION (0)
46 #define GCC_VERSION (__GNUC__ * 10000+__GNUC_MINOR__*100 + __GNUC_PATCHLEVEL__)
49 #ifndef RTE_TABLE_HASH_LRU_STRATEGY
51 #define RTE_TABLE_HASH_LRU_STRATEGY 2
52 #else /* if no SSE, use simple scalar version */
53 #define RTE_TABLE_HASH_LRU_STRATEGY 1
57 #if RTE_TABLE_HASH_LRU_STRATEGY == 2
59 #if GCC_VERSION > 40306
60 #include <x86intrin.h>
62 #include <emmintrin.h>
63 #include <smmintrin.h>
64 #include <xmmintrin.h>
67 #define lru_init(bucket) \
68 { bucket->lru_list = 0x0000000100020003LLU; }
70 #define lru_pos(bucket) (bucket->lru_list & 0xFFFFLLU)
72 #define lru_update(bucket, mru_val) \
74 /* set up the masks for all possible shuffles, depends on pos */\
75 static uint64_t masks[10] = { \
76 /* Shuffle order; Make Zero (see _mm_shuffle_epi8 manual) */\
77 0x0100070605040302, 0x8080808080808080, \
78 0x0302070605040100, 0x8080808080808080, \
79 0x0504070603020100, 0x8080808080808080, \
80 0x0706050403020100, 0x8080808080808080, \
81 0x0706050403020100, 0x8080808080808080}; \
82 /* load up one register with repeats of mru-val */ \
83 uint64_t mru2 = mru_val; \
84 uint64_t mru3 = mru2 | (mru2 << 16); \
85 uint64_t lru = bucket->lru_list; \
86 /* XOR to cause the word we're looking for to go to zero */ \
87 uint64_t mru = lru ^ ((mru3 << 32) | mru3); \
88 __m128i c = _mm_cvtsi64_si128(mru); \
89 __m128i b = _mm_cvtsi64_si128(lru); \
90 /* Find the minimum value (first zero word, if it's in there) */\
91 __m128i d = _mm_minpos_epu16(c); \
92 /* Second word is the index to found word (first word is the value) */\
93 unsigned int pos = _mm_extract_epi16(d, 1); \
94 /* move the recently used location to top of list */ \
95 __m128i k = _mm_shuffle_epi8(b, *((__m128i *) &masks[2 * pos]));\
96 /* Finally, update the original list with the reordered data */ \
97 bucket->lru_list = _mm_extract_epi64(k, 0); \
101 #elif RTE_TABLE_HASH_LRU_STRATEGY == 3
103 #if GCC_VERSION > 40306
104 #include <x86intrin.h>
106 #include <emmintrin.h>
107 #include <smmintrin.h>
108 #include <xmmintrin.h>
111 #define lru_init(bucket) \
112 { bucket->lru_list = ~0LLU; }
115 f_lru_pos(uint64_t lru_list)
117 __m128i lst = _mm_set_epi64x((uint64_t)-1, lru_list);
118 __m128i min = _mm_minpos_epu16(lst);
119 return _mm_extract_epi16(min, 1);
121 #define lru_pos(bucket) f_lru_pos(bucket->lru_list)
123 #define lru_update(bucket, mru_val) \
125 const uint64_t orvals[] = {0xFFFFLLU, 0xFFFFLLU << 16, \
126 0xFFFFLLU << 32, 0xFFFFLLU << 48, 0LLU}; \
127 const uint64_t decs[] = {0x1000100010001LLU, 0}; \
128 __m128i lru = _mm_cvtsi64_si128(bucket->lru_list); \
129 __m128i vdec = _mm_cvtsi64_si128(decs[mru_val>>2]); \
130 lru = _mm_subs_epu16(lru, vdec); \
131 bucket->lru_list = _mm_extract_epi64(lru, 0) | orvals[mru_val]; \