4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #ifndef APP_MAX_SOCKETS
39 #define APP_MAX_SOCKETS 2
42 #ifndef APP_MAX_LCORES
43 #define APP_MAX_LCORES RTE_MAX_LCORE
46 #ifndef APP_MAX_NIC_PORTS
47 #define APP_MAX_NIC_PORTS RTE_MAX_ETHPORTS
50 #ifndef APP_MAX_RX_QUEUES_PER_NIC_PORT
51 #define APP_MAX_RX_QUEUES_PER_NIC_PORT 128
54 #ifndef APP_MAX_TX_QUEUES_PER_NIC_PORT
55 #define APP_MAX_TX_QUEUES_PER_NIC_PORT 128
58 #ifndef APP_MAX_IO_LCORES
59 #if (APP_MAX_LCORES > 16)
60 #define APP_MAX_IO_LCORES 16
62 #define APP_MAX_IO_LCORES APP_MAX_LCORES
65 #if (APP_MAX_IO_LCORES > APP_MAX_LCORES)
66 #error "APP_MAX_IO_LCORES is too big"
69 #ifndef APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE
70 #define APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE 16
73 #ifndef APP_MAX_NIC_TX_PORTS_PER_IO_LCORE
74 #define APP_MAX_NIC_TX_PORTS_PER_IO_LCORE 16
76 #if (APP_MAX_NIC_TX_PORTS_PER_IO_LCORE > APP_MAX_NIC_PORTS)
77 #error "APP_MAX_NIC_TX_PORTS_PER_IO_LCORE too big"
80 #ifndef APP_MAX_WORKER_LCORES
81 #if (APP_MAX_LCORES > 16)
82 #define APP_MAX_WORKER_LCORES 16
84 #define APP_MAX_WORKER_LCORES APP_MAX_LCORES
87 #if (APP_MAX_WORKER_LCORES > APP_MAX_LCORES)
88 #error "APP_MAX_WORKER_LCORES is too big"
93 #ifndef APP_DEFAULT_MBUF_DATA_SIZE
94 #define APP_DEFAULT_MBUF_DATA_SIZE RTE_MBUF_DEFAULT_BUF_SIZE
97 #ifndef APP_DEFAULT_MEMPOOL_BUFFERS
98 #define APP_DEFAULT_MEMPOOL_BUFFERS 8192 * 4
101 #ifndef APP_DEFAULT_MEMPOOL_CACHE_SIZE
102 #define APP_DEFAULT_MEMPOOL_CACHE_SIZE 256
106 #ifndef APP_MAX_LPM_RULES
107 #define APP_MAX_LPM_RULES 1024
111 #ifndef APP_DEFAULT_NIC_RX_RING_SIZE
112 #define APP_DEFAULT_NIC_RX_RING_SIZE 1024
116 * RX and TX Prefetch, Host, and Write-back threshold values should be
117 * carefully set for optimal performance. Consult the network
118 * controller's datasheet and supporting DPDK documentation for guidance
119 * on how these parameters should be set.
121 #ifndef APP_DEFAULT_NIC_RX_PTHRESH
122 #define APP_DEFAULT_NIC_RX_PTHRESH 8
125 #ifndef APP_DEFAULT_NIC_RX_HTHRESH
126 #define APP_DEFAULT_NIC_RX_HTHRESH 8
129 #ifndef APP_DEFAULT_NIC_RX_WTHRESH
130 #define APP_DEFAULT_NIC_RX_WTHRESH 4
133 #ifndef APP_DEFAULT_NIC_RX_FREE_THRESH
134 #define APP_DEFAULT_NIC_RX_FREE_THRESH 64
137 #ifndef APP_DEFAULT_NIC_RX_DROP_EN
138 #define APP_DEFAULT_NIC_RX_DROP_EN 0
142 #ifndef APP_DEFAULT_NIC_TX_RING_SIZE
143 #define APP_DEFAULT_NIC_TX_RING_SIZE 1024
147 * These default values are optimized for use with the Intel(R) 82599 10 GbE
148 * Controller and the DPDK ixgbe PMD. Consider using other values for other
149 * network controllers and/or network drivers.
151 #ifndef APP_DEFAULT_NIC_TX_PTHRESH
152 #define APP_DEFAULT_NIC_TX_PTHRESH 36
155 #ifndef APP_DEFAULT_NIC_TX_HTHRESH
156 #define APP_DEFAULT_NIC_TX_HTHRESH 0
159 #ifndef APP_DEFAULT_NIC_TX_WTHRESH
160 #define APP_DEFAULT_NIC_TX_WTHRESH 0
163 #ifndef APP_DEFAULT_NIC_TX_FREE_THRESH
164 #define APP_DEFAULT_NIC_TX_FREE_THRESH 0
167 #ifndef APP_DEFAULT_NIC_TX_RS_THRESH
168 #define APP_DEFAULT_NIC_TX_RS_THRESH 0
172 #ifndef APP_DEFAULT_RING_RX_SIZE
173 #define APP_DEFAULT_RING_RX_SIZE 1024
176 #ifndef APP_DEFAULT_RING_TX_SIZE
177 #define APP_DEFAULT_RING_TX_SIZE 1024
181 #ifndef APP_MBUF_ARRAY_SIZE
182 #define APP_MBUF_ARRAY_SIZE 512
185 #ifndef APP_DEFAULT_BURST_SIZE_IO_RX_READ
186 #define APP_DEFAULT_BURST_SIZE_IO_RX_READ 144
188 #if (APP_DEFAULT_BURST_SIZE_IO_RX_READ > APP_MBUF_ARRAY_SIZE)
189 #error "APP_DEFAULT_BURST_SIZE_IO_RX_READ is too big"
192 #ifndef APP_DEFAULT_BURST_SIZE_IO_RX_WRITE
193 #define APP_DEFAULT_BURST_SIZE_IO_RX_WRITE 144
195 #if (APP_DEFAULT_BURST_SIZE_IO_RX_WRITE > APP_MBUF_ARRAY_SIZE)
196 #error "APP_DEFAULT_BURST_SIZE_IO_RX_WRITE is too big"
199 #ifndef APP_DEFAULT_BURST_SIZE_IO_TX_READ
200 #define APP_DEFAULT_BURST_SIZE_IO_TX_READ 144
202 #if (APP_DEFAULT_BURST_SIZE_IO_TX_READ > APP_MBUF_ARRAY_SIZE)
203 #error "APP_DEFAULT_BURST_SIZE_IO_TX_READ is too big"
206 #ifndef APP_DEFAULT_BURST_SIZE_IO_TX_WRITE
207 #define APP_DEFAULT_BURST_SIZE_IO_TX_WRITE 144
209 #if (APP_DEFAULT_BURST_SIZE_IO_TX_WRITE > APP_MBUF_ARRAY_SIZE)
210 #error "APP_DEFAULT_BURST_SIZE_IO_TX_WRITE is too big"
213 #ifndef APP_DEFAULT_BURST_SIZE_WORKER_READ
214 #define APP_DEFAULT_BURST_SIZE_WORKER_READ 144
216 #if ((2 * APP_DEFAULT_BURST_SIZE_WORKER_READ) > APP_MBUF_ARRAY_SIZE)
217 #error "APP_DEFAULT_BURST_SIZE_WORKER_READ is too big"
220 #ifndef APP_DEFAULT_BURST_SIZE_WORKER_WRITE
221 #define APP_DEFAULT_BURST_SIZE_WORKER_WRITE 144
223 #if (APP_DEFAULT_BURST_SIZE_WORKER_WRITE > APP_MBUF_ARRAY_SIZE)
224 #error "APP_DEFAULT_BURST_SIZE_WORKER_WRITE is too big"
227 /* Load balancing logic */
228 #ifndef APP_DEFAULT_IO_RX_LB_POS
229 #define APP_DEFAULT_IO_RX_LB_POS 29
231 #if (APP_DEFAULT_IO_RX_LB_POS >= 64)
232 #error "APP_DEFAULT_IO_RX_LB_POS is too big"
235 struct app_mbuf_array {
236 struct rte_mbuf *array[APP_MBUF_ARRAY_SIZE];
240 enum app_lcore_type {
241 e_APP_LCORE_DISABLED = 0,
246 struct app_lcore_params_io {
253 } nic_queues[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
254 uint32_t n_nic_queues;
257 struct rte_ring *rings[APP_MAX_WORKER_LCORES];
260 /* Internal buffers */
261 struct app_mbuf_array mbuf_in;
262 struct app_mbuf_array mbuf_out[APP_MAX_WORKER_LCORES];
263 uint8_t mbuf_out_flush[APP_MAX_WORKER_LCORES];
266 uint32_t nic_queues_count[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
267 uint32_t nic_queues_iters[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
268 uint32_t rings_count[APP_MAX_WORKER_LCORES];
269 uint32_t rings_iters[APP_MAX_WORKER_LCORES];
275 struct rte_ring *rings[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
278 uint16_t nic_ports[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
279 uint32_t n_nic_ports;
281 /* Internal buffers */
282 struct app_mbuf_array mbuf_out[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
283 uint8_t mbuf_out_flush[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
286 uint32_t rings_count[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
287 uint32_t rings_iters[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
288 uint32_t nic_ports_count[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
289 uint32_t nic_ports_iters[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
293 struct app_lcore_params_worker {
295 struct rte_ring *rings_in[APP_MAX_IO_LCORES];
297 struct rte_ring *rings_out[APP_MAX_NIC_PORTS];
300 struct rte_lpm *lpm_table;
303 /* Internal buffers */
304 struct app_mbuf_array mbuf_in;
305 struct app_mbuf_array mbuf_out[APP_MAX_NIC_PORTS];
306 uint8_t mbuf_out_flush[APP_MAX_NIC_PORTS];
309 uint32_t rings_in_count[APP_MAX_IO_LCORES];
310 uint32_t rings_in_iters[APP_MAX_IO_LCORES];
311 uint32_t rings_out_count[APP_MAX_NIC_PORTS];
312 uint32_t rings_out_iters[APP_MAX_NIC_PORTS];
315 struct app_lcore_params {
317 struct app_lcore_params_io io;
318 struct app_lcore_params_worker worker;
320 enum app_lcore_type type;
321 struct rte_mempool *pool;
322 } __rte_cache_aligned;
324 struct app_lpm_rule {
332 struct app_lcore_params lcore_params[APP_MAX_LCORES];
335 uint8_t nic_rx_queue_mask[APP_MAX_NIC_PORTS][APP_MAX_RX_QUEUES_PER_NIC_PORT];
336 uint8_t nic_tx_port_mask[APP_MAX_NIC_PORTS];
339 struct rte_mempool *pools[APP_MAX_SOCKETS];
342 struct rte_lpm *lpm_tables[APP_MAX_SOCKETS];
343 struct app_lpm_rule lpm_rules[APP_MAX_LPM_RULES];
344 uint32_t n_lpm_rules;
347 uint32_t nic_rx_ring_size;
348 uint32_t nic_tx_ring_size;
349 uint32_t ring_rx_size;
350 uint32_t ring_tx_size;
353 uint32_t burst_size_io_rx_read;
354 uint32_t burst_size_io_rx_write;
355 uint32_t burst_size_io_tx_read;
356 uint32_t burst_size_io_tx_write;
357 uint32_t burst_size_worker_read;
358 uint32_t burst_size_worker_write;
362 } __rte_cache_aligned;
364 extern struct app_params app;
366 int app_parse_args(int argc, char **argv);
367 void app_print_usage(void);
369 int app_lcore_main_loop(void *arg);
371 int app_get_nic_rx_queues_per_port(uint16_t port);
372 int app_get_lcore_for_nic_rx(uint16_t port, uint8_t queue,
373 uint32_t *lcore_out);
374 int app_get_lcore_for_nic_tx(uint16_t port, uint32_t *lcore_out);
375 int app_is_socket_used(uint32_t socket);
376 uint32_t app_get_lcores_io_rx(void);
377 uint32_t app_get_lcores_worker(void);
378 void app_print_params(void);
380 #endif /* _MAIN_H_ */