1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
11 #if EFSYS_OPT_MEDFORD2
13 static __checkReturn efx_rc_t
14 medford2_nic_get_required_pcie_bandwidth(
16 __out uint32_t *bandwidth_mbpsp)
19 uint32_t current_mode;
23 /* FIXME: support new Medford2 dynamic port modes */
25 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
26 ¤t_mode)) != 0) {
27 /* No port mode info available. */
32 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
37 *bandwidth_mbpsp = bandwidth;
42 EFSYS_PROBE1(fail1, efx_rc_t, rc);
47 __checkReturn efx_rc_t
51 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
52 uint32_t sysclk, dpcpu_clk;
58 * Enable firmware workarounds for hardware errata.
59 * Expected responses are:
61 * Success: workaround enabled or disabled as requested.
62 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
63 * Firmware does not support the MC_CMD_WORKAROUND request.
64 * (assume that the workaround is not supported).
65 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
66 * Firmware does not support the requested workaround.
67 * - MC_CMD_ERR_EPERM (reported as EACCES):
68 * Unprivileged function cannot enable/disable workarounds.
70 * See efx_mcdi_request_errcode() for MCDI error translations.
74 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
76 * Interrupt testing does not work for VFs on Medford2.
77 * See bug50084 and bug71432 comment 21.
79 encp->enc_bug41750_workaround = B_TRUE;
82 /* Chained multicast is always enabled on Medford2 */
83 encp->enc_bug26807_workaround = B_TRUE;
86 * If the bug61265 workaround is enabled, then interrupt holdoff timers
87 * cannot be controlled by timer table writes, so MCDI must be used
88 * (timer table writes can still be used for wakeup timers).
90 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
92 if ((rc == 0) || (rc == EACCES))
93 encp->enc_bug61265_workaround = B_TRUE;
94 else if ((rc == ENOTSUP) || (rc == ENOENT))
95 encp->enc_bug61265_workaround = B_FALSE;
99 /* Get clock frequencies (in MHz). */
100 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
104 * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
105 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
107 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
108 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
109 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
111 /* Alignment for receive packet DMA buffers */
112 encp->enc_rx_buf_align_start = 1;
114 /* Get the RX DMA end padding alignment configuration */
115 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
119 /* Assume largest tail padding size supported by hardware */
122 encp->enc_rx_buf_align_end = end_padding;
125 * The maximum supported transmit queue size is 2048. TXQs with 4096
126 * descriptors are not supported as the top bit is used for vfifo
129 encp->enc_txq_max_ndescs = 2048;
131 EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
132 encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
133 encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE;
134 encp->enc_piobuf_min_alloc_size = MEDFORD2_MIN_PIO_ALLOC_SIZE;
137 * Medford2 stores a single global copy of VPD, not per-PF as on
140 encp->enc_vpd_is_global = B_TRUE;
142 rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
145 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
146 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
157 EFSYS_PROBE1(fail1, efx_rc_t, rc);
162 #endif /* EFSYS_OPT_MEDFORD2 */