4 * Copyright 2017 6WIND S.A.
5 * Copyright 2017 Mellanox
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36 * Data plane functions for mlx4 driver.
43 /* Verbs headers do not support -pedantic. */
45 #pragma GCC diagnostic ignored "-Wpedantic"
47 #include <infiniband/verbs.h>
49 #pragma GCC diagnostic error "-Wpedantic"
52 #include <rte_branch_prediction.h>
53 #include <rte_common.h>
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
61 #include "mlx4_rxtx.h"
62 #include "mlx4_utils.h"
65 * Pointer-value pair structure used in tx_post_send for saving the first
66 * DWORD (32 byte) of a TXBB.
69 volatile struct mlx4_wqe_data_seg *dseg;
73 /** A table to translate Rx completion flags to packet type. */
74 uint32_t mlx4_ptype_table[0x100] __rte_cache_aligned = {
76 * The index to the array should have:
77 * bit[7] - MLX4_CQE_L2_TUNNEL
78 * bit[6] - MLX4_CQE_L2_TUNNEL_IPV4
79 * bit[5] - MLX4_CQE_STATUS_UDP
80 * bit[4] - MLX4_CQE_STATUS_TCP
81 * bit[3] - MLX4_CQE_STATUS_IPV4OPT
82 * bit[2] - MLX4_CQE_STATUS_IPV6
83 * bit[1] - MLX4_CQE_STATUS_IPV4F
84 * bit[0] - MLX4_CQE_STATUS_IPV4
85 * giving a total of up to 256 entries.
87 [0x00] = RTE_PTYPE_L2_ETHER,
88 [0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
89 [0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
91 [0x03] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
93 [0x04] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
94 [0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT,
95 [0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
97 [0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
99 [0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
101 [0x14] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
103 [0x18] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
105 [0x19] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
107 [0x1a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
109 [0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
111 [0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
113 [0x24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
115 [0x28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
117 [0x29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
119 [0x2a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
121 /* Tunneled - L3 IPV6 */
122 [0x80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
123 [0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
124 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
125 [0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
126 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
127 RTE_PTYPE_INNER_L4_FRAG,
128 [0x83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
129 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
130 RTE_PTYPE_INNER_L4_FRAG,
131 [0x84] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
132 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
133 [0x88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
134 RTE_PTYPE_INNER_L3_IPV4_EXT,
135 [0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
136 RTE_PTYPE_INNER_L3_IPV4_EXT,
137 [0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
138 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG,
139 /* Tunneled - L3 IPV6, TCP */
140 [0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
141 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
142 RTE_PTYPE_INNER_L4_TCP,
143 [0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
144 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
145 RTE_PTYPE_INNER_L4_FRAG |
146 RTE_PTYPE_INNER_L4_TCP,
147 [0x93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
149 RTE_PTYPE_INNER_L4_FRAG |
150 RTE_PTYPE_INNER_L4_TCP,
151 [0x94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
152 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
153 RTE_PTYPE_INNER_L4_TCP,
154 [0x98] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
155 RTE_PTYPE_INNER_L3_IPV4_EXT |
156 RTE_PTYPE_INNER_L4_TCP,
157 [0x99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
158 RTE_PTYPE_INNER_L3_IPV4_EXT |
159 RTE_PTYPE_INNER_L4_TCP,
160 [0x9a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
161 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
162 RTE_PTYPE_INNER_L4_TCP,
163 /* Tunneled - L3 IPV6, UDP */
164 [0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
165 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
166 RTE_PTYPE_INNER_L4_UDP,
167 [0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
169 RTE_PTYPE_INNER_L4_FRAG |
170 RTE_PTYPE_INNER_L4_UDP,
171 [0xa3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
172 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L4_FRAG |
174 RTE_PTYPE_INNER_L4_UDP,
175 [0xa4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L4_UDP,
178 [0xa8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
179 RTE_PTYPE_INNER_L3_IPV4_EXT |
180 RTE_PTYPE_INNER_L4_UDP,
181 [0xa9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
182 RTE_PTYPE_INNER_L3_IPV4_EXT |
183 RTE_PTYPE_INNER_L4_UDP,
184 [0xaa] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
185 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
186 RTE_PTYPE_INNER_L4_UDP,
187 /* Tunneled - L3 IPV4 */
188 [0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
189 [0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
190 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
191 [0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
192 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
193 RTE_PTYPE_INNER_L4_FRAG,
194 [0xc3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
195 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
196 RTE_PTYPE_INNER_L4_FRAG,
197 [0xc4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
198 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
199 [0xc8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
200 RTE_PTYPE_INNER_L3_IPV4_EXT,
201 [0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
202 RTE_PTYPE_INNER_L3_IPV4_EXT,
203 [0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
204 RTE_PTYPE_INNER_L3_IPV4_EXT |
205 RTE_PTYPE_INNER_L4_FRAG,
206 /* Tunneled - L3 IPV4, TCP */
207 [0xd0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
208 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
209 RTE_PTYPE_INNER_L4_TCP,
210 [0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
212 RTE_PTYPE_INNER_L4_TCP,
213 [0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
215 RTE_PTYPE_INNER_L4_FRAG |
216 RTE_PTYPE_INNER_L4_TCP,
217 [0xd3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
218 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
219 RTE_PTYPE_INNER_L4_FRAG |
220 RTE_PTYPE_INNER_L4_TCP,
221 [0xd4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
222 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
223 RTE_PTYPE_INNER_L4_TCP,
224 [0xd8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
225 RTE_PTYPE_INNER_L3_IPV4_EXT |
226 RTE_PTYPE_INNER_L4_TCP,
227 [0xd9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
228 RTE_PTYPE_INNER_L3_IPV4_EXT |
229 RTE_PTYPE_INNER_L4_TCP,
230 [0xda] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
231 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
232 RTE_PTYPE_INNER_L4_TCP,
233 /* Tunneled - L3 IPV4, UDP */
234 [0xe0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
235 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
236 RTE_PTYPE_INNER_L4_UDP,
237 [0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
238 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
239 RTE_PTYPE_INNER_L4_UDP,
240 [0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
241 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
242 RTE_PTYPE_INNER_L4_FRAG |
243 RTE_PTYPE_INNER_L4_UDP,
244 [0xe3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
245 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
246 RTE_PTYPE_INNER_L4_FRAG |
247 RTE_PTYPE_INNER_L4_UDP,
248 [0xe4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
249 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
250 RTE_PTYPE_INNER_L4_UDP,
251 [0xe8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
252 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
253 [0xe9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
254 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
255 [0xea] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
256 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
257 RTE_PTYPE_INNER_L4_UDP,
261 * Stamp TXBB burst so it won't be reused by the HW.
263 * Routine is used when freeing WQE used by the chip or when failing
264 * building an WQ entry has failed leaving partial information on the queue.
267 * Pointer to the SQ structure.
269 * Pointer to the first TXBB to stamp.
271 * Pointer to the followed end TXBB to stamp.
274 * Stamping burst size in byte units.
277 mlx4_txq_stamp_freed_wqe(struct mlx4_sq *sq, volatile uint32_t *start,
278 volatile uint32_t *end)
280 uint32_t stamp = sq->stamp;
281 int32_t size = (intptr_t)end - (intptr_t)start;
283 assert(start != end);
284 /* Hold SQ ring wrap around. */
286 size = (int32_t)sq->size + size;
289 start += MLX4_SQ_STAMP_DWORDS;
290 } while (start != (volatile uint32_t *)sq->eob);
291 start = (volatile uint32_t *)sq->buf;
292 /* Flip invalid stamping ownership. */
293 stamp ^= RTE_BE32(0x1 << MLX4_SQ_OWNER_BIT);
300 start += MLX4_SQ_STAMP_DWORDS;
301 } while (start != end);
302 return (uint32_t)size;
306 * Manage Tx completions.
308 * When sending a burst, mlx4_tx_burst() posts several WRs.
309 * To improve performance, a completion event is only required once every
310 * MLX4_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information
311 * for other WRs, but this information would not be used anyway.
314 * Pointer to Tx queue structure.
316 * Tx elements number mask.
318 * Pointer to the SQ structure.
321 mlx4_txq_complete(struct txq *txq, const unsigned int elts_m,
324 unsigned int elts_tail = txq->elts_tail;
325 struct mlx4_cq *cq = &txq->mcq;
326 volatile struct mlx4_cqe *cqe;
328 uint32_t cons_index = cq->cons_index;
329 volatile uint32_t *first_txbb;
332 * Traverse over all CQ entries reported and handle each WQ entry
336 cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cons_index);
337 if (unlikely(!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
338 !!(cons_index & cq->cqe_cnt)))
342 * Make sure we read the CQE after we read the ownership bit.
345 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
346 MLX4_CQE_OPCODE_ERROR)) {
347 volatile struct mlx4_err_cqe *cqe_err =
348 (volatile struct mlx4_err_cqe *)cqe;
349 ERROR("%p CQE error - vendor syndrome: 0x%x"
351 (void *)txq, cqe_err->vendor_err,
358 completed = (cons_index - cq->cons_index) * txq->elts_comp_cd_init;
359 if (unlikely(!completed))
361 /* First stamping address is the end of the last one. */
362 first_txbb = (&(*txq->elts)[elts_tail & elts_m])->eocb;
363 elts_tail += completed;
364 /* The new tail element holds the end address. */
365 sq->remain_size += mlx4_txq_stamp_freed_wqe(sq, first_txbb,
366 (&(*txq->elts)[elts_tail & elts_m])->eocb);
367 /* Update CQ consumer index. */
368 cq->cons_index = cons_index;
369 *cq->set_ci_db = rte_cpu_to_be_32(cons_index & MLX4_CQ_DB_CI_MASK);
370 txq->elts_tail = elts_tail;
374 * Get memory pool (MP) from mbuf. If mbuf is indirect, the pool from which
375 * the cloned mbuf is allocated is returned instead.
381 * Memory pool where data is located for given mbuf.
383 static struct rte_mempool *
384 mlx4_txq_mb2mp(struct rte_mbuf *buf)
386 if (unlikely(RTE_MBUF_INDIRECT(buf)))
387 return rte_mbuf_from_indirect(buf)->pool;
392 * Write Tx data segment to the SQ.
395 * Pointer to data segment in SQ.
397 * Memory region lkey.
401 * Big endian bytes count of the data to send.
404 mlx4_fill_tx_data_seg(volatile struct mlx4_wqe_data_seg *dseg,
405 uint32_t lkey, uintptr_t addr, rte_be32_t byte_count)
407 dseg->addr = rte_cpu_to_be_64(addr);
408 dseg->lkey = rte_cpu_to_be_32(lkey);
409 #if RTE_CACHE_LINE_SIZE < 64
411 * Need a barrier here before writing the byte_count
412 * fields to make sure that all the data is visible
413 * before the byte_count field is set.
414 * Otherwise, if the segment begins a new cacheline,
415 * the HCA prefetcher could grab the 64-byte chunk and
416 * get a valid (!= 0xffffffff) byte count but stale
417 * data, and end up sending the wrong data.
420 #endif /* RTE_CACHE_LINE_SIZE */
421 dseg->byte_count = byte_count;
425 * Write data segments of multi-segment packet.
428 * Pointer to the first packet mbuf.
430 * Pointer to Tx queue structure.
432 * Pointer to the WQE control segment.
435 * Pointer to the next WQE control segment on success, NULL otherwise.
437 static volatile struct mlx4_wqe_ctrl_seg *
438 mlx4_tx_burst_segs(struct rte_mbuf *buf, struct txq *txq,
439 volatile struct mlx4_wqe_ctrl_seg *ctrl)
441 struct pv *pv = (struct pv *)txq->bounce_buf;
442 struct mlx4_sq *sq = &txq->msq;
443 struct rte_mbuf *sbuf = buf;
446 int nb_segs = buf->nb_segs;
448 volatile struct mlx4_wqe_data_seg *dseg =
449 (volatile struct mlx4_wqe_data_seg *)(ctrl + 1);
451 ctrl->fence_size = 1 + nb_segs;
452 wqe_size = RTE_ALIGN((uint32_t)(ctrl->fence_size << MLX4_SEG_SHIFT),
454 /* Validate WQE size and WQE space in the send queue. */
455 if (sq->remain_size < wqe_size ||
456 wqe_size > MLX4_MAX_WQE_SIZE)
459 * Fill the data segments with buffer information.
460 * First WQE TXBB head segment is always control segment,
461 * so jump to tail TXBB data segments code for the first
462 * WQE data segments filling.
466 /* Memory region key (big endian) for this memory pool. */
467 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
468 if (unlikely(lkey == (uint32_t)-1)) {
469 DEBUG("%p: unable to get MP <-> MR association",
473 /* Handle WQE wraparound. */
475 (volatile struct mlx4_wqe_data_seg *)sq->eob)
476 dseg = (volatile struct mlx4_wqe_data_seg *)
478 dseg->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(sbuf, uintptr_t));
479 dseg->lkey = rte_cpu_to_be_32(lkey);
481 * This data segment starts at the beginning of a new
482 * TXBB, so we need to postpone its byte_count writing
485 pv[pv_counter].dseg = dseg;
487 * Zero length segment is treated as inline segment
490 pv[pv_counter++].val = rte_cpu_to_be_32(sbuf->data_len ?
491 sbuf->data_len : 0x80000000);
496 /* Jump to default if there are more than two segments remaining. */
499 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
500 if (unlikely(lkey == (uint32_t)-1)) {
501 DEBUG("%p: unable to get MP <-> MR association",
505 mlx4_fill_tx_data_seg(dseg, lkey,
506 rte_pktmbuf_mtod(sbuf, uintptr_t),
507 rte_cpu_to_be_32(sbuf->data_len ?
515 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
516 if (unlikely(lkey == (uint32_t)-1)) {
517 DEBUG("%p: unable to get MP <-> MR association",
521 mlx4_fill_tx_data_seg(dseg, lkey,
522 rte_pktmbuf_mtod(sbuf, uintptr_t),
523 rte_cpu_to_be_32(sbuf->data_len ?
531 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
532 if (unlikely(lkey == (uint32_t)-1)) {
533 DEBUG("%p: unable to get MP <-> MR association",
537 mlx4_fill_tx_data_seg(dseg, lkey,
538 rte_pktmbuf_mtod(sbuf, uintptr_t),
539 rte_cpu_to_be_32(sbuf->data_len ?
552 /* Write the first DWORD of each TXBB save earlier. */
554 /* Need a barrier here before writing the byte_count. */
556 for (--pv_counter; pv_counter >= 0; pv_counter--)
557 pv[pv_counter].dseg->byte_count = pv[pv_counter].val;
559 sq->remain_size -= wqe_size;
560 /* Align next WQE address to the next TXBB. */
561 return (volatile struct mlx4_wqe_ctrl_seg *)
562 ((volatile uint8_t *)ctrl + wqe_size);
566 * DPDK callback for Tx.
569 * Generic pointer to Tx queue structure.
571 * Packets to transmit.
573 * Number of packets in array.
576 * Number of packets successfully transmitted (<= pkts_n).
579 mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
581 struct txq *txq = (struct txq *)dpdk_txq;
582 unsigned int elts_head = txq->elts_head;
583 const unsigned int elts_n = txq->elts_n;
584 const unsigned int elts_m = elts_n - 1;
585 unsigned int bytes_sent = 0;
587 unsigned int max = elts_head - txq->elts_tail;
588 struct mlx4_sq *sq = &txq->msq;
589 volatile struct mlx4_wqe_ctrl_seg *ctrl;
592 assert(txq->elts_comp_cd != 0);
593 if (likely(max >= txq->elts_comp_cd_init))
594 mlx4_txq_complete(txq, elts_m, sq);
597 assert(max <= elts_n);
598 /* Always leave one free entry in the ring. */
602 elt = &(*txq->elts)[elts_head & elts_m];
603 /* First Tx burst element saves the next WQE control segment. */
605 for (i = 0; (i != max); ++i) {
606 struct rte_mbuf *buf = pkts[i];
607 struct txq_elt *elt_next = &(*txq->elts)[++elts_head & elts_m];
608 uint32_t owner_opcode = sq->owner_opcode;
609 volatile struct mlx4_wqe_data_seg *dseg =
610 (volatile struct mlx4_wqe_data_seg *)(ctrl + 1);
611 volatile struct mlx4_wqe_ctrl_seg *ctrl_next;
618 /* Clean up old buffer. */
619 if (likely(elt->buf != NULL)) {
620 struct rte_mbuf *tmp = elt->buf;
624 memset(&elt->buf, 0x66, sizeof(struct rte_mbuf *));
626 /* Faster than rte_pktmbuf_free(). */
628 struct rte_mbuf *next = tmp->next;
630 rte_pktmbuf_free_seg(tmp);
632 } while (tmp != NULL);
634 RTE_MBUF_PREFETCH_TO_FREE(elt_next->buf);
635 if (buf->nb_segs == 1) {
636 /* Validate WQE space in the send queue. */
637 if (sq->remain_size < MLX4_TXBB_SIZE) {
641 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(buf));
642 if (unlikely(lkey == (uint32_t)-1)) {
643 /* MR does not exist. */
644 DEBUG("%p: unable to get MP <-> MR association",
649 mlx4_fill_tx_data_seg(dseg++, lkey,
650 rte_pktmbuf_mtod(buf, uintptr_t),
651 rte_cpu_to_be_32(buf->data_len));
652 /* Set WQE size in 16-byte units. */
653 ctrl->fence_size = 0x2;
654 sq->remain_size -= MLX4_TXBB_SIZE;
655 /* Align next WQE address to the next TXBB. */
656 ctrl_next = ctrl + 0x4;
658 ctrl_next = mlx4_tx_burst_segs(buf, txq, ctrl);
664 /* Hold SQ ring wrap around. */
665 if ((volatile uint8_t *)ctrl_next >= sq->eob) {
666 ctrl_next = (volatile struct mlx4_wqe_ctrl_seg *)
667 ((volatile uint8_t *)ctrl_next - sq->size);
668 /* Flip HW valid ownership. */
669 sq->owner_opcode ^= 0x1 << MLX4_SQ_OWNER_BIT;
672 * For raw Ethernet, the SOLICIT flag is used to indicate
673 * that no ICRC should be calculated.
675 if (--txq->elts_comp_cd == 0) {
676 /* Save the completion burst end address. */
677 elt_next->eocb = (volatile uint32_t *)ctrl_next;
678 txq->elts_comp_cd = txq->elts_comp_cd_init;
679 srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT |
680 MLX4_WQE_CTRL_CQ_UPDATE);
682 srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT);
684 /* Enable HW checksum offload if requested */
687 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))) {
688 const uint64_t is_tunneled = (buf->ol_flags &
690 PKT_TX_TUNNEL_VXLAN));
692 if (is_tunneled && txq->csum_l2tun) {
693 owner_opcode |= MLX4_WQE_CTRL_IIP_HDR_CSUM |
694 MLX4_WQE_CTRL_IL4_HDR_CSUM;
695 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
697 RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM);
700 RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM |
701 MLX4_WQE_CTRL_TCP_UDP_CSUM);
706 * Copy destination MAC address to the WQE, this allows
707 * loopback in eSwitch, so that VFs and PF can
708 * communicate with each other.
710 srcrb.flags16[0] = *(rte_pktmbuf_mtod(buf, uint16_t *));
711 ctrl->imm = *(rte_pktmbuf_mtod_offset(buf, uint32_t *,
716 ctrl->srcrb_flags = srcrb.flags;
718 * Make sure descriptor is fully written before
719 * setting ownership bit (because HW can start
720 * executing as soon as we do).
723 ctrl->owner_opcode = rte_cpu_to_be_32(owner_opcode);
725 bytes_sent += buf->pkt_len;
729 /* Take a shortcut if nothing must be sent. */
730 if (unlikely(i == 0))
732 /* Save WQE address of the next Tx burst element. */
734 /* Increment send statistics counters. */
735 txq->stats.opackets += i;
736 txq->stats.obytes += bytes_sent;
737 /* Make sure that descriptors are written before doorbell record. */
739 /* Ring QP doorbell. */
740 rte_write32(txq->msq.doorbell_qpn, txq->msq.db);
746 * Translate Rx completion flags to packet type.
752 * Packet type for struct rte_mbuf.
754 static inline uint32_t
755 rxq_cq_to_pkt_type(volatile struct mlx4_cqe *cqe,
756 uint32_t l2tun_offload)
759 uint32_t pinfo = rte_be_to_cpu_32(cqe->vlan_my_qpn);
760 uint32_t status = rte_be_to_cpu_32(cqe->status);
763 * The index to the array should have:
764 * bit[7] - MLX4_CQE_L2_TUNNEL
765 * bit[6] - MLX4_CQE_L2_TUNNEL_IPV4
767 if (l2tun_offload && (pinfo & MLX4_CQE_L2_TUNNEL))
768 idx |= ((pinfo & MLX4_CQE_L2_TUNNEL) >> 20) |
769 ((pinfo & MLX4_CQE_L2_TUNNEL_IPV4) >> 19);
771 * The index to the array should have:
772 * bit[5] - MLX4_CQE_STATUS_UDP
773 * bit[4] - MLX4_CQE_STATUS_TCP
774 * bit[3] - MLX4_CQE_STATUS_IPV4OPT
775 * bit[2] - MLX4_CQE_STATUS_IPV6
776 * bit[1] - MLX4_CQE_STATUS_IPV4F
777 * bit[0] - MLX4_CQE_STATUS_IPV4
778 * giving a total of up to 256 entries.
780 idx |= ((status & MLX4_CQE_STATUS_PTYPE_MASK) >> 22);
781 return mlx4_ptype_table[idx];
785 * Translate Rx completion flags to offload flags.
788 * Rx completion flags returned by mlx4_cqe_flags().
790 * Whether Rx checksums are enabled.
792 * Whether Rx L2 tunnel checksums are enabled.
795 * Offload flags (ol_flags) in mbuf format.
797 static inline uint32_t
798 rxq_cq_to_ol_flags(uint32_t flags, int csum, int csum_l2tun)
800 uint32_t ol_flags = 0;
804 mlx4_transpose(flags,
805 MLX4_CQE_STATUS_IP_HDR_CSUM_OK,
806 PKT_RX_IP_CKSUM_GOOD) |
807 mlx4_transpose(flags,
808 MLX4_CQE_STATUS_TCP_UDP_CSUM_OK,
809 PKT_RX_L4_CKSUM_GOOD);
810 if ((flags & MLX4_CQE_L2_TUNNEL) && csum_l2tun)
812 mlx4_transpose(flags,
813 MLX4_CQE_L2_TUNNEL_IPOK,
814 PKT_RX_IP_CKSUM_GOOD) |
815 mlx4_transpose(flags,
816 MLX4_CQE_L2_TUNNEL_L4_CSUM,
817 PKT_RX_L4_CKSUM_GOOD);
822 * Extract checksum information from CQE flags.
825 * Pointer to CQE structure.
827 * Whether Rx checksums are enabled.
829 * Whether Rx L2 tunnel checksums are enabled.
832 * CQE checksum information.
834 static inline uint32_t
835 mlx4_cqe_flags(volatile struct mlx4_cqe *cqe, int csum, int csum_l2tun)
840 * The relevant bits are in different locations on their
841 * CQE fields therefore we can join them in one 32bit
845 flags = (rte_be_to_cpu_32(cqe->status) &
846 MLX4_CQE_STATUS_IPV4_CSUM_OK);
848 flags |= (rte_be_to_cpu_32(cqe->vlan_my_qpn) &
849 (MLX4_CQE_L2_TUNNEL |
850 MLX4_CQE_L2_TUNNEL_IPOK |
851 MLX4_CQE_L2_TUNNEL_L4_CSUM |
852 MLX4_CQE_L2_TUNNEL_IPV4));
857 * Poll one CQE from CQ.
860 * Pointer to the receive queue structure.
865 * Number of bytes of the CQE, 0 in case there is no completion.
868 mlx4_cq_poll_one(struct rxq *rxq, volatile struct mlx4_cqe **out)
871 volatile struct mlx4_cqe *cqe = NULL;
872 struct mlx4_cq *cq = &rxq->mcq;
874 cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cq->cons_index);
875 if (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
876 !!(cq->cons_index & cq->cqe_cnt))
879 * Make sure we read CQ entry contents after we've checked the
883 assert(!(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK));
884 assert((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) !=
885 MLX4_CQE_OPCODE_ERROR);
886 ret = rte_be_to_cpu_32(cqe->byte_cnt);
894 * DPDK callback for Rx with scattered packets support.
897 * Generic pointer to Rx queue structure.
899 * Array to store received packets.
901 * Maximum number of packets in array.
904 * Number of packets successfully received (<= pkts_n).
907 mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
909 struct rxq *rxq = dpdk_rxq;
910 const uint32_t wr_cnt = (1 << rxq->elts_n) - 1;
911 const uint16_t sges_n = rxq->sges_n;
912 struct rte_mbuf *pkt = NULL;
913 struct rte_mbuf *seg = NULL;
915 uint32_t rq_ci = rxq->rq_ci << sges_n;
919 volatile struct mlx4_cqe *cqe;
920 uint32_t idx = rq_ci & wr_cnt;
921 struct rte_mbuf *rep = (*rxq->elts)[idx];
922 volatile struct mlx4_wqe_data_seg *scat = &(*rxq->wqes)[idx];
924 /* Update the 'next' pointer of the previous segment. */
930 rep = rte_mbuf_raw_alloc(rxq->mp);
931 if (unlikely(rep == NULL)) {
932 ++rxq->stats.rx_nombuf;
935 * No buffers before we even started,
941 assert(pkt != (*rxq->elts)[idx]);
945 rte_mbuf_raw_free(pkt);
951 /* Looking for the new packet. */
952 len = mlx4_cq_poll_one(rxq, &cqe);
954 rte_mbuf_raw_free(rep);
957 if (unlikely(len < 0)) {
958 /* Rx error, packet is likely too large. */
959 rte_mbuf_raw_free(rep);
960 ++rxq->stats.idropped;
964 /* Update packet information. */
966 rxq_cq_to_pkt_type(cqe, rxq->l2tun_offload);
967 pkt->ol_flags = PKT_RX_RSS_HASH;
968 pkt->hash.rss = cqe->immed_rss_invalid;
970 if (rxq->csum | rxq->csum_l2tun) {
977 rxq_cq_to_ol_flags(flags,
983 rep->port = rxq->port_id;
984 rep->data_len = seg->data_len;
985 rep->data_off = seg->data_off;
986 (*rxq->elts)[idx] = rep;
988 * Fill NIC descriptor with the new buffer. The lkey and size
989 * of the buffers are already known, only the buffer address
992 scat->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
993 if (len > seg->data_len) {
994 len -= seg->data_len;
999 /* The last segment. */
1000 seg->data_len = len;
1001 /* Increment bytes counter. */
1002 rxq->stats.ibytes += pkt->pkt_len;
1003 /* Return packet. */
1009 /* Align consumer index to the next stride. */
1014 if (unlikely(i == 0 && (rq_ci >> sges_n) == rxq->rq_ci))
1016 /* Update the consumer index. */
1017 rxq->rq_ci = rq_ci >> sges_n;
1019 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1020 *rxq->mcq.set_ci_db =
1021 rte_cpu_to_be_32(rxq->mcq.cons_index & MLX4_CQ_DB_CI_MASK);
1022 /* Increment packets counter. */
1023 rxq->stats.ipackets += i;
1028 * Dummy DPDK callback for Tx.
1030 * This function is used to temporarily replace the real callback during
1031 * unsafe control operations on the queue, or in case of error.
1034 * Generic pointer to Tx queue structure.
1036 * Packets to transmit.
1038 * Number of packets in array.
1041 * Number of packets successfully transmitted (<= pkts_n).
1044 mlx4_tx_burst_removed(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1053 * Dummy DPDK callback for Rx.
1055 * This function is used to temporarily replace the real callback during
1056 * unsafe control operations on the queue, or in case of error.
1059 * Generic pointer to Rx queue structure.
1061 * Array to store received packets.
1063 * Maximum number of packets in array.
1066 * Number of packets successfully received (<= pkts_n).
1069 mlx4_rx_burst_removed(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)