4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
46 #pragma GCC diagnostic ignored "-Wpedantic"
48 #include <infiniband/verbs.h>
50 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_malloc.h>
54 #include <rte_ethdev_driver.h>
55 #include <rte_ethdev_pci.h>
57 #include <rte_bus_pci.h>
58 #include <rte_common.h>
59 #include <rte_kvargs.h>
62 #include "mlx5_utils.h"
63 #include "mlx5_rxtx.h"
64 #include "mlx5_autoconf.h"
65 #include "mlx5_defs.h"
67 /* Device parameter to enable RX completion queue compression. */
68 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
70 /* Device parameter to configure inline send. */
71 #define MLX5_TXQ_INLINE "txq_inline"
74 * Device parameter to configure the number of TX queues threshold for
75 * enabling inline send.
77 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
79 /* Device parameter to enable multi-packet send WQEs. */
80 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
82 /* Device parameter to include 2 dsegs in the title WQEBB. */
83 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
85 /* Device parameter to limit the size of inlining packet. */
86 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
88 /* Device parameter to enable hardware Tx vector. */
89 #define MLX5_TX_VEC_EN "tx_vec_en"
91 /* Device parameter to enable hardware Rx vector. */
92 #define MLX5_RX_VEC_EN "rx_vec_en"
94 #ifndef HAVE_IBV_MLX5_MOD_MPW
95 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
96 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
99 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
100 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
104 * Retrieve integer value from environment variable.
107 * Environment variable name.
110 * Integer value, 0 if the variable is not set.
113 mlx5_getenv_int(const char *name)
115 const char *val = getenv(name);
123 * Verbs callback to allocate a memory. This function should allocate the space
124 * according to the size provided residing inside a huge page.
125 * Please note that all allocation must respect the alignment from libmlx5
126 * (i.e. currently sysconf(_SC_PAGESIZE)).
129 * The size in bytes of the memory to allocate.
131 * A pointer to the callback data.
134 * a pointer to the allocate space.
137 mlx5_alloc_verbs_buf(size_t size, void *data)
139 struct priv *priv = data;
141 size_t alignment = sysconf(_SC_PAGESIZE);
143 assert(data != NULL);
144 ret = rte_malloc_socket(__func__, size, alignment,
145 priv->dev->device->numa_node);
146 DEBUG("Extern alloc size: %lu, align: %lu: %p", size, alignment, ret);
151 * Verbs callback to free a memory.
154 * A pointer to the memory to free.
156 * A pointer to the callback data.
159 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
161 assert(data != NULL);
162 DEBUG("Extern free request: %p", ptr);
167 * DPDK callback to close the device.
169 * Destroy all queues and objects, free memory.
172 * Pointer to Ethernet device structure.
175 mlx5_dev_close(struct rte_eth_dev *dev)
177 struct priv *priv = dev->data->dev_private;
182 DEBUG("%p: closing device \"%s\"",
184 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
185 /* In case mlx5_dev_stop() has not been called. */
186 priv_dev_interrupt_handler_uninstall(priv, dev);
187 priv_dev_traffic_disable(priv, dev);
188 /* Prevent crashes when queues are still in use. */
189 dev->rx_pkt_burst = removed_rx_burst;
190 dev->tx_pkt_burst = removed_tx_burst;
191 if (priv->rxqs != NULL) {
192 /* XXX race condition if mlx5_rx_burst() is still running. */
194 for (i = 0; (i != priv->rxqs_n); ++i)
195 mlx5_priv_rxq_release(priv, i);
199 if (priv->txqs != NULL) {
200 /* XXX race condition if mlx5_tx_burst() is still running. */
202 for (i = 0; (i != priv->txqs_n); ++i)
203 mlx5_priv_txq_release(priv, i);
207 if (priv->pd != NULL) {
208 assert(priv->ctx != NULL);
209 claim_zero(ibv_dealloc_pd(priv->pd));
210 claim_zero(ibv_close_device(priv->ctx));
212 assert(priv->ctx == NULL);
213 if (priv->rss_conf.rss_key != NULL)
214 rte_free(priv->rss_conf.rss_key);
215 if (priv->reta_idx != NULL)
216 rte_free(priv->reta_idx);
217 priv_socket_uninit(priv);
218 ret = mlx5_priv_hrxq_ibv_verify(priv);
220 WARN("%p: some Hash Rx queue still remain", (void *)priv);
221 ret = mlx5_priv_ind_table_ibv_verify(priv);
223 WARN("%p: some Indirection table still remain", (void *)priv);
224 ret = mlx5_priv_rxq_ibv_verify(priv);
226 WARN("%p: some Verbs Rx queue still remain", (void *)priv);
227 ret = mlx5_priv_rxq_verify(priv);
229 WARN("%p: some Rx Queues still remain", (void *)priv);
230 ret = mlx5_priv_txq_ibv_verify(priv);
232 WARN("%p: some Verbs Tx queue still remain", (void *)priv);
233 ret = mlx5_priv_txq_verify(priv);
235 WARN("%p: some Tx Queues still remain", (void *)priv);
236 ret = priv_flow_verify(priv);
238 WARN("%p: some flows still remain", (void *)priv);
239 ret = priv_mr_verify(priv);
241 WARN("%p: some Memory Region still remain", (void *)priv);
243 memset(priv, 0, sizeof(*priv));
246 const struct eth_dev_ops mlx5_dev_ops = {
247 .dev_configure = mlx5_dev_configure,
248 .dev_start = mlx5_dev_start,
249 .dev_stop = mlx5_dev_stop,
250 .dev_set_link_down = mlx5_set_link_down,
251 .dev_set_link_up = mlx5_set_link_up,
252 .dev_close = mlx5_dev_close,
253 .promiscuous_enable = mlx5_promiscuous_enable,
254 .promiscuous_disable = mlx5_promiscuous_disable,
255 .allmulticast_enable = mlx5_allmulticast_enable,
256 .allmulticast_disable = mlx5_allmulticast_disable,
257 .link_update = mlx5_link_update,
258 .stats_get = mlx5_stats_get,
259 .stats_reset = mlx5_stats_reset,
260 .xstats_get = mlx5_xstats_get,
261 .xstats_reset = mlx5_xstats_reset,
262 .xstats_get_names = mlx5_xstats_get_names,
263 .dev_infos_get = mlx5_dev_infos_get,
264 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
265 .vlan_filter_set = mlx5_vlan_filter_set,
266 .rx_queue_setup = mlx5_rx_queue_setup,
267 .tx_queue_setup = mlx5_tx_queue_setup,
268 .rx_queue_release = mlx5_rx_queue_release,
269 .tx_queue_release = mlx5_tx_queue_release,
270 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
271 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
272 .mac_addr_remove = mlx5_mac_addr_remove,
273 .mac_addr_add = mlx5_mac_addr_add,
274 .mac_addr_set = mlx5_mac_addr_set,
275 .mtu_set = mlx5_dev_set_mtu,
276 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
277 .vlan_offload_set = mlx5_vlan_offload_set,
278 .reta_update = mlx5_dev_rss_reta_update,
279 .reta_query = mlx5_dev_rss_reta_query,
280 .rss_hash_update = mlx5_rss_hash_update,
281 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
282 .filter_ctrl = mlx5_dev_filter_ctrl,
283 .rx_descriptor_status = mlx5_rx_descriptor_status,
284 .tx_descriptor_status = mlx5_tx_descriptor_status,
285 .rx_queue_intr_enable = mlx5_rx_intr_enable,
286 .rx_queue_intr_disable = mlx5_rx_intr_disable,
287 .is_removed = mlx5_is_removed,
290 static const struct eth_dev_ops mlx5_dev_sec_ops = {
291 .stats_get = mlx5_stats_get,
292 .stats_reset = mlx5_stats_reset,
293 .xstats_get = mlx5_xstats_get,
294 .xstats_reset = mlx5_xstats_reset,
295 .xstats_get_names = mlx5_xstats_get_names,
296 .dev_infos_get = mlx5_dev_infos_get,
297 .rx_descriptor_status = mlx5_rx_descriptor_status,
298 .tx_descriptor_status = mlx5_tx_descriptor_status,
301 /* Available operators in flow isolated mode. */
302 const struct eth_dev_ops mlx5_dev_ops_isolate = {
303 .dev_configure = mlx5_dev_configure,
304 .dev_start = mlx5_dev_start,
305 .dev_stop = mlx5_dev_stop,
306 .dev_set_link_down = mlx5_set_link_down,
307 .dev_set_link_up = mlx5_set_link_up,
308 .dev_close = mlx5_dev_close,
309 .link_update = mlx5_link_update,
310 .stats_get = mlx5_stats_get,
311 .stats_reset = mlx5_stats_reset,
312 .xstats_get = mlx5_xstats_get,
313 .xstats_reset = mlx5_xstats_reset,
314 .xstats_get_names = mlx5_xstats_get_names,
315 .dev_infos_get = mlx5_dev_infos_get,
316 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
317 .vlan_filter_set = mlx5_vlan_filter_set,
318 .rx_queue_setup = mlx5_rx_queue_setup,
319 .tx_queue_setup = mlx5_tx_queue_setup,
320 .rx_queue_release = mlx5_rx_queue_release,
321 .tx_queue_release = mlx5_tx_queue_release,
322 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
323 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
324 .mac_addr_remove = mlx5_mac_addr_remove,
325 .mac_addr_add = mlx5_mac_addr_add,
326 .mac_addr_set = mlx5_mac_addr_set,
327 .mtu_set = mlx5_dev_set_mtu,
328 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
329 .vlan_offload_set = mlx5_vlan_offload_set,
330 .filter_ctrl = mlx5_dev_filter_ctrl,
331 .rx_descriptor_status = mlx5_rx_descriptor_status,
332 .tx_descriptor_status = mlx5_tx_descriptor_status,
333 .rx_queue_intr_enable = mlx5_rx_intr_enable,
334 .rx_queue_intr_disable = mlx5_rx_intr_disable,
335 .is_removed = mlx5_is_removed,
339 struct rte_pci_addr pci_addr; /* associated PCI address */
340 uint32_t ports; /* physical ports bitfield. */
344 * Get device index in mlx5_dev[] from PCI bus address.
346 * @param[in] pci_addr
347 * PCI bus address to look for.
350 * mlx5_dev[] index on success, -1 on failure.
353 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
358 assert(pci_addr != NULL);
359 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
360 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
361 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
362 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
363 (mlx5_dev[i].pci_addr.function == pci_addr->function))
365 if ((mlx5_dev[i].ports == 0) && (ret == -1))
372 * Verify and store value for device argument.
375 * Key argument to verify.
377 * Value associated with key.
382 * 0 on success, negative errno value on failure.
385 mlx5_args_check(const char *key, const char *val, void *opaque)
387 struct mlx5_dev_config *config = opaque;
391 tmp = strtoul(val, NULL, 0);
393 WARN("%s: \"%s\" is not a valid integer", key, val);
396 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
397 config->cqe_comp = !!tmp;
398 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
399 config->txq_inline = tmp;
400 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
401 config->txqs_inline = tmp;
402 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
403 config->mps = !!tmp ? config->mps : 0;
404 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
405 config->mpw_hdr_dseg = !!tmp;
406 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
407 config->inline_max_packet_sz = tmp;
408 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
409 config->tx_vec_en = !!tmp;
410 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
411 config->rx_vec_en = !!tmp;
413 WARN("%s: unknown parameter", key);
420 * Parse device parameters.
423 * Pointer to device configuration structure.
425 * Device arguments structure.
428 * 0 on success, errno value on failure.
431 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
433 const char **params = (const char *[]){
434 MLX5_RXQ_CQE_COMP_EN,
436 MLX5_TXQS_MIN_INLINE,
438 MLX5_TXQ_MPW_HDR_DSEG_EN,
439 MLX5_TXQ_MAX_INLINE_LEN,
444 struct rte_kvargs *kvlist;
450 /* Following UGLY cast is done to pass checkpatch. */
451 kvlist = rte_kvargs_parse(devargs->args, params);
454 /* Process parameters. */
455 for (i = 0; (params[i] != NULL); ++i) {
456 if (rte_kvargs_count(kvlist, params[i])) {
457 ret = rte_kvargs_process(kvlist, params[i],
458 mlx5_args_check, config);
460 rte_kvargs_free(kvlist);
465 rte_kvargs_free(kvlist);
469 static struct rte_pci_driver mlx5_driver;
472 * DPDK callback to register a PCI device.
474 * This function creates an Ethernet device for each port of a given
478 * PCI driver structure (mlx5_driver).
480 * PCI device information.
483 * 0 on success, negative errno value on failure.
486 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
488 struct ibv_device **list;
489 struct ibv_device *ibv_dev;
491 struct ibv_context *attr_ctx = NULL;
492 struct ibv_device_attr_ex device_attr;
495 unsigned int cqe_comp;
496 unsigned int tunnel_en = 0;
499 struct mlx5dv_context attrs_out;
500 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
501 struct ibv_counter_set_description cs_desc;
505 assert(pci_drv == &mlx5_driver);
506 /* Get mlx5_dev[] index. */
507 idx = mlx5_dev_idx(&pci_dev->addr);
509 ERROR("this driver cannot support any more adapters");
512 DEBUG("using driver device index %d", idx);
514 /* Save PCI address. */
515 mlx5_dev[idx].pci_addr = pci_dev->addr;
516 list = ibv_get_device_list(&i);
520 ERROR("cannot list devices, is ib_uverbs loaded?");
525 * For each listed device, check related sysfs entry against
526 * the provided PCI ID.
529 struct rte_pci_addr pci_addr;
532 DEBUG("checking device \"%s\"", list[i]->name);
533 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
535 if ((pci_dev->addr.domain != pci_addr.domain) ||
536 (pci_dev->addr.bus != pci_addr.bus) ||
537 (pci_dev->addr.devid != pci_addr.devid) ||
538 (pci_dev->addr.function != pci_addr.function))
540 sriov = ((pci_dev->id.device_id ==
541 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
542 (pci_dev->id.device_id ==
543 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
544 (pci_dev->id.device_id ==
545 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
546 (pci_dev->id.device_id ==
547 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
548 switch (pci_dev->id.device_id) {
549 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
552 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
553 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
554 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
555 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
556 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
562 INFO("PCI information matches, using device \"%s\""
565 sriov ? "true" : "false");
566 attr_ctx = ibv_open_device(list[i]);
570 if (attr_ctx == NULL) {
571 ibv_free_device_list(list);
574 ERROR("cannot access device, is mlx5_ib loaded?");
577 ERROR("cannot use device, are drivers up to date?");
585 DEBUG("device opened");
587 * Multi-packet send is supported by ConnectX-4 Lx PF as well
588 * as all ConnectX-5 devices.
590 mlx5dv_query_device(attr_ctx, &attrs_out);
591 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
592 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
593 DEBUG("Enhanced MPW is supported");
594 mps = MLX5_MPW_ENHANCED;
596 DEBUG("MPW is supported");
600 DEBUG("MPW isn't supported");
601 mps = MLX5_MPW_DISABLED;
603 if (RTE_CACHE_LINE_SIZE == 128 &&
604 !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
608 if (ibv_query_device_ex(attr_ctx, NULL, &device_attr))
610 INFO("%u port(s) detected", device_attr.orig_attr.phys_port_cnt);
612 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
613 uint32_t port = i + 1; /* ports are indexed from one */
614 uint32_t test = (1 << i);
615 struct ibv_context *ctx = NULL;
616 struct ibv_port_attr port_attr;
617 struct ibv_pd *pd = NULL;
618 struct priv *priv = NULL;
619 struct rte_eth_dev *eth_dev;
620 struct ibv_device_attr_ex device_attr_ex;
621 struct ether_addr mac;
622 uint16_t num_vfs = 0;
623 struct ibv_device_attr_ex device_attr;
624 struct mlx5_dev_config config = {
625 .cqe_comp = cqe_comp,
627 .tunnel_en = tunnel_en,
631 .txq_inline = MLX5_ARG_UNSET,
632 .txqs_inline = MLX5_ARG_UNSET,
633 .inline_max_packet_sz = MLX5_ARG_UNSET,
636 mlx5_dev[idx].ports |= test;
638 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
639 /* from rte_ethdev.c */
640 char name[RTE_ETH_NAME_MAX_LEN];
642 snprintf(name, sizeof(name), "%s port %u",
643 ibv_get_device_name(ibv_dev), port);
644 eth_dev = rte_eth_dev_attach_secondary(name);
645 if (eth_dev == NULL) {
646 ERROR("can not attach rte ethdev");
650 eth_dev->device = &pci_dev->device;
651 eth_dev->dev_ops = &mlx5_dev_sec_ops;
652 priv = eth_dev->data->dev_private;
653 /* Receive command fd from primary process */
654 err = priv_socket_connect(priv);
659 /* Remap UAR for Tx queues. */
660 err = priv_tx_uar_remap(priv, err);
666 * Ethdev pointer is still required as input since
667 * the primary device is not accessible from the
670 eth_dev->rx_pkt_burst =
671 priv_select_rx_function(priv, eth_dev);
672 eth_dev->tx_pkt_burst =
673 priv_select_tx_function(priv, eth_dev);
677 DEBUG("using port %u (%08" PRIx32 ")", port, test);
679 ctx = ibv_open_device(ibv_dev);
685 ibv_query_device_ex(ctx, NULL, &device_attr);
686 /* Check port status. */
687 err = ibv_query_port(ctx, port, &port_attr);
689 ERROR("port query failed: %s", strerror(err));
693 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
694 ERROR("port %d is not configured in Ethernet mode",
700 if (port_attr.state != IBV_PORT_ACTIVE)
701 DEBUG("port %d is not active: \"%s\" (%d)",
702 port, ibv_port_state_str(port_attr.state),
705 /* Allocate protection domain. */
706 pd = ibv_alloc_pd(ctx);
708 ERROR("PD allocation failure");
713 mlx5_dev[idx].ports |= test;
715 /* from rte_ethdev.c */
716 priv = rte_zmalloc("ethdev private structure",
718 RTE_CACHE_LINE_SIZE);
720 ERROR("priv allocation failure");
726 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
727 sizeof(priv->ibdev_path));
728 priv->device_attr = device_attr;
731 priv->mtu = ETHER_MTU;
732 err = mlx5_args(&config, pci_dev->device.devargs);
734 ERROR("failed to process device arguments: %s",
738 if (ibv_query_device_ex(ctx, NULL, &device_attr_ex)) {
739 ERROR("ibv_query_device_ex() failed");
743 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex &
744 IBV_DEVICE_RAW_IP_CSUM);
745 DEBUG("checksum offloading is %ssupported",
746 (config.hw_csum ? "" : "not "));
748 #ifdef HAVE_IBV_DEVICE_VXLAN_SUPPORT
749 config.hw_csum_l2tun =
750 !!(exp_device_attr.exp_device_cap_flags &
751 IBV_DEVICE_VXLAN_SUPPORT);
753 DEBUG("Rx L2 tunnel checksum offloads are %ssupported",
754 (config.hw_csum_l2tun ? "" : "not "));
756 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
757 config.flow_counter_en = !!(device_attr.max_counter_sets);
758 ibv_describe_counter_set(ctx, 0, &cs_desc);
759 DEBUG("counter type = %d, num of cs = %ld, attributes = %d",
760 cs_desc.counter_type, cs_desc.num_of_cs,
763 config.ind_table_max_size =
764 device_attr_ex.rss_caps.max_rwq_indirection_table_size;
765 /* Remove this check once DPDK supports larger/variable
766 * indirection tables. */
767 if (config.ind_table_max_size >
768 (unsigned int)ETH_RSS_RETA_SIZE_512)
769 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
770 DEBUG("maximum RX indirection table size is %u",
771 config.ind_table_max_size);
772 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
773 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
774 DEBUG("VLAN stripping is %ssupported",
775 (config.hw_vlan_strip ? "" : "not "));
777 config.hw_fcs_strip =
778 !!(device_attr_ex.orig_attr.device_cap_flags &
779 IBV_WQ_FLAGS_SCATTER_FCS);
780 DEBUG("FCS stripping configuration is %ssupported",
781 (config.hw_fcs_strip ? "" : "not "));
783 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
784 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
786 DEBUG("hardware RX end alignment padding is %ssupported",
787 (config.hw_padding ? "" : "not "));
789 priv_get_num_vfs(priv, &num_vfs);
790 config.sriov = (num_vfs || sriov);
791 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) &&
792 (device_attr_ex.tso_caps.supported_qpts &
793 (1 << IBV_QPT_RAW_PACKET)));
795 config.tso_max_payload_sz =
796 device_attr_ex.tso_caps.max_tso;
797 if (config.mps && !mps) {
798 ERROR("multi-packet send not supported on this device"
799 " (" MLX5_TXQ_MPW_EN ")");
804 config.mps == MLX5_MPW_ENHANCED ? "Enhanced " : "",
805 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
806 if (config.cqe_comp && !cqe_comp) {
807 WARN("Rx CQE compression isn't supported");
810 /* Configure the first MAC address by default. */
811 if (priv_get_mac(priv, &mac.addr_bytes)) {
812 ERROR("cannot get MAC address, is mlx5_en loaded?"
813 " (errno: %s)", strerror(errno));
817 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
819 mac.addr_bytes[0], mac.addr_bytes[1],
820 mac.addr_bytes[2], mac.addr_bytes[3],
821 mac.addr_bytes[4], mac.addr_bytes[5]);
824 char ifname[IF_NAMESIZE];
826 if (priv_get_ifname(priv, &ifname) == 0)
827 DEBUG("port %u ifname is \"%s\"",
830 DEBUG("port %u ifname is unknown", priv->port);
833 /* Get actual MTU if possible. */
834 priv_get_mtu(priv, &priv->mtu);
835 DEBUG("port %u MTU is %u", priv->port, priv->mtu);
837 /* from rte_ethdev.c */
839 char name[RTE_ETH_NAME_MAX_LEN];
841 snprintf(name, sizeof(name), "%s port %u",
842 ibv_get_device_name(ibv_dev), port);
843 eth_dev = rte_eth_dev_allocate(name);
845 if (eth_dev == NULL) {
846 ERROR("can not allocate rte ethdev");
850 eth_dev->data->dev_private = priv;
851 eth_dev->data->mac_addrs = priv->mac;
852 eth_dev->device = &pci_dev->device;
853 rte_eth_copy_pci_info(eth_dev, pci_dev);
854 eth_dev->device->driver = &mlx5_driver.driver;
856 eth_dev->dev_ops = &mlx5_dev_ops;
857 /* Register MAC address. */
858 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
859 TAILQ_INIT(&priv->flows);
860 TAILQ_INIT(&priv->ctrl_flows);
862 /* Hint libmlx5 to use PMD allocator for data plane resources */
863 struct mlx5dv_ctx_allocators alctr = {
864 .alloc = &mlx5_alloc_verbs_buf,
865 .free = &mlx5_free_verbs_buf,
868 mlx5dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
869 (void *)((uintptr_t)&alctr));
871 /* Bring Ethernet device up. */
872 DEBUG("forcing Ethernet interface up");
873 priv_set_flags(priv, ~IFF_UP, IFF_UP);
874 /* Store device configuration on private structure. */
875 priv->config = config;
882 claim_zero(ibv_dealloc_pd(pd));
884 claim_zero(ibv_close_device(ctx));
889 * XXX if something went wrong in the loop above, there is a resource
890 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
891 * long as the dpdk does not provide a way to deallocate a ethdev and a
892 * way to enumerate the registered ethdevs to free the previous ones.
895 /* no port found, complain */
896 if (!mlx5_dev[idx].ports) {
903 claim_zero(ibv_close_device(attr_ctx));
905 ibv_free_device_list(list);
910 static const struct rte_pci_id mlx5_pci_id_map[] = {
912 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
913 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
916 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
917 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
920 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
921 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
924 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
925 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
928 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
929 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
932 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
933 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
936 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
937 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
940 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
941 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
948 static struct rte_pci_driver mlx5_driver = {
950 .name = MLX5_DRIVER_NAME
952 .id_table = mlx5_pci_id_map,
953 .probe = mlx5_pci_probe,
954 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
958 * Driver initialization routine.
960 RTE_INIT(rte_mlx5_pmd_init);
962 rte_mlx5_pmd_init(void)
964 /* Build the static table for ptype conversion. */
965 mlx5_set_ptype_table();
967 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
968 * huge pages. Calling ibv_fork_init() during init allows
969 * applications to use fork() safely for purposes other than
970 * using this PMD, which is not supported in forked processes.
972 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
973 /* Match the size of Rx completion entry to the size of a cacheline. */
974 if (RTE_CACHE_LINE_SIZE == 128)
975 setenv("MLX5_CQE_SIZE", "128", 0);
977 rte_pci_register(&mlx5_driver);
980 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
981 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
982 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");