mlx5/mlx5_common.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2019 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <unistd.h>
   6 #include <string.h>
   7 #include <stdio.h>
   8
   9 #include <rte_errno.h>
  10
  11 #include "mlx5_common.h"
  12 #include "mlx5_common_utils.h"
  13
  14 int mlx5_common_logtype;
  15
  16 #ifdef MLX5_GLUE
  17 const struct mlx5_glue *mlx5_glue;
  18 #endif
  19
  20 uint8_t haswell_broadwell_cpu;
  21
  22 static int
  23 mlx5_class_check_handler(__rte_unused const char *key, const char *value,
  24                          void *opaque)
  25 {
  26         enum mlx5_class *ret = opaque;
  27
  28         if (strcmp(value, "vdpa") == 0) {
  29                 *ret = MLX5_CLASS_VDPA;
  30         } else if (strcmp(value, "net") == 0) {
  31                 *ret = MLX5_CLASS_NET;
  32         } else {
  33                 DRV_LOG(ERR, "Invalid mlx5 class %s. Maybe typo in device"
  34                         " class argument setting?", value);
  35                 *ret = MLX5_CLASS_INVALID;
  36         }
  37         return 0;
  38 }
  39
  40 enum mlx5_class
  41 mlx5_class_get(struct rte_devargs *devargs)
  42 {
  43         struct rte_kvargs *kvlist;
  44         const char *key = MLX5_CLASS_ARG_NAME;
  45         enum mlx5_class ret = MLX5_CLASS_NET;
  46
  47         if (devargs == NULL)
  48                 return ret;
  49         kvlist = rte_kvargs_parse(devargs->args, NULL);
  50         if (kvlist == NULL)
  51                 return ret;
  52         if (rte_kvargs_count(kvlist, key))
  53                 rte_kvargs_process(kvlist, key, mlx5_class_check_handler, &ret);
  54         rte_kvargs_free(kvlist);
  55         return ret;
  56 }
  57
  58
  59 /* In case this is an x86_64 intel processor to check if
  60  * we should use relaxed ordering.
  61  */
  62 #ifdef RTE_ARCH_X86_64
  63 /**
  64  * This function returns processor identification and feature information
  65  * into the registers.
  66  *
  67  * @param eax, ebx, ecx, edx
  68  *              Pointers to the registers that will hold cpu information.
  69  * @param level
  70  *              The main category of information returned.
  71  */
  72 static inline void mlx5_cpu_id(unsigned int level,
  73                                 unsigned int *eax, unsigned int *ebx,
  74                                 unsigned int *ecx, unsigned int *edx)
  75 {
  76         __asm__("cpuid\n\t"
  77                 : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
  78                 : "0" (level));
  79 }
  80 #endif
  81
  82 RTE_INIT_PRIO(mlx5_log_init, LOG)
  83 {
  84         mlx5_common_logtype = rte_log_register("pmd.common.mlx5");
  85         if (mlx5_common_logtype >= 0)
  86                 rte_log_set_level(mlx5_common_logtype, RTE_LOG_NOTICE);
  87 }
  88
  89 /**
  90  * Initialization routine for run-time dependency on glue library.
  91  */
  92 RTE_INIT_PRIO(mlx5_glue_init, CLASS)
  93 {
  94         mlx5_glue_constructor();
  95 }
  96
  97 /**
  98  * This function is responsible of initializing the variable
  99  *  haswell_broadwell_cpu by checking if the cpu is intel
 100  *  and reading the data returned from mlx5_cpu_id().
 101  *  since haswell and broadwell cpus don't have improved performance
 102  *  when using relaxed ordering we want to check the cpu type before
 103  *  before deciding whether to enable RO or not.
 104  *  if the cpu is haswell or broadwell the variable will be set to 1
 105  *  otherwise it will be 0.
 106  */
 107 RTE_INIT_PRIO(mlx5_is_haswell_broadwell_cpu, LOG)
 108 {
 109 #ifdef RTE_ARCH_X86_64
 110         unsigned int broadwell_models[4] = {0x3d, 0x47, 0x4F, 0x56};
 111         unsigned int haswell_models[4] = {0x3c, 0x3f, 0x45, 0x46};
 112         unsigned int i, model, family, brand_id, vendor;
 113         unsigned int signature_intel_ebx = 0x756e6547;
 114         unsigned int extended_model;
 115         unsigned int eax = 0;
 116         unsigned int ebx = 0;
 117         unsigned int ecx = 0;
 118         unsigned int edx = 0;
 119         int max_level;
 120
 121         mlx5_cpu_id(0, &eax, &ebx, &ecx, &edx);
 122         vendor = ebx;
 123         max_level = eax;
 124         if (max_level < 1) {
 125                 haswell_broadwell_cpu = 0;
 126                 return;
 127         }
 128         mlx5_cpu_id(1, &eax, &ebx, &ecx, &edx);
 129         model = (eax >> 4) & 0x0f;
 130         family = (eax >> 8) & 0x0f;
 131         brand_id = ebx & 0xff;
 132         extended_model = (eax >> 12) & 0xf0;
 133         /* Check if the processor is Haswell or Broadwell */
 134         if (vendor == signature_intel_ebx) {
 135                 if (family == 0x06)
 136                         model += extended_model;
 137                 if (brand_id == 0 && family == 0x6) {
 138                         for (i = 0; i < RTE_DIM(broadwell_models); i++)
 139                                 if (model == broadwell_models[i]) {
 140                                         haswell_broadwell_cpu = 1;
 141                                         return;
 142                                 }
 143                         for (i = 0; i < RTE_DIM(haswell_models); i++)
 144                                 if (model == haswell_models[i]) {
 145                                         haswell_broadwell_cpu = 1;
 146                                         return;
 147                                 }
 148                 }
 149         }
 150 #endif
 151         haswell_broadwell_cpu = 0;
 152 }