1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_DEFS_H_
7 #define RTE_PMD_MLX5_DEFS_H_
9 #include <rte_ethdev_driver.h>
11 #include "mlx5_autoconf.h"
13 /* Reported driver name. */
14 #define MLX5_DRIVER_NAME "net_mlx5"
16 /* Maximum number of simultaneous unicast MAC addresses. */
17 #define MLX5_MAX_UC_MAC_ADDRESSES 128
18 /* Maximum number of simultaneous Multicast MAC addresses. */
19 #define MLX5_MAX_MC_MAC_ADDRESSES 128
20 /* Maximum number of simultaneous MAC addresses. */
21 #define MLX5_MAX_MAC_ADDRESSES \
22 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES)
24 /* Maximum number of simultaneous VLAN filters. */
25 #define MLX5_MAX_VLAN_IDS 128
28 * Request TX completion every time descriptors reach this threshold since
29 * the previous request. Must be a power of two for performance reasons.
31 #define MLX5_TX_COMP_THRESH 32u
34 * Request TX completion every time the total number of WQEBBs used for inlining
35 * packets exceeds the size of WQ divided by this divisor. Better to be power of
36 * two for performance.
38 #define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3)
41 * Maximal amount of normal completion CQEs
42 * processed in one call of tx_burst() routine.
44 #define MLX5_TX_COMP_MAX_CQE 2u
47 /* Size of per-queue MR cache array for linear search. */
48 #define MLX5_MR_CACHE_N 8
50 /* Size of MR cache table for binary search. */
51 #define MLX5_MR_BTREE_CACHE_N 256
54 * If defined, only use software counters. The PMD will never ask the hardware
55 * for these, and many of them won't be available.
57 #ifndef MLX5_PMD_SOFT_COUNTERS
58 #define MLX5_PMD_SOFT_COUNTERS 1
61 /* Switch port ID parameters for bonding configurations. */
62 #define MLX5_PORT_ID_BONDING_PF_MASK 0xf
63 #define MLX5_PORT_ID_BONDING_PF_SHIFT 0xf
66 #define MLX5_ALARM_TIMEOUT_US 100000
68 /* Maximum number of extended statistics counters. */
69 #define MLX5_MAX_XSTATS 32
71 /* Maximum Packet headers size (L2+L3+L4) for TSO. */
72 #define MLX5_MAX_TSO_HEADER (128u + 34u)
74 /* Inline data size required by NICs. */
75 #define MLX5_INLINE_HSIZE_NONE 0
76 #define MLX5_INLINE_HSIZE_L2 (sizeof(struct rte_ether_hdr) + \
77 sizeof(struct rte_vlan_hdr))
78 #define MLX5_INLINE_HSIZE_L3 (MLX5_INLINE_HSIZE_L2 + \
79 sizeof(struct rte_ipv6_hdr))
80 #define MLX5_INLINE_HSIZE_L4 (MLX5_INLINE_HSIZE_L3 + \
81 sizeof(struct rte_tcp_hdr))
82 #define MLX5_INLINE_HSIZE_INNER_L2 (MLX5_INLINE_HSIZE_L3 + \
83 sizeof(struct rte_udp_hdr) + \
84 sizeof(struct rte_vxlan_hdr) + \
85 sizeof(struct rte_ether_hdr) + \
86 sizeof(struct rte_vlan_hdr))
87 #define MLX5_INLINE_HSIZE_INNER_L3 (MLX5_INLINE_HSIZE_INNER_L2 + \
88 sizeof(struct rte_ipv6_hdr))
89 #define MLX5_INLINE_HSIZE_INNER_L4 (MLX5_INLINE_HSIZE_INNER_L3 + \
90 sizeof(struct rte_tcp_hdr))
92 /* Threshold of buffer replenishment for vectorized Rx. */
93 #define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \
94 (RTE_MIN(MLX5_VPMD_RX_MAX_BURST, (unsigned int)(n) >> 2))
96 /* Maximum size of burst for vectorized Rx. */
97 #define MLX5_VPMD_RX_MAX_BURST 64U
99 /* Number of packets vectorized Rx can simultaneously process in a loop. */
100 #define MLX5_VPMD_DESCS_PER_LOOP 4
103 #define MLX5_RSS_HF_MASK (~(ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP))
105 /* Timeout in seconds to get a valid link status. */
106 #define MLX5_LINK_STATUS_TIMEOUT 10
108 /* Number of times to retry retrieving the physical link information. */
109 #define MLX5_GET_LINK_STATUS_RETRY_COUNT 3
111 /* Maximum number of UAR pages used by a port,
112 * These are the size and mask for an array of mutexes used to synchronize
113 * the access to port's UARs on platforms that do not support 64 bit writes.
114 * In such systems it is possible to issue the 64 bits DoorBells through two
115 * consecutive writes, each write 32 bits. The access to a UAR page (which can
116 * be accessible by all threads in the process) must be synchronized
117 * (for example, using a semaphore). Such a synchronization is not required
118 * when ringing DoorBells on different UAR pages.
119 * A port with 512 Tx queues uses 8, 4kBytes, UAR pages which are shared
122 #define MLX5_UAR_PAGE_NUM_MAX 64
123 #define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1)
125 /* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */
126 #define MLX5_MPRQ_STRIDE_NUM_N 6U
128 /* Two-byte shift is disabled for Multi-Packet RQ. */
129 #define MLX5_MPRQ_TWO_BYTE_SHIFT 0
132 * Minimum size of packet to be memcpy'd instead of being attached as an
135 #define MLX5_MPRQ_MEMCPY_DEFAULT_LEN 128
137 /* Minimum number Rx queues to enable Multi-Packet RQ. */
138 #define MLX5_MPRQ_MIN_RXQS 12
140 /* Cache size of mempool for Multi-Packet RQ. */
141 #define MLX5_MPRQ_MP_CACHE_SZ 32U
143 /* Definition of static_assert found in /usr/include/assert.h */
144 #ifndef HAVE_STATIC_ASSERT
145 #define static_assert _Static_assert
148 #endif /* RTE_PMD_MLX5_DEFS_H_ */