1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
30 /* Pattern outer Layer bits. */
31 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
32 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
33 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
34 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
35 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
36 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
38 /* Pattern inner Layer bits. */
39 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
40 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
41 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
42 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
43 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
44 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
46 /* Pattern tunnel Layer bits. */
47 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
48 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
49 #define MLX5_FLOW_LAYER_GRE (1u << 14)
50 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
51 /* List of tunnel Layer bits continued below. */
53 /* General pattern items bits. */
54 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
55 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
57 /* Pattern MISC bits. */
58 #define MLX5_FLOW_LAYER_ICMP (1u << 18)
59 #define MLX5_FLOW_LAYER_ICMP6 (1u << 19)
60 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 20)
62 /* Pattern tunnel Layer bits (continued). */
63 #define MLX5_FLOW_LAYER_IPIP (1u << 21)
64 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
65 #define MLX5_FLOW_LAYER_NVGRE (1u << 23)
66 #define MLX5_FLOW_LAYER_GENEVE (1u << 24)
69 #define MLX5_FLOW_LAYER_OUTER_L3 \
70 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
71 #define MLX5_FLOW_LAYER_OUTER_L4 \
72 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
73 #define MLX5_FLOW_LAYER_OUTER \
74 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
75 MLX5_FLOW_LAYER_OUTER_L4)
77 /* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */
78 #define MLX5_FLOW_LAYER_IPV4_LRO \
79 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
80 #define MLX5_FLOW_LAYER_IPV6_LRO \
81 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
84 #define MLX5_FLOW_LAYER_TUNNEL \
85 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
86 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
87 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
88 MLX5_FLOW_LAYER_GENEVE)
91 #define MLX5_FLOW_LAYER_INNER_L3 \
92 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
93 #define MLX5_FLOW_LAYER_INNER_L4 \
94 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
95 #define MLX5_FLOW_LAYER_INNER \
96 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
97 MLX5_FLOW_LAYER_INNER_L4)
100 #define MLX5_FLOW_LAYER_L2 \
101 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
102 #define MLX5_FLOW_LAYER_L3_IPV4 \
103 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
104 #define MLX5_FLOW_LAYER_L3_IPV6 \
105 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
106 #define MLX5_FLOW_LAYER_L3 \
107 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
108 #define MLX5_FLOW_LAYER_L4 \
109 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
112 #define MLX5_FLOW_ACTION_DROP (1u << 0)
113 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
114 #define MLX5_FLOW_ACTION_RSS (1u << 2)
115 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
116 #define MLX5_FLOW_ACTION_MARK (1u << 4)
117 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
118 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
119 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
120 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
121 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
122 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
123 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
124 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
125 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
126 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
127 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
128 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
129 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
130 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
131 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
132 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
133 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
134 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
135 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
136 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
137 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
138 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
139 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
140 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
141 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
142 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
143 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
145 #define MLX5_FLOW_FATE_ACTIONS \
146 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
147 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
149 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
150 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
151 MLX5_FLOW_ACTION_JUMP)
153 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
154 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
155 MLX5_FLOW_ACTION_RAW_ENCAP | \
156 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
158 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
159 MLX5_FLOW_ACTION_NVGRE_DECAP | \
160 MLX5_FLOW_ACTION_RAW_DECAP | \
161 MLX5_FLOW_ACTION_OF_POP_VLAN)
163 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
164 MLX5_FLOW_ACTION_SET_IPV4_DST | \
165 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
166 MLX5_FLOW_ACTION_SET_IPV6_DST | \
167 MLX5_FLOW_ACTION_SET_TP_SRC | \
168 MLX5_FLOW_ACTION_SET_TP_DST | \
169 MLX5_FLOW_ACTION_SET_TTL | \
170 MLX5_FLOW_ACTION_DEC_TTL | \
171 MLX5_FLOW_ACTION_SET_MAC_SRC | \
172 MLX5_FLOW_ACTION_SET_MAC_DST | \
173 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
174 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
175 MLX5_FLOW_ACTION_INC_TCP_ACK | \
176 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
177 MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
179 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
180 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
183 #define IPPROTO_MPLS 137
186 /* UDP port number for MPLS */
187 #define MLX5_UDP_PORT_MPLS 6635
189 /* UDP port numbers for VxLAN. */
190 #define MLX5_UDP_PORT_VXLAN 4789
191 #define MLX5_UDP_PORT_VXLAN_GPE 4790
193 /* UDP port numbers for GENEVE. */
194 #define MLX5_UDP_PORT_GENEVE 6081
196 /* Priority reserved for default flows. */
197 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
200 * Number of sub priorities.
201 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
202 * matching on the NIC (firmware dependent) L4 most have the higher priority
203 * followed by L3 and ending with L2.
205 #define MLX5_PRIORITY_MAP_L2 2
206 #define MLX5_PRIORITY_MAP_L3 1
207 #define MLX5_PRIORITY_MAP_L4 0
208 #define MLX5_PRIORITY_MAP_MAX 3
210 /* Valid layer type for IPV4 RSS. */
211 #define MLX5_IPV4_LAYER_TYPES \
212 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
213 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
214 ETH_RSS_NONFRAG_IPV4_OTHER)
216 /* IBV hash source bits for IPV4. */
217 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
219 /* Valid layer type for IPV6 RSS. */
220 #define MLX5_IPV6_LAYER_TYPES \
221 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
222 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
223 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
225 /* IBV hash source bits for IPV6. */
226 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
229 /* Geneve header first 16Bit */
230 #define MLX5_GENEVE_VER_MASK 0x3
231 #define MLX5_GENEVE_VER_SHIFT 14
232 #define MLX5_GENEVE_VER_VAL(a) \
233 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
234 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
235 #define MLX5_GENEVE_OPTLEN_SHIFT 7
236 #define MLX5_GENEVE_OPTLEN_VAL(a) \
237 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
238 #define MLX5_GENEVE_OAMF_MASK 0x1
239 #define MLX5_GENEVE_OAMF_SHIFT 7
240 #define MLX5_GENEVE_OAMF_VAL(a) \
241 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
242 #define MLX5_GENEVE_CRITO_MASK 0x1
243 #define MLX5_GENEVE_CRITO_SHIFT 6
244 #define MLX5_GENEVE_CRITO_VAL(a) \
245 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
246 #define MLX5_GENEVE_RSVD_MASK 0x3F
247 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
249 * The length of the Geneve options fields, expressed in four byte multiples,
250 * not including the eight byte fixed tunnel.
252 #define MLX5_GENEVE_OPT_LEN_0 14
253 #define MLX5_GENEVE_OPT_LEN_1 63
255 enum mlx5_flow_drv_type {
258 MLX5_FLOW_TYPE_VERBS,
262 /* Matcher PRM representation */
263 struct mlx5_flow_dv_match_params {
265 /**< Size of match value. Do NOT split size and key! */
266 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
267 /**< Matcher value. This value is used as the mask or as a key. */
270 /* Matcher structure. */
271 struct mlx5_flow_dv_matcher {
272 LIST_ENTRY(mlx5_flow_dv_matcher) next;
273 /* Pointer to the next element. */
274 rte_atomic32_t refcnt; /**< Reference counter. */
275 void *matcher_object; /**< Pointer to DV matcher */
276 uint16_t crc; /**< CRC of key. */
277 uint16_t priority; /**< Priority of matcher. */
278 uint8_t egress; /**< Egress matcher. */
279 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
280 uint32_t group; /**< The matcher group. */
281 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
284 #define MLX5_ENCAP_MAX_LEN 132
286 /* Encap/decap resource structure. */
287 struct mlx5_flow_dv_encap_decap_resource {
288 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
289 /* Pointer to next element. */
290 rte_atomic32_t refcnt; /**< Reference counter. */
292 /**< Verbs encap/decap action object. */
293 uint8_t buf[MLX5_ENCAP_MAX_LEN];
295 uint8_t reformat_type;
297 uint64_t flags; /**< Flags for RDMA API. */
300 /* Tag resource structure. */
301 struct mlx5_flow_dv_tag_resource {
302 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
303 /* Pointer to next element. */
304 rte_atomic32_t refcnt; /**< Reference counter. */
306 /**< Verbs tag action object. */
307 uint32_t tag; /**< the tag value. */
310 /* Number of modification commands. */
311 #define MLX5_MODIFY_NUM 8
313 /* Modify resource structure */
314 struct mlx5_flow_dv_modify_hdr_resource {
315 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
316 /* Pointer to next element. */
317 rte_atomic32_t refcnt; /**< Reference counter. */
318 struct ibv_flow_action *verbs_action;
319 /**< Verbs modify header action object. */
320 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
321 uint32_t actions_num; /**< Number of modification actions. */
322 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
323 /**< Modification actions. */
324 uint64_t flags; /**< Flags for RDMA API. */
327 /* Jump action resource structure. */
328 struct mlx5_flow_dv_jump_tbl_resource {
329 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
330 /* Pointer to next element. */
331 rte_atomic32_t refcnt; /**< Reference counter. */
332 void *action; /**< Pointer to the rdma core action. */
333 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
334 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
337 /* Port ID resource structure. */
338 struct mlx5_flow_dv_port_id_action_resource {
339 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
340 /* Pointer to next element. */
341 rte_atomic32_t refcnt; /**< Reference counter. */
343 /**< Verbs tag action object. */
344 uint32_t port_id; /**< Port ID value. */
347 /* Push VLAN action resource structure */
348 struct mlx5_flow_dv_push_vlan_action_resource {
349 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next;
350 /* Pointer to next element. */
351 rte_atomic32_t refcnt; /**< Reference counter. */
352 void *action; /**< Direct verbs action object. */
353 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
354 rte_be32_t vlan_tag; /**< VLAN tag value. */
358 * Max number of actions per DV flow.
359 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
360 * In rdma-core file providers/mlx5/verbs.c
362 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
364 /* DV flows structure. */
365 struct mlx5_flow_dv {
366 uint64_t hash_fields; /**< Fields that participate in the hash. */
367 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
369 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
370 struct mlx5_flow_dv_match_params value;
371 /**< Holds the value that the packet is compared to. */
372 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
373 /**< Pointer to encap/decap resource in cache. */
374 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
375 /**< Pointer to modify header resource in cache. */
376 struct ibv_flow *flow; /**< Installed flow. */
377 struct mlx5_flow_dv_jump_tbl_resource *jump;
378 /**< Pointer to the jump action resource. */
379 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
380 /**< Pointer to port ID action resource. */
381 struct mlx5_vf_vlan vf_vlan;
382 /**< Structure for VF VLAN workaround. */
383 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
384 /**< Pointer to push VLAN action resource in cache. */
385 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
386 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
389 int actions_n; /**< number of actions. */
392 /* Verbs specification header. */
393 struct ibv_spec_header {
394 enum ibv_flow_spec_type type;
398 /** Handles information leading to a drop fate. */
399 struct mlx5_flow_verbs {
400 LIST_ENTRY(mlx5_flow_verbs) next;
401 unsigned int size; /**< Size of the attribute. */
403 struct ibv_flow_attr *attr;
404 /**< Pointer to the Specification buffer. */
405 uint8_t *specs; /**< Pointer to the specifications. */
407 struct ibv_flow *flow; /**< Verbs flow pointer. */
408 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
409 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
410 struct mlx5_vf_vlan vf_vlan;
411 /**< Structure for VF VLAN workaround. */
414 /** Device flow structure. */
416 LIST_ENTRY(mlx5_flow) next;
417 struct rte_flow *flow; /**< Pointer to the main flow. */
419 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
421 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
422 struct mlx5_flow_dv dv;
424 struct mlx5_flow_verbs verbs;
426 bool external; /**< true if the flow is created external to PMD. */
429 /* Flow structure. */
431 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
432 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
433 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
434 struct mlx5_flow_dv_tag_resource *tag_resource;
435 /**< pointer to the tag action. */
436 struct rte_flow_action_rss rss;/**< RSS context. */
437 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
438 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
439 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
440 /**< Device flows that are part of the flow. */
442 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
443 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
444 uint8_t ingress; /**< 1 if the flow is ingress. */
445 uint32_t group; /**< The group index. */
446 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
449 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
450 const struct rte_flow_attr *attr,
451 const struct rte_flow_item items[],
452 const struct rte_flow_action actions[],
454 struct rte_flow_error *error);
455 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
456 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
457 const struct rte_flow_action actions[], struct rte_flow_error *error);
458 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
459 struct mlx5_flow *dev_flow,
460 const struct rte_flow_attr *attr,
461 const struct rte_flow_item items[],
462 const struct rte_flow_action actions[],
463 struct rte_flow_error *error);
464 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
465 struct rte_flow_error *error);
466 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
467 struct rte_flow *flow);
468 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
469 struct rte_flow *flow);
470 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
471 struct rte_flow *flow,
472 const struct rte_flow_action *actions,
474 struct rte_flow_error *error);
475 struct mlx5_flow_driver_ops {
476 mlx5_flow_validate_t validate;
477 mlx5_flow_prepare_t prepare;
478 mlx5_flow_translate_t translate;
479 mlx5_flow_apply_t apply;
480 mlx5_flow_remove_t remove;
481 mlx5_flow_destroy_t destroy;
482 mlx5_flow_query_t query;
485 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
486 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
487 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
488 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
492 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
493 bool external, uint32_t group, uint32_t *table,
494 struct rte_flow_error *error);
495 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
496 uint64_t layer_types,
497 uint64_t hash_fields);
498 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
499 uint32_t subpriority);
500 const struct rte_flow_action *mlx5_flow_find_action
501 (const struct rte_flow_action *actions,
502 enum rte_flow_action_type action);
503 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
504 const struct rte_flow_attr *attr,
505 struct rte_flow_error *error);
506 int mlx5_flow_validate_action_drop(uint64_t action_flags,
507 const struct rte_flow_attr *attr,
508 struct rte_flow_error *error);
509 int mlx5_flow_validate_action_flag(uint64_t action_flags,
510 const struct rte_flow_attr *attr,
511 struct rte_flow_error *error);
512 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
513 uint64_t action_flags,
514 const struct rte_flow_attr *attr,
515 struct rte_flow_error *error);
516 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
517 uint64_t action_flags,
518 struct rte_eth_dev *dev,
519 const struct rte_flow_attr *attr,
520 struct rte_flow_error *error);
521 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
522 uint64_t action_flags,
523 struct rte_eth_dev *dev,
524 const struct rte_flow_attr *attr,
526 struct rte_flow_error *error);
527 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
528 const struct rte_flow_attr *attributes,
529 struct rte_flow_error *error);
530 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
532 const uint8_t *nic_mask,
534 struct rte_flow_error *error);
535 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
537 struct rte_flow_error *error);
538 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
540 uint8_t target_protocol,
541 struct rte_flow_error *error);
542 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
544 const struct rte_flow_item *gre_item,
545 struct rte_flow_error *error);
546 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
548 const struct rte_flow_item_ipv4 *acc_mask,
549 struct rte_flow_error *error);
550 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
552 const struct rte_flow_item_ipv6 *acc_mask,
553 struct rte_flow_error *error);
554 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
555 const struct rte_flow_item *item,
558 struct rte_flow_error *error);
559 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
561 uint8_t target_protocol,
562 const struct rte_flow_item_tcp *flow_mask,
563 struct rte_flow_error *error);
564 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
566 uint8_t target_protocol,
567 struct rte_flow_error *error);
568 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
570 struct rte_eth_dev *dev,
571 struct rte_flow_error *error);
572 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
574 struct rte_flow_error *error);
575 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
577 struct rte_eth_dev *dev,
578 struct rte_flow_error *error);
579 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
581 uint8_t target_protocol,
582 struct rte_flow_error *error);
583 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
585 uint8_t target_protocol,
586 struct rte_flow_error *error);
587 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
589 uint8_t target_protocol,
590 struct rte_flow_error *error);
591 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
593 struct rte_eth_dev *dev,
594 struct rte_flow_error *error);
595 #endif /* RTE_PMD_MLX5_FLOW_H_ */