1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/mlx5dv.h>
18 #pragma GCC diagnostic error "-Wpedantic"
22 #include "mlx5_autoconf.h"
24 /* RSS hash key size. */
25 #define MLX5_RSS_HASH_KEY_LEN 40
27 /* Get CQE owner bit. */
28 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
31 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
34 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
36 /* Get CQE solicited event. */
37 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
39 /* Invalidate a CQE. */
40 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
42 /* WQE Segment sizes in bytes. */
43 #define MLX5_WSEG_SIZE 16u
44 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
45 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
46 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
48 /* WQE/WQEBB size in bytes. */
49 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
52 * Max size of a WQE session.
53 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
54 * the WQE size field in Control Segment is 6 bits wide.
56 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
59 * Default minimum number of Tx queues for inlining packets.
60 * If there are less queues as specified we assume we have
61 * no enough CPU resources (cycles) to perform inlining,
62 * the PCIe throughput is not supposed as bottleneck and
63 * inlining is disabled.
65 #define MLX5_INLINE_MAX_TXQS 8u
66 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
69 * Default packet length threshold to be inlined with
70 * enhanced MPW. If packet length exceeds the threshold
71 * the data are not inlined. Should be aligned in WQEBB
72 * boundary with accounting the title Control and Ethernet
75 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
76 MLX5_DSEG_MIN_INLINE_SIZE)
78 * Maximal inline data length sent with enhanced MPW.
79 * Is based on maximal WQE size.
81 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
82 MLX5_WQE_CSEG_SIZE - \
83 MLX5_WQE_ESEG_SIZE - \
84 MLX5_WQE_DSEG_SIZE + \
85 MLX5_DSEG_MIN_INLINE_SIZE)
87 * Minimal amount of packets to be sent with EMPW.
88 * This limits the minimal required size of sent EMPW.
89 * If there are no enough resources to built minimal
90 * EMPW the sending loop exits.
92 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
94 * Maximal amount of packets to be sent with EMPW.
95 * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
96 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
97 * without CQE generation request, being multiplied by
98 * MLX5_TX_COMP_MAX_CQE it may cause significant latency
99 * in tx burst routine at the moment of freeing multiple mbufs.
101 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
103 * Default packet length threshold to be inlined with
104 * ordinary SEND. Inlining saves the MR key search
105 * and extra PCIe data fetch transaction, but eats the
108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
109 MLX5_ESEG_MIN_INLINE_SIZE - \
110 MLX5_WQE_CSEG_SIZE - \
111 MLX5_WQE_ESEG_SIZE - \
114 * Maximal inline data length sent with ordinary SEND.
115 * Is based on maximal WQE size.
117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
118 MLX5_WQE_CSEG_SIZE - \
119 MLX5_WQE_ESEG_SIZE - \
120 MLX5_WQE_DSEG_SIZE + \
121 MLX5_ESEG_MIN_INLINE_SIZE)
123 /* Missed in mlv5dv.h, should define here. */
124 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
126 /* CQE value to inform that VLAN is stripped. */
127 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
130 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
133 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
136 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
139 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
142 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
144 /* IP is fragmented. */
145 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
147 /* L2 header is valid. */
148 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
150 /* L3 header is valid. */
151 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
153 /* L4 header is valid. */
154 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
156 /* Outer packet, 0 IPv4, 1 IPv6. */
157 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
159 /* Tunnel packet bit in the CQE. */
160 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
162 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
163 #define MLX5_CQE_LRO_PUSH_MASK 0x40
165 /* Mask for L4 type in the CQE hdr_type_etc field. */
166 #define MLX5_CQE_L4_TYPE_MASK 0x70
168 /* The bit index of L4 type in CQE hdr_type_etc field. */
169 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
171 /* L4 type to indicate TCP packet without acknowledgment. */
172 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
174 /* L4 type to indicate TCP packet with acknowledgment. */
175 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
177 /* Inner L3 checksum offload (Tunneled packets only). */
178 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
180 /* Inner L4 checksum offload (Tunneled packets only). */
181 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
183 /* Outer L4 type is TCP. */
184 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
186 /* Outer L4 type is UDP. */
187 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
189 /* Outer L3 type is IPV4. */
190 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
192 /* Outer L3 type is IPV6. */
193 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
195 /* Inner L4 type is TCP. */
196 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
198 /* Inner L4 type is UDP. */
199 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
201 /* Inner L3 type is IPV4. */
202 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
204 /* Inner L3 type is IPV6. */
205 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
207 /* VLAN insertion flag. */
208 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
210 /* Data inline segment flag. */
211 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
213 /* Is flow mark valid. */
214 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
215 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
217 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
220 /* INVALID is used by packets matching no flow rules. */
221 #define MLX5_FLOW_MARK_INVALID 0
223 /* Maximum allowed value to mark a packet. */
224 #define MLX5_FLOW_MARK_MAX 0xfffff0
226 /* Default mark value used when none is provided. */
227 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
229 /* Maximum number of DS in WQE. Limited by 6-bit field. */
230 #define MLX5_DSEG_MAX 63
232 /* The completion mode offset in the WQE control segment line 2. */
233 #define MLX5_COMP_MODE_OFFSET 2
235 /* Amount of data bytes in minimal inline data segment. */
236 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
238 /* Amount of data bytes in minimal inline eth segment. */
239 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
241 /* Amount of data bytes after eth data segment. */
242 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
244 /* The maximum log value of segments per RQ WQE. */
245 #define MLX5_MAX_LOG_RQ_SEGS 5u
247 /* The alignment needed for WQ buffer. */
248 #define MLX5_WQE_BUF_ALIGNMENT 512
250 /* Completion mode. */
251 enum mlx5_completion_mode {
252 MLX5_COMP_ONLY_ERR = 0x0,
253 MLX5_COMP_ONLY_FIRST_ERR = 0x1,
254 MLX5_COMP_ALWAYS = 0x2,
255 MLX5_COMP_CQE_AND_EQE = 0x3,
262 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
265 /* WQE Control segment. */
266 struct mlx5_wqe_cseg {
271 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
273 /* Header of data segment. Minimal size Data Segment */
274 struct mlx5_wqe_dseg {
277 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
285 /* Subset of struct WQE Ethernet Segment. */
286 struct mlx5_wqe_eseg {
294 uint16_t inline_hdr_sz;
296 uint16_t inline_data;
303 uint32_t flow_metadata;
309 /* The title WQEBB, header of WQE. */
312 struct mlx5_wqe_cseg cseg;
315 struct mlx5_wqe_eseg eseg;
317 struct mlx5_wqe_dseg dseg[2];
318 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
322 /* WQE for Multi-Packet RQ. */
323 struct mlx5_wqe_mprq {
324 struct mlx5_wqe_srq_next_seg next_seg;
325 struct mlx5_wqe_data_seg dseg;
328 #define MLX5_MPRQ_LEN_MASK 0x000ffff
329 #define MLX5_MPRQ_LEN_SHIFT 0
330 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
331 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
332 #define MLX5_MPRQ_FILLER_MASK 0x80000000
333 #define MLX5_MPRQ_FILLER_SHIFT 31
335 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
337 /* CQ element structure - should be equal to the cache line size */
339 #if (RTE_CACHE_LINE_SIZE == 128)
345 uint8_t lro_tcppsh_abort_dupack;
347 uint16_t lro_tcp_win;
348 uint32_t lro_ack_seq_num;
349 uint32_t rx_hash_res;
350 uint8_t rx_hash_type;
354 uint16_t hdr_type_etc;
360 uint32_t sop_drop_qpn;
361 uint16_t wqe_counter;
366 /* Adding direct verbs to data-path. */
368 /* CQ sequence number mask. */
369 #define MLX5_CQ_SQN_MASK 0x3
371 /* CQ sequence number index. */
372 #define MLX5_CQ_SQN_OFFSET 28
374 /* CQ doorbell index mask. */
375 #define MLX5_CI_MASK 0xffffff
377 /* CQ doorbell offset. */
378 #define MLX5_CQ_ARM_DB 1
380 /* CQ doorbell offset*/
381 #define MLX5_CQ_DOORBELL 0x20
383 /* CQE format value. */
384 #define MLX5_COMPRESSED 0x3
386 /* Write a specific data value to a field. */
387 #define MLX5_MODIFICATION_TYPE_SET 1
389 /* Add a specific data value to a field. */
390 #define MLX5_MODIFICATION_TYPE_ADD 2
392 /* The field of packet to be modified. */
393 enum mlx5_modification_field {
394 MLX5_MODI_OUT_SMAC_47_16 = 1,
395 MLX5_MODI_OUT_SMAC_15_0,
396 MLX5_MODI_OUT_ETHERTYPE,
397 MLX5_MODI_OUT_DMAC_47_16,
398 MLX5_MODI_OUT_DMAC_15_0,
399 MLX5_MODI_OUT_IP_DSCP,
400 MLX5_MODI_OUT_TCP_FLAGS,
401 MLX5_MODI_OUT_TCP_SPORT,
402 MLX5_MODI_OUT_TCP_DPORT,
403 MLX5_MODI_OUT_IPV4_TTL,
404 MLX5_MODI_OUT_UDP_SPORT,
405 MLX5_MODI_OUT_UDP_DPORT,
406 MLX5_MODI_OUT_SIPV6_127_96,
407 MLX5_MODI_OUT_SIPV6_95_64,
408 MLX5_MODI_OUT_SIPV6_63_32,
409 MLX5_MODI_OUT_SIPV6_31_0,
410 MLX5_MODI_OUT_DIPV6_127_96,
411 MLX5_MODI_OUT_DIPV6_95_64,
412 MLX5_MODI_OUT_DIPV6_63_32,
413 MLX5_MODI_OUT_DIPV6_31_0,
416 MLX5_MODI_OUT_FIRST_VID,
417 MLX5_MODI_IN_SMAC_47_16 = 0x31,
418 MLX5_MODI_IN_SMAC_15_0,
419 MLX5_MODI_IN_ETHERTYPE,
420 MLX5_MODI_IN_DMAC_47_16,
421 MLX5_MODI_IN_DMAC_15_0,
422 MLX5_MODI_IN_IP_DSCP,
423 MLX5_MODI_IN_TCP_FLAGS,
424 MLX5_MODI_IN_TCP_SPORT,
425 MLX5_MODI_IN_TCP_DPORT,
426 MLX5_MODI_IN_IPV4_TTL,
427 MLX5_MODI_IN_UDP_SPORT,
428 MLX5_MODI_IN_UDP_DPORT,
429 MLX5_MODI_IN_SIPV6_127_96,
430 MLX5_MODI_IN_SIPV6_95_64,
431 MLX5_MODI_IN_SIPV6_63_32,
432 MLX5_MODI_IN_SIPV6_31_0,
433 MLX5_MODI_IN_DIPV6_127_96,
434 MLX5_MODI_IN_DIPV6_95_64,
435 MLX5_MODI_IN_DIPV6_63_32,
436 MLX5_MODI_IN_DIPV6_31_0,
439 MLX5_MODI_OUT_IPV6_HOPLIMIT,
440 MLX5_MODI_IN_IPV6_HOPLIMIT,
441 MLX5_MODI_META_DATA_REG_A,
442 MLX5_MODI_META_DATA_REG_B = 0x50,
443 MLX5_MODI_META_REG_C_0,
444 MLX5_MODI_META_REG_C_1,
445 MLX5_MODI_META_REG_C_2,
446 MLX5_MODI_META_REG_C_3,
447 MLX5_MODI_META_REG_C_4,
448 MLX5_MODI_META_REG_C_5,
449 MLX5_MODI_META_REG_C_6,
450 MLX5_MODI_META_REG_C_7,
451 MLX5_MODI_OUT_TCP_SEQ_NUM,
452 MLX5_MODI_IN_TCP_SEQ_NUM,
453 MLX5_MODI_OUT_TCP_ACK_NUM,
454 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
457 /* Modification sub command. */
458 struct mlx5_modification_cmd {
462 unsigned int length:5;
463 unsigned int rsvd0:3;
464 unsigned int offset:5;
465 unsigned int rsvd1:3;
466 unsigned int field:12;
467 unsigned int action_type:4;
476 typedef uint32_t u32;
477 typedef uint16_t u16;
480 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
481 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
482 #define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
483 (&(__mlx5_nullp(typ)->fld)))
484 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
485 (__mlx5_bit_off(typ, fld) & 0x1f))
486 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
487 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
488 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
489 __mlx5_dw_bit_off(typ, fld))
490 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
491 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
492 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
493 (__mlx5_bit_off(typ, fld) & 0xf))
494 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
495 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
496 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
497 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
498 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
500 /* insert a value to a struct */
501 #define MLX5_SET(typ, p, fld, v) \
504 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
505 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
506 __mlx5_dw_off(typ, fld))) & \
507 (~__mlx5_dw_mask(typ, fld))) | \
508 (((_v) & __mlx5_mask(typ, fld)) << \
509 __mlx5_dw_bit_off(typ, fld))); \
512 #define MLX5_SET64(typ, p, fld, v) \
514 assert(__mlx5_bit_sz(typ, fld) == 64); \
515 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \
516 rte_cpu_to_be_64(v); \
519 #define MLX5_GET(typ, p, fld) \
520 ((rte_be_to_cpu_32(*((__be32 *)(p) +\
521 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
522 __mlx5_mask(typ, fld))
523 #define MLX5_GET16(typ, p, fld) \
524 ((rte_be_to_cpu_16(*((__be16 *)(p) + \
525 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
526 __mlx5_mask16(typ, fld))
527 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((__be64 *)(p) + \
528 __mlx5_64_off(typ, fld)))
529 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
531 struct mlx5_ifc_fte_match_set_misc_bits {
532 u8 gre_c_present[0x1];
533 u8 reserved_at_1[0x1];
534 u8 gre_k_present[0x1];
535 u8 gre_s_present[0x1];
536 u8 source_vhci_port[0x4];
538 u8 reserved_at_20[0x10];
539 u8 source_port[0x10];
540 u8 outer_second_prio[0x3];
541 u8 outer_second_cfi[0x1];
542 u8 outer_second_vid[0xc];
543 u8 inner_second_prio[0x3];
544 u8 inner_second_cfi[0x1];
545 u8 inner_second_vid[0xc];
546 u8 outer_second_cvlan_tag[0x1];
547 u8 inner_second_cvlan_tag[0x1];
548 u8 outer_second_svlan_tag[0x1];
549 u8 inner_second_svlan_tag[0x1];
550 u8 reserved_at_64[0xc];
551 u8 gre_protocol[0x10];
555 u8 reserved_at_b8[0x8];
557 u8 reserved_at_e4[0x7];
559 u8 reserved_at_e0[0xc];
560 u8 outer_ipv6_flow_label[0x14];
561 u8 reserved_at_100[0xc];
562 u8 inner_ipv6_flow_label[0x14];
563 u8 reserved_at_120[0xa];
564 u8 geneve_opt_len[0x6];
565 u8 geneve_protocol_type[0x10];
566 u8 reserved_at_140[0xc0];
569 struct mlx5_ifc_ipv4_layout_bits {
570 u8 reserved_at_0[0x60];
574 struct mlx5_ifc_ipv6_layout_bits {
578 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
579 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
580 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
581 u8 reserved_at_0[0x80];
584 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
603 u8 reserved_at_c0[0x20];
606 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
607 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
610 struct mlx5_ifc_fte_match_mpls_bits {
617 struct mlx5_ifc_fte_match_set_misc2_bits {
618 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
619 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
620 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
621 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
622 u8 metadata_reg_c_7[0x20];
623 u8 metadata_reg_c_6[0x20];
624 u8 metadata_reg_c_5[0x20];
625 u8 metadata_reg_c_4[0x20];
626 u8 metadata_reg_c_3[0x20];
627 u8 metadata_reg_c_2[0x20];
628 u8 metadata_reg_c_1[0x20];
629 u8 metadata_reg_c_0[0x20];
630 u8 metadata_reg_a[0x20];
631 u8 reserved_at_1a0[0x60];
634 struct mlx5_ifc_fte_match_set_misc3_bits {
635 u8 inner_tcp_seq_num[0x20];
636 u8 outer_tcp_seq_num[0x20];
637 u8 inner_tcp_ack_num[0x20];
638 u8 outer_tcp_ack_num[0x20];
639 u8 reserved_at_auto1[0x8];
640 u8 outer_vxlan_gpe_vni[0x18];
641 u8 outer_vxlan_gpe_next_protocol[0x8];
642 u8 outer_vxlan_gpe_flags[0x8];
643 u8 reserved_at_a8[0x10];
644 u8 icmp_header_data[0x20];
645 u8 icmpv6_header_data[0x20];
650 u8 reserved_at_1a0[0xe0];
654 struct mlx5_ifc_fte_match_param_bits {
655 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
656 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
657 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
658 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
659 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
663 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
664 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
665 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
666 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
667 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT
671 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
672 MLX5_CMD_OP_CREATE_MKEY = 0x200,
673 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
674 MLX5_CMD_OP_CREATE_TIR = 0x900,
675 MLX5_CMD_OP_CREATE_RQ = 0x908,
676 MLX5_CMD_OP_MODIFY_RQ = 0x909,
677 MLX5_CMD_OP_QUERY_TIS = 0x915,
678 MLX5_CMD_OP_CREATE_RQT = 0x916,
679 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
680 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
684 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
688 struct mlx5_ifc_alloc_flow_counter_out_bits {
690 u8 reserved_at_8[0x18];
692 u8 flow_counter_id[0x20];
693 u8 reserved_at_60[0x20];
696 struct mlx5_ifc_alloc_flow_counter_in_bits {
698 u8 reserved_at_10[0x10];
699 u8 reserved_at_20[0x10];
701 u8 flow_counter_id[0x20];
702 u8 reserved_at_40[0x18];
703 u8 flow_counter_bulk[0x8];
706 struct mlx5_ifc_dealloc_flow_counter_out_bits {
708 u8 reserved_at_8[0x18];
710 u8 reserved_at_40[0x40];
713 struct mlx5_ifc_dealloc_flow_counter_in_bits {
715 u8 reserved_at_10[0x10];
716 u8 reserved_at_20[0x10];
718 u8 flow_counter_id[0x20];
719 u8 reserved_at_60[0x20];
722 struct mlx5_ifc_traffic_counter_bits {
727 struct mlx5_ifc_query_flow_counter_out_bits {
729 u8 reserved_at_8[0x18];
731 u8 reserved_at_40[0x40];
732 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
735 struct mlx5_ifc_query_flow_counter_in_bits {
737 u8 reserved_at_10[0x10];
738 u8 reserved_at_20[0x10];
740 u8 reserved_at_40[0x20];
744 u8 dump_to_memory[0x1];
745 u8 num_of_counters[0x1e];
746 u8 flow_counter_id[0x20];
749 struct mlx5_ifc_mkc_bits {
750 u8 reserved_at_0[0x1];
752 u8 reserved_at_2[0x1];
753 u8 access_mode_4_2[0x3];
754 u8 reserved_at_6[0x7];
755 u8 relaxed_ordering_write[0x1];
756 u8 reserved_at_e[0x1];
757 u8 small_fence_on_rdma_read_response[0x1];
764 u8 access_mode_1_0[0x2];
765 u8 reserved_at_18[0x8];
770 u8 reserved_at_40[0x20];
775 u8 reserved_at_63[0x2];
776 u8 expected_sigerr_count[0x1];
777 u8 reserved_at_66[0x1];
785 u8 bsf_octword_size[0x20];
787 u8 reserved_at_120[0x80];
789 u8 translations_octword_size[0x20];
791 u8 reserved_at_1c0[0x1b];
792 u8 log_page_size[0x5];
794 u8 reserved_at_1e0[0x20];
797 struct mlx5_ifc_create_mkey_out_bits {
799 u8 reserved_at_8[0x18];
803 u8 reserved_at_40[0x8];
806 u8 reserved_at_60[0x20];
809 struct mlx5_ifc_create_mkey_in_bits {
811 u8 reserved_at_10[0x10];
813 u8 reserved_at_20[0x10];
816 u8 reserved_at_40[0x20];
819 u8 reserved_at_61[0x1f];
821 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
823 u8 reserved_at_280[0x80];
825 u8 translations_octword_actual_size[0x20];
827 u8 mkey_umem_id[0x20];
829 u8 mkey_umem_offset[0x40];
831 u8 reserved_at_380[0x500];
833 u8 klm_pas_mtt[][0x20];
837 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
838 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
839 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
843 MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
844 MLX5_HCA_CAP_OPMOD_GET_CUR = 1,
848 MLX5_CAP_INLINE_MODE_L2,
849 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
850 MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
854 MLX5_INLINE_MODE_NONE,
857 MLX5_INLINE_MODE_TCP_UDP,
858 MLX5_INLINE_MODE_RESERVED4,
859 MLX5_INLINE_MODE_INNER_L2,
860 MLX5_INLINE_MODE_INNER_IP,
861 MLX5_INLINE_MODE_INNER_TCP_UDP,
864 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
865 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
866 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
867 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
868 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
869 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
870 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
871 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
872 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
873 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
874 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
876 struct mlx5_ifc_cmd_hca_cap_bits {
877 u8 reserved_at_0[0x30];
879 u8 reserved_at_40[0x40];
880 u8 log_max_srq_sz[0x8];
881 u8 log_max_qp_sz[0x8];
882 u8 reserved_at_90[0xb];
884 u8 reserved_at_a0[0xb];
886 u8 reserved_at_b0[0x10];
887 u8 reserved_at_c0[0x8];
888 u8 log_max_cq_sz[0x8];
889 u8 reserved_at_d0[0xb];
891 u8 log_max_eq_sz[0x8];
892 u8 reserved_at_e8[0x2];
893 u8 log_max_mkey[0x6];
894 u8 reserved_at_f0[0x8];
895 u8 dump_fill_mkey[0x1];
896 u8 reserved_at_f9[0x3];
898 u8 max_indirection[0x8];
899 u8 fixed_buffer_size[0x1];
900 u8 log_max_mrw_sz[0x7];
901 u8 force_teardown[0x1];
902 u8 reserved_at_111[0x1];
903 u8 log_max_bsf_list_size[0x6];
904 u8 umr_extended_translation_offset[0x1];
906 u8 log_max_klm_list_size[0x6];
907 u8 reserved_at_120[0xa];
908 u8 log_max_ra_req_dc[0x6];
909 u8 reserved_at_130[0xa];
910 u8 log_max_ra_res_dc[0x6];
911 u8 reserved_at_140[0xa];
912 u8 log_max_ra_req_qp[0x6];
913 u8 reserved_at_150[0xa];
914 u8 log_max_ra_res_qp[0x6];
916 u8 cc_query_allowed[0x1];
917 u8 cc_modify_allowed[0x1];
919 u8 cache_line_128byte[0x1];
920 u8 reserved_at_165[0xa];
922 u8 gid_table_size[0x10];
923 u8 out_of_seq_cnt[0x1];
924 u8 vport_counters[0x1];
925 u8 retransmission_q_counters[0x1];
927 u8 modify_rq_counter_set_id[0x1];
928 u8 rq_delay_drop[0x1];
930 u8 pkey_table_size[0x10];
931 u8 vport_group_manager[0x1];
932 u8 vhca_group_manager[0x1];
935 u8 vnic_env_queue_counters[0x1];
937 u8 nic_flow_table[0x1];
938 u8 eswitch_manager[0x1];
939 u8 device_memory[0x1];
942 u8 local_ca_ack_delay[0x5];
943 u8 port_module_event[0x1];
944 u8 enhanced_error_q_counters[0x1];
946 u8 reserved_at_1b3[0x1];
947 u8 disable_link_up[0x1];
951 u8 reserved_at_1c0[0x1];
955 u8 reserved_at_1c8[0x4];
957 u8 temp_warn_event[0x1];
959 u8 general_notification_event[0x1];
960 u8 reserved_at_1d3[0x2];
964 u8 reserved_at_1d8[0x1];
972 u8 stat_rate_support[0x10];
973 u8 reserved_at_1f0[0xc];
975 u8 compact_address_vector[0x1];
977 u8 reserved_at_202[0x1];
978 u8 ipoib_enhanced_offloads[0x1];
979 u8 ipoib_basic_offloads[0x1];
980 u8 reserved_at_205[0x1];
981 u8 repeated_block_disabled[0x1];
982 u8 umr_modify_entity_size_disabled[0x1];
983 u8 umr_modify_atomic_disabled[0x1];
984 u8 umr_indirect_mkey_disabled[0x1];
986 u8 reserved_at_20c[0x3];
987 u8 drain_sigerr[0x1];
988 u8 cmdif_checksum[0x2];
990 u8 reserved_at_213[0x1];
991 u8 wq_signature[0x1];
992 u8 sctr_data_cqe[0x1];
993 u8 reserved_at_216[0x1];
999 u8 eth_net_offloads[0x1];
1002 u8 reserved_at_21f[0x1];
1005 u8 cq_moderation[0x1];
1006 u8 reserved_at_223[0x3];
1007 u8 cq_eq_remap[0x1];
1009 u8 block_lb_mc[0x1];
1010 u8 reserved_at_229[0x1];
1011 u8 scqe_break_moderation[0x1];
1012 u8 cq_period_start_from_cqe[0x1];
1014 u8 reserved_at_22d[0x1];
1016 u8 vector_calc[0x1];
1017 u8 umr_ptr_rlky[0x1];
1019 u8 reserved_at_232[0x4];
1022 u8 set_deth_sqpn[0x1];
1023 u8 reserved_at_239[0x3];
1029 u8 reserved_at_241[0x9];
1031 u8 reserved_at_250[0x8];
1034 u8 driver_version[0x1];
1035 u8 pad_tx_eth_packet[0x1];
1036 u8 reserved_at_263[0x8];
1037 u8 log_bf_reg_size[0x5];
1038 u8 reserved_at_270[0xb];
1040 u8 num_lag_ports[0x4];
1041 u8 reserved_at_280[0x10];
1042 u8 max_wqe_sz_sq[0x10];
1043 u8 reserved_at_2a0[0x10];
1044 u8 max_wqe_sz_rq[0x10];
1045 u8 max_flow_counter_31_16[0x10];
1046 u8 max_wqe_sz_sq_dc[0x10];
1047 u8 reserved_at_2e0[0x7];
1048 u8 max_qp_mcg[0x19];
1049 u8 reserved_at_300[0x10];
1050 u8 flow_counter_bulk_alloc[0x08];
1051 u8 log_max_mcg[0x8];
1052 u8 reserved_at_320[0x3];
1053 u8 log_max_transport_domain[0x5];
1054 u8 reserved_at_328[0x3];
1056 u8 reserved_at_330[0xb];
1057 u8 log_max_xrcd[0x5];
1058 u8 nic_receive_steering_discard[0x1];
1059 u8 receive_discard_vport_down[0x1];
1060 u8 transmit_discard_vport_down[0x1];
1061 u8 reserved_at_343[0x5];
1062 u8 log_max_flow_counter_bulk[0x8];
1063 u8 max_flow_counter_15_0[0x10];
1065 u8 flow_counters_dump[0x1];
1066 u8 reserved_at_360[0x1];
1068 u8 reserved_at_368[0x3];
1070 u8 reserved_at_370[0x3];
1071 u8 log_max_tir[0x5];
1072 u8 reserved_at_378[0x3];
1073 u8 log_max_tis[0x5];
1074 u8 basic_cyclic_rcv_wqe[0x1];
1075 u8 reserved_at_381[0x2];
1076 u8 log_max_rmp[0x5];
1077 u8 reserved_at_388[0x3];
1078 u8 log_max_rqt[0x5];
1079 u8 reserved_at_390[0x3];
1080 u8 log_max_rqt_size[0x5];
1081 u8 reserved_at_398[0x3];
1082 u8 log_max_tis_per_sq[0x5];
1083 u8 ext_stride_num_range[0x1];
1084 u8 reserved_at_3a1[0x2];
1085 u8 log_max_stride_sz_rq[0x5];
1086 u8 reserved_at_3a8[0x3];
1087 u8 log_min_stride_sz_rq[0x5];
1088 u8 reserved_at_3b0[0x3];
1089 u8 log_max_stride_sz_sq[0x5];
1090 u8 reserved_at_3b8[0x3];
1091 u8 log_min_stride_sz_sq[0x5];
1093 u8 reserved_at_3c1[0x2];
1094 u8 log_max_hairpin_queues[0x5];
1095 u8 reserved_at_3c8[0x3];
1096 u8 log_max_hairpin_wq_data_sz[0x5];
1097 u8 reserved_at_3d0[0x3];
1098 u8 log_max_hairpin_num_packets[0x5];
1099 u8 reserved_at_3d8[0x3];
1100 u8 log_max_wq_sz[0x5];
1101 u8 nic_vport_change_event[0x1];
1102 u8 disable_local_lb_uc[0x1];
1103 u8 disable_local_lb_mc[0x1];
1104 u8 log_min_hairpin_wq_data_sz[0x5];
1105 u8 reserved_at_3e8[0x3];
1106 u8 log_max_vlan_list[0x5];
1107 u8 reserved_at_3f0[0x3];
1108 u8 log_max_current_mc_list[0x5];
1109 u8 reserved_at_3f8[0x3];
1110 u8 log_max_current_uc_list[0x5];
1111 u8 general_obj_types[0x40];
1112 u8 reserved_at_440[0x20];
1113 u8 reserved_at_460[0x10];
1114 u8 max_num_eqs[0x10];
1115 u8 reserved_at_480[0x3];
1116 u8 log_max_l2_table[0x5];
1117 u8 reserved_at_488[0x8];
1118 u8 log_uar_page_sz[0x10];
1119 u8 reserved_at_4a0[0x20];
1120 u8 device_frequency_mhz[0x20];
1121 u8 device_frequency_khz[0x20];
1122 u8 reserved_at_500[0x20];
1123 u8 num_of_uars_per_page[0x20];
1124 u8 flex_parser_protocols[0x20];
1125 u8 reserved_at_560[0x20];
1126 u8 reserved_at_580[0x3c];
1127 u8 mini_cqe_resp_stride_index[0x1];
1128 u8 cqe_128_always[0x1];
1129 u8 cqe_compression_128[0x1];
1130 u8 cqe_compression[0x1];
1131 u8 cqe_compression_timeout[0x10];
1132 u8 cqe_compression_max_num[0x10];
1133 u8 reserved_at_5e0[0x10];
1134 u8 tag_matching[0x1];
1135 u8 rndv_offload_rc[0x1];
1136 u8 rndv_offload_dc[0x1];
1137 u8 log_tag_matching_list_sz[0x5];
1138 u8 reserved_at_5f8[0x3];
1139 u8 log_max_xrq[0x5];
1140 u8 affiliate_nic_vport_criteria[0x8];
1141 u8 native_port_num[0x8];
1142 u8 num_vhca_ports[0x8];
1143 u8 reserved_at_618[0x6];
1144 u8 sw_owner_id[0x1];
1145 u8 reserved_at_61f[0x1e1];
1148 struct mlx5_ifc_qos_cap_bits {
1149 u8 packet_pacing[0x1];
1150 u8 esw_scheduling[0x1];
1151 u8 esw_bw_share[0x1];
1152 u8 esw_rate_limit[0x1];
1153 u8 reserved_at_4[0x1];
1154 u8 packet_pacing_burst_bound[0x1];
1155 u8 packet_pacing_typical_size[0x1];
1156 u8 flow_meter_srtcm[0x1];
1157 u8 reserved_at_8[0x8];
1158 u8 log_max_flow_meter[0x8];
1159 u8 flow_meter_reg_id[0x8];
1160 u8 reserved_at_25[0x20];
1161 u8 packet_pacing_max_rate[0x20];
1162 u8 packet_pacing_min_rate[0x20];
1163 u8 reserved_at_80[0x10];
1164 u8 packet_pacing_rate_table_size[0x10];
1165 u8 esw_element_type[0x10];
1166 u8 esw_tsar_type[0x10];
1167 u8 reserved_at_c0[0x10];
1168 u8 max_qos_para_vport[0x10];
1169 u8 max_tsar_bw_share[0x20];
1170 u8 reserved_at_100[0x6e8];
1173 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1177 u8 lro_psh_flag[0x1];
1178 u8 lro_time_stamp[0x1];
1179 u8 lro_max_msg_sz_mode[0x2];
1180 u8 wqe_vlan_insert[0x1];
1181 u8 self_lb_en_modifiable[0x1];
1184 u8 max_lso_cap[0x5];
1185 u8 multi_pkt_send_wqe[0x2];
1186 u8 wqe_inline_mode[0x2];
1187 u8 rss_ind_tbl_cap[0x4];
1189 u8 scatter_fcs[0x1];
1190 u8 enhanced_multi_pkt_send_wqe[0x1];
1191 u8 tunnel_lso_const_out_ip_id[0x1];
1192 u8 tunnel_lro_gre[0x1];
1193 u8 tunnel_lro_vxlan[0x1];
1194 u8 tunnel_stateless_gre[0x1];
1195 u8 tunnel_stateless_vxlan[0x1];
1199 u8 reserved_at_23[0xd];
1200 u8 max_vxlan_udp_ports[0x8];
1201 u8 reserved_at_38[0x6];
1202 u8 max_geneve_opt_len[0x1];
1203 u8 tunnel_stateless_geneve_rx[0x1];
1204 u8 reserved_at_40[0x10];
1205 u8 lro_min_mss_size[0x10];
1206 u8 reserved_at_60[0x120];
1207 u8 lro_timer_supported_periods[4][0x20];
1208 u8 reserved_at_200[0x600];
1211 union mlx5_ifc_hca_cap_union_bits {
1212 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1213 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1214 per_protocol_networking_offload_caps;
1215 struct mlx5_ifc_qos_cap_bits qos_cap;
1216 u8 reserved_at_0[0x8000];
1219 struct mlx5_ifc_query_hca_cap_out_bits {
1221 u8 reserved_at_8[0x18];
1223 u8 reserved_at_40[0x40];
1224 union mlx5_ifc_hca_cap_union_bits capability;
1227 struct mlx5_ifc_query_hca_cap_in_bits {
1229 u8 reserved_at_10[0x10];
1230 u8 reserved_at_20[0x10];
1232 u8 reserved_at_40[0x40];
1235 struct mlx5_ifc_mac_address_layout_bits {
1236 u8 reserved_at_0[0x10];
1237 u8 mac_addr_47_32[0x10];
1238 u8 mac_addr_31_0[0x20];
1241 struct mlx5_ifc_nic_vport_context_bits {
1242 u8 reserved_at_0[0x5];
1243 u8 min_wqe_inline_mode[0x3];
1244 u8 reserved_at_8[0x15];
1245 u8 disable_mc_local_lb[0x1];
1246 u8 disable_uc_local_lb[0x1];
1248 u8 arm_change_event[0x1];
1249 u8 reserved_at_21[0x1a];
1250 u8 event_on_mtu[0x1];
1251 u8 event_on_promisc_change[0x1];
1252 u8 event_on_vlan_change[0x1];
1253 u8 event_on_mc_address_change[0x1];
1254 u8 event_on_uc_address_change[0x1];
1255 u8 reserved_at_40[0xc];
1256 u8 affiliation_criteria[0x4];
1257 u8 affiliated_vhca_id[0x10];
1258 u8 reserved_at_60[0xd0];
1260 u8 system_image_guid[0x40];
1263 u8 reserved_at_200[0x140];
1264 u8 qkey_violation_counter[0x10];
1265 u8 reserved_at_350[0x430];
1268 u8 promisc_all[0x1];
1269 u8 reserved_at_783[0x2];
1270 u8 allowed_list_type[0x3];
1271 u8 reserved_at_788[0xc];
1272 u8 allowed_list_size[0xc];
1273 struct mlx5_ifc_mac_address_layout_bits permanent_address;
1274 u8 reserved_at_7e0[0x20];
1277 struct mlx5_ifc_query_nic_vport_context_out_bits {
1279 u8 reserved_at_8[0x18];
1281 u8 reserved_at_40[0x40];
1282 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1285 struct mlx5_ifc_query_nic_vport_context_in_bits {
1287 u8 reserved_at_10[0x10];
1288 u8 reserved_at_20[0x10];
1290 u8 other_vport[0x1];
1291 u8 reserved_at_41[0xf];
1292 u8 vport_number[0x10];
1293 u8 reserved_at_60[0x5];
1294 u8 allowed_list_type[0x3];
1295 u8 reserved_at_68[0x18];
1298 struct mlx5_ifc_tisc_bits {
1299 u8 strict_lag_tx_port_affinity[0x1];
1300 u8 reserved_at_1[0x3];
1301 u8 lag_tx_port_affinity[0x04];
1302 u8 reserved_at_8[0x4];
1304 u8 reserved_at_10[0x10];
1305 u8 reserved_at_20[0x100];
1306 u8 reserved_at_120[0x8];
1307 u8 transport_domain[0x18];
1308 u8 reserved_at_140[0x8];
1309 u8 underlay_qpn[0x18];
1310 u8 reserved_at_160[0x3a0];
1313 struct mlx5_ifc_query_tis_out_bits {
1315 u8 reserved_at_8[0x18];
1317 u8 reserved_at_40[0x40];
1318 struct mlx5_ifc_tisc_bits tis_context;
1321 struct mlx5_ifc_query_tis_in_bits {
1323 u8 reserved_at_10[0x10];
1324 u8 reserved_at_20[0x10];
1326 u8 reserved_at_40[0x8];
1328 u8 reserved_at_60[0x20];
1332 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1333 MLX5_WQ_TYPE_CYCLIC = 0x1,
1334 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1335 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1339 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1340 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1343 struct mlx5_ifc_wq_bits {
1345 u8 wq_signature[0x1];
1346 u8 end_padding_mode[0x2];
1348 u8 reserved_at_8[0x18];
1349 u8 hds_skip_first_sge[0x1];
1350 u8 log2_hds_buf_size[0x3];
1351 u8 reserved_at_24[0x7];
1352 u8 page_offset[0x5];
1354 u8 reserved_at_40[0x8];
1356 u8 reserved_at_60[0x8];
1359 u8 hw_counter[0x20];
1360 u8 sw_counter[0x20];
1361 u8 reserved_at_100[0xc];
1362 u8 log_wq_stride[0x4];
1363 u8 reserved_at_110[0x3];
1364 u8 log_wq_pg_sz[0x5];
1365 u8 reserved_at_118[0x3];
1367 u8 dbr_umem_valid[0x1];
1368 u8 wq_umem_valid[0x1];
1369 u8 reserved_at_122[0x1];
1370 u8 log_hairpin_num_packets[0x5];
1371 u8 reserved_at_128[0x3];
1372 u8 log_hairpin_data_sz[0x5];
1373 u8 reserved_at_130[0x4];
1374 u8 single_wqe_log_num_of_strides[0x4];
1375 u8 two_byte_shift_en[0x1];
1376 u8 reserved_at_139[0x4];
1377 u8 single_stride_log_num_of_bytes[0x3];
1378 u8 dbr_umem_id[0x20];
1379 u8 wq_umem_id[0x20];
1380 u8 wq_umem_offset[0x40];
1381 u8 reserved_at_1c0[0x440];
1385 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1386 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
1390 MLX5_RQC_STATE_RST = 0x0,
1391 MLX5_RQC_STATE_RDY = 0x1,
1392 MLX5_RQC_STATE_ERR = 0x3,
1395 struct mlx5_ifc_rqc_bits {
1397 u8 delay_drop_en[0x1];
1398 u8 scatter_fcs[0x1];
1400 u8 mem_rq_type[0x4];
1402 u8 reserved_at_c[0x1];
1403 u8 flush_in_error_en[0x1];
1405 u8 reserved_at_f[0x11];
1406 u8 reserved_at_20[0x8];
1407 u8 user_index[0x18];
1408 u8 reserved_at_40[0x8];
1410 u8 counter_set_id[0x8];
1411 u8 reserved_at_68[0x18];
1412 u8 reserved_at_80[0x8];
1414 u8 reserved_at_a0[0x8];
1415 u8 hairpin_peer_sq[0x18];
1416 u8 reserved_at_c0[0x10];
1417 u8 hairpin_peer_vhca[0x10];
1418 u8 reserved_at_e0[0xa0];
1419 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
1422 struct mlx5_ifc_create_rq_out_bits {
1424 u8 reserved_at_8[0x18];
1426 u8 reserved_at_40[0x8];
1428 u8 reserved_at_60[0x20];
1431 struct mlx5_ifc_create_rq_in_bits {
1434 u8 reserved_at_20[0x10];
1436 u8 reserved_at_40[0xc0];
1437 struct mlx5_ifc_rqc_bits ctx;
1440 struct mlx5_ifc_modify_rq_out_bits {
1442 u8 reserved_at_8[0x18];
1444 u8 reserved_at_40[0x40];
1448 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
1449 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
1450 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
1451 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
1454 struct mlx5_ifc_modify_rq_in_bits {
1457 u8 reserved_at_20[0x10];
1460 u8 reserved_at_44[0x4];
1462 u8 reserved_at_60[0x20];
1463 u8 modify_bitmask[0x40];
1464 u8 reserved_at_c0[0x40];
1465 struct mlx5_ifc_rqc_bits ctx;
1469 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1470 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1471 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1472 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1473 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1476 struct mlx5_ifc_rx_hash_field_select_bits {
1477 u8 l3_prot_type[0x1];
1478 u8 l4_prot_type[0x1];
1479 u8 selected_fields[0x1e];
1483 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1484 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1488 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1489 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1493 MLX5_RX_HASH_FN_NONE = 0x0,
1494 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
1495 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
1499 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
1500 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
1504 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0,
1505 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1,
1508 struct mlx5_ifc_tirc_bits {
1509 u8 reserved_at_0[0x20];
1511 u8 reserved_at_24[0x1c];
1512 u8 reserved_at_40[0x40];
1513 u8 reserved_at_80[0x4];
1514 u8 lro_timeout_period_usecs[0x10];
1515 u8 lro_enable_mask[0x4];
1516 u8 lro_max_msg_sz[0x8];
1517 u8 reserved_at_a0[0x40];
1518 u8 reserved_at_e0[0x8];
1519 u8 inline_rqn[0x18];
1520 u8 rx_hash_symmetric[0x1];
1521 u8 reserved_at_101[0x1];
1522 u8 tunneled_offload_en[0x1];
1523 u8 reserved_at_103[0x5];
1524 u8 indirect_table[0x18];
1526 u8 reserved_at_124[0x2];
1527 u8 self_lb_block[0x2];
1528 u8 transport_domain[0x18];
1529 u8 rx_hash_toeplitz_key[10][0x20];
1530 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1531 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1532 u8 reserved_at_2c0[0x4c0];
1535 struct mlx5_ifc_create_tir_out_bits {
1537 u8 reserved_at_8[0x18];
1539 u8 reserved_at_40[0x8];
1541 u8 reserved_at_60[0x20];
1544 struct mlx5_ifc_create_tir_in_bits {
1547 u8 reserved_at_20[0x10];
1549 u8 reserved_at_40[0xc0];
1550 struct mlx5_ifc_tirc_bits ctx;
1553 struct mlx5_ifc_rq_num_bits {
1554 u8 reserved_at_0[0x8];
1558 struct mlx5_ifc_rqtc_bits {
1559 u8 reserved_at_0[0xa0];
1560 u8 reserved_at_a0[0x10];
1561 u8 rqt_max_size[0x10];
1562 u8 reserved_at_c0[0x10];
1563 u8 rqt_actual_size[0x10];
1564 u8 reserved_at_e0[0x6a0];
1565 struct mlx5_ifc_rq_num_bits rq_num[];
1568 struct mlx5_ifc_create_rqt_out_bits {
1570 u8 reserved_at_8[0x18];
1572 u8 reserved_at_40[0x8];
1574 u8 reserved_at_60[0x20];
1578 #pragma GCC diagnostic ignored "-Wpedantic"
1580 struct mlx5_ifc_create_rqt_in_bits {
1583 u8 reserved_at_20[0x10];
1585 u8 reserved_at_40[0xc0];
1586 struct mlx5_ifc_rqtc_bits rqt_context;
1589 #pragma GCC diagnostic error "-Wpedantic"
1592 /* CQE format mask. */
1593 #define MLX5E_CQE_FORMAT_MASK 0xc
1596 #define MLX5_OPC_MOD_MPW 0x01
1598 /* Compressed Rx CQE structure. */
1599 struct mlx5_mini_cqe8 {
1601 uint32_t rx_hash_result;
1604 uint16_t stride_idx;
1607 uint16_t wqe_counter;
1608 uint8_t s_wqe_opcode;
1616 * Convert a user mark to flow mark.
1619 * Mark value to convert.
1622 * Converted mark value.
1624 static inline uint32_t
1625 mlx5_flow_mark_set(uint32_t val)
1630 * Add one to the user value to differentiate un-marked flows from
1631 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
1632 * remains untouched.
1634 if (val != MLX5_FLOW_MARK_DEFAULT)
1636 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1638 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
1639 * word, byte-swapped by the kernel on little-endian systems. In this
1640 * case, left-shifting the resulting big-endian value ensures the
1641 * least significant 24 bits are retained when converting it back.
1643 ret = rte_cpu_to_be_32(val) >> 8;
1651 * Convert a mark to user mark.
1654 * Mark value to convert.
1657 * Converted mark value.
1659 static inline uint32_t
1660 mlx5_flow_mark_get(uint32_t val)
1663 * Subtract one from the retrieved value. It was added by
1664 * mlx5_flow_mark_set() to distinguish unmarked flows.
1666 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1667 return (val >> 8) - 1;
1673 #endif /* RTE_PMD_MLX5_PRM_H_ */