1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
8 #include <rte_malloc.h>
12 #include <mlx5_common.h>
14 #include "mlx5_vdpa_utils.h"
15 #include "mlx5_vdpa.h"
19 mlx5_vdpa_virtq_handler(void *cb_arg)
21 struct mlx5_vdpa_virtq *virtq = cb_arg;
22 struct mlx5_vdpa_priv *priv = virtq->priv;
27 nbytes = read(virtq->intr_handle.fd, &buf, 8);
30 errno == EWOULDBLOCK ||
33 DRV_LOG(ERR, "Failed to read kickfd of virtq %d: %s",
34 virtq->index, strerror(errno));
38 rte_write32(virtq->index, priv->virtq_db_addr);
39 if (virtq->notifier_state == MLX5_VDPA_NOTIFIER_STATE_DISABLED) {
40 if (rte_vhost_host_notifier_ctrl(priv->vid, virtq->index, true))
41 virtq->notifier_state = MLX5_VDPA_NOTIFIER_STATE_ERR;
43 virtq->notifier_state =
44 MLX5_VDPA_NOTIFIER_STATE_ENABLED;
45 DRV_LOG(INFO, "Virtq %u notifier state is %s.", virtq->index,
46 virtq->notifier_state ==
47 MLX5_VDPA_NOTIFIER_STATE_ENABLED ? "enabled" :
50 DRV_LOG(DEBUG, "Ring virtq %u doorbell.", virtq->index);
54 mlx5_vdpa_virtq_unset(struct mlx5_vdpa_virtq *virtq)
57 int retries = MLX5_VDPA_INTR_RETRIES;
60 if (virtq->intr_handle.fd != -1) {
61 while (retries-- && ret == -EAGAIN) {
62 ret = rte_intr_callback_unregister(&virtq->intr_handle,
63 mlx5_vdpa_virtq_handler,
66 DRV_LOG(DEBUG, "Try again to unregister fd %d "
67 "of virtq %d interrupt, retries = %d.",
68 virtq->intr_handle.fd,
69 (int)virtq->index, retries);
70 usleep(MLX5_VDPA_INTR_RETRIES_USEC);
73 virtq->intr_handle.fd = -1;
76 ret = mlx5_vdpa_virtq_stop(virtq->priv, virtq->index);
78 DRV_LOG(WARNING, "Failed to stop virtq %d.",
80 claim_zero(mlx5_devx_cmd_destroy(virtq->virtq));
83 for (i = 0; i < RTE_DIM(virtq->umems); ++i) {
84 if (virtq->umems[i].obj)
85 claim_zero(mlx5_glue->devx_umem_dereg
86 (virtq->umems[i].obj));
87 if (virtq->umems[i].buf)
88 rte_free(virtq->umems[i].buf);
90 memset(&virtq->umems, 0, sizeof(virtq->umems));
92 mlx5_vdpa_event_qp_destroy(&virtq->eqp);
93 virtq->notifier_state = MLX5_VDPA_NOTIFIER_STATE_DISABLED;
98 mlx5_vdpa_virtqs_release(struct mlx5_vdpa_priv *priv)
101 struct mlx5_vdpa_virtq *virtq;
103 for (i = 0; i < priv->nr_virtqs; i++) {
104 virtq = &priv->virtqs[i];
105 mlx5_vdpa_virtq_unset(virtq);
107 claim_zero(mlx5_devx_cmd_destroy(virtq->counters));
109 for (i = 0; i < priv->num_lag_ports; i++) {
111 claim_zero(mlx5_devx_cmd_destroy(priv->tiss[i]));
112 priv->tiss[i] = NULL;
116 claim_zero(mlx5_devx_cmd_destroy(priv->td));
119 if (priv->virtq_db_addr) {
120 claim_zero(munmap(priv->virtq_db_addr, priv->var->length));
121 priv->virtq_db_addr = NULL;
124 memset(priv->virtqs, 0, sizeof(*virtq) * priv->nr_virtqs);
129 mlx5_vdpa_virtq_modify(struct mlx5_vdpa_virtq *virtq, int state)
131 struct mlx5_devx_virtq_attr attr = {
132 .type = MLX5_VIRTQ_MODIFY_TYPE_STATE,
133 .state = state ? MLX5_VIRTQ_STATE_RDY :
134 MLX5_VIRTQ_STATE_SUSPEND,
135 .queue_index = virtq->index,
138 return mlx5_devx_cmd_modify_virtq(virtq->virtq, &attr);
142 mlx5_vdpa_virtq_stop(struct mlx5_vdpa_priv *priv, int index)
144 struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index];
149 ret = mlx5_vdpa_virtq_modify(virtq, 0);
152 virtq->stopped = true;
153 DRV_LOG(DEBUG, "vid %u virtq %u was stopped.", priv->vid, index);
154 return mlx5_vdpa_virtq_query(priv, index);
158 mlx5_vdpa_virtq_query(struct mlx5_vdpa_priv *priv, int index)
160 struct mlx5_devx_virtq_attr attr = {0};
161 struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index];
164 if (mlx5_devx_cmd_query_virtq(virtq->virtq, &attr)) {
165 DRV_LOG(ERR, "Failed to query virtq %d.", index);
168 DRV_LOG(INFO, "Query vid %d vring %d: hw_available_idx=%d, "
169 "hw_used_index=%d", priv->vid, index,
170 attr.hw_available_index, attr.hw_used_index);
171 ret = rte_vhost_set_vring_base(priv->vid, index,
172 attr.hw_available_index,
175 DRV_LOG(ERR, "Failed to set virtq %d base.", index);
178 if (attr.state == MLX5_VIRTQ_STATE_ERROR)
179 DRV_LOG(WARNING, "vid %d vring %d hw error=%hhu",
180 priv->vid, index, attr.error_type);
185 mlx5_vdpa_hva_to_gpa(struct rte_vhost_memory *mem, uint64_t hva)
187 struct rte_vhost_mem_region *reg;
191 for (i = 0; i < mem->nregions; i++) {
192 reg = &mem->regions[i];
193 if (hva >= reg->host_user_addr &&
194 hva < reg->host_user_addr + reg->size) {
195 gpa = hva - reg->host_user_addr + reg->guest_phys_addr;
203 mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index)
205 struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index];
206 struct rte_vhost_vring vq;
207 struct mlx5_devx_virtq_attr attr = {0};
211 uint16_t last_avail_idx;
212 uint16_t last_used_idx;
213 uint16_t event_num = MLX5_EVENT_TYPE_OBJECT_CHANGE;
216 ret = rte_vhost_get_vhost_vring(priv->vid, index, &vq);
219 virtq->index = index;
220 virtq->vq_size = vq.size;
221 attr.tso_ipv4 = !!(priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO4));
222 attr.tso_ipv6 = !!(priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO6));
223 attr.tx_csum = !!(priv->features & (1ULL << VIRTIO_NET_F_CSUM));
224 attr.rx_csum = !!(priv->features & (1ULL << VIRTIO_NET_F_GUEST_CSUM));
225 attr.virtio_version_1_0 = !!(priv->features & (1ULL <<
226 VIRTIO_F_VERSION_1));
227 attr.type = (priv->features & (1ULL << VIRTIO_F_RING_PACKED)) ?
228 MLX5_VIRTQ_TYPE_PACKED : MLX5_VIRTQ_TYPE_SPLIT;
230 * No need event QPs creation when the guest in poll mode or when the
231 * capability allows it.
233 attr.event_mode = vq.callfd != -1 || !(priv->caps.event_mode & (1 <<
234 MLX5_VIRTQ_EVENT_MODE_NO_MSIX)) ?
235 MLX5_VIRTQ_EVENT_MODE_QP :
236 MLX5_VIRTQ_EVENT_MODE_NO_MSIX;
237 if (attr.event_mode == MLX5_VIRTQ_EVENT_MODE_QP) {
238 ret = mlx5_vdpa_event_qp_create(priv, vq.size, vq.callfd,
241 DRV_LOG(ERR, "Failed to create event QPs for virtq %d.",
245 attr.qp_id = virtq->eqp.fw_qp->id;
247 DRV_LOG(INFO, "Virtq %d is, for sure, working by poll mode, no"
248 " need event QPs and event mechanism.", index);
250 if (priv->caps.queue_counters_valid) {
251 if (!virtq->counters)
252 virtq->counters = mlx5_devx_cmd_create_virtio_q_counters
254 if (!virtq->counters) {
255 DRV_LOG(ERR, "Failed to create virtq couners for virtq"
259 attr.counters_obj_id = virtq->counters->id;
261 /* Setup 3 UMEMs for each virtq. */
262 for (i = 0; i < RTE_DIM(virtq->umems); ++i) {
263 virtq->umems[i].size = priv->caps.umems[i].a * vq.size +
264 priv->caps.umems[i].b;
265 virtq->umems[i].buf = rte_zmalloc(__func__,
266 virtq->umems[i].size, 4096);
267 if (!virtq->umems[i].buf) {
268 DRV_LOG(ERR, "Cannot allocate umem %d memory for virtq"
272 virtq->umems[i].obj = mlx5_glue->devx_umem_reg(priv->ctx,
274 virtq->umems[i].size,
275 IBV_ACCESS_LOCAL_WRITE);
276 if (!virtq->umems[i].obj) {
277 DRV_LOG(ERR, "Failed to register umem %d for virtq %u.",
281 attr.umems[i].id = virtq->umems[i].obj->umem_id;
282 attr.umems[i].offset = 0;
283 attr.umems[i].size = virtq->umems[i].size;
285 if (attr.type == MLX5_VIRTQ_TYPE_SPLIT) {
286 gpa = mlx5_vdpa_hva_to_gpa(priv->vmem,
287 (uint64_t)(uintptr_t)vq.desc);
289 DRV_LOG(ERR, "Failed to get descriptor ring GPA.");
292 attr.desc_addr = gpa;
293 gpa = mlx5_vdpa_hva_to_gpa(priv->vmem,
294 (uint64_t)(uintptr_t)vq.used);
296 DRV_LOG(ERR, "Failed to get GPA for used ring.");
299 attr.used_addr = gpa;
300 gpa = mlx5_vdpa_hva_to_gpa(priv->vmem,
301 (uint64_t)(uintptr_t)vq.avail);
303 DRV_LOG(ERR, "Failed to get GPA for available ring.");
306 attr.available_addr = gpa;
308 ret = rte_vhost_get_vring_base(priv->vid, index, &last_avail_idx,
313 DRV_LOG(WARNING, "Couldn't get vring base, idx are set to 0");
315 DRV_LOG(INFO, "vid %d: Init last_avail_idx=%d, last_used_idx=%d for "
316 "virtq %d.", priv->vid, last_avail_idx,
317 last_used_idx, index);
319 attr.hw_available_index = last_avail_idx;
320 attr.hw_used_index = last_used_idx;
321 attr.q_size = vq.size;
322 attr.mkey = priv->gpa_mkey_index;
323 attr.tis_id = priv->tiss[(index / 2) % priv->num_lag_ports]->id;
324 attr.queue_index = index;
326 attr.hw_latency_mode = priv->hw_latency_mode;
327 attr.hw_max_latency_us = priv->hw_max_latency_us;
328 attr.hw_max_pending_comp = priv->hw_max_pending_comp;
329 virtq->virtq = mlx5_devx_cmd_create_virtq(priv->ctx, &attr);
333 claim_zero(rte_vhost_enable_guest_notification(priv->vid, index, 1));
334 if (mlx5_vdpa_virtq_modify(virtq, 1))
337 rte_write32(virtq->index, priv->virtq_db_addr);
338 /* Setup doorbell mapping. */
339 virtq->intr_handle.fd = vq.kickfd;
340 if (virtq->intr_handle.fd == -1) {
341 DRV_LOG(WARNING, "Virtq %d kickfd is invalid.", index);
343 virtq->intr_handle.type = RTE_INTR_HANDLE_EXT;
344 if (rte_intr_callback_register(&virtq->intr_handle,
345 mlx5_vdpa_virtq_handler,
347 virtq->intr_handle.fd = -1;
348 DRV_LOG(ERR, "Failed to register virtq %d interrupt.",
352 DRV_LOG(DEBUG, "Register fd %d interrupt for virtq %d.",
353 virtq->intr_handle.fd, index);
356 /* Subscribe virtq error event. */
358 cookie = ((uint64_t)virtq->version << 32) + index;
359 ret = mlx5_glue->devx_subscribe_devx_event(priv->err_chnl,
364 DRV_LOG(ERR, "Failed to subscribe device %d virtq %d error event.",
369 virtq->stopped = false;
370 DRV_LOG(DEBUG, "vid %u virtq %u was created successfully.", priv->vid,
374 mlx5_vdpa_virtq_unset(virtq);
379 mlx5_vdpa_features_validate(struct mlx5_vdpa_priv *priv)
381 if (priv->features & (1ULL << VIRTIO_F_RING_PACKED)) {
382 if (!(priv->caps.virtio_queue_type & (1 <<
383 MLX5_VIRTQ_TYPE_PACKED))) {
384 DRV_LOG(ERR, "Failed to configur PACKED mode for vdev "
385 "%d - it was not reported by HW/driver"
386 " capability.", priv->vid);
390 if (priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO4)) {
391 if (!priv->caps.tso_ipv4) {
392 DRV_LOG(ERR, "Failed to enable TSO4 for vdev %d - TSO4"
393 " was not reported by HW/driver capability.",
398 if (priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO6)) {
399 if (!priv->caps.tso_ipv6) {
400 DRV_LOG(ERR, "Failed to enable TSO6 for vdev %d - TSO6"
401 " was not reported by HW/driver capability.",
406 if (priv->features & (1ULL << VIRTIO_NET_F_CSUM)) {
407 if (!priv->caps.tx_csum) {
408 DRV_LOG(ERR, "Failed to enable CSUM for vdev %d - CSUM"
409 " was not reported by HW/driver capability.",
414 if (priv->features & (1ULL << VIRTIO_NET_F_GUEST_CSUM)) {
415 if (!priv->caps.rx_csum) {
416 DRV_LOG(ERR, "Failed to enable GUEST CSUM for vdev %d"
417 " GUEST CSUM was not reported by HW/driver "
418 "capability.", priv->vid);
422 if (priv->features & (1ULL << VIRTIO_F_VERSION_1)) {
423 if (!priv->caps.virtio_version_1_0) {
424 DRV_LOG(ERR, "Failed to enable version 1 for vdev %d "
425 "version 1 was not reported by HW/driver"
426 " capability.", priv->vid);
434 mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv)
436 struct mlx5_devx_tis_attr tis_attr = {0};
438 uint16_t nr_vring = rte_vhost_get_vring_num(priv->vid);
439 int ret = rte_vhost_get_negotiated_features(priv->vid, &priv->features);
441 if (ret || mlx5_vdpa_features_validate(priv)) {
442 DRV_LOG(ERR, "Failed to configure negotiated features.");
445 if ((priv->features & (1ULL << VIRTIO_NET_F_CSUM)) == 0 &&
446 ((priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO4)) > 0 ||
447 (priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO6)) > 0)) {
448 /* Packet may be corrupted if TSO is enabled without CSUM. */
449 DRV_LOG(INFO, "TSO is enabled without CSUM, force CSUM.");
450 priv->features |= (1ULL << VIRTIO_NET_F_CSUM);
452 if (nr_vring > priv->caps.max_num_virtio_queues * 2) {
453 DRV_LOG(ERR, "Do not support more than %d virtqs(%d).",
454 (int)priv->caps.max_num_virtio_queues * 2,
458 /* Always map the entire page. */
459 priv->virtq_db_addr = mmap(NULL, priv->var->length, PROT_READ |
460 PROT_WRITE, MAP_SHARED, priv->ctx->cmd_fd,
461 priv->var->mmap_off);
462 if (priv->virtq_db_addr == MAP_FAILED) {
463 DRV_LOG(ERR, "Failed to map doorbell page %u.", errno);
464 priv->virtq_db_addr = NULL;
467 DRV_LOG(DEBUG, "VAR address of doorbell mapping is %p.",
468 priv->virtq_db_addr);
470 priv->td = mlx5_devx_cmd_create_td(priv->ctx);
472 DRV_LOG(ERR, "Failed to create transport domain.");
475 tis_attr.transport_domain = priv->td->id;
476 for (i = 0; i < priv->num_lag_ports; i++) {
477 /* 0 is auto affinity, non-zero value to propose port. */
478 tis_attr.lag_tx_port_affinity = i + 1;
479 priv->tiss[i] = mlx5_devx_cmd_create_tis(priv->ctx, &tis_attr);
480 if (!priv->tiss[i]) {
481 DRV_LOG(ERR, "Failed to create TIS %u.", i);
485 priv->nr_virtqs = nr_vring;
486 for (i = 0; i < nr_vring; i++)
487 if (priv->virtqs[i].enable && mlx5_vdpa_virtq_setup(priv, i))
491 mlx5_vdpa_virtqs_release(priv);
496 mlx5_vdpa_virtq_is_modified(struct mlx5_vdpa_priv *priv,
497 struct mlx5_vdpa_virtq *virtq)
499 struct rte_vhost_vring vq;
500 int ret = rte_vhost_get_vhost_vring(priv->vid, virtq->index, &vq);
504 if (vq.size != virtq->vq_size || vq.kickfd != virtq->intr_handle.fd)
506 if (virtq->eqp.cq.cq_obj.cq) {
507 if (vq.callfd != virtq->eqp.cq.callfd)
509 } else if (vq.callfd != -1) {
516 mlx5_vdpa_virtq_enable(struct mlx5_vdpa_priv *priv, int index, int enable)
518 struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index];
521 DRV_LOG(INFO, "Update virtq %d status %sable -> %sable.", index,
522 virtq->enable ? "en" : "dis", enable ? "en" : "dis");
523 if (!priv->configured) {
524 virtq->enable = !!enable;
527 if (virtq->enable == !!enable) {
530 ret = mlx5_vdpa_virtq_is_modified(priv, virtq);
532 DRV_LOG(ERR, "Virtq %d modify check failed.", index);
537 DRV_LOG(INFO, "Virtq %d was modified, recreate it.", index);
541 if (is_virtq_recvq(virtq->index, priv->nr_virtqs)) {
542 ret = mlx5_vdpa_steer_update(priv);
544 DRV_LOG(WARNING, "Failed to disable steering "
545 "for virtq %d.", index);
547 mlx5_vdpa_virtq_unset(virtq);
550 ret = mlx5_vdpa_virtq_setup(priv, index);
552 DRV_LOG(ERR, "Failed to setup virtq %d.", index);
556 if (is_virtq_recvq(virtq->index, priv->nr_virtqs)) {
557 ret = mlx5_vdpa_steer_update(priv);
559 DRV_LOG(WARNING, "Failed to enable steering "
560 "for virtq %d.", index);
567 mlx5_vdpa_virtq_stats_get(struct mlx5_vdpa_priv *priv, int qid,
568 struct rte_vdpa_stat *stats, unsigned int n)
570 struct mlx5_vdpa_virtq *virtq = &priv->virtqs[qid];
571 struct mlx5_devx_virtio_q_couners_attr attr = {0};
574 if (!virtq->counters) {
575 DRV_LOG(ERR, "Failed to read virtq %d statistics - virtq "
579 ret = mlx5_devx_cmd_query_virtio_q_counters(virtq->counters, &attr);
581 DRV_LOG(ERR, "Failed to read virtq %d stats from HW.", qid);
584 ret = (int)RTE_MIN(n, (unsigned int)MLX5_VDPA_STATS_MAX);
585 if (ret == MLX5_VDPA_STATS_RECEIVED_DESCRIPTORS)
587 stats[MLX5_VDPA_STATS_RECEIVED_DESCRIPTORS] = (struct rte_vdpa_stat) {
588 .id = MLX5_VDPA_STATS_RECEIVED_DESCRIPTORS,
589 .value = attr.received_desc - virtq->reset.received_desc,
591 if (ret == MLX5_VDPA_STATS_COMPLETED_DESCRIPTORS)
593 stats[MLX5_VDPA_STATS_COMPLETED_DESCRIPTORS] = (struct rte_vdpa_stat) {
594 .id = MLX5_VDPA_STATS_COMPLETED_DESCRIPTORS,
595 .value = attr.completed_desc - virtq->reset.completed_desc,
597 if (ret == MLX5_VDPA_STATS_BAD_DESCRIPTOR_ERRORS)
599 stats[MLX5_VDPA_STATS_BAD_DESCRIPTOR_ERRORS] = (struct rte_vdpa_stat) {
600 .id = MLX5_VDPA_STATS_BAD_DESCRIPTOR_ERRORS,
601 .value = attr.bad_desc_errors - virtq->reset.bad_desc_errors,
603 if (ret == MLX5_VDPA_STATS_EXCEED_MAX_CHAIN)
605 stats[MLX5_VDPA_STATS_EXCEED_MAX_CHAIN] = (struct rte_vdpa_stat) {
606 .id = MLX5_VDPA_STATS_EXCEED_MAX_CHAIN,
607 .value = attr.exceed_max_chain - virtq->reset.exceed_max_chain,
609 if (ret == MLX5_VDPA_STATS_INVALID_BUFFER)
611 stats[MLX5_VDPA_STATS_INVALID_BUFFER] = (struct rte_vdpa_stat) {
612 .id = MLX5_VDPA_STATS_INVALID_BUFFER,
613 .value = attr.invalid_buffer - virtq->reset.invalid_buffer,
615 if (ret == MLX5_VDPA_STATS_COMPLETION_ERRORS)
617 stats[MLX5_VDPA_STATS_COMPLETION_ERRORS] = (struct rte_vdpa_stat) {
618 .id = MLX5_VDPA_STATS_COMPLETION_ERRORS,
619 .value = attr.error_cqes - virtq->reset.error_cqes,
625 mlx5_vdpa_virtq_stats_reset(struct mlx5_vdpa_priv *priv, int qid)
627 struct mlx5_vdpa_virtq *virtq = &priv->virtqs[qid];
630 if (!virtq->counters) {
631 DRV_LOG(ERR, "Failed to read virtq %d statistics - virtq "
635 ret = mlx5_devx_cmd_query_virtio_q_counters(virtq->counters,
638 DRV_LOG(ERR, "Failed to read virtq %d reset stats from HW.",