1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 #include <rte_ether.h>
18 #include <rte_ethdev_driver.h>
19 #include <rte_rwlock.h>
20 #include <rte_interrupts.h>
21 #include <rte_errno.h>
24 #include <mlx5_glue.h>
25 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common_mp.h>
28 #include <mlx5_common_mr.h>
30 #include "mlx5_defs.h"
31 #include "mlx5_utils.h"
33 #include "mlx5_autoconf.h"
35 enum mlx5_ipool_index {
36 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
37 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
38 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
39 MLX5_IPOOL_TAG, /* Pool for tag resource. */
40 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
41 MLX5_IPOOL_JUMP, /* Pool for jump resource. */
42 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */
43 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */
45 MLX5_IPOOL_MTR, /* Pool for meter resource. */
46 MLX5_IPOOL_MCP, /* Pool for metadata resource. */
47 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */
48 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */
49 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */
54 * There are three reclaim memory mode supported.
55 * 0(none) means no memory reclaim.
56 * 1(light) means only PMD level reclaim.
57 * 2(aggressive) means both PMD and rdma-core level reclaim.
59 enum mlx5_reclaim_mem_mode {
60 MLX5_RCM_NONE, /* Don't reclaim memory. */
61 MLX5_RCM_LIGHT, /* Reclaim PMD level. */
62 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */
65 /* Device attributes used in mlx5 PMD */
66 struct mlx5_dev_attr {
67 uint64_t device_cap_flags_ex;
72 uint32_t raw_packet_caps;
73 uint32_t max_rwq_indirection_table_size;
75 uint32_t tso_supported_qpts;
78 uint32_t sw_parsing_offloads;
79 uint32_t min_single_stride_log_num_of_bytes;
80 uint32_t max_single_stride_log_num_of_bytes;
81 uint32_t min_single_wqe_log_num_of_strides;
82 uint32_t max_single_wqe_log_num_of_strides;
83 uint32_t stride_supported_qpts;
84 uint32_t tunnel_offloads_caps;
88 /** Data associated with devices to spawn. */
89 struct mlx5_dev_spawn_data {
90 uint32_t ifindex; /**< Network interface index. */
91 uint32_t max_port; /**< Device maximal port index. */
92 uint32_t phys_port; /**< Device physical port index. */
93 int pf_bond; /**< bonding device PF index. < 0 - no bonding */
94 struct mlx5_switch_info info; /**< Switch information. */
95 void *phys_dev; /**< Associated physical device. */
96 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
97 struct rte_pci_device *pci_dev; /**< Backend PCI device. */
100 /** Key string for IPC. */
101 #define MLX5_MP_NAME "net_mlx5_mp"
104 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared);
106 /* Shared data between primary and secondary processes. */
107 struct mlx5_shared_data {
109 /* Global spinlock for primary and secondary processes. */
110 int init_done; /* Whether primary has done initialization. */
111 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
112 struct mlx5_dev_list mem_event_cb_list;
113 rte_rwlock_t mem_event_rwlock;
116 /* Per-process data structure, not visible to other processes. */
117 struct mlx5_local_data {
118 int init_done; /* Whether a secondary has done initialization. */
121 extern struct mlx5_shared_data *mlx5_shared_data;
123 /* Dev ops structs */
124 extern const struct eth_dev_ops mlx5_os_dev_ops;
125 extern const struct eth_dev_ops mlx5_os_dev_sec_ops;
126 extern const struct eth_dev_ops mlx5_os_dev_ops_isolate;
128 struct mlx5_counter_ctrl {
129 /* Name of the counter. */
130 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
131 /* Name of the counter on the device table. */
132 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
133 uint32_t dev:1; /**< Nonzero for dev counters. */
136 struct mlx5_xstats_ctrl {
137 /* Number of device stats. */
139 /* Number of device stats identified by PMD. */
140 uint16_t mlx5_stats_n;
141 /* Index in the device counters table. */
142 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
143 uint64_t base[MLX5_MAX_XSTATS];
144 uint64_t xstats[MLX5_MAX_XSTATS];
145 uint64_t hw_stats[MLX5_MAX_XSTATS];
146 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
149 struct mlx5_stats_ctrl {
150 /* Base for imissed counter. */
151 uint64_t imissed_base;
155 /* Default PMD specific parameter value. */
156 #define MLX5_ARG_UNSET (-1)
158 #define MLX5_LRO_SUPPORTED(dev) \
159 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
161 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
162 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
164 /* Maximal size of aggregated LRO packet. */
165 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
167 /* Maximal number of segments to split. */
168 #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS)
170 /* LRO configurations structure. */
171 struct mlx5_lro_config {
172 uint32_t supported:1; /* Whether LRO is supported. */
173 uint32_t timeout; /* User configuration. */
177 * Device configuration structure.
179 * Merged configuration from:
181 * - Device capabilities,
182 * - User device parameters disabled features.
184 struct mlx5_dev_config {
185 unsigned int hw_csum:1; /* Checksum offload is supported. */
186 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
187 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
188 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
189 unsigned int hw_padding:1; /* End alignment padding is supported. */
190 unsigned int vf:1; /* This is a VF. */
191 unsigned int tunnel_en:1;
192 /* Whether tunnel stateless offloads are supported. */
193 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
194 unsigned int cqe_comp:1; /* CQE compression is enabled. */
195 unsigned int cqe_pad:1; /* CQE padding is enabled. */
196 unsigned int tso:1; /* Whether TSO is supported. */
197 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
198 unsigned int mr_ext_memseg_en:1;
199 /* Whether memseg should be extended for MR creation. */
200 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
201 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
202 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
203 unsigned int dv_flow_en:1; /* Enable DV flow. */
204 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
205 unsigned int lacp_by_user:1;
206 /* Enable user to manage LACP traffic. */
207 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
208 unsigned int devx:1; /* Whether devx interface is available or not. */
209 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
210 unsigned int reclaim_mode:2; /* Memory reclaim mode. */
211 unsigned int rt_timestamp:1; /* realtime timestamp format. */
212 unsigned int sys_mem_en:1; /* The default memory allocator. */
213 unsigned int decap_en:1; /* Whether decap will be used or not. */
214 unsigned int dv_miss_info:1; /* restore packet after partial hw miss */
216 unsigned int enabled:1; /* Whether MPRQ is enabled. */
217 unsigned int stride_num_n; /* Number of strides. */
218 unsigned int stride_size_n; /* Size of a stride. */
219 unsigned int min_stride_size_n; /* Min size of a stride. */
220 unsigned int max_stride_size_n; /* Max size of a stride. */
221 unsigned int max_memcpy_len;
222 /* Maximum packet size to memcpy Rx packets. */
223 unsigned int min_rxqs_num;
224 /* Rx queue count threshold to enable MPRQ. */
225 } mprq; /* Configurations for Multi-Packet RQ. */
226 int mps; /* Multi-packet send supported mode. */
227 int dbnc; /* Skip doorbell register write barrier. */
228 unsigned int flow_prio; /* Number of flow priorities. */
229 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
230 /* Availibility of mreg_c's. */
231 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
232 unsigned int ind_table_max_size; /* Maximum indirection table size. */
233 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
234 unsigned int log_hp_size; /* Single hairpin queue data size in total. */
235 int txqs_inline; /* Queue number threshold for inlining. */
236 int txq_inline_min; /* Minimal amount of data bytes to inline. */
237 int txq_inline_max; /* Max packet size for inlining with SEND. */
238 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
239 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */
240 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */
241 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
242 struct mlx5_lro_config lro; /* LRO configuration. */
247 * Type of object being allocated.
249 enum mlx5_verbs_alloc_type {
250 MLX5_VERBS_ALLOC_TYPE_NONE,
251 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
252 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
255 /* Structure for VF VLAN workaround. */
256 struct mlx5_vf_vlan {
262 * Verbs allocator needs a context to know in the callback which kind of
263 * resources it is allocating.
265 struct mlx5_verbs_alloc_ctx {
266 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
267 const void *obj; /* Pointer to the DPDK object. */
270 /* Flow drop context necessary due to Verbs API. */
272 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
273 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
276 #define MLX5_COUNTERS_PER_POOL 512
277 #define MLX5_MAX_PENDING_QUERIES 4
278 #define MLX5_CNT_CONTAINER_RESIZE 64
279 #define MLX5_CNT_SHARED_OFFSET 0x80000000
280 #define IS_SHARED_CNT(cnt) (!!((cnt) & MLX5_CNT_SHARED_OFFSET))
281 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \
282 MLX5_CNT_BATCH_OFFSET)
283 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter))
284 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param))
286 #define MLX5_CNT_LEN(pool) \
288 ((pool)->is_aged ? MLX5_AGE_SIZE : 0))
289 #define MLX5_POOL_GET_CNT(pool, index) \
290 ((struct mlx5_flow_counter *) \
291 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool))))
292 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \
293 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \
296 * The pool index and offset of counter in the pool array makes up the
297 * counter index. In case the counter is from pool 0 and offset 0, it
298 * should plus 1 to avoid index 0, since 0 means invalid counter index
301 #define MLX5_MAKE_CNT_IDX(pi, offset) \
302 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1)
303 #define MLX5_CNT_TO_AGE(cnt) \
304 ((struct mlx5_age_param *)((cnt) + 1))
306 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET
307 * defines. The pool size is 512, pool index should never reach
310 #define POOL_IDX_INVALID UINT16_MAX
314 AGE_FREE, /* Initialized state. */
315 AGE_CANDIDATE, /* Counter assigned to flows. */
316 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */
319 enum mlx5_counter_type {
320 MLX5_COUNTER_TYPE_ORIGIN,
321 MLX5_COUNTER_TYPE_AGE,
322 MLX5_COUNTER_TYPE_MAX,
325 /* Counter age parameter. */
326 struct mlx5_age_param {
327 uint16_t state; /**< Age state (atomically accessed). */
328 uint16_t port_id; /**< Port id of the counter. */
329 uint32_t timeout:24; /**< Aging timeout in seconds. */
330 uint32_t sec_since_last_hit;
331 /**< Time in seconds since last hit (atomically accessed). */
332 void *context; /**< Flow counter age context. */
335 struct flow_counter_stats {
340 /* Shared counters information for counters. */
341 struct mlx5_flow_counter_shared {
342 uint32_t id; /**< User counter ID. */
345 /* Shared counter configuration. */
346 struct mlx5_shared_counter_conf {
347 struct rte_eth_dev *dev; /* The device shared counter belongs to. */
348 uint32_t id; /* The shared counter ID. */
351 struct mlx5_flow_counter_pool;
352 /* Generic counters information. */
353 struct mlx5_flow_counter {
356 * User-defined counter shared info is only used during
357 * counter active time. And aging counter sharing is not
358 * supported, so active shared counter will not be chained
359 * to the aging list. For shared counter, only when it is
360 * released, the TAILQ entry memory will be used, at that
361 * time, shared memory is not used anymore.
363 * Similarly to none-batch counter dcs, since it doesn't
364 * support aging, while counter is allocated, the entry
365 * memory is not used anymore. In this case, as bytes
366 * memory is used only when counter is allocated, and
367 * entry memory is used only when counter is free. The
368 * dcs pointer can be saved to these two different place
369 * at different stage. It will eliminate the individual
370 * counter extend struct.
372 TAILQ_ENTRY(mlx5_flow_counter) next;
373 /**< Pointer to the next flow counter structure. */
375 struct mlx5_flow_counter_shared shared_info;
376 /**< Shared counter information. */
377 void *dcs_when_active;
379 * For non-batch mode, the dcs will be saved
380 * here when the counter is free.
385 uint64_t hits; /**< Reset value of hits packets. */
386 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */
389 uint64_t bytes; /**< Reset value of bytes. */
392 * For non-batch mode, the dcs will be saved here
393 * when the counter is free.
396 void *action; /**< Pointer to the dv action. */
399 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
401 /* Generic counter pool structure - query is in pool resolution. */
402 struct mlx5_flow_counter_pool {
403 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
404 struct mlx5_counters counters[2]; /* Free counter list. */
406 struct mlx5_devx_obj *min_dcs;
407 rte_atomic64_t a64_dcs;
409 /* The devx object of the minimum counter ID. */
410 uint64_t time_of_last_age_check;
411 /* System time (from rte_rdtsc()) read in the last aging check. */
412 uint32_t index:30; /* Pool index in container. */
413 uint32_t is_aged:1; /* Pool with aging counter. */
414 volatile uint32_t query_gen:1; /* Query round. */
415 rte_spinlock_t sl; /* The pool lock. */
416 rte_spinlock_t csl; /* The pool counter free list lock. */
417 struct mlx5_counter_stats_raw *raw;
418 struct mlx5_counter_stats_raw *raw_hw;
419 /* The raw on HW working. */
422 /* Memory management structure for group of counter statistics raws. */
423 struct mlx5_counter_stats_mem_mng {
424 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
425 struct mlx5_counter_stats_raw *raws;
426 struct mlx5_devx_obj *dm;
430 /* Raw memory structure for the counter statistics values of a pool. */
431 struct mlx5_counter_stats_raw {
432 LIST_ENTRY(mlx5_counter_stats_raw) next;
433 struct mlx5_counter_stats_mem_mng *mem_mng;
434 volatile struct flow_counter_stats *data;
437 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
439 /* Counter global management structure. */
440 struct mlx5_flow_counter_mng {
441 volatile uint16_t n_valid; /* Number of valid pools. */
442 uint16_t n; /* Number of pools. */
443 uint16_t last_pool_idx; /* Last used pool index */
444 int min_id; /* The minimum counter ID in the pools. */
445 int max_id; /* The maximum counter ID in the pools. */
446 rte_spinlock_t pool_update_sl; /* The pool update lock. */
447 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX];
448 /* The counter free list lock. */
449 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX];
450 /* Free counter list. */
451 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
452 struct mlx5_counter_stats_mem_mng *mem_mng;
453 /* Hold the memory management for the next allocated pools raws. */
454 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
455 uint8_t pending_queries;
457 uint8_t query_thread_on;
458 bool relaxed_ordering;
459 bool counter_fallback; /* Use counter fallback management. */
460 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
461 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
464 /* Default miss action resource structure. */
465 struct mlx5_flow_default_miss_resource {
466 void *action; /* Pointer to the rdma-core action. */
467 rte_atomic32_t refcnt; /* Default miss action reference counter. */
470 #define MLX5_AGE_EVENT_NEW 1
471 #define MLX5_AGE_TRIGGER 2
472 #define MLX5_AGE_SET(age_info, BIT) \
473 ((age_info)->flags |= (1 << (BIT)))
474 #define MLX5_AGE_GET(age_info, BIT) \
475 ((age_info)->flags & (1 << (BIT)))
476 #define GET_PORT_AGE_INFO(priv) \
477 (&((priv)->sh->port[(priv)->dev_port - 1].age_info))
478 /* Current time in seconds. */
479 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz())
481 /* Aging information for per port. */
482 struct mlx5_age_info {
483 uint8_t flags; /* Indicate if is new event or need to be triggered. */
484 struct mlx5_counters aged_counters; /* Aged flow counter list. */
485 rte_spinlock_t aged_sl; /* Aged flow counter list lock. */
488 /* Per port data of shared IB device. */
489 struct mlx5_dev_shared_port {
491 uint32_t devx_ih_port_id;
493 * Interrupt handler port_id. Used by shared interrupt
494 * handler to find the corresponding rte_eth device
495 * by IB port index. If value is equal or greater
496 * RTE_MAX_ETHPORTS it means there is no subhandler
497 * installed for specified IB port index.
499 struct mlx5_age_info age_info;
500 /* Aging information for per port. */
503 /* Table key of the hash organization. */
504 union mlx5_flow_tbl_key {
506 /* Table ID should be at the lowest address. */
507 uint32_t table_id; /**< ID of the table. */
508 uint16_t reserved; /**< must be zero for comparison. */
509 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */
510 uint8_t direction; /**< 1 - egress, 0 - ingress. */
512 uint64_t v64; /**< full 64bits value of key */
515 /* Table structure. */
516 struct mlx5_flow_tbl_resource {
517 void *obj; /**< Pointer to DR table object. */
518 rte_atomic32_t refcnt; /**< Reference counter. */
521 #define MLX5_MAX_TABLES UINT16_MAX
522 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
523 /* Reserve the last two tables for metadata register copy. */
524 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
525 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
526 /* Tables for metering splits should be added here. */
527 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3)
528 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 4)
529 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (MLX5_MAX_TABLES - 3)
530 #define MLX5_MAX_TABLES_FDB UINT16_MAX
531 #define MLX5_FLOW_TABLE_FACTOR 10
533 /* ID generation structure. */
534 struct mlx5_flow_id_pool {
535 uint32_t *free_arr; /**< Pointer to the a array of free values. */
537 /**< The next index that can be used without any free elements. */
538 uint32_t *curr; /**< Pointer to the index to pop. */
539 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
540 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
543 /* Tx pacing queue structure - for Clock and Rearm queues. */
544 struct mlx5_txpp_wq {
545 /* Completion Queue related data.*/
546 struct mlx5_devx_obj *cq;
549 volatile void *cq_buf;
550 volatile struct mlx5_cqe *cqes;
552 volatile uint32_t *cq_dbrec;
555 /* Send Queue related data.*/
556 struct mlx5_devx_obj *sq;
559 volatile void *sq_buf;
560 volatile struct mlx5_wqe *wqes;
562 uint16_t sq_size; /* Number of WQEs in the queue. */
563 uint16_t sq_ci; /* Next WQE to execute. */
564 volatile uint32_t *sq_dbrec;
567 /* Tx packet pacing internal timestamp. */
568 struct mlx5_txpp_ts {
569 rte_atomic64_t ci_ts;
573 /* Tx packet pacing structure. */
574 struct mlx5_dev_txpp {
575 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */
576 uint32_t refcnt; /* Pacing reference counter. */
577 uint32_t freq; /* Timestamp frequency, Hz. */
578 uint32_t tick; /* Completion tick duration in nanoseconds. */
579 uint32_t test; /* Packet pacing test mode. */
580 int32_t skew; /* Scheduling skew. */
581 struct rte_intr_handle intr_handle; /* Periodic interrupt. */
582 void *echan; /* Event Channel. */
583 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */
584 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */
585 void *pp; /* Packet pacing context. */
586 uint16_t pp_id; /* Packet pacing context index. */
587 uint16_t ts_n; /* Number of captured timestamps. */
588 uint16_t ts_p; /* Pointer to statisticks timestamp. */
589 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */
590 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */
591 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */
592 /* Statistics counters. */
593 rte_atomic32_t err_miss_int; /* Missed service interrupt. */
594 rte_atomic32_t err_rearm_queue; /* Rearm Queue errors. */
595 rte_atomic32_t err_clock_queue; /* Clock Queue errors. */
596 rte_atomic32_t err_ts_past; /* Timestamp in the past. */
597 rte_atomic32_t err_ts_future; /* Timestamp in the distant future. */
600 /* Supported flex parser profile ID. */
601 enum mlx5_flex_parser_profile_id {
602 MLX5_FLEX_PARSER_ECPRI_0 = 0,
603 MLX5_FLEX_PARSER_MAX = 8,
606 /* Sample ID information of flex parser structure. */
607 struct mlx5_flex_parser_profiles {
608 uint32_t num; /* Actual number of samples. */
609 uint32_t ids[8]; /* Sample IDs for this profile. */
610 uint8_t offset[8]; /* Bytes offset of each parser. */
611 void *obj; /* Flex parser node object. */
615 * Shared Infiniband device context for Master/Representors
616 * which belong to same IB device with multiple IB ports.
618 struct mlx5_dev_ctx_shared {
619 LIST_ENTRY(mlx5_dev_ctx_shared) next;
621 uint32_t devx:1; /* Opened with DV. */
622 uint32_t eqn; /* Event Queue number. */
623 uint32_t max_port; /* Maximal IB device port index. */
624 void *ctx; /* Verbs/DV/DevX context. */
625 void *pd; /* Protection Domain. */
626 uint32_t pdn; /* Protection Domain number. */
627 uint32_t tdn; /* Transport Domain number. */
628 char ibdev_name[DEV_SYSFS_NAME_MAX]; /* SYSFS dev name. */
629 char ibdev_path[DEV_SYSFS_PATH_MAX]; /* SYSFS dev path for secondary */
630 struct mlx5_dev_attr device_attr; /* Device properties. */
631 int numa_node; /* Numa node of backing physical device. */
632 LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb;
633 /**< Called by memory event callback. */
634 struct mlx5_mr_share_cache share_cache;
635 /* Packet pacing related structure. */
636 struct mlx5_dev_txpp txpp;
637 /* Shared DV/DR flow data section. */
638 pthread_mutex_t dv_mutex; /* DV context mutex. */
639 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
640 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
641 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
642 void *fdb_domain; /* FDB Direct Rules name space handle. */
643 void *rx_domain; /* RX Direct Rules name space handle. */
644 void *tx_domain; /* TX Direct Rules name space handle. */
646 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
647 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
648 /* UAR same-page access control required in 32bit implementations. */
650 struct mlx5_hlist *flow_tbls;
651 struct mlx5_flow_tunnel_hub *tunnel_hub;
652 /* Direct Rules tables for FDB, NIC TX+RX */
653 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
654 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
655 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */
656 struct mlx5_hlist *modify_cmds;
657 struct mlx5_hlist *tag_table;
658 uint32_t port_id_action_list; /* List of port ID actions. */
659 uint32_t push_vlan_action_list; /* List of push VLAN actions. */
660 uint32_t sample_action_list; /* List of sample actions. */
661 uint32_t dest_array_list; /* List of destination array actions. */
662 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
663 struct mlx5_flow_default_miss_resource default_miss;
664 /* Default miss action resource structure. */
665 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
666 /* Memory Pool for mlx5 flow resources. */
667 struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */
668 /* Shared interrupt handler section. */
669 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
670 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
671 void *devx_comp; /* DEVX async comp obj. */
672 struct mlx5_devx_obj *tis; /* TIS object. */
673 struct mlx5_devx_obj *td; /* Transport domain. */
674 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
675 void *tx_uar; /* Tx/packet pacing shared UAR. */
676 struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX];
677 /* Flex parser profiles information. */
678 void *devx_rx_uar; /* DevX UAR for Rx. */
679 struct mlx5_dev_shared_port port[]; /* per device port data array. */
682 /* Per-process private structure. */
683 struct mlx5_proc_priv {
685 /* Size of UAR register table. */
687 /* Table of UAR registers for each process. */
690 /* MTR profile list. */
691 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
693 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter);
695 #define MLX5_PROC_PRIV(port_id) \
696 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
698 /* Verbs/DevX Rx queue elements. */
699 struct mlx5_rxq_obj {
700 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
701 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
702 int fd; /* File descriptor for event channel */
706 void *wq; /* Work Queue. */
707 void *ibv_cq; /* Completion Queue. */
711 struct mlx5_devx_obj *rq; /* DevX Rx Queue object. */
712 struct mlx5_devx_obj *devx_cq; /* DevX CQ object. */
718 /* Indirection table. */
719 struct mlx5_ind_table_obj {
720 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
721 rte_atomic32_t refcnt; /* Reference counter. */
724 void *ind_table; /**< Indirection table. */
725 struct mlx5_devx_obj *rqt; /* DevX RQT object. */
727 uint32_t queues_n; /**< Number of queues in the list. */
728 uint16_t queues[]; /**< Queue list. */
734 ILIST_ENTRY(uint32_t)next; /* Index to the next element. */
735 rte_atomic32_t refcnt; /* Reference counter. */
736 uint32_t shared:1; /* This object used in shared action. */
737 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
740 void *qp; /* Verbs queue pair. */
741 struct mlx5_devx_obj *tir; /* DevX TIR object. */
743 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
744 void *action; /* DV QP action pointer. */
746 uint64_t hash_fields; /* Verbs Hash fields. */
747 uint32_t rss_key_len; /* Hash key length in bytes. */
748 uint8_t rss_key[]; /* Hash key. */
751 /* Verbs/DevX Tx queue elements. */
752 struct mlx5_txq_obj {
753 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */
754 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
758 void *cq; /* Completion Queue. */
759 void *qp; /* Queue Pair. */
762 struct mlx5_devx_obj *sq;
763 /* DevX object for Sx queue. */
764 struct mlx5_devx_obj *tis; /* The TIS object. */
767 struct rte_eth_dev *dev;
768 struct mlx5_devx_obj *cq_devx;
771 int64_t cq_dbrec_offset;
772 struct mlx5_devx_dbr_page *cq_dbrec_page;
773 struct mlx5_devx_obj *sq_devx;
776 int64_t sq_dbrec_offset;
777 struct mlx5_devx_dbr_page *sq_dbrec_page;
782 enum mlx5_rxq_modify_type {
783 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */
784 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */
785 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */
786 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */
789 enum mlx5_txq_modify_type {
790 MLX5_TXQ_MOD_RDY2RDY, /* modify state from ready to ready. */
791 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */
792 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */
793 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */
796 /* HW objects operations structure. */
797 struct mlx5_obj_ops {
798 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on);
799 int (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
800 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj);
801 int (*rxq_obj_modify)(struct mlx5_rxq_obj *rxq_obj, uint8_t type);
802 void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj);
803 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n,
804 struct mlx5_ind_table_obj *ind_tbl);
805 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl);
806 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
807 int tunnel __rte_unused);
808 int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
809 const uint8_t *rss_key,
810 uint64_t hash_fields,
811 const struct mlx5_ind_table_obj *ind_tbl);
812 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq);
813 int (*drop_action_create)(struct rte_eth_dev *dev);
814 void (*drop_action_destroy)(struct rte_eth_dev *dev);
815 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
816 int (*txq_obj_modify)(struct mlx5_txq_obj *obj,
817 enum mlx5_txq_modify_type type, uint8_t dev_port);
818 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj);
822 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
823 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */
824 uint32_t dev_port; /* Device port number. */
825 struct rte_pci_device *pci_dev; /* Backend PCI device. */
826 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
827 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
828 /* Bit-field of MAC addresses owned by the PMD. */
829 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
830 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
831 /* Device properties. */
832 uint16_t mtu; /* Configured MTU. */
833 unsigned int isolated:1; /* Whether isolated mode is enabled. */
834 unsigned int representor:1; /* Device is a port representor. */
835 unsigned int master:1; /* Device is a E-Switch master. */
836 unsigned int txpp_en:1; /* Tx packet pacing enabled. */
837 unsigned int mtr_en:1; /* Whether support meter. */
838 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
839 unsigned int sampler_en:1; /* Whether support sampler. */
840 uint16_t domain_id; /* Switch domain identifier. */
841 uint16_t vport_id; /* Associated VF vport index (if any). */
842 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
843 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
844 int32_t representor_id; /* Port representor identifier. */
845 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
846 unsigned int if_index; /* Associated kernel network device index. */
847 uint32_t bond_ifindex; /**< Bond interface index. */
848 char bond_name[IF_NAMESIZE]; /**< Bond interface name. */
850 unsigned int rxqs_n; /* RX queues array size. */
851 unsigned int txqs_n; /* TX queues array size. */
852 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
853 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
854 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
855 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
856 unsigned int (*reta_idx)[]; /* RETA index table. */
857 unsigned int reta_idx_n; /* RETA index size. */
858 struct mlx5_drop drop_queue; /* Flow drop queues. */
859 uint32_t flows; /* RTE Flow rules. */
860 uint32_t ctrl_flows; /* Control flow rules. */
861 void *inter_flows; /* Intermediate resources for flow creation. */
862 void *rss_desc; /* Intermediate rss description resources. */
863 int flow_idx; /* Intermediate device flow index. */
864 int flow_nested_idx; /* Intermediate device flow index, nested. */
865 struct mlx5_obj_ops obj_ops; /* HW objects operations. */
866 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
867 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
868 uint32_t hrxqs; /* Verbs Hash Rx queues. */
869 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
870 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
871 /* Indirection tables. */
872 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
873 /* Pointer to next element. */
874 rte_atomic32_t refcnt; /**< Reference counter. */
875 /**< Verbs modify header action object. */
876 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
877 uint8_t max_lro_msg_size;
878 /* Tags resources cache. */
879 uint32_t link_speed_capa; /* Link speed capabilities. */
880 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
881 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
882 struct mlx5_dev_config config; /* Device configuration. */
883 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
884 /* Context for Verbs allocator. */
885 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
886 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
887 struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */
888 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
889 struct mlx5_flow_id_pool *qrss_id_pool;
890 struct mlx5_hlist *mreg_cp_tbl;
891 /* Hash table of Rx metadata register copy table. */
892 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
893 uint8_t mtr_color_reg; /* Meter color match REG_C. */
894 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
895 struct mlx5_flow_meters flow_meters; /* MTR list. */
896 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
897 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
898 struct mlx5_mp_id mp_id; /* ID of a multi-process process */
899 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */
900 LIST_HEAD(shared_action, rte_flow_shared_action) shared_actions;
904 #define PORT_ID(priv) ((priv)->dev_data->port_id)
905 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
909 int mlx5_getenv_int(const char *);
910 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
911 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
912 struct rte_eth_udp_tunnel *udp_tunnel);
913 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
914 int mlx5_dev_close(struct rte_eth_dev *dev);
916 /* Macro to iterate over all valid ports for mlx5 driver. */
917 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
918 for (port_id = mlx5_eth_find_next(0, pci_dev); \
919 port_id < RTE_MAX_ETHPORTS; \
920 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
921 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs);
922 struct mlx5_dev_ctx_shared *
923 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
924 const struct mlx5_dev_config *config);
925 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh);
926 void mlx5_free_table_hash_list(struct mlx5_priv *priv);
927 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv);
928 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
929 struct mlx5_dev_config *config);
930 void mlx5_set_metadata_mask(struct rte_eth_dev *dev);
931 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
932 struct mlx5_dev_config *config);
933 int mlx5_dev_configure(struct rte_eth_dev *dev);
934 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
935 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
936 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
937 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
938 struct rte_eth_hairpin_cap *cap);
939 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev);
940 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);
944 int mlx5_dev_configure(struct rte_eth_dev *dev);
945 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver,
947 int mlx5_dev_infos_get(struct rte_eth_dev *dev,
948 struct rte_eth_dev_info *info);
949 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
950 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
951 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
952 struct rte_eth_hairpin_cap *cap);
953 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
954 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
955 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
956 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
958 /* mlx5_ethdev_os.c */
960 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
961 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
962 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
963 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
964 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
965 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
966 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
967 struct rte_eth_fc_conf *fc_conf);
968 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
969 struct rte_eth_fc_conf *fc_conf);
970 void mlx5_dev_interrupt_handler(void *arg);
971 void mlx5_dev_interrupt_handler_devx(void *arg);
972 int mlx5_set_link_down(struct rte_eth_dev *dev);
973 int mlx5_set_link_up(struct rte_eth_dev *dev);
974 int mlx5_is_removed(struct rte_eth_dev *dev);
975 int mlx5_sysfs_switch_info(unsigned int ifindex,
976 struct mlx5_switch_info *info);
977 void mlx5_translate_port_name(const char *port_name_in,
978 struct mlx5_switch_info *port_info_out);
979 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
980 rte_intr_callback_fn cb_fn, void *cb_arg);
981 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex,
983 int mlx5_get_module_info(struct rte_eth_dev *dev,
984 struct rte_eth_dev_module_info *modinfo);
985 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
986 struct rte_dev_eeprom_info *info);
987 int mlx5_os_read_dev_stat(struct mlx5_priv *priv,
988 const char *ctr_name, uint64_t *stat);
989 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats);
990 int mlx5_os_get_stats_n(struct rte_eth_dev *dev);
991 void mlx5_os_stats_init(struct rte_eth_dev *dev);
995 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
996 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
997 uint32_t index, uint32_t vmdq);
998 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
999 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
1000 struct rte_ether_addr *mc_addr_set,
1001 uint32_t nb_mc_addr);
1005 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
1006 struct rte_eth_rss_conf *rss_conf);
1007 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
1008 struct rte_eth_rss_conf *rss_conf);
1009 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
1010 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
1011 struct rte_eth_rss_reta_entry64 *reta_conf,
1012 uint16_t reta_size);
1013 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
1014 struct rte_eth_rss_reta_entry64 *reta_conf,
1015 uint16_t reta_size);
1019 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
1020 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
1021 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
1022 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
1026 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
1027 int mlx5_stats_reset(struct rte_eth_dev *dev);
1028 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
1030 int mlx5_xstats_reset(struct rte_eth_dev *dev);
1031 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1032 struct rte_eth_xstat_name *xstats_names,
1037 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
1038 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
1039 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
1041 /* mlx5_vlan_os.c */
1043 void mlx5_vlan_vmwa_exit(void *ctx);
1044 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
1045 struct mlx5_vf_vlan *vf_vlan);
1046 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
1047 struct mlx5_vf_vlan *vf_vlan);
1048 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex);
1050 /* mlx5_trigger.c */
1052 int mlx5_dev_start(struct rte_eth_dev *dev);
1053 int mlx5_dev_stop(struct rte_eth_dev *dev);
1054 int mlx5_traffic_enable(struct rte_eth_dev *dev);
1055 void mlx5_traffic_disable(struct rte_eth_dev *dev);
1056 int mlx5_traffic_restart(struct rte_eth_dev *dev);
1060 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
1061 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
1062 void mlx5_flow_print(struct rte_flow *flow);
1063 int mlx5_flow_validate(struct rte_eth_dev *dev,
1064 const struct rte_flow_attr *attr,
1065 const struct rte_flow_item items[],
1066 const struct rte_flow_action actions[],
1067 struct rte_flow_error *error);
1068 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
1069 const struct rte_flow_attr *attr,
1070 const struct rte_flow_item items[],
1071 const struct rte_flow_action actions[],
1072 struct rte_flow_error *error);
1073 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
1074 struct rte_flow_error *error);
1075 void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active);
1076 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
1077 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
1078 const struct rte_flow_action *action, void *data,
1079 struct rte_flow_error *error);
1080 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
1081 struct rte_flow_error *error);
1082 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
1083 enum rte_filter_type filter_type,
1084 enum rte_filter_op filter_op,
1086 int mlx5_flow_start(struct rte_eth_dev *dev, uint32_t *list);
1087 void mlx5_flow_stop(struct rte_eth_dev *dev, uint32_t *list);
1088 int mlx5_flow_start_default(struct rte_eth_dev *dev);
1089 void mlx5_flow_stop_default(struct rte_eth_dev *dev);
1090 void mlx5_flow_alloc_intermediate(struct rte_eth_dev *dev);
1091 void mlx5_flow_free_intermediate(struct rte_eth_dev *dev);
1092 int mlx5_flow_verify(struct rte_eth_dev *dev);
1093 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
1094 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
1095 struct rte_flow_item_eth *eth_spec,
1096 struct rte_flow_item_eth *eth_mask,
1097 struct rte_flow_item_vlan *vlan_spec,
1098 struct rte_flow_item_vlan *vlan_mask);
1099 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
1100 struct rte_flow_item_eth *eth_spec,
1101 struct rte_flow_item_eth *eth_mask);
1102 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev);
1103 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
1104 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
1105 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
1106 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,
1107 uint64_t async_id, int status);
1108 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh);
1109 void mlx5_flow_query_alarm(void *arg);
1110 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
1111 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
1112 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
1113 bool clear, uint64_t *pkts, uint64_t *bytes);
1114 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file,
1115 struct rte_flow_error *error);
1116 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev);
1117 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
1118 uint32_t nb_contexts, struct rte_flow_error *error);
1122 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg,
1124 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg,
1126 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev);
1127 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev);
1128 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id,
1129 enum mlx5_mp_req_type req_type);
1133 int mlx5_pmd_socket_init(void);
1135 /* mlx5_flow_meter.c */
1137 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
1138 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv,
1140 struct mlx5_flow_meter *mlx5_flow_meter_attach
1141 (struct mlx5_priv *priv,
1143 const struct rte_flow_attr *attr,
1144 struct rte_flow_error *error);
1145 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm);
1148 struct rte_pci_driver;
1149 int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr);
1150 void mlx5_os_free_shared_dr(struct mlx5_priv *priv);
1151 int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,
1152 const struct mlx5_dev_config *config,
1153 struct mlx5_dev_ctx_shared *sh);
1154 int mlx5_os_get_pdn(void *pd, uint32_t *pdn);
1155 int mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1156 struct rte_pci_device *pci_dev);
1157 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh);
1158 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh);
1159 void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,
1160 mlx5_dereg_mr_t *dereg_mr_cb);
1161 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
1162 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
1164 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx,
1165 struct rte_ether_addr *mac_addr,
1167 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable);
1168 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable);
1169 int mlx5_os_set_nonblock_channel_fd(int fd);
1170 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev);
1174 int mlx5_txpp_start(struct rte_eth_dev *dev);
1175 void mlx5_txpp_stop(struct rte_eth_dev *dev);
1176 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp);
1177 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev,
1178 struct rte_eth_xstat *stats,
1179 unsigned int n, unsigned int n_used);
1180 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev);
1181 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev,
1182 struct rte_eth_xstat_name *xstats_names,
1183 unsigned int n, unsigned int n_used);
1184 void mlx5_txpp_interrupt_handler(void *cb_arg);
1188 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
1190 #endif /* RTE_PMD_MLX5_H_ */