1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_DEFS_H_
7 #define RTE_PMD_MLX5_DEFS_H_
9 #include <rte_ethdev_driver.h>
10 #include <rte_vxlan.h>
12 #include "mlx5_autoconf.h"
14 /* Reported driver name. */
15 #define MLX5_DRIVER_NAME "net_mlx5"
17 /* Maximum number of simultaneous unicast MAC addresses. */
18 #define MLX5_MAX_UC_MAC_ADDRESSES 128
19 /* Maximum number of simultaneous Multicast MAC addresses. */
20 #define MLX5_MAX_MC_MAC_ADDRESSES 128
21 /* Maximum number of simultaneous MAC addresses. */
22 #define MLX5_MAX_MAC_ADDRESSES \
23 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES)
25 /* Maximum number of simultaneous VLAN filters. */
26 #define MLX5_MAX_VLAN_IDS 128
29 * Request TX completion every time descriptors reach this threshold since
30 * the previous request. Must be a power of two for performance reasons.
32 #define MLX5_TX_COMP_THRESH 32u
35 * Request TX completion every time the total number of WQEBBs used for inlining
36 * packets exceeds the size of WQ divided by this divisor. Better to be power of
37 * two for performance.
39 #define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3)
42 * Maximal amount of normal completion CQEs
43 * processed in one call of tx_burst() routine.
45 #define MLX5_TX_COMP_MAX_CQE 2u
48 /* Size of per-queue MR cache array for linear search. */
49 #define MLX5_MR_CACHE_N 8
51 /* Size of MR cache table for binary search. */
52 #define MLX5_MR_BTREE_CACHE_N 256
55 * If defined, only use software counters. The PMD will never ask the hardware
56 * for these, and many of them won't be available.
58 #ifndef MLX5_PMD_SOFT_COUNTERS
59 #define MLX5_PMD_SOFT_COUNTERS 1
62 /* Switch port ID parameters for bonding configurations. */
63 #define MLX5_PORT_ID_BONDING_PF_MASK 0xf
64 #define MLX5_PORT_ID_BONDING_PF_SHIFT 0xf
67 #define MLX5_ALARM_TIMEOUT_US 100000
69 /* Maximum number of extended statistics counters. */
70 #define MLX5_MAX_XSTATS 32
72 /* Maximum Packet headers size (L2+L3+L4) for TSO. */
73 #define MLX5_MAX_TSO_HEADER (128u + 34u)
75 /* Inline data size required by NICs. */
76 #define MLX5_INLINE_HSIZE_NONE 0
77 #define MLX5_INLINE_HSIZE_L2 (sizeof(struct rte_ether_hdr) + \
78 sizeof(struct rte_vlan_hdr))
79 #define MLX5_INLINE_HSIZE_L3 (MLX5_INLINE_HSIZE_L2 + \
80 sizeof(struct rte_ipv6_hdr))
81 #define MLX5_INLINE_HSIZE_L4 (MLX5_INLINE_HSIZE_L3 + \
82 sizeof(struct rte_tcp_hdr))
83 #define MLX5_INLINE_HSIZE_INNER_L2 (MLX5_INLINE_HSIZE_L3 + \
84 sizeof(struct rte_udp_hdr) + \
85 sizeof(struct rte_vxlan_hdr) + \
86 sizeof(struct rte_ether_hdr) + \
87 sizeof(struct rte_vlan_hdr))
88 #define MLX5_INLINE_HSIZE_INNER_L3 (MLX5_INLINE_HSIZE_INNER_L2 + \
89 sizeof(struct rte_ipv6_hdr))
90 #define MLX5_INLINE_HSIZE_INNER_L4 (MLX5_INLINE_HSIZE_INNER_L3 + \
91 sizeof(struct rte_tcp_hdr))
93 /* Threshold of buffer replenishment for vectorized Rx. */
94 #define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \
95 (RTE_MIN(MLX5_VPMD_RX_MAX_BURST, (unsigned int)(n) >> 2))
97 /* Maximum size of burst for vectorized Rx. */
98 #define MLX5_VPMD_RX_MAX_BURST 64U
100 /* Recommended optimal burst size. */
101 #define MLX5_RX_DEFAULT_BURST 64U
102 #define MLX5_TX_DEFAULT_BURST 64U
104 /* Number of packets vectorized Rx can simultaneously process in a loop. */
105 #define MLX5_VPMD_DESCS_PER_LOOP 4
107 /* Mask of RSS on source only or destination only. */
108 #define MLX5_RSS_SRC_DST_ONLY (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | \
109 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY)
112 #define MLX5_RSS_HF_MASK (~(ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \
113 MLX5_RSS_SRC_DST_ONLY))
115 /* Timeout in seconds to get a valid link status. */
116 #define MLX5_LINK_STATUS_TIMEOUT 10
118 /* Number of times to retry retrieving the physical link information. */
119 #define MLX5_GET_LINK_STATUS_RETRY_COUNT 3
121 /* Maximum number of UAR pages used by a port,
122 * These are the size and mask for an array of mutexes used to synchronize
123 * the access to port's UARs on platforms that do not support 64 bit writes.
124 * In such systems it is possible to issue the 64 bits DoorBells through two
125 * consecutive writes, each write 32 bits. The access to a UAR page (which can
126 * be accessible by all threads in the process) must be synchronized
127 * (for example, using a semaphore). Such a synchronization is not required
128 * when ringing DoorBells on different UAR pages.
129 * A port with 512 Tx queues uses 8, 4kBytes, UAR pages which are shared
132 #define MLX5_UAR_PAGE_NUM_MAX 64
133 #define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1)
135 /* Fields of memory mapping type in offset parameter of mmap() */
136 #define MLX5_UAR_MMAP_CMD_SHIFT 8
137 #define MLX5_UAR_MMAP_CMD_MASK 0xff
139 /* Environment variable to control the doorbell register mapping. */
140 #define MLX5_SHUT_UP_BF "MLX5_SHUT_UP_BF"
141 #if defined(RTE_ARCH_ARM64)
142 #define MLX5_SHUT_UP_BF_DEFAULT "0"
144 #define MLX5_SHUT_UP_BF_DEFAULT "1"
147 #ifndef HAVE_MLX5DV_MMAP_GET_NC_PAGES_CMD
148 #define MLX5_MMAP_GET_NC_PAGES_CMD 3
151 /* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */
152 #define MLX5_MPRQ_STRIDE_NUM_N 6U
154 /* Two-byte shift is disabled for Multi-Packet RQ. */
155 #define MLX5_MPRQ_TWO_BYTE_SHIFT 0
158 * Minimum size of packet to be memcpy'd instead of being attached as an
161 #define MLX5_MPRQ_MEMCPY_DEFAULT_LEN 128
163 /* Minimum number Rx queues to enable Multi-Packet RQ. */
164 #define MLX5_MPRQ_MIN_RXQS 12
166 /* Cache size of mempool for Multi-Packet RQ. */
167 #define MLX5_MPRQ_MP_CACHE_SZ 32U
169 /* MLX5_DV_XMETA_EN supported values. */
170 #define MLX5_XMETA_MODE_LEGACY 0
171 #define MLX5_XMETA_MODE_META16 1
172 #define MLX5_XMETA_MODE_META32 2
174 /* MLX5_TX_DB_NC supported values. */
175 #define MLX5_TXDB_CACHED 0
176 #define MLX5_TXDB_NCACHED 1
177 #define MLX5_TXDB_HEURISTIC 2
179 /* Size of the simple hash table for metadata register table. */
180 #define MLX5_FLOW_MREG_HTABLE_SZ 4096
181 #define MLX5_FLOW_MREG_HNAME "MARK_COPY_TABLE"
182 #define MLX5_DEFAULT_COPY_ID UINT32_MAX
184 /* Definition of static_assert found in /usr/include/assert.h */
185 #ifndef HAVE_STATIC_ASSERT
186 #define static_assert _Static_assert
189 #endif /* RTE_PMD_MLX5_DEFS_H_ */