1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
11 #include <rte_mempool.h>
12 #include <rte_prefetch.h>
13 #include <rte_common.h>
14 #include <rte_branch_prediction.h>
15 #include <rte_ether.h>
16 #include <rte_cycles.h>
20 #include <mlx5_common.h>
22 #include "mlx5_autoconf.h"
23 #include "mlx5_defs.h"
26 #include "mlx5_utils.h"
27 #include "mlx5_rxtx.h"
29 /* TX burst subroutines return codes. */
30 enum mlx5_txcmp_code {
31 MLX5_TXCMP_CODE_EXIT = 0,
32 MLX5_TXCMP_CODE_ERROR,
33 MLX5_TXCMP_CODE_SINGLE,
34 MLX5_TXCMP_CODE_MULTI,
40 * These defines are used to configure Tx burst routine option set
41 * supported at compile time. The not specified options are optimized out
42 * out due to if conditions can be explicitly calculated at compile time.
43 * The offloads with bigger runtime check (require more CPU cycles to
44 * skip) overhead should have the bigger index - this is needed to
45 * select the better matching routine function if no exact match and
46 * some offloads are not actually requested.
48 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
49 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
50 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
51 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
52 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
53 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
54 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
55 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
56 #define MLX5_TXOFF_CONFIG_MPW (1u << 9) /* Legacy MPW supported.*/
57 #define MLX5_TXOFF_CONFIG_TXPP (1u << 10) /* Scheduling on timestamp.*/
59 /* The most common offloads groups. */
60 #define MLX5_TXOFF_CONFIG_NONE 0
61 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
62 MLX5_TXOFF_CONFIG_TSO | \
63 MLX5_TXOFF_CONFIG_SWP | \
64 MLX5_TXOFF_CONFIG_CSUM | \
65 MLX5_TXOFF_CONFIG_INLINE | \
66 MLX5_TXOFF_CONFIG_VLAN | \
67 MLX5_TXOFF_CONFIG_METADATA)
69 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
71 #define MLX5_TXOFF_DECL(func, olx) \
72 static uint16_t mlx5_tx_burst_##func(void *txq, \
73 struct rte_mbuf **pkts, \
76 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
77 pkts, pkts_n, (olx)); \
80 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
82 static __rte_always_inline uint32_t
83 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
85 static __rte_always_inline int
86 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
87 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
89 static __rte_always_inline uint32_t
90 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
92 static __rte_always_inline void
93 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
94 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
97 mlx5_queue_state_modify(struct rte_eth_dev *dev,
98 struct mlx5_mp_arg_queue_state_modify *sm);
101 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *__rte_restrict tcp,
102 volatile struct mlx5_cqe *__rte_restrict cqe,
106 mlx5_lro_update_hdr(uint8_t *__rte_restrict padd,
107 volatile struct mlx5_cqe *__rte_restrict cqe,
110 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
111 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
114 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
115 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
117 uint64_t rte_net_mlx5_dynf_inline_mask;
118 #define PKT_TX_DYNF_NOINLINE rte_net_mlx5_dynf_inline_mask
121 * Build a table to translate Rx completion flags to packet type.
123 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
126 mlx5_set_ptype_table(void)
129 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
131 /* Last entry must not be overwritten, reserved for errored packet. */
132 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
133 (*p)[i] = RTE_PTYPE_UNKNOWN;
135 * The index to the array should have:
136 * bit[1:0] = l3_hdr_type
137 * bit[4:2] = l4_hdr_type
140 * bit[7] = outer_l3_type
143 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
145 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
146 RTE_PTYPE_L4_NONFRAG;
147 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
148 RTE_PTYPE_L4_NONFRAG;
150 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
152 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
155 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
157 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
159 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
161 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
163 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
165 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
168 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
170 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
172 /* Repeat with outer_l3_type being set. Just in case. */
173 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
174 RTE_PTYPE_L4_NONFRAG;
175 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
176 RTE_PTYPE_L4_NONFRAG;
177 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
179 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
181 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
183 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
185 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
187 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
189 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
191 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
193 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
195 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
198 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
199 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
200 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
201 RTE_PTYPE_INNER_L4_NONFRAG;
202 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
203 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
204 RTE_PTYPE_INNER_L4_NONFRAG;
205 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
206 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
207 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
208 RTE_PTYPE_INNER_L4_NONFRAG;
209 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
210 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L4_NONFRAG;
212 /* Tunneled - Fragmented */
213 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
215 RTE_PTYPE_INNER_L4_FRAG;
216 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
217 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
218 RTE_PTYPE_INNER_L4_FRAG;
219 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
220 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
221 RTE_PTYPE_INNER_L4_FRAG;
222 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
223 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
224 RTE_PTYPE_INNER_L4_FRAG;
226 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
227 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
228 RTE_PTYPE_INNER_L4_TCP;
229 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
230 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
231 RTE_PTYPE_INNER_L4_TCP;
232 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
233 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
234 RTE_PTYPE_INNER_L4_TCP;
235 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
236 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
237 RTE_PTYPE_INNER_L4_TCP;
238 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
239 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
240 RTE_PTYPE_INNER_L4_TCP;
241 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
242 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
243 RTE_PTYPE_INNER_L4_TCP;
244 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
245 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
246 RTE_PTYPE_INNER_L4_TCP;
247 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
248 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
249 RTE_PTYPE_INNER_L4_TCP;
250 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
251 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
252 RTE_PTYPE_INNER_L4_TCP;
253 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
254 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
255 RTE_PTYPE_INNER_L4_TCP;
256 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
257 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L4_TCP;
259 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
260 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
261 RTE_PTYPE_INNER_L4_TCP;
263 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
265 RTE_PTYPE_INNER_L4_UDP;
266 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
267 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
268 RTE_PTYPE_INNER_L4_UDP;
269 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
270 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
271 RTE_PTYPE_INNER_L4_UDP;
272 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
273 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
274 RTE_PTYPE_INNER_L4_UDP;
278 * Build a table to translate packet to checksum type of Verbs.
281 mlx5_set_cksum_table(void)
287 * The index should have:
288 * bit[0] = PKT_TX_TCP_SEG
289 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
290 * bit[4] = PKT_TX_IP_CKSUM
291 * bit[8] = PKT_TX_OUTER_IP_CKSUM
294 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
297 /* Tunneled packet. */
298 if (i & (1 << 8)) /* Outer IP. */
299 v |= MLX5_ETH_WQE_L3_CSUM;
300 if (i & (1 << 4)) /* Inner IP. */
301 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
302 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
303 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
306 if (i & (1 << 4)) /* IP. */
307 v |= MLX5_ETH_WQE_L3_CSUM;
308 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
309 v |= MLX5_ETH_WQE_L4_CSUM;
311 mlx5_cksum_table[i] = v;
316 * Build a table to translate packet type of mbuf to SWP type of Verbs.
319 mlx5_set_swp_types_table(void)
325 * The index should have:
326 * bit[0:1] = PKT_TX_L4_MASK
327 * bit[4] = PKT_TX_IPV6
328 * bit[8] = PKT_TX_OUTER_IPV6
329 * bit[9] = PKT_TX_OUTER_UDP
331 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
334 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
336 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
338 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
339 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
340 v |= MLX5_ETH_WQE_L4_INNER_UDP;
341 mlx5_swp_types_table[i] = v;
346 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
347 * Flags must be preliminary initialized to zero.
350 * Pointer to burst routine local context.
352 * Pointer to store Software Parser flags
354 * Configured Tx offloads mask. It is fully defined at
355 * compile time and may be used for optimization.
358 * Software Parser offsets packed in dword.
359 * Software Parser flags are set by pointer.
361 static __rte_always_inline uint32_t
362 txq_mbuf_to_swp(struct mlx5_txq_local *__rte_restrict loc,
367 unsigned int idx, off;
370 if (!MLX5_TXOFF_CONFIG(SWP))
372 ol = loc->mbuf->ol_flags;
373 tunnel = ol & PKT_TX_TUNNEL_MASK;
375 * Check whether Software Parser is required.
376 * Only customized tunnels may ask for.
378 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
381 * The index should have:
382 * bit[0:1] = PKT_TX_L4_MASK
383 * bit[4] = PKT_TX_IPV6
384 * bit[8] = PKT_TX_OUTER_IPV6
385 * bit[9] = PKT_TX_OUTER_UDP
387 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
388 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
389 *swp_flags = mlx5_swp_types_table[idx];
391 * Set offsets for SW parser. Since ConnectX-5, SW parser just
392 * complements HW parser. SW parser starts to engage only if HW parser
393 * can't reach a header. For the older devices, HW parser will not kick
394 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
395 * should be set regardless of HW offload.
397 off = loc->mbuf->outer_l2_len;
398 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
399 off += sizeof(struct rte_vlan_hdr);
400 set = (off >> 1) << 8; /* Outer L3 offset. */
401 off += loc->mbuf->outer_l3_len;
402 if (tunnel == PKT_TX_TUNNEL_UDP)
403 set |= off >> 1; /* Outer L4 offset. */
404 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
405 const uint64_t csum = ol & PKT_TX_L4_MASK;
406 off += loc->mbuf->l2_len;
407 set |= (off >> 1) << 24; /* Inner L3 offset. */
408 if (csum == PKT_TX_TCP_CKSUM ||
409 csum == PKT_TX_UDP_CKSUM ||
410 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
411 off += loc->mbuf->l3_len;
412 set |= (off >> 1) << 16; /* Inner L4 offset. */
415 set = rte_cpu_to_le_32(set);
420 * Convert the Checksum offloads to Verbs.
423 * Pointer to the mbuf.
426 * Converted checksum flags.
428 static __rte_always_inline uint8_t
429 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
432 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
433 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
434 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
437 * The index should have:
438 * bit[0] = PKT_TX_TCP_SEG
439 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
440 * bit[4] = PKT_TX_IP_CKSUM
441 * bit[8] = PKT_TX_OUTER_IP_CKSUM
444 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
445 return mlx5_cksum_table[idx];
449 * Internal function to compute the number of used descriptors in an RX queue
455 * The number of used rx descriptor.
458 rx_queue_count(struct mlx5_rxq_data *rxq)
460 struct rxq_zip *zip = &rxq->zip;
461 volatile struct mlx5_cqe *cqe;
462 unsigned int cq_ci = rxq->cq_ci;
463 const unsigned int cqe_n = (1 << rxq->cqe_n);
464 const unsigned int cqe_cnt = cqe_n - 1;
465 unsigned int used = 0;
467 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
468 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
472 op_own = cqe->op_own;
473 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
474 if (unlikely(zip->ai))
475 n = zip->cqe_cnt - zip->ai;
477 n = rte_be_to_cpu_32(cqe->byte_cnt);
482 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
484 used = RTE_MIN(used, cqe_n);
489 * DPDK callback to check the status of a rx descriptor.
494 * The index of the descriptor in the ring.
497 * The status of the tx descriptor.
500 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
502 struct mlx5_rxq_data *rxq = rx_queue;
503 struct mlx5_rxq_ctrl *rxq_ctrl =
504 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
505 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
507 if (dev->rx_pkt_burst == NULL ||
508 dev->rx_pkt_burst == removed_rx_burst) {
512 if (offset >= (1 << rxq->cqe_n)) {
516 if (offset < rx_queue_count(rxq))
517 return RTE_ETH_RX_DESC_DONE;
518 return RTE_ETH_RX_DESC_AVAIL;
522 * DPDK callback to get the RX queue information
525 * Pointer to the device structure.
528 * Rx queue identificator.
531 * Pointer to the RX queue information structure.
538 mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
539 struct rte_eth_rxq_info *qinfo)
541 struct mlx5_priv *priv = dev->data->dev_private;
542 struct mlx5_rxq_data *rxq = (*priv->rxqs)[rx_queue_id];
543 struct mlx5_rxq_ctrl *rxq_ctrl =
544 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
548 qinfo->mp = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
549 rxq->mprq_mp : rxq->mp;
550 qinfo->conf.rx_thresh.pthresh = 0;
551 qinfo->conf.rx_thresh.hthresh = 0;
552 qinfo->conf.rx_thresh.wthresh = 0;
553 qinfo->conf.rx_free_thresh = rxq->rq_repl_thresh;
554 qinfo->conf.rx_drop_en = 1;
555 qinfo->conf.rx_deferred_start = rxq_ctrl ? 0 : 1;
556 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
557 qinfo->scattered_rx = dev->data->scattered_rx;
558 qinfo->nb_desc = 1 << rxq->elts_n;
562 * DPDK callback to get the RX packet burst mode information
565 * Pointer to the device structure.
568 * Rx queue identificatior.
571 * Pointer to the burts mode information.
574 * 0 as success, -EINVAL as failure.
578 mlx5_rx_burst_mode_get(struct rte_eth_dev *dev,
579 uint16_t rx_queue_id __rte_unused,
580 struct rte_eth_burst_mode *mode)
582 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
583 struct mlx5_priv *priv = dev->data->dev_private;
584 struct mlx5_rxq_data *rxq;
586 rxq = (*priv->rxqs)[rx_queue_id];
591 if (pkt_burst == mlx5_rx_burst) {
592 snprintf(mode->info, sizeof(mode->info), "%s", "Scalar");
593 } else if (pkt_burst == mlx5_rx_burst_mprq) {
594 snprintf(mode->info, sizeof(mode->info), "%s", "Multi-Packet RQ");
595 } else if (pkt_burst == mlx5_rx_burst_vec) {
596 #if defined RTE_ARCH_X86_64
597 snprintf(mode->info, sizeof(mode->info), "%s", "Vector SSE");
598 #elif defined RTE_ARCH_ARM64
599 snprintf(mode->info, sizeof(mode->info), "%s", "Vector Neon");
600 #elif defined RTE_ARCH_PPC_64
601 snprintf(mode->info, sizeof(mode->info), "%s", "Vector AltiVec");
605 } else if (pkt_burst == mlx5_rx_burst_mprq_vec) {
606 #if defined RTE_ARCH_X86_64
607 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector SSE");
608 #elif defined RTE_ARCH_ARM64
609 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector Neon");
610 #elif defined RTE_ARCH_PPC_64
611 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector AltiVec");
622 * DPDK callback to get the number of used descriptors in a RX queue
625 * Pointer to the device structure.
631 * The number of used rx descriptor.
632 * -EINVAL if the queue is invalid
635 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
637 struct mlx5_priv *priv = dev->data->dev_private;
638 struct mlx5_rxq_data *rxq;
640 if (dev->rx_pkt_burst == NULL ||
641 dev->rx_pkt_burst == removed_rx_burst) {
645 rxq = (*priv->rxqs)[rx_queue_id];
650 return rx_queue_count(rxq);
653 #define MLX5_SYSTEM_LOG_DIR "/var/log"
655 * Dump debug information to log file.
660 * If not NULL this string is printed as a header to the output
661 * and the output will be in hexadecimal view.
663 * This is the buffer address to print out.
665 * The number of bytes to dump out.
668 mlx5_dump_debug_information(const char *fname, const char *hex_title,
669 const void *buf, unsigned int hex_len)
673 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
674 fd = fopen(path, "a+");
676 DRV_LOG(WARNING, "cannot open %s for debug dump", path);
677 MKSTR(path2, "./%s", fname);
678 fd = fopen(path2, "a+");
680 DRV_LOG(ERR, "cannot open %s for debug dump", path2);
683 DRV_LOG(INFO, "New debug dump in file %s", path2);
685 DRV_LOG(INFO, "New debug dump in file %s", path);
688 rte_hexdump(fd, hex_title, buf, hex_len);
690 fprintf(fd, "%s", (const char *)buf);
691 fprintf(fd, "\n\n\n");
696 * Move QP from error state to running state and initialize indexes.
699 * Pointer to TX queue control structure.
702 * 0 on success, else -1.
705 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
707 struct mlx5_mp_arg_queue_state_modify sm = {
709 .queue_id = txq_ctrl->txq.idx,
712 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
714 txq_ctrl->txq.wqe_ci = 0;
715 txq_ctrl->txq.wqe_pi = 0;
716 txq_ctrl->txq.elts_comp = 0;
720 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
722 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
724 static const uint8_t magic[] = "seen";
728 for (i = 0; i < sizeof(magic); ++i)
729 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
731 err_cqe->rsvd1[i] = magic[i];
740 * Pointer to TX queue structure.
742 * Pointer to the error CQE.
745 * Negative value if queue recovery failed, otherwise
746 * the error completion entry is handled successfully.
749 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *__rte_restrict txq,
750 volatile struct mlx5_err_cqe *err_cqe)
752 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
753 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
754 struct mlx5_txq_ctrl *txq_ctrl =
755 container_of(txq, struct mlx5_txq_ctrl, txq);
756 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
757 int seen = check_err_cqe_seen(err_cqe);
759 if (!seen && txq_ctrl->dump_file_n <
760 txq_ctrl->priv->config.max_dump_files_num) {
761 MKSTR(err_str, "Unexpected CQE error syndrome "
762 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
763 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
764 txq->cqe_s, txq->qp_num_8s >> 8,
765 rte_be_to_cpu_16(err_cqe->wqe_counter),
766 txq->wqe_ci, txq->cq_ci);
767 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
768 PORT_ID(txq_ctrl->priv), txq->idx,
769 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
770 mlx5_dump_debug_information(name, NULL, err_str, 0);
771 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
772 (const void *)((uintptr_t)
776 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
777 (const void *)((uintptr_t)
781 txq_ctrl->dump_file_n++;
785 * Count errors in WQEs units.
786 * Later it can be improved to count error packets,
787 * for example, by SQ parsing to find how much packets
788 * should be counted for each WQE.
790 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
792 if (tx_recover_qp(txq_ctrl)) {
793 /* Recovering failed - retry later on the same WQE. */
796 /* Release all the remaining buffers. */
797 txq_free_elts(txq_ctrl);
803 * Translate RX completion flags to packet type.
806 * Pointer to RX queue structure.
810 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
813 * Packet type for struct rte_mbuf.
815 static inline uint32_t
816 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
819 uint8_t pinfo = cqe->pkt_info;
820 uint16_t ptype = cqe->hdr_type_etc;
823 * The index to the array should have:
824 * bit[1:0] = l3_hdr_type
825 * bit[4:2] = l4_hdr_type
828 * bit[7] = outer_l3_type
830 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
831 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
835 * Initialize Rx WQ and indexes.
838 * Pointer to RX queue structure.
841 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
843 const unsigned int wqe_n = 1 << rxq->elts_n;
846 for (i = 0; (i != wqe_n); ++i) {
847 volatile struct mlx5_wqe_data_seg *scat;
851 if (mlx5_rxq_mprq_enabled(rxq)) {
852 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
854 scat = &((volatile struct mlx5_wqe_mprq *)
856 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
857 1 << rxq->strd_num_n);
858 byte_count = (1 << rxq->strd_sz_n) *
859 (1 << rxq->strd_num_n);
861 struct rte_mbuf *buf = (*rxq->elts)[i];
863 scat = &((volatile struct mlx5_wqe_data_seg *)
865 addr = rte_pktmbuf_mtod(buf, uintptr_t);
866 byte_count = DATA_LEN(buf);
868 /* scat->addr must be able to store a pointer. */
869 MLX5_ASSERT(sizeof(scat->addr) >= sizeof(uintptr_t));
870 *scat = (struct mlx5_wqe_data_seg){
871 .addr = rte_cpu_to_be_64(addr),
872 .byte_count = rte_cpu_to_be_32(byte_count),
873 .lkey = mlx5_rx_addr2mr(rxq, addr),
876 rxq->consumed_strd = 0;
877 rxq->decompressed = 0;
879 rxq->zip = (struct rxq_zip){
882 rxq->elts_ci = mlx5_rxq_mprq_enabled(rxq) ?
883 (wqe_n >> rxq->sges_n) * (1 << rxq->strd_num_n) : 0;
884 /* Update doorbell counter. */
885 rxq->rq_ci = wqe_n >> rxq->sges_n;
887 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
891 * Modify a Verbs/DevX queue state.
892 * This must be called from the primary process.
895 * Pointer to Ethernet device.
897 * State modify request parameters.
900 * 0 in case of success else non-zero value and rte_errno is set.
903 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
904 const struct mlx5_mp_arg_queue_state_modify *sm)
907 struct mlx5_priv *priv = dev->data->dev_private;
910 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
911 struct mlx5_rxq_ctrl *rxq_ctrl =
912 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
914 ret = priv->obj_ops.rxq_obj_modify(rxq_ctrl->obj, sm->state);
916 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s",
917 sm->state, strerror(errno));
922 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
923 struct mlx5_txq_ctrl *txq_ctrl =
924 container_of(txq, struct mlx5_txq_ctrl, txq);
926 ret = priv->obj_ops.txq_obj_modify(txq_ctrl->obj,
927 MLX5_TXQ_MOD_ERR2RDY,
928 (uint8_t)priv->dev_port);
936 * Modify a Verbs queue state.
939 * Pointer to Ethernet device.
941 * State modify request parameters.
944 * 0 in case of success else non-zero value.
947 mlx5_queue_state_modify(struct rte_eth_dev *dev,
948 struct mlx5_mp_arg_queue_state_modify *sm)
950 struct mlx5_priv *priv = dev->data->dev_private;
953 switch (rte_eal_process_type()) {
954 case RTE_PROC_PRIMARY:
955 ret = mlx5_queue_state_modify_primary(dev, sm);
957 case RTE_PROC_SECONDARY:
958 ret = mlx5_mp_req_queue_state_modify(&priv->mp_id, sm);
968 * The function inserts the RQ state to reset when the first error CQE is
969 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
970 * it moves the RQ state to ready and initializes the RQ.
971 * Next CQE identification and error counting are in the caller responsibility.
974 * Pointer to RX queue structure.
976 * 1 when called from vectorized Rx burst, need to prepare mbufs for the RQ.
977 * 0 when called from non-vectorized Rx burst.
980 * -1 in case of recovery error, otherwise the CQE status.
983 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec)
985 const uint16_t cqe_n = 1 << rxq->cqe_n;
986 const uint16_t cqe_mask = cqe_n - 1;
987 const uint16_t wqe_n = 1 << rxq->elts_n;
988 const uint16_t strd_n = 1 << rxq->strd_num_n;
989 struct mlx5_rxq_ctrl *rxq_ctrl =
990 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
992 volatile struct mlx5_cqe *cqe;
993 volatile struct mlx5_err_cqe *err_cqe;
995 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
997 struct mlx5_mp_arg_queue_state_modify sm;
1000 switch (rxq->err_state) {
1001 case MLX5_RXQ_ERR_STATE_NO_ERROR:
1002 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
1004 case MLX5_RXQ_ERR_STATE_NEED_RESET:
1006 sm.queue_id = rxq->idx;
1007 sm.state = IBV_WQS_RESET;
1008 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
1010 if (rxq_ctrl->dump_file_n <
1011 rxq_ctrl->priv->config.max_dump_files_num) {
1012 MKSTR(err_str, "Unexpected CQE error syndrome "
1013 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
1014 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
1015 rxq->cqn, rxq_ctrl->wqn,
1016 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
1017 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
1018 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
1019 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
1020 mlx5_dump_debug_information(name, NULL, err_str, 0);
1021 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
1022 (const void *)((uintptr_t)
1024 sizeof(*u.cqe) * cqe_n);
1025 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
1026 (const void *)((uintptr_t)
1029 rxq_ctrl->dump_file_n++;
1031 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
1033 case MLX5_RXQ_ERR_STATE_NEED_READY:
1034 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
1035 if (ret == MLX5_CQE_STATUS_HW_OWN) {
1037 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1040 * The RQ consumer index must be zeroed while moving
1041 * from RESET state to RDY state.
1043 *rxq->rq_db = rte_cpu_to_be_32(0);
1046 sm.queue_id = rxq->idx;
1047 sm.state = IBV_WQS_RDY;
1048 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1052 const uint32_t elts_n =
1053 mlx5_rxq_mprq_enabled(rxq) ?
1054 wqe_n * strd_n : wqe_n;
1055 const uint32_t e_mask = elts_n - 1;
1057 mlx5_rxq_mprq_enabled(rxq) ?
1058 rxq->elts_ci : rxq->rq_ci;
1060 struct rte_mbuf **elt;
1062 unsigned int n = elts_n - (elts_ci -
1065 for (i = 0; i < (int)n; ++i) {
1066 elt_idx = (elts_ci + i) & e_mask;
1067 elt = &(*rxq->elts)[elt_idx];
1068 *elt = rte_mbuf_raw_alloc(rxq->mp);
1070 for (i--; i >= 0; --i) {
1071 elt_idx = (elts_ci +
1075 rte_pktmbuf_free_seg
1081 for (i = 0; i < (int)elts_n; ++i) {
1082 elt = &(*rxq->elts)[i];
1084 (uint16_t)((*elt)->buf_len -
1085 rte_pktmbuf_headroom(*elt));
1087 /* Padding with a fake mbuf for vec Rx. */
1088 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i)
1089 (*rxq->elts)[elts_n + i] =
1092 mlx5_rxq_initialize(rxq);
1093 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1102 * Get size of the next packet for a given CQE. For compressed CQEs, the
1103 * consumer index is updated only once all packets of the current one have
1107 * Pointer to RX queue.
1111 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1115 * 0 in case of empty CQE, otherwise the packet size in bytes.
1118 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1119 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1121 struct rxq_zip *zip = &rxq->zip;
1122 uint16_t cqe_n = cqe_cnt + 1;
1128 /* Process compressed data in the CQE and mini arrays. */
1130 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1131 (volatile struct mlx5_mini_cqe8 (*)[8])
1132 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1135 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1136 *mcqe = &(*mc)[zip->ai & 7];
1137 if ((++zip->ai & 7) == 0) {
1138 /* Invalidate consumed CQEs */
1141 while (idx != end) {
1142 (*rxq->cqes)[idx & cqe_cnt].op_own =
1143 MLX5_CQE_INVALIDATE;
1147 * Increment consumer index to skip the number
1148 * of CQEs consumed. Hardware leaves holes in
1149 * the CQ ring for software use.
1154 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1155 /* Invalidate the rest */
1159 while (idx != end) {
1160 (*rxq->cqes)[idx & cqe_cnt].op_own =
1161 MLX5_CQE_INVALIDATE;
1164 rxq->cq_ci = zip->cq_ci;
1168 * No compressed data, get next CQE and verify if it is
1175 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1176 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1177 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1179 ret = mlx5_rx_err_handle(rxq, 0);
1180 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1188 op_own = cqe->op_own;
1189 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1190 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1191 (volatile struct mlx5_mini_cqe8 (*)[8])
1192 (uintptr_t)(&(*rxq->cqes)
1196 /* Fix endianness. */
1197 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1199 * Current mini array position is the one
1200 * returned by check_cqe64().
1202 * If completion comprises several mini arrays,
1203 * as a special case the second one is located
1204 * 7 CQEs after the initial CQE instead of 8
1205 * for subsequent ones.
1207 zip->ca = rxq->cq_ci;
1208 zip->na = zip->ca + 7;
1209 /* Compute the next non compressed CQE. */
1211 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1212 /* Get packet size to return. */
1213 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1216 /* Prefetch all to be invalidated */
1219 while (idx != end) {
1220 rte_prefetch0(&(*rxq->cqes)[(idx) &
1225 len = rte_be_to_cpu_32(cqe->byte_cnt);
1228 if (unlikely(rxq->err_state)) {
1229 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1230 ++rxq->stats.idropped;
1238 * Translate RX completion flags to offload flags.
1244 * Offload flags (ol_flags) for struct rte_mbuf.
1246 static inline uint32_t
1247 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1249 uint32_t ol_flags = 0;
1250 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1254 MLX5_CQE_RX_L3_HDR_VALID,
1255 PKT_RX_IP_CKSUM_GOOD) |
1257 MLX5_CQE_RX_L4_HDR_VALID,
1258 PKT_RX_L4_CKSUM_GOOD);
1263 * Fill in mbuf fields from RX completion flags.
1264 * Note that pkt->ol_flags should be initialized outside of this function.
1267 * Pointer to RX queue.
1272 * @param rss_hash_res
1273 * Packet RSS Hash result.
1276 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1277 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1279 /* Update packet information. */
1280 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1281 if (rss_hash_res && rxq->rss_hash) {
1282 pkt->hash.rss = rss_hash_res;
1283 pkt->ol_flags |= PKT_RX_RSS_HASH;
1285 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1286 pkt->ol_flags |= PKT_RX_FDIR;
1287 if (cqe->sop_drop_qpn !=
1288 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1289 uint32_t mark = cqe->sop_drop_qpn;
1291 pkt->ol_flags |= PKT_RX_FDIR_ID;
1292 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1295 if (rxq->dynf_meta && cqe->flow_table_metadata) {
1296 pkt->ol_flags |= rxq->flow_meta_mask;
1297 *RTE_MBUF_DYNFIELD(pkt, rxq->flow_meta_offset, uint32_t *) =
1298 cqe->flow_table_metadata;
1301 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1302 if (rxq->vlan_strip &&
1303 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1304 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1305 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1307 if (rxq->hw_timestamp) {
1308 uint64_t ts = rte_be_to_cpu_64(cqe->timestamp);
1310 if (rxq->rt_timestamp)
1311 ts = mlx5_txpp_convert_rx_ts(rxq->sh, ts);
1312 mlx5_timestamp_set(pkt, rxq->timestamp_offset, ts);
1313 pkt->ol_flags |= rxq->timestamp_rx_flag;
1318 * DPDK callback for RX.
1321 * Generic pointer to RX queue structure.
1323 * Array to store received packets.
1325 * Maximum number of packets in array.
1328 * Number of packets successfully received (<= pkts_n).
1331 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1333 struct mlx5_rxq_data *rxq = dpdk_rxq;
1334 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1335 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1336 const unsigned int sges_n = rxq->sges_n;
1337 struct rte_mbuf *pkt = NULL;
1338 struct rte_mbuf *seg = NULL;
1339 volatile struct mlx5_cqe *cqe =
1340 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1342 unsigned int rq_ci = rxq->rq_ci << sges_n;
1343 int len = 0; /* keep its value across iterations. */
1346 unsigned int idx = rq_ci & wqe_cnt;
1347 volatile struct mlx5_wqe_data_seg *wqe =
1348 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1349 struct rte_mbuf *rep = (*rxq->elts)[idx];
1350 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1351 uint32_t rss_hash_res;
1359 rep = rte_mbuf_raw_alloc(rxq->mp);
1360 if (unlikely(rep == NULL)) {
1361 ++rxq->stats.rx_nombuf;
1364 * no buffers before we even started,
1365 * bail out silently.
1369 while (pkt != seg) {
1370 MLX5_ASSERT(pkt != (*rxq->elts)[idx]);
1374 rte_mbuf_raw_free(pkt);
1380 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1381 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1383 rte_mbuf_raw_free(rep);
1387 MLX5_ASSERT(len >= (rxq->crc_present << 2));
1388 pkt->ol_flags &= EXT_ATTACHED_MBUF;
1389 /* If compressed, take hash result from mini-CQE. */
1390 rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
1392 mcqe->rx_hash_result);
1393 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1394 if (rxq->crc_present)
1395 len -= RTE_ETHER_CRC_LEN;
1397 if (cqe->lro_num_seg > 1) {
1399 (rte_pktmbuf_mtod(pkt, uint8_t *), cqe,
1401 pkt->ol_flags |= PKT_RX_LRO;
1402 pkt->tso_segsz = len / cqe->lro_num_seg;
1405 DATA_LEN(rep) = DATA_LEN(seg);
1406 PKT_LEN(rep) = PKT_LEN(seg);
1407 SET_DATA_OFF(rep, DATA_OFF(seg));
1408 PORT(rep) = PORT(seg);
1409 (*rxq->elts)[idx] = rep;
1411 * Fill NIC descriptor with the new buffer. The lkey and size
1412 * of the buffers are already known, only the buffer address
1415 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1416 /* If there's only one MR, no need to replace LKey in WQE. */
1417 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1418 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1419 if (len > DATA_LEN(seg)) {
1420 len -= DATA_LEN(seg);
1425 DATA_LEN(seg) = len;
1426 #ifdef MLX5_PMD_SOFT_COUNTERS
1427 /* Increment bytes counter. */
1428 rxq->stats.ibytes += PKT_LEN(pkt);
1430 /* Return packet. */
1435 /* Align consumer index to the next stride. */
1440 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1442 /* Update the consumer index. */
1443 rxq->rq_ci = rq_ci >> sges_n;
1445 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1447 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1448 #ifdef MLX5_PMD_SOFT_COUNTERS
1449 /* Increment packets counter. */
1450 rxq->stats.ipackets += i;
1456 * Update LRO packet TCP header.
1457 * The HW LRO feature doesn't update the TCP header after coalescing the
1458 * TCP segments but supplies information in CQE to fill it by SW.
1461 * Pointer to the TCP header.
1463 * Pointer to the completion entry..
1465 * The L3 pseudo-header checksum.
1468 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *__rte_restrict tcp,
1469 volatile struct mlx5_cqe *__rte_restrict cqe,
1472 uint8_t l4_type = (rte_be_to_cpu_16(cqe->hdr_type_etc) &
1473 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1475 * The HW calculates only the TCP payload checksum, need to complete
1476 * the TCP header checksum and the L3 pseudo-header checksum.
1478 uint32_t csum = phcsum + cqe->csum;
1480 if (l4_type == MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK ||
1481 l4_type == MLX5_L4_HDR_TYPE_TCP_WITH_ACL) {
1482 tcp->tcp_flags |= RTE_TCP_ACK_FLAG;
1483 tcp->recv_ack = cqe->lro_ack_seq_num;
1484 tcp->rx_win = cqe->lro_tcp_win;
1486 if (cqe->lro_tcppsh_abort_dupack & MLX5_CQE_LRO_PUSH_MASK)
1487 tcp->tcp_flags |= RTE_TCP_PSH_FLAG;
1489 csum += rte_raw_cksum(tcp, (tcp->data_off >> 4) * 4);
1490 csum = ((csum & 0xffff0000) >> 16) + (csum & 0xffff);
1491 csum = (~csum) & 0xffff;
1498 * Update LRO packet headers.
1499 * The HW LRO feature doesn't update the L3/TCP headers after coalescing the
1500 * TCP segments but supply information in CQE to fill it by SW.
1503 * The packet address.
1505 * Pointer to the completion entry..
1507 * The packet length.
1510 mlx5_lro_update_hdr(uint8_t *__rte_restrict padd,
1511 volatile struct mlx5_cqe *__rte_restrict cqe,
1515 struct rte_ether_hdr *eth;
1516 struct rte_vlan_hdr *vlan;
1517 struct rte_ipv4_hdr *ipv4;
1518 struct rte_ipv6_hdr *ipv6;
1519 struct rte_tcp_hdr *tcp;
1524 uint16_t proto = h.eth->ether_type;
1528 while (proto == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
1529 proto == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
1530 proto = h.vlan->eth_proto;
1533 if (proto == RTE_BE16(RTE_ETHER_TYPE_IPV4)) {
1534 h.ipv4->time_to_live = cqe->lro_min_ttl;
1535 h.ipv4->total_length = rte_cpu_to_be_16(len - (h.hdr - padd));
1536 h.ipv4->hdr_checksum = 0;
1537 h.ipv4->hdr_checksum = rte_ipv4_cksum(h.ipv4);
1538 phcsum = rte_ipv4_phdr_cksum(h.ipv4, 0);
1541 h.ipv6->hop_limits = cqe->lro_min_ttl;
1542 h.ipv6->payload_len = rte_cpu_to_be_16(len - (h.hdr - padd) -
1544 phcsum = rte_ipv6_phdr_cksum(h.ipv6, 0);
1547 mlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum);
1551 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1553 struct mlx5_mprq_buf *buf = opaque;
1555 if (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) == 1) {
1556 rte_mempool_put(buf->mp, buf);
1557 } else if (unlikely(__atomic_sub_fetch(&buf->refcnt, 1,
1558 __ATOMIC_RELAXED) == 0)) {
1559 __atomic_store_n(&buf->refcnt, 1, __ATOMIC_RELAXED);
1560 rte_mempool_put(buf->mp, buf);
1565 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1567 mlx5_mprq_buf_free_cb(NULL, buf);
1571 * DPDK callback for RX with Multi-Packet RQ support.
1574 * Generic pointer to RX queue structure.
1576 * Array to store received packets.
1578 * Maximum number of packets in array.
1581 * Number of packets successfully received (<= pkts_n).
1584 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1586 struct mlx5_rxq_data *rxq = dpdk_rxq;
1587 const uint32_t strd_n = 1 << rxq->strd_num_n;
1588 const uint32_t cq_mask = (1 << rxq->cqe_n) - 1;
1589 const uint32_t wq_mask = (1 << rxq->elts_n) - 1;
1590 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1592 uint32_t rq_ci = rxq->rq_ci;
1593 uint16_t consumed_strd = rxq->consumed_strd;
1594 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1596 while (i < pkts_n) {
1597 struct rte_mbuf *pkt;
1603 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1604 uint32_t rss_hash_res = 0;
1605 enum mlx5_rqx_code rxq_code;
1607 if (consumed_strd == strd_n) {
1608 /* Replace WQE if the buffer is still in use. */
1609 mprq_buf_replace(rxq, rq_ci & wq_mask);
1610 /* Advance to the next WQE. */
1613 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1615 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1616 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1620 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1621 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1622 MLX5_ASSERT(strd_cnt);
1623 consumed_strd += strd_cnt;
1624 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1627 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1628 strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
1630 /* mini-CQE for MPRQ doesn't have hash result. */
1631 strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
1633 MLX5_ASSERT(strd_idx < strd_n);
1634 MLX5_ASSERT(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) &
1636 pkt = rte_pktmbuf_alloc(rxq->mp);
1637 if (unlikely(pkt == NULL)) {
1638 ++rxq->stats.rx_nombuf;
1641 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1642 MLX5_ASSERT((int)len >= (rxq->crc_present << 2));
1643 if (rxq->crc_present)
1644 len -= RTE_ETHER_CRC_LEN;
1645 rxq_code = mprq_buf_to_pkt(rxq, pkt, len, buf,
1646 strd_idx, strd_cnt);
1647 if (unlikely(rxq_code != MLX5_RXQ_CODE_EXIT)) {
1648 rte_pktmbuf_free_seg(pkt);
1649 if (rxq_code == MLX5_RXQ_CODE_DROPPED) {
1650 ++rxq->stats.idropped;
1653 if (rxq_code == MLX5_RXQ_CODE_NOMBUF) {
1654 ++rxq->stats.rx_nombuf;
1658 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1659 if (cqe->lro_num_seg > 1) {
1660 mlx5_lro_update_hdr(rte_pktmbuf_mtod(pkt, uint8_t *),
1662 pkt->ol_flags |= PKT_RX_LRO;
1663 pkt->tso_segsz = len / cqe->lro_num_seg;
1666 PORT(pkt) = rxq->port_id;
1667 #ifdef MLX5_PMD_SOFT_COUNTERS
1668 /* Increment bytes counter. */
1669 rxq->stats.ibytes += PKT_LEN(pkt);
1671 /* Return packet. */
1675 /* Update the consumer indexes. */
1676 rxq->consumed_strd = consumed_strd;
1678 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1679 if (rq_ci != rxq->rq_ci) {
1682 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1684 #ifdef MLX5_PMD_SOFT_COUNTERS
1685 /* Increment packets counter. */
1686 rxq->stats.ipackets += i;
1692 * Dummy DPDK callback for TX.
1694 * This function is used to temporarily replace the real callback during
1695 * unsafe control operations on the queue, or in case of error.
1698 * Generic pointer to TX queue structure.
1700 * Packets to transmit.
1702 * Number of packets in array.
1705 * Number of packets successfully transmitted (<= pkts_n).
1708 removed_tx_burst(void *dpdk_txq __rte_unused,
1709 struct rte_mbuf **pkts __rte_unused,
1710 uint16_t pkts_n __rte_unused)
1717 * Dummy DPDK callback for RX.
1719 * This function is used to temporarily replace the real callback during
1720 * unsafe control operations on the queue, or in case of error.
1723 * Generic pointer to RX queue structure.
1725 * Array to store received packets.
1727 * Maximum number of packets in array.
1730 * Number of packets successfully received (<= pkts_n).
1733 removed_rx_burst(void *dpdk_txq __rte_unused,
1734 struct rte_mbuf **pkts __rte_unused,
1735 uint16_t pkts_n __rte_unused)
1742 * Vectorized Rx/Tx routines are not compiled in when required vector
1743 * instructions are not supported on a target architecture. The following null
1744 * stubs are needed for linkage when those are not included outside of this file
1745 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1749 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1750 struct rte_mbuf **pkts __rte_unused,
1751 uint16_t pkts_n __rte_unused)
1757 mlx5_rx_burst_mprq_vec(void *dpdk_txq __rte_unused,
1758 struct rte_mbuf **pkts __rte_unused,
1759 uint16_t pkts_n __rte_unused)
1765 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1771 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1777 * Free the mbufs from the linear array of pointers.
1780 * Pointer to array of packets to be free.
1782 * Number of packets to be freed.
1784 * Configured Tx offloads mask. It is fully defined at
1785 * compile time and may be used for optimization.
1787 static __rte_always_inline void
1788 mlx5_tx_free_mbuf(struct rte_mbuf **__rte_restrict pkts,
1789 unsigned int pkts_n,
1790 unsigned int olx __rte_unused)
1792 struct rte_mempool *pool = NULL;
1793 struct rte_mbuf **p_free = NULL;
1794 struct rte_mbuf *mbuf;
1795 unsigned int n_free = 0;
1798 * The implemented algorithm eliminates
1799 * copying pointers to temporary array
1800 * for rte_mempool_put_bulk() calls.
1803 MLX5_ASSERT(pkts_n);
1807 * Decrement mbuf reference counter, detach
1808 * indirect and external buffers if needed.
1810 mbuf = rte_pktmbuf_prefree_seg(*pkts);
1811 if (likely(mbuf != NULL)) {
1812 MLX5_ASSERT(mbuf == *pkts);
1813 if (likely(n_free != 0)) {
1814 if (unlikely(pool != mbuf->pool))
1815 /* From different pool. */
1818 /* Start new scan array. */
1825 if (unlikely(pkts_n == 0)) {
1831 * This happens if mbuf is still referenced.
1832 * We can't put it back to the pool, skip.
1836 if (unlikely(n_free != 0))
1837 /* There is some array to free.*/
1839 if (unlikely(pkts_n == 0))
1840 /* Last mbuf, nothing to free. */
1846 * This loop is implemented to avoid multiple
1847 * inlining of rte_mempool_put_bulk().
1850 MLX5_ASSERT(p_free);
1851 MLX5_ASSERT(n_free);
1853 * Free the array of pre-freed mbufs
1854 * belonging to the same memory pool.
1856 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
1857 if (unlikely(mbuf != NULL)) {
1858 /* There is the request to start new scan. */
1863 if (likely(pkts_n != 0))
1866 * This is the last mbuf to be freed.
1867 * Do one more loop iteration to complete.
1868 * This is rare case of the last unique mbuf.
1873 if (likely(pkts_n == 0))
1882 * Free the mbuf from the elts ring buffer till new tail.
1885 * Pointer to Tx queue structure.
1887 * Index in elts to free up to, becomes new elts tail.
1889 * Configured Tx offloads mask. It is fully defined at
1890 * compile time and may be used for optimization.
1892 static __rte_always_inline void
1893 mlx5_tx_free_elts(struct mlx5_txq_data *__rte_restrict txq,
1895 unsigned int olx __rte_unused)
1897 uint16_t n_elts = tail - txq->elts_tail;
1899 MLX5_ASSERT(n_elts);
1900 MLX5_ASSERT(n_elts <= txq->elts_s);
1902 * Implement a loop to support ring buffer wraparound
1903 * with single inlining of mlx5_tx_free_mbuf().
1908 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
1909 part = RTE_MIN(part, n_elts);
1911 MLX5_ASSERT(part <= txq->elts_s);
1912 mlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],
1914 txq->elts_tail += part;
1920 * Store the mbuf being sent into elts ring buffer.
1921 * On Tx completion these mbufs will be freed.
1924 * Pointer to Tx queue structure.
1926 * Pointer to array of packets to be stored.
1928 * Number of packets to be stored.
1930 * Configured Tx offloads mask. It is fully defined at
1931 * compile time and may be used for optimization.
1933 static __rte_always_inline void
1934 mlx5_tx_copy_elts(struct mlx5_txq_data *__rte_restrict txq,
1935 struct rte_mbuf **__rte_restrict pkts,
1936 unsigned int pkts_n,
1937 unsigned int olx __rte_unused)
1940 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
1943 MLX5_ASSERT(pkts_n);
1944 part = txq->elts_s - (txq->elts_head & txq->elts_m);
1946 MLX5_ASSERT(part <= txq->elts_s);
1947 /* This code is a good candidate for vectorizing with SIMD. */
1948 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
1950 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
1951 txq->elts_head += pkts_n;
1952 if (unlikely(part < pkts_n))
1953 /* The copy is wrapping around the elts array. */
1954 rte_memcpy((void *)elts, (void *)(pkts + part),
1955 (pkts_n - part) * sizeof(struct rte_mbuf *));
1959 * Update completion queue consuming index via doorbell
1960 * and flush the completed data buffers.
1963 * Pointer to TX queue structure.
1964 * @param valid CQE pointer
1965 * if not NULL update txq->wqe_pi and flush the buffers
1967 * Configured Tx offloads mask. It is fully defined at
1968 * compile time and may be used for optimization.
1970 static __rte_always_inline void
1971 mlx5_tx_comp_flush(struct mlx5_txq_data *__rte_restrict txq,
1972 volatile struct mlx5_cqe *last_cqe,
1973 unsigned int olx __rte_unused)
1975 if (likely(last_cqe != NULL)) {
1978 txq->wqe_pi = rte_be_to_cpu_16(last_cqe->wqe_counter);
1979 tail = txq->fcqs[(txq->cq_ci - 1) & txq->cqe_m];
1980 if (likely(tail != txq->elts_tail)) {
1981 mlx5_tx_free_elts(txq, tail, olx);
1982 MLX5_ASSERT(tail == txq->elts_tail);
1988 * Manage TX completions. This routine checks the CQ for
1989 * arrived CQEs, deduces the last accomplished WQE in SQ,
1990 * updates SQ producing index and frees all completed mbufs.
1993 * Pointer to TX queue structure.
1995 * Configured Tx offloads mask. It is fully defined at
1996 * compile time and may be used for optimization.
1998 * NOTE: not inlined intentionally, it makes tx_burst
1999 * routine smaller, simple and faster - from experiments.
2002 mlx5_tx_handle_completion(struct mlx5_txq_data *__rte_restrict txq,
2003 unsigned int olx __rte_unused)
2005 unsigned int count = MLX5_TX_COMP_MAX_CQE;
2006 volatile struct mlx5_cqe *last_cqe = NULL;
2007 bool ring_doorbell = false;
2010 static_assert(MLX5_CQE_STATUS_HW_OWN < 0, "Must be negative value");
2011 static_assert(MLX5_CQE_STATUS_SW_OWN < 0, "Must be negative value");
2013 volatile struct mlx5_cqe *cqe;
2015 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
2016 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
2017 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2018 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
2019 /* No new CQEs in completion queue. */
2020 MLX5_ASSERT(ret == MLX5_CQE_STATUS_HW_OWN);
2024 * Some error occurred, try to restart.
2025 * We have no barrier after WQE related Doorbell
2026 * written, make sure all writes are completed
2027 * here, before we might perform SQ reset.
2030 ret = mlx5_tx_error_cqe_handle
2031 (txq, (volatile struct mlx5_err_cqe *)cqe);
2032 if (unlikely(ret < 0)) {
2034 * Some error occurred on queue error
2035 * handling, we do not advance the index
2036 * here, allowing to retry on next call.
2041 * We are going to fetch all entries with
2042 * MLX5_CQE_SYNDROME_WR_FLUSH_ERR status.
2043 * The send queue is supposed to be empty.
2045 ring_doorbell = true;
2047 txq->cq_pi = txq->cq_ci;
2051 /* Normal transmit completion. */
2052 MLX5_ASSERT(txq->cq_ci != txq->cq_pi);
2053 MLX5_ASSERT((txq->fcqs[txq->cq_ci & txq->cqe_m] >> 16) ==
2055 ring_doorbell = true;
2059 * We have to restrict the amount of processed CQEs
2060 * in one tx_burst routine call. The CQ may be large
2061 * and many CQEs may be updated by the NIC in one
2062 * transaction. Buffers freeing is time consuming,
2063 * multiple iterations may introduce significant
2066 if (likely(--count == 0))
2069 if (likely(ring_doorbell)) {
2070 /* Ring doorbell to notify hardware. */
2071 rte_compiler_barrier();
2072 *txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
2073 mlx5_tx_comp_flush(txq, last_cqe, olx);
2078 * Check if the completion request flag should be set in the last WQE.
2079 * Both pushed mbufs and WQEs are monitored and the completion request
2080 * flag is set if any of thresholds is reached.
2083 * Pointer to TX queue structure.
2085 * Pointer to burst routine local context.
2087 * Configured Tx offloads mask. It is fully defined at
2088 * compile time and may be used for optimization.
2090 static __rte_always_inline void
2091 mlx5_tx_request_completion(struct mlx5_txq_data *__rte_restrict txq,
2092 struct mlx5_txq_local *__rte_restrict loc,
2095 uint16_t head = txq->elts_head;
2098 part = MLX5_TXOFF_CONFIG(INLINE) ?
2099 0 : loc->pkts_sent - loc->pkts_copy;
2101 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
2102 (MLX5_TXOFF_CONFIG(INLINE) &&
2103 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {
2104 volatile struct mlx5_wqe *last = loc->wqe_last;
2107 txq->elts_comp = head;
2108 if (MLX5_TXOFF_CONFIG(INLINE))
2109 txq->wqe_comp = txq->wqe_ci;
2110 /* Request unconditional completion on last WQE. */
2111 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
2112 MLX5_COMP_MODE_OFFSET);
2113 /* Save elts_head in dedicated free on completion queue. */
2114 #ifdef RTE_LIBRTE_MLX5_DEBUG
2115 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head |
2116 (last->cseg.opcode >> 8) << 16;
2118 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head;
2120 /* A CQE slot must always be available. */
2121 MLX5_ASSERT((txq->cq_pi - txq->cq_ci) <= txq->cqe_s);
2126 * DPDK callback to check the status of a tx descriptor.
2131 * The index of the descriptor in the ring.
2134 * The status of the tx descriptor.
2137 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
2139 struct mlx5_txq_data *__rte_restrict txq = tx_queue;
2142 mlx5_tx_handle_completion(txq, 0);
2143 used = txq->elts_head - txq->elts_tail;
2145 return RTE_ETH_TX_DESC_FULL;
2146 return RTE_ETH_TX_DESC_DONE;
2150 * Build the Control Segment with specified opcode:
2151 * - MLX5_OPCODE_SEND
2152 * - MLX5_OPCODE_ENHANCED_MPSW
2156 * Pointer to TX queue structure.
2158 * Pointer to burst routine local context.
2160 * Pointer to WQE to fill with built Control Segment.
2162 * Supposed length of WQE in segments.
2164 * SQ WQE opcode to put into Control Segment.
2166 * Configured Tx offloads mask. It is fully defined at
2167 * compile time and may be used for optimization.
2169 static __rte_always_inline void
2170 mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq,
2171 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2172 struct mlx5_wqe *__rte_restrict wqe,
2174 unsigned int opcode,
2175 unsigned int olx __rte_unused)
2177 struct mlx5_wqe_cseg *__rte_restrict cs = &wqe->cseg;
2179 /* For legacy MPW replace the EMPW by TSO with modifier. */
2180 if (MLX5_TXOFF_CONFIG(MPW) && opcode == MLX5_OPCODE_ENHANCED_MPSW)
2181 opcode = MLX5_OPCODE_TSO | MLX5_OPC_MOD_MPW << 24;
2182 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2183 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2184 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2185 MLX5_COMP_MODE_OFFSET);
2186 cs->misc = RTE_BE32(0);
2190 * Build the Synchronize Queue Segment with specified completion index.
2193 * Pointer to TX queue structure.
2195 * Pointer to burst routine local context.
2197 * Pointer to WQE to fill with built Control Segment.
2199 * Completion index in Clock Queue to wait.
2201 * Configured Tx offloads mask. It is fully defined at
2202 * compile time and may be used for optimization.
2204 static __rte_always_inline void
2205 mlx5_tx_wseg_init(struct mlx5_txq_data *restrict txq,
2206 struct mlx5_txq_local *restrict loc __rte_unused,
2207 struct mlx5_wqe *restrict wqe,
2209 unsigned int olx __rte_unused)
2211 struct mlx5_wqe_qseg *qs;
2213 qs = RTE_PTR_ADD(wqe, MLX5_WSEG_SIZE);
2214 qs->max_index = rte_cpu_to_be_32(wci);
2215 qs->qpn_cqn = rte_cpu_to_be_32(txq->sh->txpp.clock_queue.cq->id);
2216 qs->reserved0 = RTE_BE32(0);
2217 qs->reserved1 = RTE_BE32(0);
2221 * Build the Ethernet Segment without inlined data.
2222 * Supports Software Parser, Checksums and VLAN
2223 * insertion Tx offload features.
2226 * Pointer to TX queue structure.
2228 * Pointer to burst routine local context.
2230 * Pointer to WQE to fill with built Ethernet Segment.
2232 * Configured Tx offloads mask. It is fully defined at
2233 * compile time and may be used for optimization.
2235 static __rte_always_inline void
2236 mlx5_tx_eseg_none(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
2237 struct mlx5_txq_local *__rte_restrict loc,
2238 struct mlx5_wqe *__rte_restrict wqe,
2241 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2245 * Calculate and set check sum flags first, dword field
2246 * in segment may be shared with Software Parser flags.
2248 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2249 es->flags = rte_cpu_to_le_32(csum);
2251 * Calculate and set Software Parser offsets and flags.
2252 * These flags a set for custom UDP and IP tunnel packets.
2254 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2255 /* Fill metadata field if needed. */
2256 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2257 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2258 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2259 /* Engage VLAN tag insertion feature if requested. */
2260 if (MLX5_TXOFF_CONFIG(VLAN) &&
2261 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2263 * We should get here only if device support
2264 * this feature correctly.
2266 MLX5_ASSERT(txq->vlan_en);
2267 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2268 loc->mbuf->vlan_tci);
2270 es->inline_hdr = RTE_BE32(0);
2275 * Build the Ethernet Segment with minimal inlined data
2276 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2277 * used to fill the gap in single WQEBB WQEs.
2278 * Supports Software Parser, Checksums and VLAN
2279 * insertion Tx offload features.
2282 * Pointer to TX queue structure.
2284 * Pointer to burst routine local context.
2286 * Pointer to WQE to fill with built Ethernet Segment.
2288 * Length of VLAN tag insertion if any.
2290 * Configured Tx offloads mask. It is fully defined at
2291 * compile time and may be used for optimization.
2293 static __rte_always_inline void
2294 mlx5_tx_eseg_dmin(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
2295 struct mlx5_txq_local *__rte_restrict loc,
2296 struct mlx5_wqe *__rte_restrict wqe,
2300 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2302 uint8_t *psrc, *pdst;
2305 * Calculate and set check sum flags first, dword field
2306 * in segment may be shared with Software Parser flags.
2308 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2309 es->flags = rte_cpu_to_le_32(csum);
2311 * Calculate and set Software Parser offsets and flags.
2312 * These flags a set for custom UDP and IP tunnel packets.
2314 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2315 /* Fill metadata field if needed. */
2316 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2317 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2318 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2319 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2321 sizeof(rte_v128u32_t)),
2322 "invalid Ethernet Segment data size");
2323 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2325 sizeof(struct rte_vlan_hdr) +
2326 2 * RTE_ETHER_ADDR_LEN),
2327 "invalid Ethernet Segment data size");
2328 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2329 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2330 es->inline_data = *(unaligned_uint16_t *)psrc;
2331 psrc += sizeof(uint16_t);
2332 pdst = (uint8_t *)(es + 1);
2333 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2334 /* Implement VLAN tag insertion as part inline data. */
2335 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2336 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2337 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2338 /* Insert VLAN ethertype + VLAN tag. */
2339 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2340 ((RTE_ETHER_TYPE_VLAN << 16) |
2341 loc->mbuf->vlan_tci);
2342 pdst += sizeof(struct rte_vlan_hdr);
2343 /* Copy the rest two bytes from packet data. */
2344 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2345 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2347 /* Fill the gap in the title WQEBB with inline data. */
2348 rte_mov16(pdst, psrc);
2353 * Build the Ethernet Segment with entire packet
2354 * data inlining. Checks the boundary of WQEBB and
2355 * ring buffer wrapping, supports Software Parser,
2356 * Checksums and VLAN insertion Tx offload features.
2359 * Pointer to TX queue structure.
2361 * Pointer to burst routine local context.
2363 * Pointer to WQE to fill with built Ethernet Segment.
2365 * Length of VLAN tag insertion if any.
2367 * Length of data to inline (VLAN included, if any).
2369 * TSO flag, set mss field from the packet.
2371 * Configured Tx offloads mask. It is fully defined at
2372 * compile time and may be used for optimization.
2375 * Pointer to the next Data Segment (aligned and wrapped around).
2377 static __rte_always_inline struct mlx5_wqe_dseg *
2378 mlx5_tx_eseg_data(struct mlx5_txq_data *__rte_restrict txq,
2379 struct mlx5_txq_local *__rte_restrict loc,
2380 struct mlx5_wqe *__rte_restrict wqe,
2386 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2388 uint8_t *psrc, *pdst;
2392 * Calculate and set check sum flags first, dword field
2393 * in segment may be shared with Software Parser flags.
2395 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2398 csum |= loc->mbuf->tso_segsz;
2399 es->flags = rte_cpu_to_be_32(csum);
2401 es->flags = rte_cpu_to_le_32(csum);
2404 * Calculate and set Software Parser offsets and flags.
2405 * These flags a set for custom UDP and IP tunnel packets.
2407 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2408 /* Fill metadata field if needed. */
2409 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2410 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2411 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2412 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2414 sizeof(rte_v128u32_t)),
2415 "invalid Ethernet Segment data size");
2416 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2418 sizeof(struct rte_vlan_hdr) +
2419 2 * RTE_ETHER_ADDR_LEN),
2420 "invalid Ethernet Segment data size");
2421 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2422 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2423 es->inline_data = *(unaligned_uint16_t *)psrc;
2424 psrc += sizeof(uint16_t);
2425 pdst = (uint8_t *)(es + 1);
2426 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2427 /* Implement VLAN tag insertion as part inline data. */
2428 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2429 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2430 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2431 /* Insert VLAN ethertype + VLAN tag. */
2432 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2433 ((RTE_ETHER_TYPE_VLAN << 16) |
2434 loc->mbuf->vlan_tci);
2435 pdst += sizeof(struct rte_vlan_hdr);
2436 /* Copy the rest two bytes from packet data. */
2437 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2438 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2439 psrc += sizeof(uint16_t);
2441 /* Fill the gap in the title WQEBB with inline data. */
2442 rte_mov16(pdst, psrc);
2443 psrc += sizeof(rte_v128u32_t);
2445 pdst = (uint8_t *)(es + 2);
2446 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2447 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2448 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2450 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2451 return (struct mlx5_wqe_dseg *)pdst;
2454 * The WQEBB space availability is checked by caller.
2455 * Here we should be aware of WQE ring buffer wraparound only.
2457 part = (uint8_t *)txq->wqes_end - pdst;
2458 part = RTE_MIN(part, inlen);
2460 rte_memcpy(pdst, psrc, part);
2462 if (likely(!inlen)) {
2464 * If return value is not used by the caller
2465 * the code below will be optimized out.
2468 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2469 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2470 pdst = (uint8_t *)txq->wqes;
2471 return (struct mlx5_wqe_dseg *)pdst;
2473 pdst = (uint8_t *)txq->wqes;
2480 * Copy data from chain of mbuf to the specified linear buffer.
2481 * Checksums and VLAN insertion Tx offload features. If data
2482 * from some mbuf copied completely this mbuf is freed. Local
2483 * structure is used to keep the byte stream state.
2486 * Pointer to the destination linear buffer.
2488 * Pointer to burst routine local context.
2490 * Length of data to be copied.
2492 * Length of data to be copied ignoring no inline hint.
2494 * Configured Tx offloads mask. It is fully defined at
2495 * compile time and may be used for optimization.
2498 * Number of actual copied data bytes. This is always greater than or
2499 * equal to must parameter and might be lesser than len in no inline
2500 * hint flag is encountered.
2502 static __rte_always_inline unsigned int
2503 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2504 struct mlx5_txq_local *__rte_restrict loc,
2507 unsigned int olx __rte_unused)
2509 struct rte_mbuf *mbuf;
2510 unsigned int part, dlen, copy = 0;
2514 MLX5_ASSERT(must <= len);
2516 /* Allow zero length packets, must check first. */
2517 dlen = rte_pktmbuf_data_len(loc->mbuf);
2518 if (dlen <= loc->mbuf_off) {
2519 /* Exhausted packet, just free. */
2521 loc->mbuf = mbuf->next;
2522 rte_pktmbuf_free_seg(mbuf);
2524 MLX5_ASSERT(loc->mbuf_nseg > 1);
2525 MLX5_ASSERT(loc->mbuf);
2527 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
2532 * We already copied the minimal
2533 * requested amount of data.
2538 if (diff <= rte_pktmbuf_data_len(loc->mbuf)) {
2540 * Copy only the minimal required
2541 * part of the data buffer.
2548 dlen -= loc->mbuf_off;
2549 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2551 part = RTE_MIN(len, dlen);
2552 rte_memcpy(pdst, psrc, part);
2554 loc->mbuf_off += part;
2557 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2559 /* Exhausted packet, just free. */
2561 loc->mbuf = mbuf->next;
2562 rte_pktmbuf_free_seg(mbuf);
2564 MLX5_ASSERT(loc->mbuf_nseg >= 1);
2574 * Build the Ethernet Segment with inlined data from
2575 * multi-segment packet. Checks the boundary of WQEBB
2576 * and ring buffer wrapping, supports Software Parser,
2577 * Checksums and VLAN insertion Tx offload features.
2580 * Pointer to TX queue structure.
2582 * Pointer to burst routine local context.
2584 * Pointer to WQE to fill with built Ethernet Segment.
2586 * Length of VLAN tag insertion if any.
2588 * Length of data to inline (VLAN included, if any).
2590 * TSO flag, set mss field from the packet.
2592 * Configured Tx offloads mask. It is fully defined at
2593 * compile time and may be used for optimization.
2596 * Pointer to the next Data Segment (aligned and
2597 * possible NOT wrapped around - caller should do
2598 * wrapping check on its own).
2600 static __rte_always_inline struct mlx5_wqe_dseg *
2601 mlx5_tx_eseg_mdat(struct mlx5_txq_data *__rte_restrict txq,
2602 struct mlx5_txq_local *__rte_restrict loc,
2603 struct mlx5_wqe *__rte_restrict wqe,
2609 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2612 unsigned int part, tlen = 0;
2615 * Calculate and set check sum flags first, uint32_t field
2616 * in segment may be shared with Software Parser flags.
2618 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2621 csum |= loc->mbuf->tso_segsz;
2622 es->flags = rte_cpu_to_be_32(csum);
2624 es->flags = rte_cpu_to_le_32(csum);
2627 * Calculate and set Software Parser offsets and flags.
2628 * These flags a set for custom UDP and IP tunnel packets.
2630 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2631 /* Fill metadata field if needed. */
2632 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2633 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2634 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2635 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2637 sizeof(rte_v128u32_t)),
2638 "invalid Ethernet Segment data size");
2639 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2641 sizeof(struct rte_vlan_hdr) +
2642 2 * RTE_ETHER_ADDR_LEN),
2643 "invalid Ethernet Segment data size");
2644 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2645 pdst = (uint8_t *)&es->inline_data;
2646 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2647 /* Implement VLAN tag insertion as part inline data. */
2648 mlx5_tx_mseg_memcpy(pdst, loc,
2649 2 * RTE_ETHER_ADDR_LEN,
2650 2 * RTE_ETHER_ADDR_LEN, olx);
2651 pdst += 2 * RTE_ETHER_ADDR_LEN;
2652 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2653 ((RTE_ETHER_TYPE_VLAN << 16) |
2654 loc->mbuf->vlan_tci);
2655 pdst += sizeof(struct rte_vlan_hdr);
2656 tlen += 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2658 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2660 * The WQEBB space availability is checked by caller.
2661 * Here we should be aware of WQE ring buffer wraparound only.
2663 part = (uint8_t *)txq->wqes_end - pdst;
2664 part = RTE_MIN(part, inlen - tlen);
2670 * Copying may be interrupted inside the routine
2671 * if run into no inline hint flag.
2673 copy = tlen >= txq->inlen_mode ? 0 : (txq->inlen_mode - tlen);
2674 copy = mlx5_tx_mseg_memcpy(pdst, loc, part, copy, olx);
2676 if (likely(inlen <= tlen) || copy < part) {
2677 es->inline_hdr_sz = rte_cpu_to_be_16(tlen);
2679 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2680 return (struct mlx5_wqe_dseg *)pdst;
2682 pdst = (uint8_t *)txq->wqes;
2683 part = inlen - tlen;
2688 * Build the Data Segment of pointer type.
2691 * Pointer to TX queue structure.
2693 * Pointer to burst routine local context.
2695 * Pointer to WQE to fill with built Data Segment.
2697 * Data buffer to point.
2699 * Data buffer length.
2701 * Configured Tx offloads mask. It is fully defined at
2702 * compile time and may be used for optimization.
2704 static __rte_always_inline void
2705 mlx5_tx_dseg_ptr(struct mlx5_txq_data *__rte_restrict txq,
2706 struct mlx5_txq_local *__rte_restrict loc,
2707 struct mlx5_wqe_dseg *__rte_restrict dseg,
2710 unsigned int olx __rte_unused)
2714 dseg->bcount = rte_cpu_to_be_32(len);
2715 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2716 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2720 * Build the Data Segment of pointer type or inline
2721 * if data length is less than buffer in minimal
2722 * Data Segment size.
2725 * Pointer to TX queue structure.
2727 * Pointer to burst routine local context.
2729 * Pointer to WQE to fill with built Data Segment.
2731 * Data buffer to point.
2733 * Data buffer length.
2735 * Configured Tx offloads mask. It is fully defined at
2736 * compile time and may be used for optimization.
2738 static __rte_always_inline void
2739 mlx5_tx_dseg_iptr(struct mlx5_txq_data *__rte_restrict txq,
2740 struct mlx5_txq_local *__rte_restrict loc,
2741 struct mlx5_wqe_dseg *__rte_restrict dseg,
2744 unsigned int olx __rte_unused)
2750 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2751 dseg->bcount = rte_cpu_to_be_32(len);
2752 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2753 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2757 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2758 /* Unrolled implementation of generic rte_memcpy. */
2759 dst = (uintptr_t)&dseg->inline_data[0];
2760 src = (uintptr_t)buf;
2762 #ifdef RTE_ARCH_STRICT_ALIGN
2763 MLX5_ASSERT(dst == RTE_PTR_ALIGN(dst, sizeof(uint32_t)));
2764 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2765 dst += sizeof(uint32_t);
2766 src += sizeof(uint32_t);
2767 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2768 dst += sizeof(uint32_t);
2769 src += sizeof(uint32_t);
2771 *(uint64_t *)dst = *(unaligned_uint64_t *)src;
2772 dst += sizeof(uint64_t);
2773 src += sizeof(uint64_t);
2777 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2778 dst += sizeof(uint32_t);
2779 src += sizeof(uint32_t);
2782 *(uint16_t *)dst = *(unaligned_uint16_t *)src;
2783 dst += sizeof(uint16_t);
2784 src += sizeof(uint16_t);
2787 *(uint8_t *)dst = *(uint8_t *)src;
2791 * Build the Data Segment of inlined data from single
2792 * segment packet, no VLAN insertion.
2795 * Pointer to TX queue structure.
2797 * Pointer to burst routine local context.
2799 * Pointer to WQE to fill with built Data Segment.
2801 * Data buffer to point.
2803 * Data buffer length.
2805 * Configured Tx offloads mask. It is fully defined at
2806 * compile time and may be used for optimization.
2809 * Pointer to the next Data Segment after inlined data.
2810 * Ring buffer wraparound check is needed. We do not
2811 * do it here because it may not be needed for the
2812 * last packet in the eMPW session.
2814 static __rte_always_inline struct mlx5_wqe_dseg *
2815 mlx5_tx_dseg_empw(struct mlx5_txq_data *__rte_restrict txq,
2816 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2817 struct mlx5_wqe_dseg *__rte_restrict dseg,
2820 unsigned int olx __rte_unused)
2825 if (!MLX5_TXOFF_CONFIG(MPW)) {
2826 /* Store the descriptor byte counter for eMPW sessions. */
2827 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2828 pdst = &dseg->inline_data[0];
2830 /* The entire legacy MPW session counter is stored on close. */
2831 pdst = (uint8_t *)dseg;
2834 * The WQEBB space availability is checked by caller.
2835 * Here we should be aware of WQE ring buffer wraparound only.
2837 part = (uint8_t *)txq->wqes_end - pdst;
2838 part = RTE_MIN(part, len);
2840 rte_memcpy(pdst, buf, part);
2844 if (!MLX5_TXOFF_CONFIG(MPW))
2845 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2846 /* Note: no final wraparound check here. */
2847 return (struct mlx5_wqe_dseg *)pdst;
2849 pdst = (uint8_t *)txq->wqes;
2856 * Build the Data Segment of inlined data from single
2857 * segment packet with VLAN insertion.
2860 * Pointer to TX queue structure.
2862 * Pointer to burst routine local context.
2864 * Pointer to the dseg fill with built Data Segment.
2866 * Data buffer to point.
2868 * Data buffer length.
2870 * Configured Tx offloads mask. It is fully defined at
2871 * compile time and may be used for optimization.
2874 * Pointer to the next Data Segment after inlined data.
2875 * Ring buffer wraparound check is needed.
2877 static __rte_always_inline struct mlx5_wqe_dseg *
2878 mlx5_tx_dseg_vlan(struct mlx5_txq_data *__rte_restrict txq,
2879 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2880 struct mlx5_wqe_dseg *__rte_restrict dseg,
2883 unsigned int olx __rte_unused)
2889 MLX5_ASSERT(len > MLX5_ESEG_MIN_INLINE_SIZE);
2890 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
2891 (2 * RTE_ETHER_ADDR_LEN),
2892 "invalid Data Segment data size");
2893 if (!MLX5_TXOFF_CONFIG(MPW)) {
2894 /* Store the descriptor byte counter for eMPW sessions. */
2895 dseg->bcount = rte_cpu_to_be_32
2896 ((len + sizeof(struct rte_vlan_hdr)) |
2897 MLX5_ETH_WQE_DATA_INLINE);
2898 pdst = &dseg->inline_data[0];
2900 /* The entire legacy MPW session counter is stored on close. */
2901 pdst = (uint8_t *)dseg;
2903 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
2904 buf += MLX5_DSEG_MIN_INLINE_SIZE;
2905 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
2906 len -= MLX5_DSEG_MIN_INLINE_SIZE;
2907 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
2908 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2909 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2910 pdst = (uint8_t *)txq->wqes;
2911 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
2912 loc->mbuf->vlan_tci);
2913 pdst += sizeof(struct rte_vlan_hdr);
2915 * The WQEBB space availability is checked by caller.
2916 * Here we should be aware of WQE ring buffer wraparound only.
2918 part = (uint8_t *)txq->wqes_end - pdst;
2919 part = RTE_MIN(part, len);
2921 rte_memcpy(pdst, buf, part);
2925 if (!MLX5_TXOFF_CONFIG(MPW))
2926 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2927 /* Note: no final wraparound check here. */
2928 return (struct mlx5_wqe_dseg *)pdst;
2930 pdst = (uint8_t *)txq->wqes;
2937 * Build the Ethernet Segment with optionally inlined data with
2938 * VLAN insertion and following Data Segments (if any) from
2939 * multi-segment packet. Used by ordinary send and TSO.
2942 * Pointer to TX queue structure.
2944 * Pointer to burst routine local context.
2946 * Pointer to WQE to fill with built Ethernet/Data Segments.
2948 * Length of VLAN header to insert, 0 means no VLAN insertion.
2950 * Data length to inline. For TSO this parameter specifies
2951 * exact value, for ordinary send routine can be aligned by
2952 * caller to provide better WQE space saving and data buffer
2953 * start address alignment. This length includes VLAN header
2956 * Zero means ordinary send, inlined data can be extended,
2957 * otherwise this is TSO, inlined data length is fixed.
2959 * Configured Tx offloads mask. It is fully defined at
2960 * compile time and may be used for optimization.
2963 * Actual size of built WQE in segments.
2965 static __rte_always_inline unsigned int
2966 mlx5_tx_mseg_build(struct mlx5_txq_data *__rte_restrict txq,
2967 struct mlx5_txq_local *__rte_restrict loc,
2968 struct mlx5_wqe *__rte_restrict wqe,
2972 unsigned int olx __rte_unused)
2974 struct mlx5_wqe_dseg *__rte_restrict dseg;
2977 MLX5_ASSERT((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
2978 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
2981 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
2982 if (!loc->mbuf_nseg)
2985 * There are still some mbuf remaining, not inlined.
2986 * The first mbuf may be partially inlined and we
2987 * must process the possible non-zero data offset.
2989 if (loc->mbuf_off) {
2994 * Exhausted packets must be dropped before.
2995 * Non-zero offset means there are some data
2996 * remained in the packet.
2998 MLX5_ASSERT(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
2999 MLX5_ASSERT(rte_pktmbuf_data_len(loc->mbuf));
3000 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
3002 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
3004 * Build the pointer/minimal data Data Segment.
3005 * Do ring buffer wrapping check in advance.
3007 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3008 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3009 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
3010 /* Store the mbuf to be freed on completion. */
3011 MLX5_ASSERT(loc->elts_free);
3012 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3015 if (--loc->mbuf_nseg == 0)
3017 loc->mbuf = loc->mbuf->next;
3021 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3022 struct rte_mbuf *mbuf;
3024 /* Zero length segment found, just skip. */
3026 loc->mbuf = loc->mbuf->next;
3027 rte_pktmbuf_free_seg(mbuf);
3028 if (--loc->mbuf_nseg == 0)
3031 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3032 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3035 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3036 rte_pktmbuf_data_len(loc->mbuf), olx);
3037 MLX5_ASSERT(loc->elts_free);
3038 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3041 if (--loc->mbuf_nseg == 0)
3043 loc->mbuf = loc->mbuf->next;
3048 /* Calculate actual segments used from the dseg pointer. */
3049 if ((uintptr_t)wqe < (uintptr_t)dseg)
3050 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
3052 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
3053 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
3058 * The routine checks timestamp flag in the current packet,
3059 * and push WAIT WQE into the queue if scheduling is required.
3062 * Pointer to TX queue structure.
3064 * Pointer to burst routine local context.
3066 * Configured Tx offloads mask. It is fully defined at
3067 * compile time and may be used for optimization.
3070 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3071 * MLX5_TXCMP_CODE_SINGLE - continue processing with the packet.
3072 * MLX5_TXCMP_CODE_MULTI - the WAIT inserted, continue processing.
3073 * Local context variables partially updated.
3075 static __rte_always_inline enum mlx5_txcmp_code
3076 mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,
3077 struct mlx5_txq_local *restrict loc,
3080 if (MLX5_TXOFF_CONFIG(TXPP) &&
3081 loc->mbuf->ol_flags & txq->ts_mask) {
3082 struct mlx5_wqe *wqe;
3087 * Estimate the required space quickly and roughly.
3088 * We would like to ensure the packet can be pushed
3089 * to the queue and we won't get the orphan WAIT WQE.
3091 if (loc->wqe_free <= MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE ||
3092 loc->elts_free < NB_SEGS(loc->mbuf))
3093 return MLX5_TXCMP_CODE_EXIT;
3094 /* Convert the timestamp into completion to wait. */
3095 ts = *RTE_MBUF_DYNFIELD(loc->mbuf, txq->ts_offset, uint64_t *);
3096 wci = mlx5_txpp_convert_tx_ts(txq->sh, ts);
3097 if (unlikely(wci < 0))
3098 return MLX5_TXCMP_CODE_SINGLE;
3099 /* Build the WAIT WQE with specified completion. */
3100 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3101 mlx5_tx_cseg_init(txq, loc, wqe, 2, MLX5_OPCODE_WAIT, olx);
3102 mlx5_tx_wseg_init(txq, loc, wqe, wci, olx);
3105 return MLX5_TXCMP_CODE_MULTI;
3107 return MLX5_TXCMP_CODE_SINGLE;
3111 * Tx one packet function for multi-segment TSO. Supports all
3112 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
3113 * sends one packet per WQE.
3115 * This routine is responsible for storing processed mbuf
3116 * into elts ring buffer and update elts_head.
3119 * Pointer to TX queue structure.
3121 * Pointer to burst routine local context.
3123 * Configured Tx offloads mask. It is fully defined at
3124 * compile time and may be used for optimization.
3127 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3128 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3129 * Local context variables partially updated.
3131 static __rte_always_inline enum mlx5_txcmp_code
3132 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *__rte_restrict txq,
3133 struct mlx5_txq_local *__rte_restrict loc,
3136 struct mlx5_wqe *__rte_restrict wqe;
3137 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
3139 if (MLX5_TXOFF_CONFIG(TXPP)) {
3140 enum mlx5_txcmp_code wret;
3142 /* Generate WAIT for scheduling if requested. */
3143 wret = mlx5_tx_schedule_send(txq, loc, olx);
3144 if (wret == MLX5_TXCMP_CODE_EXIT)
3145 return MLX5_TXCMP_CODE_EXIT;
3146 if (wret == MLX5_TXCMP_CODE_ERROR)
3147 return MLX5_TXCMP_CODE_ERROR;
3150 * Calculate data length to be inlined to estimate
3151 * the required space in WQE ring buffer.
3153 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3154 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3155 vlan = sizeof(struct rte_vlan_hdr);
3156 inlen = loc->mbuf->l2_len + vlan +
3157 loc->mbuf->l3_len + loc->mbuf->l4_len;
3158 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
3159 return MLX5_TXCMP_CODE_ERROR;
3160 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3161 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
3162 /* Packet must contain all TSO headers. */
3163 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
3164 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3165 inlen > (dlen + vlan)))
3166 return MLX5_TXCMP_CODE_ERROR;
3167 MLX5_ASSERT(inlen >= txq->inlen_mode);
3169 * Check whether there are enough free WQEBBs:
3171 * - Ethernet Segment
3172 * - First Segment of inlined Ethernet data
3173 * - ... data continued ...
3174 * - Data Segments of pointer/min inline type
3176 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3177 MLX5_ESEG_MIN_INLINE_SIZE +
3179 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3180 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3181 return MLX5_TXCMP_CODE_EXIT;
3182 /* Check for maximal WQE size. */
3183 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3184 return MLX5_TXCMP_CODE_ERROR;
3185 #ifdef MLX5_PMD_SOFT_COUNTERS
3186 /* Update sent data bytes/packets counters. */
3187 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
3188 loc->mbuf->tso_segsz;
3190 * One will be added for mbuf itself
3191 * at the end of the mlx5_tx_burst from
3192 * loc->pkts_sent field.
3195 txq->stats.opackets += ntcp;
3196 txq->stats.obytes += dlen + vlan + ntcp * inlen;
3198 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3199 loc->wqe_last = wqe;
3200 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
3201 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
3202 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3203 txq->wqe_ci += (ds + 3) / 4;
3204 loc->wqe_free -= (ds + 3) / 4;
3205 return MLX5_TXCMP_CODE_MULTI;
3209 * Tx one packet function for multi-segment SEND. Supports all
3210 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3211 * sends one packet per WQE, without any data inlining in
3214 * This routine is responsible for storing processed mbuf
3215 * into elts ring buffer and update elts_head.
3218 * Pointer to TX queue structure.
3220 * Pointer to burst routine local context.
3222 * Configured Tx offloads mask. It is fully defined at
3223 * compile time and may be used for optimization.
3226 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3227 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3228 * Local context variables partially updated.
3230 static __rte_always_inline enum mlx5_txcmp_code
3231 mlx5_tx_packet_multi_send(struct mlx5_txq_data *__rte_restrict txq,
3232 struct mlx5_txq_local *__rte_restrict loc,
3235 struct mlx5_wqe_dseg *__rte_restrict dseg;
3236 struct mlx5_wqe *__rte_restrict wqe;
3237 unsigned int ds, nseg;
3239 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3240 if (MLX5_TXOFF_CONFIG(TXPP)) {
3241 enum mlx5_txcmp_code wret;
3243 /* Generate WAIT for scheduling if requested. */
3244 wret = mlx5_tx_schedule_send(txq, loc, olx);
3245 if (wret == MLX5_TXCMP_CODE_EXIT)
3246 return MLX5_TXCMP_CODE_EXIT;
3247 if (wret == MLX5_TXCMP_CODE_ERROR)
3248 return MLX5_TXCMP_CODE_ERROR;
3251 * No inline at all, it means the CPU cycles saving
3252 * is prioritized at configuration, we should not
3253 * copy any packet data to WQE.
3255 nseg = NB_SEGS(loc->mbuf);
3257 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3258 return MLX5_TXCMP_CODE_EXIT;
3259 /* Check for maximal WQE size. */
3260 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3261 return MLX5_TXCMP_CODE_ERROR;
3263 * Some Tx offloads may cause an error if
3264 * packet is not long enough, check against
3265 * assumed minimal length.
3267 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
3268 return MLX5_TXCMP_CODE_ERROR;
3269 #ifdef MLX5_PMD_SOFT_COUNTERS
3270 /* Update sent data bytes counter. */
3271 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
3272 if (MLX5_TXOFF_CONFIG(VLAN) &&
3273 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3274 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
3277 * SEND WQE, one WQEBB:
3278 * - Control Segment, SEND opcode
3279 * - Ethernet Segment, optional VLAN, no inline
3280 * - Data Segments, pointer only type
3282 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3283 loc->wqe_last = wqe;
3284 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
3285 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3286 dseg = &wqe->dseg[0];
3288 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3289 struct rte_mbuf *mbuf;
3292 * Zero length segment found, have to
3293 * correct total size of WQE in segments.
3294 * It is supposed to be rare occasion, so
3295 * in normal case (no zero length segments)
3296 * we avoid extra writing to the Control
3300 wqe->cseg.sq_ds -= RTE_BE32(1);
3302 loc->mbuf = mbuf->next;
3303 rte_pktmbuf_free_seg(mbuf);
3309 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3310 rte_pktmbuf_data_len(loc->mbuf), olx);
3311 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3316 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3317 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3318 loc->mbuf = loc->mbuf->next;
3321 txq->wqe_ci += (ds + 3) / 4;
3322 loc->wqe_free -= (ds + 3) / 4;
3323 return MLX5_TXCMP_CODE_MULTI;
3327 * Tx one packet function for multi-segment SEND. Supports all
3328 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3329 * sends one packet per WQE, with data inlining in
3330 * Ethernet Segment and minimal Data Segments.
3332 * This routine is responsible for storing processed mbuf
3333 * into elts ring buffer and update elts_head.
3336 * Pointer to TX queue structure.
3338 * Pointer to burst routine local context.
3340 * Configured Tx offloads mask. It is fully defined at
3341 * compile time and may be used for optimization.
3344 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3345 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3346 * Local context variables partially updated.
3348 static __rte_always_inline enum mlx5_txcmp_code
3349 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,
3350 struct mlx5_txq_local *__rte_restrict loc,
3353 struct mlx5_wqe *__rte_restrict wqe;
3354 unsigned int ds, inlen, dlen, vlan = 0;
3356 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3357 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3358 if (MLX5_TXOFF_CONFIG(TXPP)) {
3359 enum mlx5_txcmp_code wret;
3361 /* Generate WAIT for scheduling if requested. */
3362 wret = mlx5_tx_schedule_send(txq, loc, olx);
3363 if (wret == MLX5_TXCMP_CODE_EXIT)
3364 return MLX5_TXCMP_CODE_EXIT;
3365 if (wret == MLX5_TXCMP_CODE_ERROR)
3366 return MLX5_TXCMP_CODE_ERROR;
3369 * First calculate data length to be inlined
3370 * to estimate the required space for WQE.
3372 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3373 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3374 vlan = sizeof(struct rte_vlan_hdr);
3375 inlen = dlen + vlan;
3376 /* Check against minimal length. */
3377 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3378 return MLX5_TXCMP_CODE_ERROR;
3379 MLX5_ASSERT(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3380 if (inlen > txq->inlen_send ||
3381 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
3382 struct rte_mbuf *mbuf;
3387 * Packet length exceeds the allowed inline
3388 * data length, check whether the minimal
3389 * inlining is required.
3391 if (txq->inlen_mode) {
3392 MLX5_ASSERT(txq->inlen_mode >=
3393 MLX5_ESEG_MIN_INLINE_SIZE);
3394 MLX5_ASSERT(txq->inlen_mode <= txq->inlen_send);
3395 inlen = txq->inlen_mode;
3397 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE ||
3398 !vlan || txq->vlan_en) {
3400 * VLAN insertion will be done inside by HW.
3401 * It is not utmost effective - VLAN flag is
3402 * checked twice, but we should proceed the
3403 * inlining length correctly and take into
3404 * account the VLAN header being inserted.
3406 return mlx5_tx_packet_multi_send
3409 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3412 * Now we know the minimal amount of data is requested
3413 * to inline. Check whether we should inline the buffers
3414 * from the chain beginning to eliminate some mbufs.
3417 nxlen = rte_pktmbuf_data_len(mbuf);
3418 if (unlikely(nxlen <= txq->inlen_send)) {
3419 /* We can inline first mbuf at least. */
3420 if (nxlen < inlen) {
3423 /* Scan mbufs till inlen filled. */
3428 nxlen = rte_pktmbuf_data_len(mbuf);
3430 } while (unlikely(nxlen < inlen));
3431 if (unlikely(nxlen > txq->inlen_send)) {
3432 /* We cannot inline entire mbuf. */
3433 smlen = inlen - smlen;
3434 start = rte_pktmbuf_mtod_offset
3435 (mbuf, uintptr_t, smlen);
3442 /* There should be not end of packet. */
3444 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3445 } while (unlikely(nxlen < txq->inlen_send));
3447 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3449 * Check whether we can do inline to align start
3450 * address of data buffer to cacheline.
3453 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3454 if (unlikely(start)) {
3456 if (start <= txq->inlen_send)
3461 * Check whether there are enough free WQEBBs:
3463 * - Ethernet Segment
3464 * - First Segment of inlined Ethernet data
3465 * - ... data continued ...
3466 * - Data Segments of pointer/min inline type
3468 * Estimate the number of Data Segments conservatively,
3469 * supposing no any mbufs is being freed during inlining.
3471 MLX5_ASSERT(inlen <= txq->inlen_send);
3472 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3473 MLX5_ESEG_MIN_INLINE_SIZE +
3475 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3476 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3477 return MLX5_TXCMP_CODE_EXIT;
3478 /* Check for maximal WQE size. */
3479 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3480 return MLX5_TXCMP_CODE_ERROR;
3481 #ifdef MLX5_PMD_SOFT_COUNTERS
3482 /* Update sent data bytes/packets counters. */
3483 txq->stats.obytes += dlen + vlan;
3485 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3486 loc->wqe_last = wqe;
3487 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3488 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3489 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3490 txq->wqe_ci += (ds + 3) / 4;
3491 loc->wqe_free -= (ds + 3) / 4;
3492 return MLX5_TXCMP_CODE_MULTI;
3496 * Tx burst function for multi-segment packets. Supports all
3497 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3498 * sends one packet per WQE. Function stops sending if it
3499 * encounters the single-segment packet.
3501 * This routine is responsible for storing processed mbuf
3502 * into elts ring buffer and update elts_head.
3505 * Pointer to TX queue structure.
3507 * Packets to transmit.
3509 * Number of packets in array.
3511 * Pointer to burst routine local context.
3513 * Configured Tx offloads mask. It is fully defined at
3514 * compile time and may be used for optimization.
3517 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3518 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3519 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3520 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3521 * Local context variables updated.
3523 static __rte_always_inline enum mlx5_txcmp_code
3524 mlx5_tx_burst_mseg(struct mlx5_txq_data *__rte_restrict txq,
3525 struct rte_mbuf **__rte_restrict pkts,
3526 unsigned int pkts_n,
3527 struct mlx5_txq_local *__rte_restrict loc,
3530 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3531 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3532 pkts += loc->pkts_sent + 1;
3533 pkts_n -= loc->pkts_sent;
3535 enum mlx5_txcmp_code ret;
3537 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3539 * Estimate the number of free elts quickly but
3540 * conservatively. Some segment may be fully inlined
3541 * and freed, ignore this here - precise estimation
3544 if (loc->elts_free < NB_SEGS(loc->mbuf))
3545 return MLX5_TXCMP_CODE_EXIT;
3546 if (MLX5_TXOFF_CONFIG(TSO) &&
3547 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3548 /* Proceed with multi-segment TSO. */
3549 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3550 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3551 /* Proceed with multi-segment SEND with inlining. */
3552 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3554 /* Proceed with multi-segment SEND w/o inlining. */
3555 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3557 if (ret == MLX5_TXCMP_CODE_EXIT)
3558 return MLX5_TXCMP_CODE_EXIT;
3559 if (ret == MLX5_TXCMP_CODE_ERROR)
3560 return MLX5_TXCMP_CODE_ERROR;
3561 /* WQE is built, go to the next packet. */
3564 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3565 return MLX5_TXCMP_CODE_EXIT;
3566 loc->mbuf = *pkts++;
3568 rte_prefetch0(*pkts);
3569 if (likely(NB_SEGS(loc->mbuf) > 1))
3571 /* Here ends the series of multi-segment packets. */
3572 if (MLX5_TXOFF_CONFIG(TSO) &&
3573 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3574 return MLX5_TXCMP_CODE_TSO;
3575 return MLX5_TXCMP_CODE_SINGLE;
3581 * Tx burst function for single-segment packets with TSO.
3582 * Supports all types of Tx offloads, except multi-packets.
3583 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3584 * Function stops sending if it encounters the multi-segment
3585 * packet or packet without TSO requested.
3587 * The routine is responsible for storing processed mbuf
3588 * into elts ring buffer and update elts_head if inline
3589 * offloads is requested due to possible early freeing
3590 * of the inlined mbufs (can not store pkts array in elts
3594 * Pointer to TX queue structure.
3596 * Packets to transmit.
3598 * Number of packets in array.
3600 * Pointer to burst routine local context.
3602 * Configured Tx offloads mask. It is fully defined at
3603 * compile time and may be used for optimization.
3606 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3607 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3608 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3609 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3610 * Local context variables updated.
3612 static __rte_always_inline enum mlx5_txcmp_code
3613 mlx5_tx_burst_tso(struct mlx5_txq_data *__rte_restrict txq,
3614 struct rte_mbuf **__rte_restrict pkts,
3615 unsigned int pkts_n,
3616 struct mlx5_txq_local *__rte_restrict loc,
3619 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3620 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3621 pkts += loc->pkts_sent + 1;
3622 pkts_n -= loc->pkts_sent;
3624 struct mlx5_wqe_dseg *__rte_restrict dseg;
3625 struct mlx5_wqe *__rte_restrict wqe;
3626 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3629 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
3630 if (MLX5_TXOFF_CONFIG(TXPP)) {
3631 enum mlx5_txcmp_code wret;
3633 /* Generate WAIT for scheduling if requested. */
3634 wret = mlx5_tx_schedule_send(txq, loc, olx);
3635 if (wret == MLX5_TXCMP_CODE_EXIT)
3636 return MLX5_TXCMP_CODE_EXIT;
3637 if (wret == MLX5_TXCMP_CODE_ERROR)
3638 return MLX5_TXCMP_CODE_ERROR;
3640 dlen = rte_pktmbuf_data_len(loc->mbuf);
3641 if (MLX5_TXOFF_CONFIG(VLAN) &&
3642 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3643 vlan = sizeof(struct rte_vlan_hdr);
3646 * First calculate the WQE size to check
3647 * whether we have enough space in ring buffer.
3649 hlen = loc->mbuf->l2_len + vlan +
3650 loc->mbuf->l3_len + loc->mbuf->l4_len;
3651 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3652 return MLX5_TXCMP_CODE_ERROR;
3653 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3654 hlen += loc->mbuf->outer_l2_len +
3655 loc->mbuf->outer_l3_len;
3656 /* Segment must contain all TSO headers. */
3657 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3658 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3659 hlen > (dlen + vlan)))
3660 return MLX5_TXCMP_CODE_ERROR;
3662 * Check whether there are enough free WQEBBs:
3664 * - Ethernet Segment
3665 * - First Segment of inlined Ethernet data
3666 * - ... data continued ...
3667 * - Finishing Data Segment of pointer type
3669 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3670 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3671 if (loc->wqe_free < ((ds + 3) / 4))
3672 return MLX5_TXCMP_CODE_EXIT;
3673 #ifdef MLX5_PMD_SOFT_COUNTERS
3674 /* Update sent data bytes/packets counters. */
3675 ntcp = (dlen + vlan - hlen +
3676 loc->mbuf->tso_segsz - 1) /
3677 loc->mbuf->tso_segsz;
3679 * One will be added for mbuf itself at the end
3680 * of the mlx5_tx_burst from loc->pkts_sent field.
3683 txq->stats.opackets += ntcp;
3684 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3687 * Build the TSO WQE:
3689 * - Ethernet Segment with hlen bytes inlined
3690 * - Data Segment of pointer type
3692 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3693 loc->wqe_last = wqe;
3694 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3695 MLX5_OPCODE_TSO, olx);
3696 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3697 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3698 dlen -= hlen - vlan;
3699 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3701 * WQE is built, update the loop parameters
3702 * and go to the next packet.
3704 txq->wqe_ci += (ds + 3) / 4;
3705 loc->wqe_free -= (ds + 3) / 4;
3706 if (MLX5_TXOFF_CONFIG(INLINE))
3707 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3711 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3712 return MLX5_TXCMP_CODE_EXIT;
3713 loc->mbuf = *pkts++;
3715 rte_prefetch0(*pkts);
3716 if (MLX5_TXOFF_CONFIG(MULTI) &&
3717 unlikely(NB_SEGS(loc->mbuf) > 1))
3718 return MLX5_TXCMP_CODE_MULTI;
3719 if (likely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3720 return MLX5_TXCMP_CODE_SINGLE;
3721 /* Continue with the next TSO packet. */
3727 * Analyze the packet and select the best method to send.
3730 * Pointer to TX queue structure.
3732 * Pointer to burst routine local context.
3734 * Configured Tx offloads mask. It is fully defined at
3735 * compile time and may be used for optimization.
3737 * The predefined flag whether do complete check for
3738 * multi-segment packets and TSO.
3741 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3742 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3743 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3744 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3746 static __rte_always_inline enum mlx5_txcmp_code
3747 mlx5_tx_able_to_empw(struct mlx5_txq_data *__rte_restrict txq,
3748 struct mlx5_txq_local *__rte_restrict loc,
3752 /* Check for multi-segment packet. */
3754 MLX5_TXOFF_CONFIG(MULTI) &&
3755 unlikely(NB_SEGS(loc->mbuf) > 1))
3756 return MLX5_TXCMP_CODE_MULTI;
3757 /* Check for TSO packet. */
3759 MLX5_TXOFF_CONFIG(TSO) &&
3760 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3761 return MLX5_TXCMP_CODE_TSO;
3762 /* Check if eMPW is enabled at all. */
3763 if (!MLX5_TXOFF_CONFIG(EMPW))
3764 return MLX5_TXCMP_CODE_SINGLE;
3765 /* Check if eMPW can be engaged. */
3766 if (MLX5_TXOFF_CONFIG(VLAN) &&
3767 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3768 (!MLX5_TXOFF_CONFIG(INLINE) ||
3769 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3770 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3772 * eMPW does not support VLAN insertion offload,
3773 * we have to inline the entire packet but
3774 * packet is too long for inlining.
3776 return MLX5_TXCMP_CODE_SINGLE;
3778 return MLX5_TXCMP_CODE_EMPW;
3782 * Check the next packet attributes to match with the eMPW batch ones.
3783 * In addition, for legacy MPW the packet length is checked either.
3786 * Pointer to TX queue structure.
3788 * Pointer to Ethernet Segment of eMPW batch.
3790 * Pointer to burst routine local context.
3792 * Length of previous packet in MPW descriptor.
3794 * Configured Tx offloads mask. It is fully defined at
3795 * compile time and may be used for optimization.
3798 * true - packet match with eMPW batch attributes.
3799 * false - no match, eMPW should be restarted.
3801 static __rte_always_inline bool
3802 mlx5_tx_match_empw(struct mlx5_txq_data *__rte_restrict txq,
3803 struct mlx5_wqe_eseg *__rte_restrict es,
3804 struct mlx5_txq_local *__rte_restrict loc,
3808 uint8_t swp_flags = 0;
3810 /* Compare the checksum flags, if any. */
3811 if (MLX5_TXOFF_CONFIG(CSUM) &&
3812 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3814 /* Compare the Software Parser offsets and flags. */
3815 if (MLX5_TXOFF_CONFIG(SWP) &&
3816 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3817 es->swp_flags != swp_flags))
3819 /* Fill metadata field if needed. */
3820 if (MLX5_TXOFF_CONFIG(METADATA) &&
3821 es->metadata != (loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
3822 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0))
3824 /* Legacy MPW can send packets with the same lengt only. */
3825 if (MLX5_TXOFF_CONFIG(MPW) &&
3826 dlen != rte_pktmbuf_data_len(loc->mbuf))
3828 /* There must be no VLAN packets in eMPW loop. */
3829 if (MLX5_TXOFF_CONFIG(VLAN))
3830 MLX5_ASSERT(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3831 /* Check if the scheduling is requested. */
3832 if (MLX5_TXOFF_CONFIG(TXPP) &&
3833 loc->mbuf->ol_flags & txq->ts_mask)
3839 * Update send loop variables and WQE for eMPW loop
3840 * without data inlining. Number of Data Segments is
3841 * equal to the number of sent packets.
3844 * Pointer to TX queue structure.
3846 * Pointer to burst routine local context.
3848 * Number of packets/Data Segments/Packets.
3850 * Accumulated statistics, bytes sent
3852 * Configured Tx offloads mask. It is fully defined at
3853 * compile time and may be used for optimization.
3856 * true - packet match with eMPW batch attributes.
3857 * false - no match, eMPW should be restarted.
3859 static __rte_always_inline void
3860 mlx5_tx_sdone_empw(struct mlx5_txq_data *__rte_restrict txq,
3861 struct mlx5_txq_local *__rte_restrict loc,
3864 unsigned int olx __rte_unused)
3866 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
3867 #ifdef MLX5_PMD_SOFT_COUNTERS
3868 /* Update sent data bytes counter. */
3869 txq->stats.obytes += slen;
3873 loc->elts_free -= ds;
3874 loc->pkts_sent += ds;
3876 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3877 txq->wqe_ci += (ds + 3) / 4;
3878 loc->wqe_free -= (ds + 3) / 4;
3882 * Update send loop variables and WQE for eMPW loop
3883 * with data inlining. Gets the size of pushed descriptors
3884 * and data to the WQE.
3887 * Pointer to TX queue structure.
3889 * Pointer to burst routine local context.
3891 * Total size of descriptor/data in bytes.
3893 * Accumulated statistics, data bytes sent.
3895 * The base WQE for the eMPW/MPW descriptor.
3897 * Configured Tx offloads mask. It is fully defined at
3898 * compile time and may be used for optimization.
3901 * true - packet match with eMPW batch attributes.
3902 * false - no match, eMPW should be restarted.
3904 static __rte_always_inline void
3905 mlx5_tx_idone_empw(struct mlx5_txq_data *__rte_restrict txq,
3906 struct mlx5_txq_local *__rte_restrict loc,
3909 struct mlx5_wqe *__rte_restrict wqem,
3910 unsigned int olx __rte_unused)
3912 struct mlx5_wqe_dseg *dseg = &wqem->dseg[0];
3914 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3915 #ifdef MLX5_PMD_SOFT_COUNTERS
3916 /* Update sent data bytes counter. */
3917 txq->stats.obytes += slen;
3921 if (MLX5_TXOFF_CONFIG(MPW) && dseg->bcount == RTE_BE32(0)) {
3923 * If the legacy MPW session contains the inline packets
3924 * we should set the only inline data segment length
3925 * and align the total length to the segment size.
3927 MLX5_ASSERT(len > sizeof(dseg->bcount));
3928 dseg->bcount = rte_cpu_to_be_32((len - sizeof(dseg->bcount)) |
3929 MLX5_ETH_WQE_DATA_INLINE);
3930 len = (len + MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE + 2;
3933 * The session is not legacy MPW or contains the
3934 * data buffer pointer segments.
3936 MLX5_ASSERT((len % MLX5_WSEG_SIZE) == 0);
3937 len = len / MLX5_WSEG_SIZE + 2;
3939 wqem->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
3940 txq->wqe_ci += (len + 3) / 4;
3941 loc->wqe_free -= (len + 3) / 4;
3942 loc->wqe_last = wqem;
3946 * The set of Tx burst functions for single-segment packets
3947 * without TSO and with Multi-Packet Writing feature support.
3948 * Supports all types of Tx offloads, except multi-packets
3951 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
3952 * as many packet per WQE as it can. If eMPW is not configured
3953 * or packet can not be sent with eMPW (VLAN insertion) the
3954 * ordinary SEND opcode is used and only one packet placed
3957 * Functions stop sending if it encounters the multi-segment
3958 * packet or packet with TSO requested.
3960 * The routines are responsible for storing processed mbuf
3961 * into elts ring buffer and update elts_head if inlining
3962 * offload is requested. Otherwise the copying mbufs to elts
3963 * can be postponed and completed at the end of burst routine.
3966 * Pointer to TX queue structure.
3968 * Packets to transmit.
3970 * Number of packets in array.
3972 * Pointer to burst routine local context.
3974 * Configured Tx offloads mask. It is fully defined at
3975 * compile time and may be used for optimization.
3978 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3979 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3980 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3981 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
3982 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
3983 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
3985 * Local context variables updated.
3988 * The routine sends packets with MLX5_OPCODE_EMPW
3989 * without inlining, this is dedicated optimized branch.
3990 * No VLAN insertion is supported.
3992 static __rte_always_inline enum mlx5_txcmp_code
3993 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *__rte_restrict txq,
3994 struct rte_mbuf **__rte_restrict pkts,
3995 unsigned int pkts_n,
3996 struct mlx5_txq_local *__rte_restrict loc,
4000 * Subroutine is the part of mlx5_tx_burst_single()
4001 * and sends single-segment packet with eMPW opcode
4002 * without data inlining.
4004 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4005 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4006 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4007 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4008 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
4009 pkts += loc->pkts_sent + 1;
4010 pkts_n -= loc->pkts_sent;
4012 struct mlx5_wqe_dseg *__rte_restrict dseg;
4013 struct mlx5_wqe_eseg *__rte_restrict eseg;
4014 enum mlx5_txcmp_code ret;
4015 unsigned int part, loop;
4016 unsigned int slen = 0;
4019 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4020 if (MLX5_TXOFF_CONFIG(TXPP)) {
4021 enum mlx5_txcmp_code wret;
4023 /* Generate WAIT for scheduling if requested. */
4024 wret = mlx5_tx_schedule_send(txq, loc, olx);
4025 if (wret == MLX5_TXCMP_CODE_EXIT)
4026 return MLX5_TXCMP_CODE_EXIT;
4027 if (wret == MLX5_TXCMP_CODE_ERROR)
4028 return MLX5_TXCMP_CODE_ERROR;
4030 part = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4031 MLX5_MPW_MAX_PACKETS :
4032 MLX5_EMPW_MAX_PACKETS);
4033 if (unlikely(loc->elts_free < part)) {
4034 /* We have no enough elts to save all mbufs. */
4035 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
4036 return MLX5_TXCMP_CODE_EXIT;
4037 /* But we still able to send at least minimal eMPW. */
4038 part = loc->elts_free;
4040 /* Check whether we have enough WQEs */
4041 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
4042 if (unlikely(loc->wqe_free <
4043 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4044 return MLX5_TXCMP_CODE_EXIT;
4045 part = (loc->wqe_free * 4) - 2;
4047 if (likely(part > 1))
4048 rte_prefetch0(*pkts);
4049 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4051 * Build eMPW title WQEBB:
4052 * - Control Segment, eMPW opcode
4053 * - Ethernet Segment, no inline
4055 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
4056 MLX5_OPCODE_ENHANCED_MPSW, olx);
4057 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
4058 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4059 eseg = &loc->wqe_last->eseg;
4060 dseg = &loc->wqe_last->dseg[0];
4062 /* Store the packet length for legacy MPW. */
4063 if (MLX5_TXOFF_CONFIG(MPW))
4064 eseg->mss = rte_cpu_to_be_16
4065 (rte_pktmbuf_data_len(loc->mbuf));
4067 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4068 #ifdef MLX5_PMD_SOFT_COUNTERS
4069 /* Update sent data bytes counter. */
4074 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4076 if (unlikely(--loop == 0))
4078 loc->mbuf = *pkts++;
4079 if (likely(loop > 1))
4080 rte_prefetch0(*pkts);
4081 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4083 * Unroll the completion code to avoid
4084 * returning variable value - it results in
4085 * unoptimized sequent checking in caller.
4087 if (ret == MLX5_TXCMP_CODE_MULTI) {
4089 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4090 if (unlikely(!loc->elts_free ||
4092 return MLX5_TXCMP_CODE_EXIT;
4093 return MLX5_TXCMP_CODE_MULTI;
4095 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4096 if (ret == MLX5_TXCMP_CODE_TSO) {
4098 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4099 if (unlikely(!loc->elts_free ||
4101 return MLX5_TXCMP_CODE_EXIT;
4102 return MLX5_TXCMP_CODE_TSO;
4104 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4106 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4107 if (unlikely(!loc->elts_free ||
4109 return MLX5_TXCMP_CODE_EXIT;
4110 return MLX5_TXCMP_CODE_SINGLE;
4112 if (ret != MLX5_TXCMP_CODE_EMPW) {
4115 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4116 return MLX5_TXCMP_CODE_ERROR;
4119 * Check whether packet parameters coincide
4120 * within assumed eMPW batch:
4121 * - check sum settings
4123 * - software parser settings
4124 * - packets length (legacy MPW only)
4125 * - scheduling is not required
4127 if (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx)) {
4130 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4131 if (unlikely(!loc->elts_free ||
4133 return MLX5_TXCMP_CODE_EXIT;
4137 /* Packet attributes match, continue the same eMPW. */
4139 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4140 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4142 /* eMPW is built successfully, update loop parameters. */
4144 MLX5_ASSERT(pkts_n >= part);
4145 #ifdef MLX5_PMD_SOFT_COUNTERS
4146 /* Update sent data bytes counter. */
4147 txq->stats.obytes += slen;
4149 loc->elts_free -= part;
4150 loc->pkts_sent += part;
4151 txq->wqe_ci += (2 + part + 3) / 4;
4152 loc->wqe_free -= (2 + part + 3) / 4;
4154 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4155 return MLX5_TXCMP_CODE_EXIT;
4156 loc->mbuf = *pkts++;
4157 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4158 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
4160 /* Continue sending eMPW batches. */
4166 * The routine sends packets with MLX5_OPCODE_EMPW
4167 * with inlining, optionally supports VLAN insertion.
4169 static __rte_always_inline enum mlx5_txcmp_code
4170 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,
4171 struct rte_mbuf **__rte_restrict pkts,
4172 unsigned int pkts_n,
4173 struct mlx5_txq_local *__rte_restrict loc,
4177 * Subroutine is the part of mlx5_tx_burst_single()
4178 * and sends single-segment packet with eMPW opcode
4179 * with data inlining.
4181 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4182 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4183 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4184 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4185 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
4186 pkts += loc->pkts_sent + 1;
4187 pkts_n -= loc->pkts_sent;
4189 struct mlx5_wqe_dseg *__rte_restrict dseg;
4190 struct mlx5_wqe *__rte_restrict wqem;
4191 enum mlx5_txcmp_code ret;
4192 unsigned int room, part, nlim;
4193 unsigned int slen = 0;
4195 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4196 if (MLX5_TXOFF_CONFIG(TXPP)) {
4197 enum mlx5_txcmp_code wret;
4199 /* Generate WAIT for scheduling if requested. */
4200 wret = mlx5_tx_schedule_send(txq, loc, olx);
4201 if (wret == MLX5_TXCMP_CODE_EXIT)
4202 return MLX5_TXCMP_CODE_EXIT;
4203 if (wret == MLX5_TXCMP_CODE_ERROR)
4204 return MLX5_TXCMP_CODE_ERROR;
4207 * Limits the amount of packets in one WQE
4208 * to improve CQE latency generation.
4210 nlim = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4211 MLX5_MPW_INLINE_MAX_PACKETS :
4212 MLX5_EMPW_MAX_PACKETS);
4213 /* Check whether we have minimal amount WQEs */
4214 if (unlikely(loc->wqe_free <
4215 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4216 return MLX5_TXCMP_CODE_EXIT;
4217 if (likely(pkts_n > 1))
4218 rte_prefetch0(*pkts);
4219 wqem = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4221 * Build eMPW title WQEBB:
4222 * - Control Segment, eMPW opcode, zero DS
4223 * - Ethernet Segment, no inline
4225 mlx5_tx_cseg_init(txq, loc, wqem, 0,
4226 MLX5_OPCODE_ENHANCED_MPSW, olx);
4227 mlx5_tx_eseg_none(txq, loc, wqem,
4228 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4229 dseg = &wqem->dseg[0];
4230 /* Store the packet length for legacy MPW. */
4231 if (MLX5_TXOFF_CONFIG(MPW))
4232 wqem->eseg.mss = rte_cpu_to_be_16
4233 (rte_pktmbuf_data_len(loc->mbuf));
4234 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
4235 loc->wqe_free) * MLX5_WQE_SIZE -
4236 MLX5_WQE_CSEG_SIZE -
4238 /* Limit the room for legacy MPW sessions for performance. */
4239 if (MLX5_TXOFF_CONFIG(MPW))
4240 room = RTE_MIN(room,
4241 RTE_MAX(txq->inlen_empw +
4242 sizeof(dseg->bcount) +
4243 (MLX5_TXOFF_CONFIG(VLAN) ?
4244 sizeof(struct rte_vlan_hdr) : 0),
4245 MLX5_MPW_INLINE_MAX_PACKETS *
4246 MLX5_WQE_DSEG_SIZE));
4247 /* Build WQE till we have space, packets and resources. */
4250 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4251 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
4254 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4255 MLX5_ASSERT((room % MLX5_WQE_DSEG_SIZE) == 0);
4256 MLX5_ASSERT((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
4258 * Some Tx offloads may cause an error if
4259 * packet is not long enough, check against
4260 * assumed minimal length.
4262 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
4264 if (unlikely(!part))
4265 return MLX5_TXCMP_CODE_ERROR;
4267 * We have some successfully built
4268 * packet Data Segments to send.
4270 mlx5_tx_idone_empw(txq, loc, part,
4272 return MLX5_TXCMP_CODE_ERROR;
4274 /* Inline or not inline - that's the Question. */
4275 if (dlen > txq->inlen_empw ||
4276 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE)
4278 if (MLX5_TXOFF_CONFIG(MPW)) {
4279 if (dlen > txq->inlen_send)
4283 /* Open new inline MPW session. */
4284 tlen += sizeof(dseg->bcount);
4285 dseg->bcount = RTE_BE32(0);
4287 (dseg, sizeof(dseg->bcount));
4290 * No pointer and inline descriptor
4291 * intermix for legacy MPW sessions.
4293 if (wqem->dseg[0].bcount)
4297 tlen = sizeof(dseg->bcount) + dlen;
4299 /* Inline entire packet, optional VLAN insertion. */
4300 if (MLX5_TXOFF_CONFIG(VLAN) &&
4301 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4303 * The packet length must be checked in
4304 * mlx5_tx_able_to_empw() and packet
4305 * fits into inline length guaranteed.
4308 sizeof(struct rte_vlan_hdr)) <=
4310 tlen += sizeof(struct rte_vlan_hdr);
4313 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
4315 #ifdef MLX5_PMD_SOFT_COUNTERS
4316 /* Update sent data bytes counter. */
4317 slen += sizeof(struct rte_vlan_hdr);
4322 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
4325 if (!MLX5_TXOFF_CONFIG(MPW))
4326 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
4327 MLX5_ASSERT(room >= tlen);
4330 * Packet data are completely inlined,
4331 * free the packet immediately.
4333 rte_pktmbuf_free_seg(loc->mbuf);
4337 * No pointer and inline descriptor
4338 * intermix for legacy MPW sessions.
4340 if (MLX5_TXOFF_CONFIG(MPW) &&
4342 wqem->dseg[0].bcount == RTE_BE32(0))
4345 * Not inlinable VLAN packets are
4346 * proceeded outside of this routine.
4348 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4349 if (MLX5_TXOFF_CONFIG(VLAN))
4350 MLX5_ASSERT(!(loc->mbuf->ol_flags &
4352 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
4353 /* We have to store mbuf in elts.*/
4354 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4355 room -= MLX5_WQE_DSEG_SIZE;
4356 /* Ring buffer wraparound is checked at the loop end.*/
4359 #ifdef MLX5_PMD_SOFT_COUNTERS
4360 /* Update sent data bytes counter. */
4366 if (unlikely(!pkts_n || !loc->elts_free)) {
4368 * We have no resources/packets to
4369 * continue build descriptors.
4372 mlx5_tx_idone_empw(txq, loc, part,
4374 return MLX5_TXCMP_CODE_EXIT;
4376 loc->mbuf = *pkts++;
4377 if (likely(pkts_n > 1))
4378 rte_prefetch0(*pkts);
4379 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4381 * Unroll the completion code to avoid
4382 * returning variable value - it results in
4383 * unoptimized sequent checking in caller.
4385 if (ret == MLX5_TXCMP_CODE_MULTI) {
4387 mlx5_tx_idone_empw(txq, loc, part,
4389 if (unlikely(!loc->elts_free ||
4391 return MLX5_TXCMP_CODE_EXIT;
4392 return MLX5_TXCMP_CODE_MULTI;
4394 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4395 if (ret == MLX5_TXCMP_CODE_TSO) {
4397 mlx5_tx_idone_empw(txq, loc, part,
4399 if (unlikely(!loc->elts_free ||
4401 return MLX5_TXCMP_CODE_EXIT;
4402 return MLX5_TXCMP_CODE_TSO;
4404 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4406 mlx5_tx_idone_empw(txq, loc, part,
4408 if (unlikely(!loc->elts_free ||
4410 return MLX5_TXCMP_CODE_EXIT;
4411 return MLX5_TXCMP_CODE_SINGLE;
4413 if (ret != MLX5_TXCMP_CODE_EMPW) {
4416 mlx5_tx_idone_empw(txq, loc, part,
4418 return MLX5_TXCMP_CODE_ERROR;
4420 /* Check if we have minimal room left. */
4422 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE))
4425 * Check whether packet parameters coincide
4426 * within assumed eMPW batch:
4427 * - check sum settings
4429 * - software parser settings
4430 * - packets length (legacy MPW only)
4431 * - scheduling is not required
4433 if (!mlx5_tx_match_empw(txq, &wqem->eseg,
4436 /* Packet attributes match, continue the same eMPW. */
4437 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4438 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4441 * We get here to close an existing eMPW
4442 * session and start the new one.
4444 MLX5_ASSERT(pkts_n);
4446 if (unlikely(!part))
4447 return MLX5_TXCMP_CODE_EXIT;
4448 mlx5_tx_idone_empw(txq, loc, part, slen, wqem, olx);
4449 if (unlikely(!loc->elts_free ||
4451 return MLX5_TXCMP_CODE_EXIT;
4452 /* Continue the loop with new eMPW session. */
4458 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4459 * Data inlining and VLAN insertion are supported.
4461 static __rte_always_inline enum mlx5_txcmp_code
4462 mlx5_tx_burst_single_send(struct mlx5_txq_data *__rte_restrict txq,
4463 struct rte_mbuf **__rte_restrict pkts,
4464 unsigned int pkts_n,
4465 struct mlx5_txq_local *__rte_restrict loc,
4469 * Subroutine is the part of mlx5_tx_burst_single()
4470 * and sends single-segment packet with SEND opcode.
4472 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4473 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4474 pkts += loc->pkts_sent + 1;
4475 pkts_n -= loc->pkts_sent;
4477 struct mlx5_wqe *__rte_restrict wqe;
4478 enum mlx5_txcmp_code ret;
4480 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4481 if (MLX5_TXOFF_CONFIG(TXPP)) {
4482 enum mlx5_txcmp_code wret;
4484 /* Generate WAIT for scheduling if requested. */
4485 wret = mlx5_tx_schedule_send(txq, loc, olx);
4486 if (wret == MLX5_TXCMP_CODE_EXIT)
4487 return MLX5_TXCMP_CODE_EXIT;
4488 if (wret == MLX5_TXCMP_CODE_ERROR)
4489 return MLX5_TXCMP_CODE_ERROR;
4491 if (MLX5_TXOFF_CONFIG(INLINE)) {
4492 unsigned int inlen, vlan = 0;
4494 inlen = rte_pktmbuf_data_len(loc->mbuf);
4495 if (MLX5_TXOFF_CONFIG(VLAN) &&
4496 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4497 vlan = sizeof(struct rte_vlan_hdr);
4499 static_assert((sizeof(struct rte_vlan_hdr) +
4500 sizeof(struct rte_ether_hdr)) ==
4501 MLX5_ESEG_MIN_INLINE_SIZE,
4502 "invalid min inline data size");
4505 * If inlining is enabled at configuration time
4506 * the limit must be not less than minimal size.
4507 * Otherwise we would do extra check for data
4508 * size to avoid crashes due to length overflow.
4510 MLX5_ASSERT(txq->inlen_send >=
4511 MLX5_ESEG_MIN_INLINE_SIZE);
4512 if (inlen <= txq->inlen_send) {
4513 unsigned int seg_n, wqe_n;
4515 rte_prefetch0(rte_pktmbuf_mtod
4516 (loc->mbuf, uint8_t *));
4517 /* Check against minimal length. */
4518 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4519 return MLX5_TXCMP_CODE_ERROR;
4520 if (loc->mbuf->ol_flags &
4521 PKT_TX_DYNF_NOINLINE) {
4523 * The hint flag not to inline packet
4524 * data is set. Check whether we can
4527 if ((!MLX5_TXOFF_CONFIG(EMPW) &&
4529 (MLX5_TXOFF_CONFIG(MPW) &&
4531 if (inlen <= txq->inlen_send)
4534 * The hardware requires the
4535 * minimal inline data header.
4537 goto single_min_inline;
4539 if (MLX5_TXOFF_CONFIG(VLAN) &&
4540 vlan && !txq->vlan_en) {
4542 * We must insert VLAN tag
4543 * by software means.
4545 goto single_part_inline;
4547 goto single_no_inline;
4551 * Completely inlined packet data WQE:
4552 * - Control Segment, SEND opcode
4553 * - Ethernet Segment, no VLAN insertion
4554 * - Data inlined, VLAN optionally inserted
4555 * - Alignment to MLX5_WSEG_SIZE
4556 * Have to estimate amount of WQEBBs
4558 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4559 MLX5_ESEG_MIN_INLINE_SIZE +
4560 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4561 /* Check if there are enough WQEBBs. */
4562 wqe_n = (seg_n + 3) / 4;
4563 if (wqe_n > loc->wqe_free)
4564 return MLX5_TXCMP_CODE_EXIT;
4565 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4566 loc->wqe_last = wqe;
4567 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4568 MLX5_OPCODE_SEND, olx);
4569 mlx5_tx_eseg_data(txq, loc, wqe,
4570 vlan, inlen, 0, olx);
4571 txq->wqe_ci += wqe_n;
4572 loc->wqe_free -= wqe_n;
4574 * Packet data are completely inlined,
4575 * free the packet immediately.
4577 rte_pktmbuf_free_seg(loc->mbuf);
4578 } else if ((!MLX5_TXOFF_CONFIG(EMPW) ||
4579 MLX5_TXOFF_CONFIG(MPW)) &&
4582 * If minimal inlining is requested the eMPW
4583 * feature should be disabled due to data is
4584 * inlined into Ethernet Segment, which can
4585 * not contain inlined data for eMPW due to
4586 * segment shared for all packets.
4588 struct mlx5_wqe_dseg *__rte_restrict dseg;
4593 * The inline-mode settings require
4594 * to inline the specified amount of
4595 * data bytes to the Ethernet Segment.
4596 * We should check the free space in
4597 * WQE ring buffer to inline partially.
4600 MLX5_ASSERT(txq->inlen_send >= txq->inlen_mode);
4601 MLX5_ASSERT(inlen > txq->inlen_mode);
4602 MLX5_ASSERT(txq->inlen_mode >=
4603 MLX5_ESEG_MIN_INLINE_SIZE);
4605 * Check whether there are enough free WQEBBs:
4607 * - Ethernet Segment
4608 * - First Segment of inlined Ethernet data
4609 * - ... data continued ...
4610 * - Finishing Data Segment of pointer type
4612 ds = (MLX5_WQE_CSEG_SIZE +
4613 MLX5_WQE_ESEG_SIZE +
4614 MLX5_WQE_DSEG_SIZE +
4616 MLX5_ESEG_MIN_INLINE_SIZE +
4617 MLX5_WQE_DSEG_SIZE +
4618 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4619 if (loc->wqe_free < ((ds + 3) / 4))
4620 return MLX5_TXCMP_CODE_EXIT;
4622 * Build the ordinary SEND WQE:
4624 * - Ethernet Segment, inline inlen_mode bytes
4625 * - Data Segment of pointer type
4627 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4628 loc->wqe_last = wqe;
4629 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4630 MLX5_OPCODE_SEND, olx);
4631 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4634 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4635 txq->inlen_mode - vlan;
4636 inlen -= txq->inlen_mode;
4637 mlx5_tx_dseg_ptr(txq, loc, dseg,
4640 * WQE is built, update the loop parameters
4641 * and got to the next packet.
4643 txq->wqe_ci += (ds + 3) / 4;
4644 loc->wqe_free -= (ds + 3) / 4;
4645 /* We have to store mbuf in elts.*/
4646 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4647 txq->elts[txq->elts_head++ & txq->elts_m] =
4655 * Partially inlined packet data WQE, we have
4656 * some space in title WQEBB, we can fill it
4657 * with some packet data. It takes one WQEBB,
4658 * it is available, no extra space check:
4659 * - Control Segment, SEND opcode
4660 * - Ethernet Segment, no VLAN insertion
4661 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4662 * - Data Segment, pointer type
4664 * We also get here if VLAN insertion is not
4665 * supported by HW, the inline is enabled.
4668 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4669 loc->wqe_last = wqe;
4670 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4671 MLX5_OPCODE_SEND, olx);
4672 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4673 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4674 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4676 * The length check is performed above, by
4677 * comparing with txq->inlen_send. We should
4678 * not get overflow here.
4680 MLX5_ASSERT(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4681 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4682 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4686 /* We have to store mbuf in elts.*/
4687 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4688 txq->elts[txq->elts_head++ & txq->elts_m] =
4692 #ifdef MLX5_PMD_SOFT_COUNTERS
4693 /* Update sent data bytes counter. */
4694 txq->stats.obytes += vlan +
4695 rte_pktmbuf_data_len(loc->mbuf);
4699 * No inline at all, it means the CPU cycles saving
4700 * is prioritized at configuration, we should not
4701 * copy any packet data to WQE.
4703 * SEND WQE, one WQEBB:
4704 * - Control Segment, SEND opcode
4705 * - Ethernet Segment, optional VLAN, no inline
4706 * - Data Segment, pointer type
4709 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4710 loc->wqe_last = wqe;
4711 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4712 MLX5_OPCODE_SEND, olx);
4713 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4715 (txq, loc, &wqe->dseg[0],
4716 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4717 rte_pktmbuf_data_len(loc->mbuf), olx);
4721 * We should not store mbuf pointer in elts
4722 * if no inlining is configured, this is done
4723 * by calling routine in a batch copy.
4725 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4727 #ifdef MLX5_PMD_SOFT_COUNTERS
4728 /* Update sent data bytes counter. */
4729 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4730 if (MLX5_TXOFF_CONFIG(VLAN) &&
4731 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4732 txq->stats.obytes +=
4733 sizeof(struct rte_vlan_hdr);
4738 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4739 return MLX5_TXCMP_CODE_EXIT;
4740 loc->mbuf = *pkts++;
4742 rte_prefetch0(*pkts);
4743 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4744 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4750 static __rte_always_inline enum mlx5_txcmp_code
4751 mlx5_tx_burst_single(struct mlx5_txq_data *__rte_restrict txq,
4752 struct rte_mbuf **__rte_restrict pkts,
4753 unsigned int pkts_n,
4754 struct mlx5_txq_local *__rte_restrict loc,
4757 enum mlx5_txcmp_code ret;
4759 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4760 if (ret == MLX5_TXCMP_CODE_SINGLE)
4762 MLX5_ASSERT(ret == MLX5_TXCMP_CODE_EMPW);
4764 /* Optimize for inline/no inline eMPW send. */
4765 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4766 mlx5_tx_burst_empw_inline
4767 (txq, pkts, pkts_n, loc, olx) :
4768 mlx5_tx_burst_empw_simple
4769 (txq, pkts, pkts_n, loc, olx);
4770 if (ret != MLX5_TXCMP_CODE_SINGLE)
4772 /* The resources to send one packet should remain. */
4773 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4775 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4776 MLX5_ASSERT(ret != MLX5_TXCMP_CODE_SINGLE);
4777 if (ret != MLX5_TXCMP_CODE_EMPW)
4779 /* The resources to send one packet should remain. */
4780 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4785 * DPDK Tx callback template. This is configured template
4786 * used to generate routines optimized for specified offload setup.
4787 * One of this generated functions is chosen at SQ configuration
4791 * Generic pointer to TX queue structure.
4793 * Packets to transmit.
4795 * Number of packets in array.
4797 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4798 * values. Should be static to take compile time static configuration
4802 * Number of packets successfully transmitted (<= pkts_n).
4804 static __rte_always_inline uint16_t
4805 mlx5_tx_burst_tmpl(struct mlx5_txq_data *__rte_restrict txq,
4806 struct rte_mbuf **__rte_restrict pkts,
4810 struct mlx5_txq_local loc;
4811 enum mlx5_txcmp_code ret;
4814 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4815 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4816 if (unlikely(!pkts_n))
4820 loc.wqe_last = NULL;
4823 loc.pkts_loop = loc.pkts_sent;
4825 * Check if there are some CQEs, if any:
4826 * - process an encountered errors
4827 * - process the completed WQEs
4828 * - free related mbufs
4829 * - doorbell the NIC about processed CQEs
4831 rte_prefetch0(*(pkts + loc.pkts_sent));
4832 mlx5_tx_handle_completion(txq, olx);
4834 * Calculate the number of available resources - elts and WQEs.
4835 * There are two possible different scenarios:
4836 * - no data inlining into WQEs, one WQEBB may contains up to
4837 * four packets, in this case elts become scarce resource
4838 * - data inlining into WQEs, one packet may require multiple
4839 * WQEBBs, the WQEs become the limiting factor.
4841 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4842 loc.elts_free = txq->elts_s -
4843 (uint16_t)(txq->elts_head - txq->elts_tail);
4844 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4845 loc.wqe_free = txq->wqe_s -
4846 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4847 if (unlikely(!loc.elts_free || !loc.wqe_free))
4851 * Fetch the packet from array. Usually this is
4852 * the first packet in series of multi/single
4855 loc.mbuf = *(pkts + loc.pkts_sent);
4856 /* Dedicated branch for multi-segment packets. */
4857 if (MLX5_TXOFF_CONFIG(MULTI) &&
4858 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4860 * Multi-segment packet encountered.
4861 * Hardware is able to process it only
4862 * with SEND/TSO opcodes, one packet
4863 * per WQE, do it in dedicated routine.
4866 MLX5_ASSERT(loc.pkts_sent >= loc.pkts_copy);
4867 part = loc.pkts_sent - loc.pkts_copy;
4868 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4870 * There are some single-segment mbufs not
4871 * stored in elts. The mbufs must be in the
4872 * same order as WQEs, so we must copy the
4873 * mbufs to elts here, before the coming
4874 * multi-segment packet mbufs is appended.
4876 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
4878 loc.pkts_copy = loc.pkts_sent;
4880 MLX5_ASSERT(pkts_n > loc.pkts_sent);
4881 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
4882 if (!MLX5_TXOFF_CONFIG(INLINE))
4883 loc.pkts_copy = loc.pkts_sent;
4885 * These returned code checks are supposed
4886 * to be optimized out due to routine inlining.
4888 if (ret == MLX5_TXCMP_CODE_EXIT) {
4890 * The routine returns this code when
4891 * all packets are sent or there is no
4892 * enough resources to complete request.
4896 if (ret == MLX5_TXCMP_CODE_ERROR) {
4898 * The routine returns this code when
4899 * some error in the incoming packets
4902 txq->stats.oerrors++;
4905 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4907 * The single-segment packet was encountered
4908 * in the array, try to send it with the
4909 * best optimized way, possible engaging eMPW.
4911 goto enter_send_single;
4913 if (MLX5_TXOFF_CONFIG(TSO) &&
4914 ret == MLX5_TXCMP_CODE_TSO) {
4916 * The single-segment TSO packet was
4917 * encountered in the array.
4919 goto enter_send_tso;
4921 /* We must not get here. Something is going wrong. */
4923 txq->stats.oerrors++;
4926 /* Dedicated branch for single-segment TSO packets. */
4927 if (MLX5_TXOFF_CONFIG(TSO) &&
4928 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
4930 * TSO might require special way for inlining
4931 * (dedicated parameters) and is sent with
4932 * MLX5_OPCODE_TSO opcode only, provide this
4933 * in dedicated branch.
4936 MLX5_ASSERT(NB_SEGS(loc.mbuf) == 1);
4937 MLX5_ASSERT(pkts_n > loc.pkts_sent);
4938 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
4940 * These returned code checks are supposed
4941 * to be optimized out due to routine inlining.
4943 if (ret == MLX5_TXCMP_CODE_EXIT)
4945 if (ret == MLX5_TXCMP_CODE_ERROR) {
4946 txq->stats.oerrors++;
4949 if (ret == MLX5_TXCMP_CODE_SINGLE)
4950 goto enter_send_single;
4951 if (MLX5_TXOFF_CONFIG(MULTI) &&
4952 ret == MLX5_TXCMP_CODE_MULTI) {
4954 * The multi-segment packet was
4955 * encountered in the array.
4957 goto enter_send_multi;
4959 /* We must not get here. Something is going wrong. */
4961 txq->stats.oerrors++;
4965 * The dedicated branch for the single-segment packets
4966 * without TSO. Often these ones can be sent using
4967 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
4968 * The routine builds the WQEs till it encounters
4969 * the TSO or multi-segment packet (in case if these
4970 * offloads are requested at SQ configuration time).
4973 MLX5_ASSERT(pkts_n > loc.pkts_sent);
4974 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
4976 * These returned code checks are supposed
4977 * to be optimized out due to routine inlining.
4979 if (ret == MLX5_TXCMP_CODE_EXIT)
4981 if (ret == MLX5_TXCMP_CODE_ERROR) {
4982 txq->stats.oerrors++;
4985 if (MLX5_TXOFF_CONFIG(MULTI) &&
4986 ret == MLX5_TXCMP_CODE_MULTI) {
4988 * The multi-segment packet was
4989 * encountered in the array.
4991 goto enter_send_multi;
4993 if (MLX5_TXOFF_CONFIG(TSO) &&
4994 ret == MLX5_TXCMP_CODE_TSO) {
4996 * The single-segment TSO packet was
4997 * encountered in the array.
4999 goto enter_send_tso;
5001 /* We must not get here. Something is going wrong. */
5003 txq->stats.oerrors++;
5007 * Main Tx loop is completed, do the rest:
5008 * - set completion request if thresholds are reached
5009 * - doorbell the hardware
5010 * - copy the rest of mbufs to elts (if any)
5012 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE) ||
5013 loc.pkts_sent >= loc.pkts_copy);
5014 /* Take a shortcut if nothing is sent. */
5015 if (unlikely(loc.pkts_sent == loc.pkts_loop))
5017 /* Request CQE generation if limits are reached. */
5018 mlx5_tx_request_completion(txq, &loc, olx);
5020 * Ring QP doorbell immediately after WQE building completion
5021 * to improve latencies. The pure software related data treatment
5022 * can be completed after doorbell. Tx CQEs for this SQ are
5023 * processed in this thread only by the polling.
5025 * The rdma core library can map doorbell register in two ways,
5026 * depending on the environment variable "MLX5_SHUT_UP_BF":
5028 * - as regular cached memory, the variable is either missing or
5029 * set to zero. This type of mapping may cause the significant
5030 * doorbell register writing latency and requires explicit
5031 * memory write barrier to mitigate this issue and prevent
5034 * - as non-cached memory, the variable is present and set to
5035 * not "0" value. This type of mapping may cause performance
5036 * impact under heavy loading conditions but the explicit write
5037 * memory barrier is not required and it may improve core
5040 * - the legacy behaviour (prior 19.08 release) was to use some
5041 * heuristics to decide whether write memory barrier should
5042 * be performed. This behavior is supported with specifying
5043 * tx_db_nc=2, write barrier is skipped if application
5044 * provides the full recommended burst of packets, it
5045 * supposes the next packets are coming and the write barrier
5046 * will be issued on the next burst (after descriptor writing,
5049 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, !txq->db_nc &&
5050 (!txq->db_heu || pkts_n % MLX5_TX_DEFAULT_BURST));
5051 /* Not all of the mbufs may be stored into elts yet. */
5052 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;
5053 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
5055 * There are some single-segment mbufs not stored in elts.
5056 * It can be only if the last packet was single-segment.
5057 * The copying is gathered into one place due to it is
5058 * a good opportunity to optimize that with SIMD.
5059 * Unfortunately if inlining is enabled the gaps in
5060 * pointer array may happen due to early freeing of the
5063 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
5064 loc.pkts_copy = loc.pkts_sent;
5066 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
5067 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
5068 if (pkts_n > loc.pkts_sent) {
5070 * If burst size is large there might be no enough CQE
5071 * fetched from completion queue and no enough resources
5072 * freed to send all the packets.
5077 #ifdef MLX5_PMD_SOFT_COUNTERS
5078 /* Increment sent packets counter. */
5079 txq->stats.opackets += loc.pkts_sent;
5081 return loc.pkts_sent;
5084 /* Generate routines with Enhanced Multi-Packet Write support. */
5085 MLX5_TXOFF_DECL(full_empw,
5086 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
5088 MLX5_TXOFF_DECL(none_empw,
5089 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5091 MLX5_TXOFF_DECL(md_empw,
5092 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5094 MLX5_TXOFF_DECL(mt_empw,
5095 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5096 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5098 MLX5_TXOFF_DECL(mtsc_empw,
5099 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5100 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5101 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5103 MLX5_TXOFF_DECL(mti_empw,
5104 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5105 MLX5_TXOFF_CONFIG_INLINE |
5106 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5108 MLX5_TXOFF_DECL(mtv_empw,
5109 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5110 MLX5_TXOFF_CONFIG_VLAN |
5111 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5113 MLX5_TXOFF_DECL(mtiv_empw,
5114 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5115 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5116 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5118 MLX5_TXOFF_DECL(sc_empw,
5119 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5120 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5122 MLX5_TXOFF_DECL(sci_empw,
5123 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5124 MLX5_TXOFF_CONFIG_INLINE |
5125 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5127 MLX5_TXOFF_DECL(scv_empw,
5128 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5129 MLX5_TXOFF_CONFIG_VLAN |
5130 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5132 MLX5_TXOFF_DECL(sciv_empw,
5133 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5134 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5135 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5137 MLX5_TXOFF_DECL(i_empw,
5138 MLX5_TXOFF_CONFIG_INLINE |
5139 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5141 MLX5_TXOFF_DECL(v_empw,
5142 MLX5_TXOFF_CONFIG_VLAN |
5143 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5145 MLX5_TXOFF_DECL(iv_empw,
5146 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5147 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5149 /* Generate routines without Enhanced Multi-Packet Write support. */
5150 MLX5_TXOFF_DECL(full,
5151 MLX5_TXOFF_CONFIG_FULL)
5153 MLX5_TXOFF_DECL(none,
5154 MLX5_TXOFF_CONFIG_NONE)
5157 MLX5_TXOFF_CONFIG_METADATA)
5160 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5161 MLX5_TXOFF_CONFIG_METADATA)
5163 MLX5_TXOFF_DECL(mtsc,
5164 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5165 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5166 MLX5_TXOFF_CONFIG_METADATA)
5168 MLX5_TXOFF_DECL(mti,
5169 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5170 MLX5_TXOFF_CONFIG_INLINE |
5171 MLX5_TXOFF_CONFIG_METADATA)
5174 MLX5_TXOFF_DECL(mtv,
5175 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5176 MLX5_TXOFF_CONFIG_VLAN |
5177 MLX5_TXOFF_CONFIG_METADATA)
5180 MLX5_TXOFF_DECL(mtiv,
5181 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5182 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5183 MLX5_TXOFF_CONFIG_METADATA)
5186 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5187 MLX5_TXOFF_CONFIG_METADATA)
5189 MLX5_TXOFF_DECL(sci,
5190 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5191 MLX5_TXOFF_CONFIG_INLINE |
5192 MLX5_TXOFF_CONFIG_METADATA)
5195 MLX5_TXOFF_DECL(scv,
5196 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5197 MLX5_TXOFF_CONFIG_VLAN |
5198 MLX5_TXOFF_CONFIG_METADATA)
5201 MLX5_TXOFF_DECL(sciv,
5202 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5203 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5204 MLX5_TXOFF_CONFIG_METADATA)
5207 MLX5_TXOFF_CONFIG_INLINE |
5208 MLX5_TXOFF_CONFIG_METADATA)
5211 MLX5_TXOFF_CONFIG_VLAN |
5212 MLX5_TXOFF_CONFIG_METADATA)
5215 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5216 MLX5_TXOFF_CONFIG_METADATA)
5218 /* Generate routines with timestamp scheduling. */
5219 MLX5_TXOFF_DECL(full_ts_nompw,
5220 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP)
5222 MLX5_TXOFF_DECL(full_ts_nompwi,
5223 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5224 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5225 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5226 MLX5_TXOFF_CONFIG_TXPP)
5228 MLX5_TXOFF_DECL(full_ts,
5229 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP |
5230 MLX5_TXOFF_CONFIG_EMPW)
5232 MLX5_TXOFF_DECL(full_ts_noi,
5233 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5234 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5235 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5236 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5238 MLX5_TXOFF_DECL(none_ts,
5239 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_TXPP |
5240 MLX5_TXOFF_CONFIG_EMPW)
5242 MLX5_TXOFF_DECL(mdi_ts,
5243 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5244 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5246 MLX5_TXOFF_DECL(mti_ts,
5247 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5248 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5249 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5251 MLX5_TXOFF_DECL(mtiv_ts,
5252 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5253 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5254 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_TXPP |
5255 MLX5_TXOFF_CONFIG_EMPW)
5258 * Generate routines with Legacy Multi-Packet Write support.
5259 * This mode is supported by ConnectX-4 Lx only and imposes
5260 * offload limitations, not supported:
5261 * - ACL/Flows (metadata are becoming meaningless)
5262 * - WQE Inline headers
5263 * - SRIOV (E-Switch offloads)
5265 * - tunnel encapsulation/decapsulation
5268 MLX5_TXOFF_DECL(none_mpw,
5269 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5270 MLX5_TXOFF_CONFIG_MPW)
5272 MLX5_TXOFF_DECL(mci_mpw,
5273 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5274 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5275 MLX5_TXOFF_CONFIG_MPW)
5277 MLX5_TXOFF_DECL(mc_mpw,
5278 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5279 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5281 MLX5_TXOFF_DECL(i_mpw,
5282 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5283 MLX5_TXOFF_CONFIG_MPW)
5286 * Array of declared and compiled Tx burst function and corresponding
5287 * supported offloads set. The array is used to select the Tx burst
5288 * function for specified offloads set at Tx queue configuration time.
5291 eth_tx_burst_t func;
5294 MLX5_TXOFF_INFO(full_empw,
5295 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5296 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5297 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5298 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5300 MLX5_TXOFF_INFO(none_empw,
5301 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5303 MLX5_TXOFF_INFO(md_empw,
5304 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5306 MLX5_TXOFF_INFO(mt_empw,
5307 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5308 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5310 MLX5_TXOFF_INFO(mtsc_empw,
5311 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5312 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5313 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5315 MLX5_TXOFF_INFO(mti_empw,
5316 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5317 MLX5_TXOFF_CONFIG_INLINE |
5318 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5320 MLX5_TXOFF_INFO(mtv_empw,
5321 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5322 MLX5_TXOFF_CONFIG_VLAN |
5323 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5325 MLX5_TXOFF_INFO(mtiv_empw,
5326 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5327 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5328 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5330 MLX5_TXOFF_INFO(sc_empw,
5331 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5332 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5334 MLX5_TXOFF_INFO(sci_empw,
5335 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5336 MLX5_TXOFF_CONFIG_INLINE |
5337 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5339 MLX5_TXOFF_INFO(scv_empw,
5340 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5341 MLX5_TXOFF_CONFIG_VLAN |
5342 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5344 MLX5_TXOFF_INFO(sciv_empw,
5345 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5346 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5347 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5349 MLX5_TXOFF_INFO(i_empw,
5350 MLX5_TXOFF_CONFIG_INLINE |
5351 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5353 MLX5_TXOFF_INFO(v_empw,
5354 MLX5_TXOFF_CONFIG_VLAN |
5355 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5357 MLX5_TXOFF_INFO(iv_empw,
5358 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5359 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5361 MLX5_TXOFF_INFO(full_ts_nompw,
5362 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP)
5364 MLX5_TXOFF_INFO(full_ts_nompwi,
5365 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5366 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5367 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5368 MLX5_TXOFF_CONFIG_TXPP)
5370 MLX5_TXOFF_INFO(full_ts,
5371 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP |
5372 MLX5_TXOFF_CONFIG_EMPW)
5374 MLX5_TXOFF_INFO(full_ts_noi,
5375 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5376 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5377 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5378 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5380 MLX5_TXOFF_INFO(none_ts,
5381 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_TXPP |
5382 MLX5_TXOFF_CONFIG_EMPW)
5384 MLX5_TXOFF_INFO(mdi_ts,
5385 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5386 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5388 MLX5_TXOFF_INFO(mti_ts,
5389 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5390 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5391 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5393 MLX5_TXOFF_INFO(mtiv_ts,
5394 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5395 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5396 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_TXPP |
5397 MLX5_TXOFF_CONFIG_EMPW)
5399 MLX5_TXOFF_INFO(full,
5400 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5401 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5402 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5403 MLX5_TXOFF_CONFIG_METADATA)
5405 MLX5_TXOFF_INFO(none,
5406 MLX5_TXOFF_CONFIG_NONE)
5409 MLX5_TXOFF_CONFIG_METADATA)
5412 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5413 MLX5_TXOFF_CONFIG_METADATA)
5415 MLX5_TXOFF_INFO(mtsc,
5416 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5417 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5418 MLX5_TXOFF_CONFIG_METADATA)
5420 MLX5_TXOFF_INFO(mti,
5421 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5422 MLX5_TXOFF_CONFIG_INLINE |
5423 MLX5_TXOFF_CONFIG_METADATA)
5425 MLX5_TXOFF_INFO(mtv,
5426 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5427 MLX5_TXOFF_CONFIG_VLAN |
5428 MLX5_TXOFF_CONFIG_METADATA)
5430 MLX5_TXOFF_INFO(mtiv,
5431 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5432 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5433 MLX5_TXOFF_CONFIG_METADATA)
5436 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5437 MLX5_TXOFF_CONFIG_METADATA)
5439 MLX5_TXOFF_INFO(sci,
5440 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5441 MLX5_TXOFF_CONFIG_INLINE |
5442 MLX5_TXOFF_CONFIG_METADATA)
5444 MLX5_TXOFF_INFO(scv,
5445 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5446 MLX5_TXOFF_CONFIG_VLAN |
5447 MLX5_TXOFF_CONFIG_METADATA)
5449 MLX5_TXOFF_INFO(sciv,
5450 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5451 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5452 MLX5_TXOFF_CONFIG_METADATA)
5455 MLX5_TXOFF_CONFIG_INLINE |
5456 MLX5_TXOFF_CONFIG_METADATA)
5459 MLX5_TXOFF_CONFIG_VLAN |
5460 MLX5_TXOFF_CONFIG_METADATA)
5463 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5464 MLX5_TXOFF_CONFIG_METADATA)
5466 MLX5_TXOFF_INFO(none_mpw,
5467 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5468 MLX5_TXOFF_CONFIG_MPW)
5470 MLX5_TXOFF_INFO(mci_mpw,
5471 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5472 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5473 MLX5_TXOFF_CONFIG_MPW)
5475 MLX5_TXOFF_INFO(mc_mpw,
5476 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5477 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5479 MLX5_TXOFF_INFO(i_mpw,
5480 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5481 MLX5_TXOFF_CONFIG_MPW)
5485 * Configure the Tx function to use. The routine checks configured
5486 * Tx offloads for the device and selects appropriate Tx burst
5487 * routine. There are multiple Tx burst routines compiled from
5488 * the same template in the most optimal way for the dedicated
5492 * Pointer to private data structure.
5495 * Pointer to selected Tx burst function.
5498 mlx5_select_tx_function(struct rte_eth_dev *dev)
5500 struct mlx5_priv *priv = dev->data->dev_private;
5501 struct mlx5_dev_config *config = &priv->config;
5502 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
5503 unsigned int diff = 0, olx = 0, i, m;
5505 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
5506 MLX5_DSEG_MAX, "invalid WQE max size");
5507 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
5508 "invalid WQE Control Segment size");
5509 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
5510 "invalid WQE Ethernet Segment size");
5511 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
5512 "invalid WQE Data Segment size");
5513 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
5514 "invalid WQE size");
5516 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
5517 /* We should support Multi-Segment Packets. */
5518 olx |= MLX5_TXOFF_CONFIG_MULTI;
5520 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
5521 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
5522 DEV_TX_OFFLOAD_GRE_TNL_TSO |
5523 DEV_TX_OFFLOAD_IP_TNL_TSO |
5524 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
5525 /* We should support TCP Send Offload. */
5526 olx |= MLX5_TXOFF_CONFIG_TSO;
5528 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
5529 DEV_TX_OFFLOAD_UDP_TNL_TSO |
5530 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5531 /* We should support Software Parser for Tunnels. */
5532 olx |= MLX5_TXOFF_CONFIG_SWP;
5534 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
5535 DEV_TX_OFFLOAD_UDP_CKSUM |
5536 DEV_TX_OFFLOAD_TCP_CKSUM |
5537 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5538 /* We should support IP/TCP/UDP Checksums. */
5539 olx |= MLX5_TXOFF_CONFIG_CSUM;
5541 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
5542 /* We should support VLAN insertion. */
5543 olx |= MLX5_TXOFF_CONFIG_VLAN;
5545 if (tx_offloads & DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP &&
5546 rte_mbuf_dynflag_lookup
5547 (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL) >= 0 &&
5548 rte_mbuf_dynfield_lookup
5549 (RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL) >= 0) {
5550 /* Offload configured, dynamic entities registered. */
5551 olx |= MLX5_TXOFF_CONFIG_TXPP;
5553 if (priv->txqs_n && (*priv->txqs)[0]) {
5554 struct mlx5_txq_data *txd = (*priv->txqs)[0];
5556 if (txd->inlen_send) {
5558 * Check the data inline requirements. Data inline
5559 * is enabled on per device basis, we can check
5560 * the first Tx queue only.
5562 * If device does not support VLAN insertion in WQE
5563 * and some queues are requested to perform VLAN
5564 * insertion offload than inline must be enabled.
5566 olx |= MLX5_TXOFF_CONFIG_INLINE;
5569 if (config->mps == MLX5_MPW_ENHANCED &&
5570 config->txq_inline_min <= 0) {
5572 * The NIC supports Enhanced Multi-Packet Write
5573 * and does not require minimal inline data.
5575 olx |= MLX5_TXOFF_CONFIG_EMPW;
5577 if (rte_flow_dynf_metadata_avail()) {
5578 /* We should support Flow metadata. */
5579 olx |= MLX5_TXOFF_CONFIG_METADATA;
5581 if (config->mps == MLX5_MPW) {
5583 * The NIC supports Legacy Multi-Packet Write.
5584 * The MLX5_TXOFF_CONFIG_MPW controls the
5585 * descriptor building method in combination
5586 * with MLX5_TXOFF_CONFIG_EMPW.
5588 if (!(olx & (MLX5_TXOFF_CONFIG_TSO |
5589 MLX5_TXOFF_CONFIG_SWP |
5590 MLX5_TXOFF_CONFIG_VLAN |
5591 MLX5_TXOFF_CONFIG_METADATA)))
5592 olx |= MLX5_TXOFF_CONFIG_EMPW |
5593 MLX5_TXOFF_CONFIG_MPW;
5596 * Scan the routines table to find the minimal
5597 * satisfying routine with requested offloads.
5599 m = RTE_DIM(txoff_func);
5600 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5603 tmp = txoff_func[i].olx;
5605 /* Meets requested offloads exactly.*/
5609 if ((tmp & olx) != olx) {
5610 /* Does not meet requested offloads at all. */
5613 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_MPW)
5614 /* Do not enable legacy MPW if not configured. */
5616 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
5617 /* Do not enable eMPW if not configured. */
5619 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
5620 /* Do not enable inlining if not configured. */
5622 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_TXPP)
5623 /* Do not enable scheduling if not configured. */
5626 * Some routine meets the requirements.
5627 * Check whether it has minimal amount
5628 * of not requested offloads.
5630 tmp = __builtin_popcountl(tmp & ~olx);
5631 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
5632 /* First or better match, save and continue. */
5638 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
5639 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
5640 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
5641 /* Lighter not requested offload. */
5646 if (m >= RTE_DIM(txoff_func)) {
5647 DRV_LOG(DEBUG, "port %u has no selected Tx function"
5648 " for requested offloads %04X",
5649 dev->data->port_id, olx);
5652 DRV_LOG(DEBUG, "port %u has selected Tx function"
5653 " supporting offloads %04X/%04X",
5654 dev->data->port_id, olx, txoff_func[m].olx);
5655 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
5656 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
5657 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
5658 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
5659 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
5660 DRV_LOG(DEBUG, "\tSWP (software parser)");
5661 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
5662 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
5663 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
5664 DRV_LOG(DEBUG, "\tINLIN (inline data)");
5665 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
5666 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
5667 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
5668 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
5669 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TXPP)
5670 DRV_LOG(DEBUG, "\tMETAD (tx Scheduling)");
5671 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW) {
5672 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MPW)
5673 DRV_LOG(DEBUG, "\tMPW (Legacy MPW)");
5675 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
5677 return txoff_func[m].func;
5681 * DPDK callback to get the TX queue information
5684 * Pointer to the device structure.
5686 * @param tx_queue_id
5687 * Tx queue identificator.
5690 * Pointer to the TX queue information structure.
5697 mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
5698 struct rte_eth_txq_info *qinfo)
5700 struct mlx5_priv *priv = dev->data->dev_private;
5701 struct mlx5_txq_data *txq = (*priv->txqs)[tx_queue_id];
5702 struct mlx5_txq_ctrl *txq_ctrl =
5703 container_of(txq, struct mlx5_txq_ctrl, txq);
5707 qinfo->nb_desc = txq->elts_s;
5708 qinfo->conf.tx_thresh.pthresh = 0;
5709 qinfo->conf.tx_thresh.hthresh = 0;
5710 qinfo->conf.tx_thresh.wthresh = 0;
5711 qinfo->conf.tx_rs_thresh = 0;
5712 qinfo->conf.tx_free_thresh = 0;
5713 qinfo->conf.tx_deferred_start = txq_ctrl ? 0 : 1;
5714 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
5718 * DPDK callback to get the TX packet burst mode information
5721 * Pointer to the device structure.
5723 * @param tx_queue_id
5724 * Tx queue identificatior.
5727 * Pointer to the burts mode information.
5730 * 0 as success, -EINVAL as failure.
5734 mlx5_tx_burst_mode_get(struct rte_eth_dev *dev,
5735 uint16_t tx_queue_id __rte_unused,
5736 struct rte_eth_burst_mode *mode)
5738 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
5739 unsigned int i, olx;
5741 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5742 if (pkt_burst == txoff_func[i].func) {
5743 olx = txoff_func[i].olx;
5744 snprintf(mode->info, sizeof(mode->info),
5745 "%s%s%s%s%s%s%s%s%s",
5746 (olx & MLX5_TXOFF_CONFIG_EMPW) ?
5747 ((olx & MLX5_TXOFF_CONFIG_MPW) ?
5748 "Legacy MPW" : "Enhanced MPW") : "No MPW",
5749 (olx & MLX5_TXOFF_CONFIG_MULTI) ?
5751 (olx & MLX5_TXOFF_CONFIG_TSO) ?
5753 (olx & MLX5_TXOFF_CONFIG_SWP) ?
5755 (olx & MLX5_TXOFF_CONFIG_CSUM) ?
5757 (olx & MLX5_TXOFF_CONFIG_INLINE) ?
5759 (olx & MLX5_TXOFF_CONFIG_VLAN) ?
5761 (olx & MLX5_TXOFF_CONFIG_METADATA) ?
5763 (olx & MLX5_TXOFF_CONFIG_TXPP) ?