1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 #include <rte_mempool.h>
15 #include <rte_common.h>
16 #include <rte_hexdump.h>
17 #include <rte_atomic.h>
18 #include <rte_spinlock.h>
20 #include <rte_bus_pci.h>
21 #include <rte_malloc.h>
22 #include <rte_cycles.h>
24 #include <mlx5_glue.h>
26 #include <mlx5_common.h>
27 #include <mlx5_common_mr.h>
29 #include "mlx5_defs.h"
30 #include "mlx5_utils.h"
32 #include "mlx5_autoconf.h"
35 /* Support tunnel matching. */
36 #define MLX5_FLOW_TUNNEL 10
38 /* Mbuf dynamic flag offset for inline. */
39 extern uint64_t rte_net_mlx5_dynf_inline_mask;
41 struct mlx5_rxq_stats {
42 #ifdef MLX5_PMD_SOFT_COUNTERS
43 uint64_t ipackets; /**< Total of successfully received packets. */
44 uint64_t ibytes; /**< Total of successfully received bytes. */
46 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
47 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
50 struct mlx5_txq_stats {
51 #ifdef MLX5_PMD_SOFT_COUNTERS
52 uint64_t opackets; /**< Total of successfully sent packets. */
53 uint64_t obytes; /**< Total of successfully sent bytes. */
55 uint64_t oerrors; /**< Total number of failed transmitted packets. */
60 /* Compressed CQE context. */
62 uint16_t ai; /* Array index. */
63 uint16_t ca; /* Current array index. */
64 uint16_t na; /* Next array index. */
65 uint16_t cq_ci; /* The next CQE. */
66 uint32_t cqe_cnt; /* Number of CQEs. */
69 /* Multi-Packet RQ buffer header. */
70 struct mlx5_mprq_buf {
71 struct rte_mempool *mp;
72 uint16_t refcnt; /* Atomically accessed refcnt. */
73 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
74 struct rte_mbuf_ext_shared_info shinfos[];
76 * Shared information per stride.
77 * More memory will be allocated for the first stride head-room and for
80 } __rte_cache_aligned;
82 /* Get pointer to the first stride. */
83 #define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \
84 sizeof(struct mlx5_mprq_buf) + \
86 sizeof(struct rte_mbuf_ext_shared_info) + \
87 RTE_PKTMBUF_HEADROOM))
89 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
90 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
92 enum mlx5_rxq_err_state {
93 MLX5_RXQ_ERR_STATE_NO_ERROR = 0,
94 MLX5_RXQ_ERR_STATE_NEED_RESET,
95 MLX5_RXQ_ERR_STATE_NEED_READY,
99 MLX5_RXQ_CODE_EXIT = 0,
100 MLX5_RXQ_CODE_NOMBUF,
101 MLX5_RXQ_CODE_DROPPED,
104 /* RX queue descriptor. */
105 struct mlx5_rxq_data {
106 unsigned int csum:1; /* Enable checksum offloading. */
107 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
108 unsigned int rt_timestamp:1; /* Realtime timestamp format. */
109 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
110 unsigned int crc_present:1; /* CRC must be subtracted. */
111 unsigned int sges_n:3; /* Log 2 of SGEs (max buffers per packet). */
112 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
113 unsigned int elts_n:4; /* Log 2 of Mbufs. */
114 unsigned int rss_hash:1; /* RSS hash result is enabled. */
115 unsigned int mark:1; /* Marked flow available on the queue. */
116 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
117 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
118 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
119 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
120 unsigned int strd_scatter_en:1; /* Scattered packets from a stride. */
121 unsigned int lro:1; /* Enable LRO. */
122 unsigned int dynf_meta:1; /* Dynamic metadata is configured. */
123 volatile uint32_t *rq_db;
124 volatile uint32_t *cq_db;
128 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
131 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
133 struct rxq_zip zip; /* Compressed context. */
134 uint16_t decompressed;
135 /* Number of ready mbufs decompressed from the CQ. */
137 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
138 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
140 volatile struct mlx5_cqe(*cqes)[];
141 struct rte_mbuf *(*elts)[];
142 struct mlx5_mprq_buf *(*mprq_bufs)[];
143 struct rte_mempool *mp;
144 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
145 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
146 struct mlx5_dev_ctx_shared *sh; /* Shared context. */
147 uint16_t idx; /* Queue index. */
148 struct mlx5_rxq_stats stats;
149 rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */
150 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
151 void *cq_uar; /* Verbs CQ user access region. */
152 uint32_t cqn; /* CQ number. */
153 uint8_t cq_arm_sn; /* CQ arm seq number. */
155 rte_spinlock_t *uar_lock_cq;
156 /* CQ (UAR) access lock required for 32bit implementations */
158 uint32_t tunnel; /* Tunnel information. */
159 int timestamp_offset; /* Dynamic mbuf field for timestamp. */
160 uint64_t timestamp_rx_flag; /* Dynamic mbuf flag for timestamp. */
161 uint64_t flow_meta_mask;
162 int32_t flow_meta_offset;
163 } __rte_cache_aligned;
166 MLX5_RXQ_TYPE_STANDARD, /* Standard Rx queue. */
167 MLX5_RXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
168 MLX5_RXQ_TYPE_UNDEFINED,
171 /* RX queue control descriptor. */
172 struct mlx5_rxq_ctrl {
173 struct mlx5_rxq_data rxq; /* Data path structure. */
174 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
175 uint32_t refcnt; /* Reference counter. */
176 struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */
177 struct mlx5_priv *priv; /* Back pointer to private data. */
178 enum mlx5_rxq_type type; /* Rxq type. */
179 unsigned int socket; /* CPU socket ID for allocations. */
180 unsigned int irq:1; /* Whether IRQ is enabled. */
181 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
182 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
183 uint32_t wqn; /* WQ number. */
184 uint16_t dump_file_n; /* Number of dump files. */
185 struct mlx5_devx_dbr_page *rq_dbrec_page;
186 uint64_t rq_dbr_offset;
187 /* Storing RQ door-bell information, needed when freeing door-bell. */
188 struct mlx5_devx_dbr_page *cq_dbrec_page;
189 uint64_t cq_dbr_offset;
190 /* Storing CQ door-bell information, needed when freeing door-bell. */
191 void *wq_umem; /* WQ buffer registration info. */
192 void *cq_umem; /* CQ buffer registration info. */
193 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
196 /* TX queue send local data. */
198 struct mlx5_txq_local {
199 struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */
200 struct rte_mbuf *mbuf; /* first mbuf to process. */
201 uint16_t pkts_copy; /* packets copied to elts. */
202 uint16_t pkts_sent; /* packets sent. */
203 uint16_t pkts_loop; /* packets sent on loop entry. */
204 uint16_t elts_free; /* available elts remain. */
205 uint16_t wqe_free; /* available wqe remain. */
206 uint16_t mbuf_off; /* data offset in current mbuf. */
207 uint16_t mbuf_nseg; /* number of remaining mbuf. */
210 /* TX queue descriptor. */
212 struct mlx5_txq_data {
213 uint16_t elts_head; /* Current counter in (*elts)[]. */
214 uint16_t elts_tail; /* Counter of first element awaiting completion. */
215 uint16_t elts_comp; /* elts index since last completion request. */
216 uint16_t elts_s; /* Number of mbuf elements. */
217 uint16_t elts_m; /* Mask for mbuf elements indices. */
218 /* Fields related to elts mbuf storage. */
219 uint16_t wqe_ci; /* Consumer index for work queue. */
220 uint16_t wqe_pi; /* Producer index for work queue. */
221 uint16_t wqe_s; /* Number of WQ elements. */
222 uint16_t wqe_m; /* Mask Number for WQ elements. */
223 uint16_t wqe_comp; /* WQE index since last completion request. */
224 uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */
225 /* WQ related fields. */
226 uint16_t cq_ci; /* Consumer index for completion queue. */
227 uint16_t cq_pi; /* Production index for completion queue. */
228 uint16_t cqe_s; /* Number of CQ elements. */
229 uint16_t cqe_m; /* Mask for CQ indices. */
230 /* CQ related fields. */
231 uint16_t elts_n:4; /* elts[] length (in log2). */
232 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
233 uint16_t wqe_n:4; /* Number of WQ elements (in log2). */
234 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
235 uint16_t tunnel_en:1;
236 /* When set TX offload for tunneled packets are supported. */
237 uint16_t swp_en:1; /* Whether SW parser is enabled. */
238 uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */
239 uint16_t db_nc:1; /* Doorbell mapped to non-cached region. */
240 uint16_t db_heu:1; /* Doorbell heuristic write barrier. */
241 uint16_t inlen_send; /* Ordinary send data inline size. */
242 uint16_t inlen_empw; /* eMPW max packet size to inline. */
243 uint16_t inlen_mode; /* Minimal data length to inline. */
244 uint32_t qp_num_8s; /* QP number shifted by 8. */
245 uint64_t offloads; /* Offloads for Tx Queue. */
246 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
247 struct mlx5_wqe *wqes; /* Work queue. */
248 struct mlx5_wqe *wqes_end; /* Work queue array limit. */
249 #ifdef RTE_LIBRTE_MLX5_DEBUG
250 uint32_t *fcqs; /* Free completion queue (debug extended). */
252 uint16_t *fcqs; /* Free completion queue. */
254 volatile struct mlx5_cqe *cqes; /* Completion queue. */
255 volatile uint32_t *qp_db; /* Work queue doorbell. */
256 volatile uint32_t *cq_db; /* Completion queue doorbell. */
257 uint16_t port_id; /* Port ID of device. */
258 uint16_t idx; /* Queue index. */
259 uint64_t ts_mask; /* Timestamp flag dynamic mask. */
260 int32_t ts_offset; /* Timestamp field dynamic offset. */
261 struct mlx5_dev_ctx_shared *sh; /* Shared context. */
262 struct mlx5_txq_stats stats; /* TX queue counters. */
264 rte_spinlock_t *uar_lock;
265 /* UAR access lock required for 32bit implementations */
267 struct rte_mbuf *elts[0];
268 /* Storage for queued packets, must be the last field. */
269 } __rte_cache_aligned;
272 MLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */
273 MLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
276 /* TX queue control descriptor. */
277 struct mlx5_txq_ctrl {
278 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
279 uint32_t refcnt; /* Reference counter. */
280 unsigned int socket; /* CPU socket ID for allocations. */
281 enum mlx5_txq_type type; /* The txq ctrl type. */
282 unsigned int max_inline_data; /* Max inline data. */
283 unsigned int max_tso_header; /* Max TSO header size. */
284 struct mlx5_txq_obj *obj; /* Verbs/DevX queue object. */
285 struct mlx5_priv *priv; /* Back pointer to private data. */
286 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
287 void *bf_reg; /* BlueFlame register from Verbs. */
288 uint16_t dump_file_n; /* Number of dump files. */
289 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
290 struct mlx5_txq_data txq; /* Data path structure. */
291 /* Must be the last field in the structure, contains elts[]. */
294 #define MLX5_TX_BFREG(txq) \
295 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx])
299 extern uint8_t rss_hash_default_key[];
301 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
302 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
303 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
304 unsigned int mlx5_rxq_cqe_num(struct mlx5_rxq_data *rxq_data);
305 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
306 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
307 int mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id);
308 int mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id);
309 int mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id);
310 int mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id);
311 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
312 unsigned int socket, const struct rte_eth_rxconf *conf,
313 struct rte_mempool *mp);
314 int mlx5_rx_hairpin_queue_setup
315 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
316 const struct rte_eth_hairpin_conf *hairpin_conf);
317 void mlx5_rx_queue_release(void *dpdk_rxq);
318 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
319 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
320 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
321 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
322 int mlx5_rxq_obj_verify(struct rte_eth_dev *dev);
323 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
324 uint16_t desc, unsigned int socket,
325 const struct rte_eth_rxconf *conf,
326 struct rte_mempool *mp);
327 struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new
328 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
329 const struct rte_eth_hairpin_conf *hairpin_conf);
330 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
331 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
332 int mlx5_rxq_verify(struct rte_eth_dev *dev);
333 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
334 int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev);
335 struct mlx5_ind_table_obj *mlx5_ind_table_obj_get(struct rte_eth_dev *dev,
336 const uint16_t *queues,
338 int mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
339 struct mlx5_ind_table_obj *ind_tbl);
340 uint32_t mlx5_hrxq_new(struct rte_eth_dev *dev,
341 const uint8_t *rss_key, uint32_t rss_key_len,
342 uint64_t hash_fields,
343 const uint16_t *queues, uint32_t queues_n,
344 int tunnel __rte_unused);
345 uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev,
346 const uint8_t *rss_key, uint32_t rss_key_len,
347 uint64_t hash_fields,
348 const uint16_t *queues, uint32_t queues_n);
349 int mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hxrq_idx);
350 int mlx5_hrxq_verify(struct rte_eth_dev *dev);
351 enum mlx5_rxq_type mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx);
352 struct mlx5_hrxq *mlx5_drop_action_create(struct rte_eth_dev *dev);
353 void mlx5_drop_action_destroy(struct rte_eth_dev *dev);
354 uint64_t mlx5_get_rx_port_offloads(void);
355 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
356 void mlx5_rxq_timestamp_set(struct rte_eth_dev *dev);
361 int mlx5_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id);
362 int mlx5_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id);
363 int mlx5_tx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id);
364 int mlx5_tx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id);
365 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
366 unsigned int socket, const struct rte_eth_txconf *conf);
367 int mlx5_tx_hairpin_queue_setup
368 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
369 const struct rte_eth_hairpin_conf *hairpin_conf);
370 void mlx5_tx_queue_release(void *dpdk_txq);
371 void txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl);
372 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
373 void mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev);
374 int mlx5_txq_obj_verify(struct rte_eth_dev *dev);
375 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
376 uint16_t desc, unsigned int socket,
377 const struct rte_eth_txconf *conf);
378 struct mlx5_txq_ctrl *mlx5_txq_hairpin_new
379 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
380 const struct rte_eth_hairpin_conf *hairpin_conf);
381 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
382 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
383 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
384 int mlx5_txq_verify(struct rte_eth_dev *dev);
385 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
386 void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl);
387 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
388 void mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev);
392 extern uint32_t mlx5_ptype_table[];
393 extern uint8_t mlx5_cksum_table[];
394 extern uint8_t mlx5_swp_types_table[];
396 void mlx5_set_ptype_table(void);
397 void mlx5_set_cksum_table(void);
398 void mlx5_set_swp_types_table(void);
399 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
400 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);
401 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec);
402 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
403 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
404 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
406 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
408 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
410 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
411 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
412 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
413 void mlx5_dump_debug_information(const char *path, const char *title,
414 const void *buf, unsigned int len);
415 int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
416 const struct mlx5_mp_arg_queue_state_modify *sm);
417 void mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
418 struct rte_eth_rxq_info *qinfo);
419 void mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
420 struct rte_eth_txq_info *qinfo);
421 int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
422 struct rte_eth_burst_mode *mode);
423 int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
424 struct rte_eth_burst_mode *mode);
426 /* Vectorized version of mlx5_rxtx.c */
427 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
428 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
429 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
431 uint16_t mlx5_rx_burst_mprq_vec(void *dpdk_txq, struct rte_mbuf **pkts,
436 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
437 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
438 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
439 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
440 struct rte_mempool *mp);
441 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
443 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
447 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
448 * 64bit architectures.
451 * value to write in CPU endian format.
453 * Address to write to.
455 * Address of the lock to use for that UAR access.
457 static __rte_always_inline void
458 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
459 rte_spinlock_t *lock __rte_unused)
462 *(uint64_t *)addr = val;
463 #else /* !RTE_ARCH_64 */
464 rte_spinlock_lock(lock);
465 *(uint32_t *)addr = val;
467 *((uint32_t *)addr + 1) = val >> 32;
468 rte_spinlock_unlock(lock);
473 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
474 * 64bit architectures while guaranteeing the order of execution with the
475 * code being executed.
478 * value to write in CPU endian format.
480 * Address to write to.
482 * Address of the lock to use for that UAR access.
484 static __rte_always_inline void
485 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
488 __mlx5_uar_write64_relaxed(val, addr, lock);
491 /* Assist macros, used instead of directly calling the functions they wrap. */
493 #define mlx5_uar_write64_relaxed(val, dst, lock) \
494 __mlx5_uar_write64_relaxed(val, dst, NULL)
495 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
497 #define mlx5_uar_write64_relaxed(val, dst, lock) \
498 __mlx5_uar_write64_relaxed(val, dst, lock)
499 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
503 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
504 * cloned mbuf is allocated is returned instead.
510 * Memory pool where data is located for given mbuf.
512 static inline struct rte_mempool *
513 mlx5_mb2mp(struct rte_mbuf *buf)
515 if (unlikely(RTE_MBUF_CLONED(buf)))
516 return rte_mbuf_from_indirect(buf)->pool;
521 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
522 * as mempool is pre-configured and static.
525 * Pointer to Rx queue structure.
530 * Searched LKey on success, UINT32_MAX on no match.
532 static __rte_always_inline uint32_t
533 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
535 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
538 /* Linear search on MR cache array. */
539 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
540 MLX5_MR_CACHE_N, addr);
541 if (likely(lkey != UINT32_MAX))
543 /* Take slower bottom-half (Binary Search) on miss. */
544 return mlx5_rx_addr2mr_bh(rxq, addr);
547 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
550 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
553 * Pointer to Tx queue structure.
558 * Searched LKey on success, UINT32_MAX on no match.
560 static __rte_always_inline uint32_t
561 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
563 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
564 uintptr_t addr = (uintptr_t)mb->buf_addr;
567 /* Check generation bit to see if there's any change on existing MRs. */
568 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
569 mlx5_mr_flush_local_cache(mr_ctrl);
570 /* Linear search on MR cache array. */
571 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
572 MLX5_MR_CACHE_N, addr);
573 if (likely(lkey != UINT32_MAX))
575 /* Take slower bottom-half on miss. */
576 return mlx5_tx_mb2mr_bh(txq, mb);
580 * Ring TX queue doorbell and flush the update if requested.
583 * Pointer to TX queue structure.
585 * Pointer to the last WQE posted in the NIC.
587 * Request for write memory barrier after BlueFlame update.
589 static __rte_always_inline void
590 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
593 uint64_t *dst = MLX5_TX_BFREG(txq);
594 volatile uint64_t *src = ((volatile uint64_t *)wqe);
597 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
598 /* Ensure ordering between DB record and BF copy. */
600 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
606 * Ring TX queue doorbell and flush the update by write memory barrier.
609 * Pointer to TX queue structure.
611 * Pointer to the last WQE posted in the NIC.
613 static __rte_always_inline void
614 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
616 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
620 * Convert timestamp from HW format to linear counter
621 * from Packet Pacing Clock Queue CQE timestamp format.
624 * Pointer to the device shared context. Might be needed
625 * to convert according current device configuration.
627 * Timestamp from CQE to convert.
631 static __rte_always_inline uint64_t
632 mlx5_txpp_convert_rx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t ts)
635 return (ts & UINT32_MAX) + (ts >> 32) * NS_PER_S;
639 * Convert timestamp from mbuf format to linear counter
640 * of Clock Queue completions (24 bits)
643 * Pointer to the device shared context to fetch Tx
644 * packet pacing timestamp and parameters.
646 * Timestamp from mbuf to convert.
648 * positive or zero value - completion ID to wait
649 * negative value - conversion error
651 static __rte_always_inline int32_t
652 mlx5_txpp_convert_tx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t mts)
659 * Read atomically two uint64_t fields and compare lsb bits.
660 * It there is no match - the timestamp was updated in
661 * the service thread, data should be re-read.
663 rte_compiler_barrier();
664 ci = rte_atomic64_read(&sh->txpp.ts.ci_ts);
665 ts = rte_atomic64_read(&sh->txpp.ts.ts);
666 rte_compiler_barrier();
667 if (!((ts ^ ci) << (64 - MLX5_CQ_INDEX_WIDTH)))
670 /* Perform the skew correction, positive value to send earlier. */
671 mts -= sh->txpp.skew;
673 if (unlikely(mts >= UINT64_MAX / 2)) {
674 /* We have negative integer, mts is in the past. */
675 rte_atomic32_inc(&sh->txpp.err_ts_past);
678 tick = sh->txpp.tick;
680 /* Convert delta to completions, round up. */
681 mts = (mts + tick - 1) / tick;
682 if (unlikely(mts >= (1 << MLX5_CQ_INDEX_WIDTH) / 2 - 1)) {
683 /* We have mts is too distant future. */
684 rte_atomic32_inc(&sh->txpp.err_ts_future);
687 mts <<= 64 - MLX5_CQ_INDEX_WIDTH;
689 ci >>= 64 - MLX5_CQ_INDEX_WIDTH;
694 * Set timestamp in mbuf dynamic field.
697 * Structure to write into.
699 * Dynamic field offset in mbuf structure.
703 static __rte_always_inline void
704 mlx5_timestamp_set(struct rte_mbuf *mbuf, int offset,
705 rte_mbuf_timestamp_t timestamp)
707 *RTE_MBUF_DYNFIELD(mbuf, offset, rte_mbuf_timestamp_t *) = timestamp;
711 * Replace MPRQ buffer.
714 * Pointer to Rx queue structure.
716 * RQ index to replace.
718 static __rte_always_inline void
719 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx)
721 const uint32_t strd_n = 1 << rxq->strd_num_n;
722 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
723 volatile struct mlx5_wqe_data_seg *wqe =
724 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
725 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_idx];
728 if (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) > 1) {
729 MLX5_ASSERT(rep != NULL);
730 /* Replace MPRQ buf. */
731 (*rxq->mprq_bufs)[rq_idx] = rep;
733 addr = mlx5_mprq_buf_addr(rep, strd_n);
734 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
735 /* If there's only one MR, no need to replace LKey in WQE. */
736 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
737 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
738 /* Stash a mbuf for next replacement. */
739 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
740 rxq->mprq_repl = rep;
742 rxq->mprq_repl = NULL;
743 /* Release the old buffer. */
744 mlx5_mprq_buf_free(buf);
745 } else if (unlikely(rxq->mprq_repl == NULL)) {
746 struct mlx5_mprq_buf *rep;
749 * Currently, the MPRQ mempool is out of buffer
750 * and doing memcpy regardless of the size of Rx
751 * packet. Retry allocation to get back to
754 if (!rte_mempool_get(rxq->mprq_mp, (void **)&rep))
755 rxq->mprq_repl = rep;
760 * Attach or copy MPRQ buffer content to a packet.
763 * Pointer to Rx queue structure.
765 * Pointer to a packet to fill.
769 * Pointer to a MPRQ buffer to take the data from.
771 * Stride index to start from.
773 * Number of strides to consume.
775 static __rte_always_inline enum mlx5_rqx_code
776 mprq_buf_to_pkt(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt, uint32_t len,
777 struct mlx5_mprq_buf *buf, uint16_t strd_idx, uint16_t strd_cnt)
779 const uint32_t strd_n = 1 << rxq->strd_num_n;
780 const uint16_t strd_sz = 1 << rxq->strd_sz_n;
781 const uint16_t strd_shift =
782 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
783 const int32_t hdrm_overlap =
784 len + RTE_PKTMBUF_HEADROOM - strd_cnt * strd_sz;
785 const uint32_t offset = strd_idx * strd_sz + strd_shift;
786 void *addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset);
789 * Memcpy packets to the target mbuf if:
790 * - The size of packet is smaller than mprq_max_memcpy_len.
791 * - Out of buffer in the Mempool for Multi-Packet RQ.
792 * - The packet's stride overlaps a headroom and scatter is off.
794 if (len <= rxq->mprq_max_memcpy_len ||
795 rxq->mprq_repl == NULL ||
796 (hdrm_overlap > 0 && !rxq->strd_scatter_en)) {
798 (uint32_t)(pkt->buf_len - RTE_PKTMBUF_HEADROOM))) {
799 rte_memcpy(rte_pktmbuf_mtod(pkt, void *),
802 } else if (rxq->strd_scatter_en) {
803 struct rte_mbuf *prev = pkt;
804 uint32_t seg_len = RTE_MIN(len, (uint32_t)
805 (pkt->buf_len - RTE_PKTMBUF_HEADROOM));
806 uint32_t rem_len = len - seg_len;
808 rte_memcpy(rte_pktmbuf_mtod(pkt, void *),
810 DATA_LEN(pkt) = seg_len;
812 struct rte_mbuf *next =
813 rte_pktmbuf_alloc(rxq->mp);
815 if (unlikely(next == NULL))
816 return MLX5_RXQ_CODE_NOMBUF;
818 SET_DATA_OFF(next, 0);
819 addr = RTE_PTR_ADD(addr, seg_len);
820 seg_len = RTE_MIN(rem_len, (uint32_t)
821 (next->buf_len - RTE_PKTMBUF_HEADROOM));
823 (rte_pktmbuf_mtod(next, void *),
825 DATA_LEN(next) = seg_len;
831 return MLX5_RXQ_CODE_DROPPED;
835 struct rte_mbuf_ext_shared_info *shinfo;
836 uint16_t buf_len = strd_cnt * strd_sz;
839 /* Increment the refcnt of the whole chunk. */
840 __atomic_add_fetch(&buf->refcnt, 1, __ATOMIC_RELAXED);
841 MLX5_ASSERT(__atomic_load_n(&buf->refcnt,
842 __ATOMIC_RELAXED) <= strd_n + 1);
843 buf_addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
845 * MLX5 device doesn't use iova but it is necessary in a
846 * case where the Rx packet is transmitted via a
849 buf_iova = rte_mempool_virt2iova(buf) +
850 RTE_PTR_DIFF(buf_addr, buf);
851 shinfo = &buf->shinfos[strd_idx];
852 rte_mbuf_ext_refcnt_set(shinfo, 1);
854 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
855 * attaching the stride to mbuf and more offload flags
856 * will be added below by calling rxq_cq_to_mbuf().
857 * Other fields will be overwritten.
859 rte_pktmbuf_attach_extbuf(pkt, buf_addr, buf_iova,
861 /* Set mbuf head-room. */
862 SET_DATA_OFF(pkt, RTE_PKTMBUF_HEADROOM);
863 MLX5_ASSERT(pkt->ol_flags == EXT_ATTACHED_MBUF);
864 MLX5_ASSERT(rte_pktmbuf_tailroom(pkt) >=
865 len - (hdrm_overlap > 0 ? hdrm_overlap : 0));
868 * Copy the last fragment of a packet (up to headroom
869 * size bytes) in case there is a stride overlap with
870 * a next packet's headroom. Allocate a separate mbuf
871 * to store this fragment and link it. Scatter is on.
873 if (hdrm_overlap > 0) {
874 MLX5_ASSERT(rxq->strd_scatter_en);
875 struct rte_mbuf *seg =
876 rte_pktmbuf_alloc(rxq->mp);
878 if (unlikely(seg == NULL))
879 return MLX5_RXQ_CODE_NOMBUF;
880 SET_DATA_OFF(seg, 0);
881 rte_memcpy(rte_pktmbuf_mtod(seg, void *),
882 RTE_PTR_ADD(addr, len - hdrm_overlap),
884 DATA_LEN(seg) = hdrm_overlap;
885 DATA_LEN(pkt) = len - hdrm_overlap;
890 return MLX5_RXQ_CODE_EXIT;
893 #endif /* RTE_PMD_MLX5_RXTX_H_ */