1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 #include <rte_mempool.h>
15 #include <rte_common.h>
16 #include <rte_hexdump.h>
17 #include <rte_atomic.h>
18 #include <rte_spinlock.h>
20 #include <rte_bus_pci.h>
21 #include <rte_malloc.h>
22 #include <rte_cycles.h>
24 #include <mlx5_glue.h>
26 #include <mlx5_common.h>
27 #include <mlx5_common_mr.h>
29 #include "mlx5_defs.h"
30 #include "mlx5_utils.h"
32 #include "mlx5_autoconf.h"
35 /* Support tunnel matching. */
36 #define MLX5_FLOW_TUNNEL 10
38 /* Mbuf dynamic flag offset for inline. */
39 extern uint64_t rte_net_mlx5_dynf_inline_mask;
41 struct mlx5_rxq_stats {
42 #ifdef MLX5_PMD_SOFT_COUNTERS
43 uint64_t ipackets; /**< Total of successfully received packets. */
44 uint64_t ibytes; /**< Total of successfully received bytes. */
46 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
47 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
50 struct mlx5_txq_stats {
51 #ifdef MLX5_PMD_SOFT_COUNTERS
52 uint64_t opackets; /**< Total of successfully sent packets. */
53 uint64_t obytes; /**< Total of successfully sent bytes. */
55 uint64_t oerrors; /**< Total number of failed transmitted packets. */
60 /* Compressed CQE context. */
62 uint16_t ai; /* Array index. */
63 uint16_t ca; /* Current array index. */
64 uint16_t na; /* Next array index. */
65 uint16_t cq_ci; /* The next CQE. */
66 uint32_t cqe_cnt; /* Number of CQEs. */
69 /* Multi-Packet RQ buffer header. */
70 struct mlx5_mprq_buf {
71 struct rte_mempool *mp;
72 uint16_t refcnt; /* Atomically accessed refcnt. */
73 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
74 struct rte_mbuf_ext_shared_info shinfos[];
76 * Shared information per stride.
77 * More memory will be allocated for the first stride head-room and for
80 } __rte_cache_aligned;
82 /* Get pointer to the first stride. */
83 #define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \
84 sizeof(struct mlx5_mprq_buf) + \
86 sizeof(struct rte_mbuf_ext_shared_info) + \
87 RTE_PKTMBUF_HEADROOM))
89 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
90 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
92 enum mlx5_rxq_err_state {
93 MLX5_RXQ_ERR_STATE_NO_ERROR = 0,
94 MLX5_RXQ_ERR_STATE_NEED_RESET,
95 MLX5_RXQ_ERR_STATE_NEED_READY,
99 MLX5_RXQ_CODE_EXIT = 0,
100 MLX5_RXQ_CODE_NOMBUF,
101 MLX5_RXQ_CODE_DROPPED,
104 struct mlx5_eth_rxseg {
105 struct rte_mempool *mp; /**< Memory pool to allocate segment from. */
106 uint16_t length; /**< Segment data length, configures split point. */
107 uint16_t offset; /**< Data offset from beginning of mbuf data buffer. */
108 uint32_t reserved; /**< Reserved field. */
111 /* RX queue descriptor. */
112 struct mlx5_rxq_data {
113 unsigned int csum:1; /* Enable checksum offloading. */
114 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
115 unsigned int rt_timestamp:1; /* Realtime timestamp format. */
116 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
117 unsigned int crc_present:1; /* CRC must be subtracted. */
118 unsigned int sges_n:3; /* Log 2 of SGEs (max buffers per packet). */
119 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
120 unsigned int elts_n:4; /* Log 2 of Mbufs. */
121 unsigned int rss_hash:1; /* RSS hash result is enabled. */
122 unsigned int mark:1; /* Marked flow available on the queue. */
123 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
124 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
125 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
126 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
127 unsigned int strd_scatter_en:1; /* Scattered packets from a stride. */
128 unsigned int lro:1; /* Enable LRO. */
129 unsigned int dynf_meta:1; /* Dynamic metadata is configured. */
130 volatile uint32_t *rq_db;
131 volatile uint32_t *cq_db;
135 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
138 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
140 struct rxq_zip zip; /* Compressed context. */
141 uint16_t decompressed;
142 /* Number of ready mbufs decompressed from the CQ. */
144 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
145 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
147 volatile struct mlx5_cqe(*cqes)[];
148 struct rte_mbuf *(*elts)[];
149 struct mlx5_mprq_buf *(*mprq_bufs)[];
150 struct rte_mempool *mp;
151 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
152 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
153 struct mlx5_dev_ctx_shared *sh; /* Shared context. */
154 uint16_t idx; /* Queue index. */
155 struct mlx5_rxq_stats stats;
156 rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */
157 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
158 void *cq_uar; /* Verbs CQ user access region. */
159 uint32_t cqn; /* CQ number. */
160 uint8_t cq_arm_sn; /* CQ arm seq number. */
162 rte_spinlock_t *uar_lock_cq;
163 /* CQ (UAR) access lock required for 32bit implementations */
165 uint32_t tunnel; /* Tunnel information. */
166 int timestamp_offset; /* Dynamic mbuf field for timestamp. */
167 uint64_t timestamp_rx_flag; /* Dynamic mbuf flag for timestamp. */
168 uint64_t flow_meta_mask;
169 int32_t flow_meta_offset;
170 uint32_t rxseg_n; /* Number of split segment descriptions. */
171 struct mlx5_eth_rxseg rxseg[MLX5_MAX_RXQ_NSEG];
172 /* Buffer split segment descriptions - sizes, offsets, pools. */
173 } __rte_cache_aligned;
176 MLX5_RXQ_TYPE_STANDARD, /* Standard Rx queue. */
177 MLX5_RXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
178 MLX5_RXQ_TYPE_UNDEFINED,
181 /* RX queue control descriptor. */
182 struct mlx5_rxq_ctrl {
183 struct mlx5_rxq_data rxq; /* Data path structure. */
184 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
185 uint32_t refcnt; /* Reference counter. */
186 struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */
187 struct mlx5_priv *priv; /* Back pointer to private data. */
188 enum mlx5_rxq_type type; /* Rxq type. */
189 unsigned int socket; /* CPU socket ID for allocations. */
190 unsigned int irq:1; /* Whether IRQ is enabled. */
191 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
192 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
193 uint32_t wqn; /* WQ number. */
194 uint16_t dump_file_n; /* Number of dump files. */
195 struct mlx5_devx_dbr_page *rq_dbrec_page;
196 uint64_t rq_dbr_offset;
197 /* Storing RQ door-bell information, needed when freeing door-bell. */
198 struct mlx5_devx_dbr_page *cq_dbrec_page;
199 uint64_t cq_dbr_offset;
200 /* Storing CQ door-bell information, needed when freeing door-bell. */
201 void *wq_umem; /* WQ buffer registration info. */
202 void *cq_umem; /* CQ buffer registration info. */
203 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
206 /* TX queue send local data. */
208 struct mlx5_txq_local {
209 struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */
210 struct rte_mbuf *mbuf; /* first mbuf to process. */
211 uint16_t pkts_copy; /* packets copied to elts. */
212 uint16_t pkts_sent; /* packets sent. */
213 uint16_t pkts_loop; /* packets sent on loop entry. */
214 uint16_t elts_free; /* available elts remain. */
215 uint16_t wqe_free; /* available wqe remain. */
216 uint16_t mbuf_off; /* data offset in current mbuf. */
217 uint16_t mbuf_nseg; /* number of remaining mbuf. */
220 /* TX queue descriptor. */
222 struct mlx5_txq_data {
223 uint16_t elts_head; /* Current counter in (*elts)[]. */
224 uint16_t elts_tail; /* Counter of first element awaiting completion. */
225 uint16_t elts_comp; /* elts index since last completion request. */
226 uint16_t elts_s; /* Number of mbuf elements. */
227 uint16_t elts_m; /* Mask for mbuf elements indices. */
228 /* Fields related to elts mbuf storage. */
229 uint16_t wqe_ci; /* Consumer index for work queue. */
230 uint16_t wqe_pi; /* Producer index for work queue. */
231 uint16_t wqe_s; /* Number of WQ elements. */
232 uint16_t wqe_m; /* Mask Number for WQ elements. */
233 uint16_t wqe_comp; /* WQE index since last completion request. */
234 uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */
235 /* WQ related fields. */
236 uint16_t cq_ci; /* Consumer index for completion queue. */
237 uint16_t cq_pi; /* Production index for completion queue. */
238 uint16_t cqe_s; /* Number of CQ elements. */
239 uint16_t cqe_m; /* Mask for CQ indices. */
240 /* CQ related fields. */
241 uint16_t elts_n:4; /* elts[] length (in log2). */
242 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
243 uint16_t wqe_n:4; /* Number of WQ elements (in log2). */
244 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
245 uint16_t tunnel_en:1;
246 /* When set TX offload for tunneled packets are supported. */
247 uint16_t swp_en:1; /* Whether SW parser is enabled. */
248 uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */
249 uint16_t db_nc:1; /* Doorbell mapped to non-cached region. */
250 uint16_t db_heu:1; /* Doorbell heuristic write barrier. */
251 uint16_t inlen_send; /* Ordinary send data inline size. */
252 uint16_t inlen_empw; /* eMPW max packet size to inline. */
253 uint16_t inlen_mode; /* Minimal data length to inline. */
254 uint32_t qp_num_8s; /* QP number shifted by 8. */
255 uint64_t offloads; /* Offloads for Tx Queue. */
256 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
257 struct mlx5_wqe *wqes; /* Work queue. */
258 struct mlx5_wqe *wqes_end; /* Work queue array limit. */
259 #ifdef RTE_LIBRTE_MLX5_DEBUG
260 uint32_t *fcqs; /* Free completion queue (debug extended). */
262 uint16_t *fcqs; /* Free completion queue. */
264 volatile struct mlx5_cqe *cqes; /* Completion queue. */
265 volatile uint32_t *qp_db; /* Work queue doorbell. */
266 volatile uint32_t *cq_db; /* Completion queue doorbell. */
267 uint16_t port_id; /* Port ID of device. */
268 uint16_t idx; /* Queue index. */
269 uint64_t ts_mask; /* Timestamp flag dynamic mask. */
270 int32_t ts_offset; /* Timestamp field dynamic offset. */
271 struct mlx5_dev_ctx_shared *sh; /* Shared context. */
272 struct mlx5_txq_stats stats; /* TX queue counters. */
274 rte_spinlock_t *uar_lock;
275 /* UAR access lock required for 32bit implementations */
277 struct rte_mbuf *elts[0];
278 /* Storage for queued packets, must be the last field. */
279 } __rte_cache_aligned;
282 MLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */
283 MLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
286 /* TX queue control descriptor. */
287 struct mlx5_txq_ctrl {
288 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
289 uint32_t refcnt; /* Reference counter. */
290 unsigned int socket; /* CPU socket ID for allocations. */
291 enum mlx5_txq_type type; /* The txq ctrl type. */
292 unsigned int max_inline_data; /* Max inline data. */
293 unsigned int max_tso_header; /* Max TSO header size. */
294 struct mlx5_txq_obj *obj; /* Verbs/DevX queue object. */
295 struct mlx5_priv *priv; /* Back pointer to private data. */
296 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
297 void *bf_reg; /* BlueFlame register from Verbs. */
298 uint16_t dump_file_n; /* Number of dump files. */
299 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
300 struct mlx5_txq_data txq; /* Data path structure. */
301 /* Must be the last field in the structure, contains elts[]. */
304 #define MLX5_TX_BFREG(txq) \
305 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx])
309 extern uint8_t rss_hash_default_key[];
311 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
312 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
313 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
314 unsigned int mlx5_rxq_cqe_num(struct mlx5_rxq_data *rxq_data);
315 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
316 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
317 int mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id);
318 int mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id);
319 int mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id);
320 int mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id);
321 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
322 unsigned int socket, const struct rte_eth_rxconf *conf,
323 struct rte_mempool *mp);
324 int mlx5_rx_hairpin_queue_setup
325 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
326 const struct rte_eth_hairpin_conf *hairpin_conf);
327 void mlx5_rx_queue_release(void *dpdk_rxq);
328 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
329 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
330 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
331 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
332 int mlx5_rxq_obj_verify(struct rte_eth_dev *dev);
333 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
334 uint16_t desc, unsigned int socket,
335 const struct rte_eth_rxconf *conf,
336 const struct rte_eth_rxseg_split *rx_seg,
338 struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new
339 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
340 const struct rte_eth_hairpin_conf *hairpin_conf);
341 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
342 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
343 int mlx5_rxq_verify(struct rte_eth_dev *dev);
344 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
345 int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev);
346 struct mlx5_ind_table_obj *mlx5_ind_table_obj_get(struct rte_eth_dev *dev,
347 const uint16_t *queues,
349 int mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
350 struct mlx5_ind_table_obj *ind_tbl);
351 uint32_t mlx5_hrxq_new(struct rte_eth_dev *dev,
352 const uint8_t *rss_key, uint32_t rss_key_len,
353 uint64_t hash_fields,
354 const uint16_t *queues, uint32_t queues_n,
355 int tunnel, bool shared);
356 uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev,
357 const uint8_t *rss_key, uint32_t rss_key_len,
358 uint64_t hash_fields,
359 const uint16_t *queues, uint32_t queues_n);
360 int mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hxrq_idx);
361 int mlx5_hrxq_verify(struct rte_eth_dev *dev);
362 enum mlx5_rxq_type mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx);
363 struct mlx5_hrxq *mlx5_drop_action_create(struct rte_eth_dev *dev);
364 void mlx5_drop_action_destroy(struct rte_eth_dev *dev);
365 uint64_t mlx5_get_rx_port_offloads(void);
366 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
367 void mlx5_rxq_timestamp_set(struct rte_eth_dev *dev);
368 int mlx5_hrxq_modify(struct rte_eth_dev *dev, uint32_t hxrq_idx,
369 const uint8_t *rss_key, uint32_t rss_key_len,
370 uint64_t hash_fields,
371 const uint16_t *queues, uint32_t queues_n);
375 int mlx5_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id);
376 int mlx5_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id);
377 int mlx5_tx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id);
378 int mlx5_tx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id);
379 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
380 unsigned int socket, const struct rte_eth_txconf *conf);
381 int mlx5_tx_hairpin_queue_setup
382 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
383 const struct rte_eth_hairpin_conf *hairpin_conf);
384 void mlx5_tx_queue_release(void *dpdk_txq);
385 void txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl);
386 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
387 void mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev);
388 int mlx5_txq_obj_verify(struct rte_eth_dev *dev);
389 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
390 uint16_t desc, unsigned int socket,
391 const struct rte_eth_txconf *conf);
392 struct mlx5_txq_ctrl *mlx5_txq_hairpin_new
393 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
394 const struct rte_eth_hairpin_conf *hairpin_conf);
395 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
396 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
397 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
398 int mlx5_txq_verify(struct rte_eth_dev *dev);
399 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
400 void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl);
401 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
402 void mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev);
406 extern uint32_t mlx5_ptype_table[];
407 extern uint8_t mlx5_cksum_table[];
408 extern uint8_t mlx5_swp_types_table[];
410 void mlx5_set_ptype_table(void);
411 void mlx5_set_cksum_table(void);
412 void mlx5_set_swp_types_table(void);
413 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
414 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);
415 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec);
416 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
417 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
418 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
420 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
422 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
424 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
425 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
426 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
427 void mlx5_dump_debug_information(const char *path, const char *title,
428 const void *buf, unsigned int len);
429 int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
430 const struct mlx5_mp_arg_queue_state_modify *sm);
431 void mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
432 struct rte_eth_rxq_info *qinfo);
433 void mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
434 struct rte_eth_txq_info *qinfo);
435 int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
436 struct rte_eth_burst_mode *mode);
437 int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
438 struct rte_eth_burst_mode *mode);
440 /* Vectorized version of mlx5_rxtx.c */
441 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
442 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
443 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
445 uint16_t mlx5_rx_burst_mprq_vec(void *dpdk_txq, struct rte_mbuf **pkts,
450 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
451 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
452 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
453 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
454 struct rte_mempool *mp);
455 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
457 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
461 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
462 * 64bit architectures.
465 * value to write in CPU endian format.
467 * Address to write to.
469 * Address of the lock to use for that UAR access.
471 static __rte_always_inline void
472 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
473 rte_spinlock_t *lock __rte_unused)
476 *(uint64_t *)addr = val;
477 #else /* !RTE_ARCH_64 */
478 rte_spinlock_lock(lock);
479 *(uint32_t *)addr = val;
481 *((uint32_t *)addr + 1) = val >> 32;
482 rte_spinlock_unlock(lock);
487 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
488 * 64bit architectures while guaranteeing the order of execution with the
489 * code being executed.
492 * value to write in CPU endian format.
494 * Address to write to.
496 * Address of the lock to use for that UAR access.
498 static __rte_always_inline void
499 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
502 __mlx5_uar_write64_relaxed(val, addr, lock);
505 /* Assist macros, used instead of directly calling the functions they wrap. */
507 #define mlx5_uar_write64_relaxed(val, dst, lock) \
508 __mlx5_uar_write64_relaxed(val, dst, NULL)
509 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
511 #define mlx5_uar_write64_relaxed(val, dst, lock) \
512 __mlx5_uar_write64_relaxed(val, dst, lock)
513 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
517 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
518 * cloned mbuf is allocated is returned instead.
524 * Memory pool where data is located for given mbuf.
526 static inline struct rte_mempool *
527 mlx5_mb2mp(struct rte_mbuf *buf)
529 if (unlikely(RTE_MBUF_CLONED(buf)))
530 return rte_mbuf_from_indirect(buf)->pool;
535 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
536 * as mempool is pre-configured and static.
539 * Pointer to Rx queue structure.
544 * Searched LKey on success, UINT32_MAX on no match.
546 static __rte_always_inline uint32_t
547 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
549 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
552 /* Linear search on MR cache array. */
553 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
554 MLX5_MR_CACHE_N, addr);
555 if (likely(lkey != UINT32_MAX))
557 /* Take slower bottom-half (Binary Search) on miss. */
558 return mlx5_rx_addr2mr_bh(rxq, addr);
561 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
564 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
567 * Pointer to Tx queue structure.
572 * Searched LKey on success, UINT32_MAX on no match.
574 static __rte_always_inline uint32_t
575 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
577 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
578 uintptr_t addr = (uintptr_t)mb->buf_addr;
581 /* Check generation bit to see if there's any change on existing MRs. */
582 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
583 mlx5_mr_flush_local_cache(mr_ctrl);
584 /* Linear search on MR cache array. */
585 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
586 MLX5_MR_CACHE_N, addr);
587 if (likely(lkey != UINT32_MAX))
589 /* Take slower bottom-half on miss. */
590 return mlx5_tx_mb2mr_bh(txq, mb);
594 * Ring TX queue doorbell and flush the update if requested.
597 * Pointer to TX queue structure.
599 * Pointer to the last WQE posted in the NIC.
601 * Request for write memory barrier after BlueFlame update.
603 static __rte_always_inline void
604 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
607 uint64_t *dst = MLX5_TX_BFREG(txq);
608 volatile uint64_t *src = ((volatile uint64_t *)wqe);
611 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
612 /* Ensure ordering between DB record and BF copy. */
614 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
620 * Ring TX queue doorbell and flush the update by write memory barrier.
623 * Pointer to TX queue structure.
625 * Pointer to the last WQE posted in the NIC.
627 static __rte_always_inline void
628 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
630 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
634 * Convert timestamp from HW format to linear counter
635 * from Packet Pacing Clock Queue CQE timestamp format.
638 * Pointer to the device shared context. Might be needed
639 * to convert according current device configuration.
641 * Timestamp from CQE to convert.
645 static __rte_always_inline uint64_t
646 mlx5_txpp_convert_rx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t ts)
649 return (ts & UINT32_MAX) + (ts >> 32) * NS_PER_S;
653 * Convert timestamp from mbuf format to linear counter
654 * of Clock Queue completions (24 bits)
657 * Pointer to the device shared context to fetch Tx
658 * packet pacing timestamp and parameters.
660 * Timestamp from mbuf to convert.
662 * positive or zero value - completion ID to wait
663 * negative value - conversion error
665 static __rte_always_inline int32_t
666 mlx5_txpp_convert_tx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t mts)
673 * Read atomically two uint64_t fields and compare lsb bits.
674 * It there is no match - the timestamp was updated in
675 * the service thread, data should be re-read.
677 rte_compiler_barrier();
678 ci = rte_atomic64_read(&sh->txpp.ts.ci_ts);
679 ts = rte_atomic64_read(&sh->txpp.ts.ts);
680 rte_compiler_barrier();
681 if (!((ts ^ ci) << (64 - MLX5_CQ_INDEX_WIDTH)))
684 /* Perform the skew correction, positive value to send earlier. */
685 mts -= sh->txpp.skew;
687 if (unlikely(mts >= UINT64_MAX / 2)) {
688 /* We have negative integer, mts is in the past. */
689 rte_atomic32_inc(&sh->txpp.err_ts_past);
692 tick = sh->txpp.tick;
694 /* Convert delta to completions, round up. */
695 mts = (mts + tick - 1) / tick;
696 if (unlikely(mts >= (1 << MLX5_CQ_INDEX_WIDTH) / 2 - 1)) {
697 /* We have mts is too distant future. */
698 rte_atomic32_inc(&sh->txpp.err_ts_future);
701 mts <<= 64 - MLX5_CQ_INDEX_WIDTH;
703 ci >>= 64 - MLX5_CQ_INDEX_WIDTH;
708 * Set timestamp in mbuf dynamic field.
711 * Structure to write into.
713 * Dynamic field offset in mbuf structure.
717 static __rte_always_inline void
718 mlx5_timestamp_set(struct rte_mbuf *mbuf, int offset,
719 rte_mbuf_timestamp_t timestamp)
721 *RTE_MBUF_DYNFIELD(mbuf, offset, rte_mbuf_timestamp_t *) = timestamp;
725 * Replace MPRQ buffer.
728 * Pointer to Rx queue structure.
730 * RQ index to replace.
732 static __rte_always_inline void
733 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx)
735 const uint32_t strd_n = 1 << rxq->strd_num_n;
736 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
737 volatile struct mlx5_wqe_data_seg *wqe =
738 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
739 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_idx];
742 if (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) > 1) {
743 MLX5_ASSERT(rep != NULL);
744 /* Replace MPRQ buf. */
745 (*rxq->mprq_bufs)[rq_idx] = rep;
747 addr = mlx5_mprq_buf_addr(rep, strd_n);
748 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
749 /* If there's only one MR, no need to replace LKey in WQE. */
750 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
751 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
752 /* Stash a mbuf for next replacement. */
753 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
754 rxq->mprq_repl = rep;
756 rxq->mprq_repl = NULL;
757 /* Release the old buffer. */
758 mlx5_mprq_buf_free(buf);
759 } else if (unlikely(rxq->mprq_repl == NULL)) {
760 struct mlx5_mprq_buf *rep;
763 * Currently, the MPRQ mempool is out of buffer
764 * and doing memcpy regardless of the size of Rx
765 * packet. Retry allocation to get back to
768 if (!rte_mempool_get(rxq->mprq_mp, (void **)&rep))
769 rxq->mprq_repl = rep;
774 * Attach or copy MPRQ buffer content to a packet.
777 * Pointer to Rx queue structure.
779 * Pointer to a packet to fill.
783 * Pointer to a MPRQ buffer to take the data from.
785 * Stride index to start from.
787 * Number of strides to consume.
789 static __rte_always_inline enum mlx5_rqx_code
790 mprq_buf_to_pkt(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt, uint32_t len,
791 struct mlx5_mprq_buf *buf, uint16_t strd_idx, uint16_t strd_cnt)
793 const uint32_t strd_n = 1 << rxq->strd_num_n;
794 const uint16_t strd_sz = 1 << rxq->strd_sz_n;
795 const uint16_t strd_shift =
796 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
797 const int32_t hdrm_overlap =
798 len + RTE_PKTMBUF_HEADROOM - strd_cnt * strd_sz;
799 const uint32_t offset = strd_idx * strd_sz + strd_shift;
800 void *addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset);
803 * Memcpy packets to the target mbuf if:
804 * - The size of packet is smaller than mprq_max_memcpy_len.
805 * - Out of buffer in the Mempool for Multi-Packet RQ.
806 * - The packet's stride overlaps a headroom and scatter is off.
808 if (len <= rxq->mprq_max_memcpy_len ||
809 rxq->mprq_repl == NULL ||
810 (hdrm_overlap > 0 && !rxq->strd_scatter_en)) {
812 (uint32_t)(pkt->buf_len - RTE_PKTMBUF_HEADROOM))) {
813 rte_memcpy(rte_pktmbuf_mtod(pkt, void *),
816 } else if (rxq->strd_scatter_en) {
817 struct rte_mbuf *prev = pkt;
818 uint32_t seg_len = RTE_MIN(len, (uint32_t)
819 (pkt->buf_len - RTE_PKTMBUF_HEADROOM));
820 uint32_t rem_len = len - seg_len;
822 rte_memcpy(rte_pktmbuf_mtod(pkt, void *),
824 DATA_LEN(pkt) = seg_len;
826 struct rte_mbuf *next =
827 rte_pktmbuf_alloc(rxq->mp);
829 if (unlikely(next == NULL))
830 return MLX5_RXQ_CODE_NOMBUF;
832 SET_DATA_OFF(next, 0);
833 addr = RTE_PTR_ADD(addr, seg_len);
834 seg_len = RTE_MIN(rem_len, (uint32_t)
835 (next->buf_len - RTE_PKTMBUF_HEADROOM));
837 (rte_pktmbuf_mtod(next, void *),
839 DATA_LEN(next) = seg_len;
845 return MLX5_RXQ_CODE_DROPPED;
849 struct rte_mbuf_ext_shared_info *shinfo;
850 uint16_t buf_len = strd_cnt * strd_sz;
853 /* Increment the refcnt of the whole chunk. */
854 __atomic_add_fetch(&buf->refcnt, 1, __ATOMIC_RELAXED);
855 MLX5_ASSERT(__atomic_load_n(&buf->refcnt,
856 __ATOMIC_RELAXED) <= strd_n + 1);
857 buf_addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
859 * MLX5 device doesn't use iova but it is necessary in a
860 * case where the Rx packet is transmitted via a
863 buf_iova = rte_mempool_virt2iova(buf) +
864 RTE_PTR_DIFF(buf_addr, buf);
865 shinfo = &buf->shinfos[strd_idx];
866 rte_mbuf_ext_refcnt_set(shinfo, 1);
868 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
869 * attaching the stride to mbuf and more offload flags
870 * will be added below by calling rxq_cq_to_mbuf().
871 * Other fields will be overwritten.
873 rte_pktmbuf_attach_extbuf(pkt, buf_addr, buf_iova,
875 /* Set mbuf head-room. */
876 SET_DATA_OFF(pkt, RTE_PKTMBUF_HEADROOM);
877 MLX5_ASSERT(pkt->ol_flags == EXT_ATTACHED_MBUF);
878 MLX5_ASSERT(rte_pktmbuf_tailroom(pkt) >=
879 len - (hdrm_overlap > 0 ? hdrm_overlap : 0));
882 * Copy the last fragment of a packet (up to headroom
883 * size bytes) in case there is a stride overlap with
884 * a next packet's headroom. Allocate a separate mbuf
885 * to store this fragment and link it. Scatter is on.
887 if (hdrm_overlap > 0) {
888 MLX5_ASSERT(rxq->strd_scatter_en);
889 struct rte_mbuf *seg =
890 rte_pktmbuf_alloc(rxq->mp);
892 if (unlikely(seg == NULL))
893 return MLX5_RXQ_CODE_NOMBUF;
894 SET_DATA_OFF(seg, 0);
895 rte_memcpy(rte_pktmbuf_mtod(seg, void *),
896 RTE_PTR_ADD(addr, len - hdrm_overlap),
898 DATA_LEN(seg) = hdrm_overlap;
899 DATA_LEN(pkt) = len - hdrm_overlap;
904 return MLX5_RXQ_CODE_EXIT;
907 #endif /* RTE_PMD_MLX5_RXTX_H_ */