1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
11 #include <sys/queue.h>
13 #include "mlx5_autoconf.h"
16 #include <rte_malloc.h>
17 #include <rte_ethdev_driver.h>
18 #include <rte_common.h>
20 #include <mlx5_glue.h>
21 #include <mlx5_common.h>
22 #include <mlx5_common_mr.h>
23 #include <mlx5_rxtx.h>
24 #include <mlx5_verbs.h>
25 #include <mlx5_utils.h>
26 #include <mlx5_malloc.h>
29 * Register mr. Given protection domain pointer, pointer to addr and length
30 * register the memory region.
33 * Pointer to protection domain context.
35 * Pointer to memory start address.
37 * Length of the memory to register.
39 * pmd_mr struct set with lkey, address, length and pointer to mr object
42 * 0 on successful registration, -1 otherwise
45 mlx5_reg_mr(void *pd, void *addr, size_t length,
46 struct mlx5_pmd_mr *pmd_mr)
48 return mlx5_common_verbs_reg_mr(pd, addr, length, pmd_mr);
52 * Deregister mr. Given the mlx5 pmd MR - deregister the MR
55 * pmd_mr struct set with lkey, address, length and pointer to mr object
59 mlx5_dereg_mr(struct mlx5_pmd_mr *pmd_mr)
61 mlx5_common_verbs_dereg_mr(pmd_mr);
64 /* verbs operations. */
65 const struct mlx5_verbs_ops mlx5_verbs_ops = {
66 .reg_mr = mlx5_reg_mr,
67 .dereg_mr = mlx5_dereg_mr,
71 * Modify Rx WQ vlan stripping offload
76 * @return 0 on success, non-0 otherwise
79 mlx5_rxq_obj_modify_wq_vlan_strip(struct mlx5_rxq_obj *rxq_obj, int on)
81 uint16_t vlan_offloads =
82 (on ? IBV_WQ_FLAGS_CVLAN_STRIPPING : 0) |
84 struct ibv_wq_attr mod;
85 mod = (struct ibv_wq_attr){
86 .attr_mask = IBV_WQ_ATTR_FLAGS,
87 .flags_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING,
88 .flags = vlan_offloads,
91 return mlx5_glue->modify_wq(rxq_obj->wq, &mod);
95 * Modifies the attributes for the specified WQ.
98 * Verbs Rx queue object.
100 * Type of change queue state.
103 * 0 on success, a negative errno value otherwise and rte_errno is set.
106 mlx5_ibv_modify_wq(struct mlx5_rxq_obj *rxq_obj, uint8_t type)
108 struct ibv_wq_attr mod = {
109 .attr_mask = IBV_WQ_ATTR_STATE,
110 .wq_state = (enum ibv_wq_state)type,
113 return mlx5_glue->modify_wq(rxq_obj->wq, &mod);
117 * Modify QP using Verbs API.
120 * Verbs Tx queue object.
122 * Type of change queue state.
124 * IB device port number.
127 * 0 on success, a negative errno value otherwise and rte_errno is set.
130 mlx5_ibv_modify_qp(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type,
133 struct ibv_qp_attr mod = {
134 .qp_state = IBV_QPS_RESET,
135 .port_num = dev_port,
137 int attr_mask = (IBV_QP_STATE | IBV_QP_PORT);
140 if (type != MLX5_TXQ_MOD_RST2RDY) {
141 ret = mlx5_glue->modify_qp(obj->qp, &mod, IBV_QP_STATE);
143 DRV_LOG(ERR, "Cannot change Tx QP state to RESET %s",
148 if (type == MLX5_TXQ_MOD_RDY2RST)
151 if (type == MLX5_TXQ_MOD_ERR2RDY)
152 attr_mask = IBV_QP_STATE;
153 mod.qp_state = IBV_QPS_INIT;
154 ret = mlx5_glue->modify_qp(obj->qp, &mod, attr_mask);
156 DRV_LOG(ERR, "Cannot change Tx QP state to INIT %s",
161 mod.qp_state = IBV_QPS_RTR;
162 ret = mlx5_glue->modify_qp(obj->qp, &mod, IBV_QP_STATE);
164 DRV_LOG(ERR, "Cannot change Tx QP state to RTR %s",
169 mod.qp_state = IBV_QPS_RTS;
170 ret = mlx5_glue->modify_qp(obj->qp, &mod, IBV_QP_STATE);
172 DRV_LOG(ERR, "Cannot change Tx QP state to RTS %s",
181 * Create a CQ Verbs object.
184 * Pointer to Ethernet device.
186 * Queue index in DPDK Rx queue array.
189 * The Verbs CQ object initialized, NULL otherwise and rte_errno is set.
191 static struct ibv_cq *
192 mlx5_rxq_ibv_cq_create(struct rte_eth_dev *dev, uint16_t idx)
194 struct mlx5_priv *priv = dev->data->dev_private;
195 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
196 struct mlx5_rxq_ctrl *rxq_ctrl =
197 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
198 struct mlx5_rxq_obj *rxq_obj = rxq_ctrl->obj;
199 unsigned int cqe_n = mlx5_rxq_cqe_num(rxq_data);
201 struct ibv_cq_init_attr_ex ibv;
202 struct mlx5dv_cq_init_attr mlx5;
205 cq_attr.ibv = (struct ibv_cq_init_attr_ex){
207 .channel = rxq_obj->ibv_channel,
210 cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
213 if (priv->config.cqe_comp && !rxq_data->hw_timestamp) {
214 cq_attr.mlx5.comp_mask |=
215 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
216 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
217 cq_attr.mlx5.cqe_comp_res_format =
218 mlx5_rxq_mprq_enabled(rxq_data) ?
219 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
220 MLX5DV_CQE_RES_FORMAT_HASH;
222 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
225 * For vectorized Rx, it must not be doubled in order to
226 * make cq_ci and rq_ci aligned.
228 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
229 cq_attr.ibv.cqe *= 2;
230 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
232 "Port %u Rx CQE compression is disabled for HW"
236 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
237 if (priv->config.cqe_pad) {
238 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
239 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
242 return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
248 * Create a WQ Verbs object.
251 * Pointer to Ethernet device.
253 * Queue index in DPDK Rx queue array.
256 * The Verbs WQ object initialized, NULL otherwise and rte_errno is set.
258 static struct ibv_wq *
259 mlx5_rxq_ibv_wq_create(struct rte_eth_dev *dev, uint16_t idx)
261 struct mlx5_priv *priv = dev->data->dev_private;
262 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
263 struct mlx5_rxq_ctrl *rxq_ctrl =
264 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
265 struct mlx5_rxq_obj *rxq_obj = rxq_ctrl->obj;
266 unsigned int wqe_n = 1 << rxq_data->elts_n;
268 struct ibv_wq_init_attr ibv;
269 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
270 struct mlx5dv_wq_init_attr mlx5;
274 wq_attr.ibv = (struct ibv_wq_init_attr){
275 .wq_context = NULL, /* Could be useful in the future. */
276 .wq_type = IBV_WQT_RQ,
277 /* Max number of outstanding WRs. */
278 .max_wr = wqe_n >> rxq_data->sges_n,
279 /* Max number of scatter/gather elements in a WR. */
280 .max_sge = 1 << rxq_data->sges_n,
282 .cq = rxq_obj->ibv_cq,
283 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
284 .create_flags = (rxq_data->vlan_strip ?
285 IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
287 /* By default, FCS (CRC) is stripped by hardware. */
288 if (rxq_data->crc_present) {
289 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
290 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
292 if (priv->config.hw_padding) {
293 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
294 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
295 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
296 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
297 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
298 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
301 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
302 wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
305 if (mlx5_rxq_mprq_enabled(rxq_data)) {
306 struct mlx5dv_striding_rq_init_attr *mprq_attr =
307 &wq_attr.mlx5.striding_rq_attrs;
309 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
310 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
311 .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
312 .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
313 .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
316 rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
319 rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
323 * Make sure number of WRs*SGEs match expectations since a queue
324 * cannot allocate more than "desc" buffers.
326 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
327 wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
329 "Port %u Rx queue %u requested %u*%u but got"
331 dev->data->port_id, idx,
332 wqe_n >> rxq_data->sges_n,
333 (1 << rxq_data->sges_n),
334 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
335 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
344 * Create the Rx queue Verbs object.
347 * Pointer to Ethernet device.
349 * Queue index in DPDK Rx queue array.
352 * 0 on success, a negative errno value otherwise and rte_errno is set.
355 mlx5_rxq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx)
357 struct mlx5_priv *priv = dev->data->dev_private;
358 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
359 struct mlx5_rxq_ctrl *rxq_ctrl =
360 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
361 struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;
362 struct mlx5dv_cq cq_info;
363 struct mlx5dv_rwq rwq;
365 struct mlx5dv_obj obj;
367 MLX5_ASSERT(rxq_data);
369 tmpl->rxq_ctrl = rxq_ctrl;
372 mlx5_glue->create_comp_channel(priv->sh->ctx);
373 if (!tmpl->ibv_channel) {
374 DRV_LOG(ERR, "Port %u: comp channel creation failure.",
379 tmpl->fd = ((struct ibv_comp_channel *)(tmpl->ibv_channel))->fd;
381 /* Create CQ using Verbs API. */
382 tmpl->ibv_cq = mlx5_rxq_ibv_cq_create(dev, idx);
384 DRV_LOG(ERR, "Port %u Rx queue %u CQ creation failure.",
385 dev->data->port_id, idx);
389 obj.cq.in = tmpl->ibv_cq;
390 obj.cq.out = &cq_info;
391 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
396 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
398 "Port %u wrong MLX5_CQE_SIZE environment "
399 "variable value: it should be set to %u.",
400 dev->data->port_id, RTE_CACHE_LINE_SIZE);
404 /* Fill the rings. */
405 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
406 rxq_data->cq_db = cq_info.dbrec;
407 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
408 rxq_data->cq_uar = cq_info.cq_uar;
409 rxq_data->cqn = cq_info.cqn;
410 /* Create WQ (RQ) using Verbs API. */
411 tmpl->wq = mlx5_rxq_ibv_wq_create(dev, idx);
413 DRV_LOG(ERR, "Port %u Rx queue %u WQ creation failure.",
414 dev->data->port_id, idx);
418 /* Change queue state to ready. */
419 ret = mlx5_ibv_modify_wq(tmpl, IBV_WQS_RDY);
422 "Port %u Rx queue %u WQ state to IBV_WQS_RDY failed.",
423 dev->data->port_id, idx);
427 obj.rwq.in = tmpl->wq;
429 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
434 rxq_data->wqes = rwq.buf;
435 rxq_data->rq_db = rwq.dbrec;
436 rxq_data->cq_arm_sn = 0;
437 mlx5_rxq_initialize(rxq_data);
439 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
440 rxq_ctrl->wqn = ((struct ibv_wq *)(tmpl->wq))->wq_num;
443 ret = rte_errno; /* Save rte_errno before cleanup. */
445 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
447 claim_zero(mlx5_glue->destroy_cq(tmpl->ibv_cq));
448 if (tmpl->ibv_channel)
449 claim_zero(mlx5_glue->destroy_comp_channel(tmpl->ibv_channel));
450 rte_errno = ret; /* Restore rte_errno. */
455 * Release an Rx verbs queue object.
458 * Verbs Rx queue object.
461 mlx5_rxq_ibv_obj_release(struct mlx5_rxq_obj *rxq_obj)
463 MLX5_ASSERT(rxq_obj);
464 MLX5_ASSERT(rxq_obj->wq);
465 MLX5_ASSERT(rxq_obj->ibv_cq);
466 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
467 claim_zero(mlx5_glue->destroy_cq(rxq_obj->ibv_cq));
468 if (rxq_obj->ibv_channel)
469 claim_zero(mlx5_glue->destroy_comp_channel
470 (rxq_obj->ibv_channel));
474 * Get event for an Rx verbs queue object.
477 * Verbs Rx queue object.
480 * 0 on success, a negative errno value otherwise and rte_errno is set.
483 mlx5_rx_ibv_get_event(struct mlx5_rxq_obj *rxq_obj)
485 struct ibv_cq *ev_cq;
487 int ret = mlx5_glue->get_cq_event(rxq_obj->ibv_channel,
490 if (ret < 0 || ev_cq != rxq_obj->ibv_cq)
492 mlx5_glue->ack_cq_events(rxq_obj->ibv_cq, 1);
503 * Creates a receive work queue as a filed of indirection table.
506 * Pointer to Ethernet device.
508 * Log of number of queues in the array.
510 * Verbs indirection table object.
513 * 0 on success, a negative errno value otherwise and rte_errno is set.
516 mlx5_ibv_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n,
517 struct mlx5_ind_table_obj *ind_tbl)
519 struct mlx5_priv *priv = dev->data->dev_private;
520 struct ibv_wq *wq[1 << log_n];
523 MLX5_ASSERT(ind_tbl);
524 for (i = 0; i != ind_tbl->queues_n; ++i) {
525 struct mlx5_rxq_data *rxq = (*priv->rxqs)[ind_tbl->queues[i]];
526 struct mlx5_rxq_ctrl *rxq_ctrl =
527 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
529 wq[i] = rxq_ctrl->obj->wq;
532 /* Finalise indirection table. */
533 for (j = 0; i != (unsigned int)(1 << log_n); ++j, ++i)
535 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table(priv->sh->ctx,
536 &(struct ibv_rwq_ind_table_init_attr){
537 .log_ind_tbl_size = log_n,
541 if (!ind_tbl->ind_table) {
549 * Destroys the specified Indirection Table.
552 * Indirection table to release.
555 mlx5_ibv_ind_table_destroy(struct mlx5_ind_table_obj *ind_tbl)
557 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
561 * Create an Rx Hash queue.
564 * Pointer to Ethernet device.
566 * Pointer to Rx Hash queue.
571 * 0 on success, a negative errno value otherwise and rte_errno is set.
574 mlx5_ibv_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
575 int tunnel __rte_unused)
577 struct mlx5_priv *priv = dev->data->dev_private;
578 struct ibv_qp *qp = NULL;
579 struct mlx5_ind_table_obj *ind_tbl = hrxq->ind_table;
580 const uint8_t *rss_key = hrxq->rss_key;
581 uint64_t hash_fields = hrxq->hash_fields;
583 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
584 struct mlx5dv_qp_init_attr qp_init_attr;
586 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
588 qp_init_attr.comp_mask =
589 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
590 qp_init_attr.create_flags = MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
592 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
593 if (dev->data->dev_conf.lpbk_mode) {
594 /* Allow packet sent from NIC loop back w/o source MAC check. */
595 qp_init_attr.comp_mask |=
596 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
597 qp_init_attr.create_flags |=
598 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
601 qp = mlx5_glue->dv_create_qp
603 &(struct ibv_qp_init_attr_ex){
604 .qp_type = IBV_QPT_RAW_PACKET,
606 IBV_QP_INIT_ATTR_PD |
607 IBV_QP_INIT_ATTR_IND_TABLE |
608 IBV_QP_INIT_ATTR_RX_HASH,
609 .rx_hash_conf = (struct ibv_rx_hash_conf){
611 IBV_RX_HASH_FUNC_TOEPLITZ,
612 .rx_hash_key_len = hrxq->rss_key_len,
614 (void *)(uintptr_t)rss_key,
615 .rx_hash_fields_mask = hash_fields,
617 .rwq_ind_tbl = ind_tbl->ind_table,
622 qp = mlx5_glue->create_qp_ex
624 &(struct ibv_qp_init_attr_ex){
625 .qp_type = IBV_QPT_RAW_PACKET,
627 IBV_QP_INIT_ATTR_PD |
628 IBV_QP_INIT_ATTR_IND_TABLE |
629 IBV_QP_INIT_ATTR_RX_HASH,
630 .rx_hash_conf = (struct ibv_rx_hash_conf){
632 IBV_RX_HASH_FUNC_TOEPLITZ,
633 .rx_hash_key_len = hrxq->rss_key_len,
635 (void *)(uintptr_t)rss_key,
636 .rx_hash_fields_mask = hash_fields,
638 .rwq_ind_tbl = ind_tbl->ind_table,
647 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
648 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
656 err = rte_errno; /* Save rte_errno before cleanup. */
658 claim_zero(mlx5_glue->destroy_qp(qp));
659 rte_errno = err; /* Restore rte_errno. */
664 * Destroy a Verbs queue pair.
667 * Hash Rx queue to release its qp.
670 mlx5_ibv_qp_destroy(struct mlx5_hrxq *hrxq)
672 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
676 * Release a drop Rx queue Verbs object.
679 * Pointer to Ethernet device.
682 mlx5_rxq_ibv_obj_drop_release(struct rte_eth_dev *dev)
684 struct mlx5_priv *priv = dev->data->dev_private;
685 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
688 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
690 claim_zero(mlx5_glue->destroy_cq(rxq->ibv_cq));
692 priv->drop_queue.rxq = NULL;
696 * Create a drop Rx queue Verbs object.
699 * Pointer to Ethernet device.
702 * 0 on success, a negative errno value otherwise and rte_errno is set.
705 mlx5_rxq_ibv_obj_drop_create(struct rte_eth_dev *dev)
707 struct mlx5_priv *priv = dev->data->dev_private;
708 struct ibv_context *ctx = priv->sh->ctx;
709 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
713 rxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq), 0, SOCKET_ID_ANY);
715 DEBUG("Port %u cannot allocate drop Rx queue memory.",
720 priv->drop_queue.rxq = rxq;
721 rxq->ibv_cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
723 DEBUG("Port %u cannot allocate CQ for drop queue.",
728 rxq->wq = mlx5_glue->create_wq(ctx, &(struct ibv_wq_init_attr){
729 .wq_type = IBV_WQT_RQ,
736 DEBUG("Port %u cannot allocate WQ for drop queue.",
741 priv->drop_queue.rxq = rxq;
744 mlx5_rxq_ibv_obj_drop_release(dev);
749 * Create a Verbs drop action for Rx Hash queue.
752 * Pointer to Ethernet device.
755 * 0 on success, a negative errno value otherwise and rte_errno is set.
758 mlx5_ibv_drop_action_create(struct rte_eth_dev *dev)
760 struct mlx5_priv *priv = dev->data->dev_private;
761 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
762 struct ibv_rwq_ind_table *ind_tbl = NULL;
763 struct mlx5_rxq_obj *rxq;
766 MLX5_ASSERT(hrxq && hrxq->ind_table);
767 ret = mlx5_rxq_ibv_obj_drop_create(dev);
770 rxq = priv->drop_queue.rxq;
771 ind_tbl = mlx5_glue->create_rwq_ind_table
773 &(struct ibv_rwq_ind_table_init_attr){
774 .log_ind_tbl_size = 0,
775 .ind_tbl = (struct ibv_wq **)&rxq->wq,
779 DEBUG("Port %u cannot allocate indirection table for drop"
780 " queue.", dev->data->port_id);
784 hrxq->qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
785 &(struct ibv_qp_init_attr_ex){
786 .qp_type = IBV_QPT_RAW_PACKET,
787 .comp_mask = IBV_QP_INIT_ATTR_PD |
788 IBV_QP_INIT_ATTR_IND_TABLE |
789 IBV_QP_INIT_ATTR_RX_HASH,
790 .rx_hash_conf = (struct ibv_rx_hash_conf){
791 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
792 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
793 .rx_hash_key = rss_hash_default_key,
794 .rx_hash_fields_mask = 0,
796 .rwq_ind_tbl = ind_tbl,
800 DEBUG("Port %u cannot allocate QP for drop queue.",
805 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
806 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
812 hrxq->ind_table->ind_table = ind_tbl;
816 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
818 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl));
819 if (priv->drop_queue.rxq)
820 mlx5_rxq_ibv_obj_drop_release(dev);
825 * Release a drop hash Rx queue.
828 * Pointer to Ethernet device.
831 mlx5_ibv_drop_action_destroy(struct rte_eth_dev *dev)
833 struct mlx5_priv *priv = dev->data->dev_private;
834 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
835 struct ibv_rwq_ind_table *ind_tbl = hrxq->ind_table->ind_table;
837 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
838 claim_zero(mlx5_glue->destroy_flow_action(hrxq->action));
840 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
841 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl));
842 mlx5_rxq_ibv_obj_drop_release(dev);
846 * Create a QP Verbs object.
849 * Pointer to Ethernet device.
851 * Queue index in DPDK Tx queue array.
854 * The QP Verbs object, NULL otherwise and rte_errno is set.
856 static struct ibv_qp *
857 mlx5_txq_ibv_qp_create(struct rte_eth_dev *dev, uint16_t idx)
859 struct mlx5_priv *priv = dev->data->dev_private;
860 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
861 struct mlx5_txq_ctrl *txq_ctrl =
862 container_of(txq_data, struct mlx5_txq_ctrl, txq);
863 struct ibv_qp *qp_obj = NULL;
864 struct ibv_qp_init_attr_ex qp_attr = { 0 };
865 const int desc = 1 << txq_data->elts_n;
867 MLX5_ASSERT(txq_ctrl->obj->cq);
868 /* CQ to be associated with the send queue. */
869 qp_attr.send_cq = txq_ctrl->obj->cq;
870 /* CQ to be associated with the receive queue. */
871 qp_attr.recv_cq = txq_ctrl->obj->cq;
872 /* Max number of outstanding WRs. */
873 qp_attr.cap.max_send_wr = ((priv->sh->device_attr.max_qp_wr < desc) ?
874 priv->sh->device_attr.max_qp_wr : desc);
876 * Max number of scatter/gather elements in a WR, must be 1 to prevent
877 * libmlx5 from trying to affect must be 1 to prevent libmlx5 from
878 * trying to affect too much memory. TX gather is not impacted by the
879 * device_attr.max_sge limit and will still work properly.
881 qp_attr.cap.max_send_sge = 1;
882 qp_attr.qp_type = IBV_QPT_RAW_PACKET,
883 /* Do *NOT* enable this, completions events are managed per Tx burst. */
884 qp_attr.sq_sig_all = 0;
885 qp_attr.pd = priv->sh->pd;
886 qp_attr.comp_mask = IBV_QP_INIT_ATTR_PD;
887 if (txq_data->inlen_send)
888 qp_attr.cap.max_inline_data = txq_ctrl->max_inline_data;
889 if (txq_data->tso_en) {
890 qp_attr.max_tso_header = txq_ctrl->max_tso_header;
891 qp_attr.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
893 qp_obj = mlx5_glue->create_qp_ex(priv->sh->ctx, &qp_attr);
894 if (qp_obj == NULL) {
895 DRV_LOG(ERR, "Port %u Tx queue %u QP creation failure.",
896 dev->data->port_id, idx);
903 * Create the Tx queue Verbs object.
906 * Pointer to Ethernet device.
908 * Queue index in DPDK Tx queue array.
911 * 0 on success, a negative errno value otherwise and rte_errno is set.
914 mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx)
916 struct mlx5_priv *priv = dev->data->dev_private;
917 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
918 struct mlx5_txq_ctrl *txq_ctrl =
919 container_of(txq_data, struct mlx5_txq_ctrl, txq);
920 struct mlx5_txq_obj *txq_obj = txq_ctrl->obj;
923 struct mlx5dv_cq cq_info;
924 struct mlx5dv_obj obj;
925 const int desc = 1 << txq_data->elts_n;
928 MLX5_ASSERT(txq_data);
929 MLX5_ASSERT(txq_obj);
930 txq_obj->txq_ctrl = txq_ctrl;
931 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
932 DRV_LOG(ERR, "Port %u MLX5_ENABLE_CQE_COMPRESSION "
933 "must never be set.", dev->data->port_id);
937 cqe_n = desc / MLX5_TX_COMP_THRESH +
938 1 + MLX5_TX_COMP_THRESH_INLINE_DIV;
939 txq_obj->cq = mlx5_glue->create_cq(priv->sh->ctx, cqe_n, NULL, NULL, 0);
940 if (txq_obj->cq == NULL) {
941 DRV_LOG(ERR, "Port %u Tx queue %u CQ creation failure.",
942 dev->data->port_id, idx);
946 txq_obj->qp = mlx5_txq_ibv_qp_create(dev, idx);
947 if (txq_obj->qp == NULL) {
951 ret = mlx5_ibv_modify_qp(txq_obj, MLX5_TXQ_MOD_RST2RDY,
952 (uint8_t)priv->dev_port);
954 DRV_LOG(ERR, "Port %u Tx queue %u QP state modifying failed.",
955 dev->data->port_id, idx);
959 qp.comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET;
960 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
961 /* If using DevX, need additional mask to read tisn value. */
962 if (priv->sh->devx && !priv->sh->tdn)
963 qp.comp_mask |= MLX5DV_QP_MASK_RAW_QP_HANDLES;
965 obj.cq.in = txq_obj->cq;
966 obj.cq.out = &cq_info;
967 obj.qp.in = txq_obj->qp;
969 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
974 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
976 "Port %u wrong MLX5_CQE_SIZE environment variable"
977 " value: it should be set to %u.",
978 dev->data->port_id, RTE_CACHE_LINE_SIZE);
982 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
983 txq_data->cqe_s = 1 << txq_data->cqe_n;
984 txq_data->cqe_m = txq_data->cqe_s - 1;
985 txq_data->qp_num_8s = ((struct ibv_qp *)txq_obj->qp)->qp_num << 8;
986 txq_data->wqes = qp.sq.buf;
987 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
988 txq_data->wqe_s = 1 << txq_data->wqe_n;
989 txq_data->wqe_m = txq_data->wqe_s - 1;
990 txq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;
991 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
992 txq_data->cq_db = cq_info.dbrec;
993 txq_data->cqes = (volatile struct mlx5_cqe *)cq_info.buf;
996 txq_data->wqe_ci = 0;
997 txq_data->wqe_pi = 0;
998 txq_data->wqe_comp = 0;
999 txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;
1000 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1002 * If using DevX need to query and store TIS transport domain value.
1003 * This is done once per port.
1004 * Will use this value on Rx, when creating matching TIR.
1006 if (priv->sh->devx && !priv->sh->tdn) {
1007 ret = mlx5_devx_cmd_qp_query_tis_td(txq_obj->qp, qp.tisn,
1010 DRV_LOG(ERR, "Fail to query port %u Tx queue %u QP TIS "
1011 "transport domain.", dev->data->port_id, idx);
1015 DRV_LOG(DEBUG, "Port %u Tx queue %u TIS number %d "
1016 "transport domain %d.", dev->data->port_id,
1017 idx, qp.tisn, priv->sh->tdn);
1021 txq_ctrl->bf_reg = qp.bf.reg;
1022 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
1023 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
1024 DRV_LOG(DEBUG, "Port %u: uar_mmap_offset 0x%" PRIx64 ".",
1025 dev->data->port_id, txq_ctrl->uar_mmap_offset);
1028 "Port %u failed to retrieve UAR info, invalid"
1030 dev->data->port_id);
1034 txq_uar_init(txq_ctrl);
1035 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
1038 ret = rte_errno; /* Save rte_errno before cleanup. */
1040 claim_zero(mlx5_glue->destroy_cq(txq_obj->cq));
1042 claim_zero(mlx5_glue->destroy_qp(txq_obj->qp));
1043 rte_errno = ret; /* Restore rte_errno. */
1048 * Release an Tx verbs queue object.
1051 * Verbs Tx queue object..
1054 mlx5_txq_ibv_obj_release(struct mlx5_txq_obj *txq_obj)
1056 MLX5_ASSERT(txq_obj);
1057 claim_zero(mlx5_glue->destroy_qp(txq_obj->qp));
1058 claim_zero(mlx5_glue->destroy_cq(txq_obj->cq));
1061 struct mlx5_obj_ops ibv_obj_ops = {
1062 .rxq_obj_modify_vlan_strip = mlx5_rxq_obj_modify_wq_vlan_strip,
1063 .rxq_obj_new = mlx5_rxq_ibv_obj_new,
1064 .rxq_event_get = mlx5_rx_ibv_get_event,
1065 .rxq_obj_modify = mlx5_ibv_modify_wq,
1066 .rxq_obj_release = mlx5_rxq_ibv_obj_release,
1067 .ind_table_new = mlx5_ibv_ind_table_new,
1068 .ind_table_destroy = mlx5_ibv_ind_table_destroy,
1069 .hrxq_new = mlx5_ibv_hrxq_new,
1070 .hrxq_destroy = mlx5_ibv_qp_destroy,
1071 .drop_action_create = mlx5_ibv_drop_action_create,
1072 .drop_action_destroy = mlx5_ibv_drop_action_destroy,
1073 .txq_obj_new = mlx5_txq_ibv_obj_new,
1074 .txq_obj_modify = mlx5_ibv_modify_qp,
1075 .txq_obj_release = mlx5_txq_ibv_obj_release,