1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Marvell International Ltd.
3 * Copyright(c) 2017 Semihalf.
7 #include <rte_ethdev_driver.h>
8 #include <rte_kvargs.h>
10 #include <rte_malloc.h>
11 #include <rte_bus_vdev.h>
13 /* Unluckily, container_of is defined by both DPDK and MUSDK,
14 * we'll declare only one version.
16 * Note that it is not used in this PMD anyway.
23 #include <linux/ethtool.h>
24 #include <linux/sockios.h>
26 #include <net/if_arp.h>
27 #include <sys/ioctl.h>
28 #include <sys/socket.h>
30 #include <sys/types.h>
32 #include "mrvl_ethdev.h"
35 /* bitmask with reserved hifs */
36 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
37 /* bitmask with reserved bpools */
38 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
39 /* bitmask with reserved kernel RSS tables */
40 #define MRVL_MUSDK_RSS_RESERVED 0x01
41 /* maximum number of available hifs */
42 #define MRVL_MUSDK_HIFS_MAX 9
45 #define MRVL_MUSDK_PREFETCH_SHIFT 2
47 /* TCAM has 25 entries reserved for uc/mc filter entries */
48 #define MRVL_MAC_ADDRS_MAX 25
49 #define MRVL_MATCH_LEN 16
50 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
51 /* Maximum allowable packet size */
52 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
54 #define MRVL_IFACE_NAME_ARG "iface"
55 #define MRVL_CFG_ARG "cfg"
57 #define MRVL_BURST_SIZE 64
59 #define MRVL_ARP_LENGTH 28
61 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
63 #define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8)
64 #define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
66 /* Memory size (in bytes) for MUSDK dma buffers */
67 #define MRVL_MUSDK_DMA_MEMSIZE 41943040
69 /** Port Rx offload capabilities */
70 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
71 DEV_RX_OFFLOAD_JUMBO_FRAME | \
72 DEV_RX_OFFLOAD_CRC_STRIP | \
73 DEV_RX_OFFLOAD_CHECKSUM)
75 /** Port Tx offloads capabilities */
76 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
77 DEV_TX_OFFLOAD_UDP_CKSUM | \
78 DEV_TX_OFFLOAD_TCP_CKSUM)
80 static const char * const valid_args[] = {
86 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
87 static struct pp2_hif *hifs[RTE_MAX_LCORE];
88 static int used_bpools[PP2_NUM_PKT_PROC] = {
89 MRVL_MUSDK_BPOOLS_RESERVED,
90 MRVL_MUSDK_BPOOLS_RESERVED
93 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
94 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
95 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
98 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
103 * To use buffer harvesting based on loopback port shadow queue structure
104 * was introduced for buffers information bookkeeping.
106 * Before sending the packet, related buffer information (pp2_buff_inf) is
107 * stored in shadow queue. After packet is transmitted no longer used
108 * packet buffer is released back to it's original hardware pool,
109 * on condition it originated from interface.
110 * In case it was generated by application itself i.e: mbuf->port field is
111 * 0xff then its released to software mempool.
113 struct mrvl_shadow_txq {
114 int head; /* write index - used when sending buffers */
115 int tail; /* read index - used when releasing buffers */
116 u16 size; /* queue occupied size */
117 u16 num_to_release; /* number of buffers sent, that can be released */
118 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
122 struct mrvl_priv *priv;
123 struct rte_mempool *mp;
132 struct mrvl_priv *priv;
136 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
137 int tx_deferred_start;
140 static int mrvl_lcore_first;
141 static int mrvl_lcore_last;
142 static int mrvl_dev_num;
144 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
145 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
146 struct pp2_hif *hif, unsigned int core_id,
147 struct mrvl_shadow_txq *sq, int qid, int force);
149 #define MRVL_XSTATS_TBL_ENTRY(name) { \
150 #name, offsetof(struct pp2_ppio_statistics, name), \
151 sizeof(((struct pp2_ppio_statistics *)0)->name) \
154 /* Table with xstats data */
159 } mrvl_xstats_tbl[] = {
160 MRVL_XSTATS_TBL_ENTRY(rx_bytes),
161 MRVL_XSTATS_TBL_ENTRY(rx_packets),
162 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
163 MRVL_XSTATS_TBL_ENTRY(rx_errors),
164 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
165 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
166 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
167 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
168 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
169 MRVL_XSTATS_TBL_ENTRY(tx_bytes),
170 MRVL_XSTATS_TBL_ENTRY(tx_packets),
171 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
172 MRVL_XSTATS_TBL_ENTRY(tx_errors)
176 mrvl_get_bpool_size(int pp2_id, int pool_id)
181 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
182 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
188 mrvl_reserve_bit(int *bitmap, int max)
190 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
201 mrvl_init_hif(int core_id)
203 struct pp2_hif_params params;
204 char match[MRVL_MATCH_LEN];
207 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
209 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
213 snprintf(match, sizeof(match), "hif-%d", ret);
214 memset(¶ms, 0, sizeof(params));
215 params.match = match;
216 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
217 ret = pp2_hif_init(¶ms, &hifs[core_id]);
219 RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", core_id);
226 static inline struct pp2_hif*
227 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
231 if (likely(hifs[core_id] != NULL))
232 return hifs[core_id];
234 rte_spinlock_lock(&priv->lock);
236 ret = mrvl_init_hif(core_id);
238 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
242 if (core_id < mrvl_lcore_first)
243 mrvl_lcore_first = core_id;
245 if (core_id > mrvl_lcore_last)
246 mrvl_lcore_last = core_id;
248 rte_spinlock_unlock(&priv->lock);
250 return hifs[core_id];
254 * Configure rss based on dpdk rss configuration.
257 * Pointer to private structure.
259 * Pointer to RSS configuration.
262 * 0 on success, negative error value otherwise.
265 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
267 if (rss_conf->rss_key)
268 RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");
270 if (rss_conf->rss_hf == 0) {
271 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
272 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
273 priv->ppio_params.inqs_params.hash_type =
274 PP2_PPIO_HASH_T_2_TUPLE;
275 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
276 priv->ppio_params.inqs_params.hash_type =
277 PP2_PPIO_HASH_T_5_TUPLE;
278 priv->rss_hf_tcp = 1;
279 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
280 priv->ppio_params.inqs_params.hash_type =
281 PP2_PPIO_HASH_T_5_TUPLE;
282 priv->rss_hf_tcp = 0;
291 * Ethernet device configuration.
293 * Prepare the driver for a given number of TX and RX queues and
297 * Pointer to Ethernet device structure.
300 * 0 on success, negative error value otherwise.
303 mrvl_dev_configure(struct rte_eth_dev *dev)
305 struct mrvl_priv *priv = dev->data->dev_private;
308 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
309 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
310 RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
311 dev->data->dev_conf.rxmode.mq_mode);
315 if (!(dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
317 "L2 CRC stripping is always enabled in hw\n");
318 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
321 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
322 RTE_LOG(INFO, PMD, "VLAN stripping not supported\n");
326 if (dev->data->dev_conf.rxmode.split_hdr_size) {
327 RTE_LOG(INFO, PMD, "Split headers not supported\n");
331 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) {
332 RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n");
336 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) {
337 RTE_LOG(INFO, PMD, "LRO not supported\n");
341 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
342 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
343 ETHER_HDR_LEN - ETHER_CRC_LEN;
345 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
346 dev->data->nb_rx_queues);
350 ret = mrvl_configure_txqs(priv, dev->data->port_id,
351 dev->data->nb_tx_queues);
355 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
356 priv->ppio_params.maintain_stats = 1;
357 priv->nb_rx_queues = dev->data->nb_rx_queues;
359 if (dev->data->nb_rx_queues == 1 &&
360 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
361 RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
362 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
367 return mrvl_configure_rss(priv,
368 &dev->data->dev_conf.rx_adv_conf.rss_conf);
372 * DPDK callback to change the MTU.
374 * Setting the MTU affects hardware MRU (packets larger than the MRU
378 * Pointer to Ethernet device structure.
383 * 0 on success, negative error value otherwise.
386 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
388 struct mrvl_priv *priv = dev->data->dev_private;
389 /* extra MV_MH_SIZE bytes are required for Marvell tag */
390 uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
393 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
399 ret = pp2_ppio_set_mru(priv->ppio, mru);
403 return pp2_ppio_set_mtu(priv->ppio, mtu);
407 * DPDK callback to bring the link up.
410 * Pointer to Ethernet device structure.
413 * 0 on success, negative error value otherwise.
416 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
418 struct mrvl_priv *priv = dev->data->dev_private;
424 ret = pp2_ppio_enable(priv->ppio);
429 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
430 * as pp2_ppio_enable() changes port->t_mode from default 0 to
431 * PP2_TRAFFIC_INGRESS_EGRESS.
433 * Set mtu to default DPDK value here.
435 ret = mrvl_mtu_set(dev, dev->data->mtu);
437 pp2_ppio_disable(priv->ppio);
443 * DPDK callback to bring the link down.
446 * Pointer to Ethernet device structure.
449 * 0 on success, negative error value otherwise.
452 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
454 struct mrvl_priv *priv = dev->data->dev_private;
459 return pp2_ppio_disable(priv->ppio);
463 * DPDK callback to start tx queue.
466 * Pointer to Ethernet device structure.
468 * Transmit queue index.
471 * 0 on success, negative error value otherwise.
474 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
476 struct mrvl_priv *priv = dev->data->dev_private;
482 /* passing 1 enables given tx queue */
483 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
485 RTE_LOG(ERR, PMD, "Failed to start txq %d\n", queue_id);
489 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
495 * DPDK callback to stop tx queue.
498 * Pointer to Ethernet device structure.
500 * Transmit queue index.
503 * 0 on success, negative error value otherwise.
506 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
508 struct mrvl_priv *priv = dev->data->dev_private;
514 /* passing 0 disables given tx queue */
515 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
517 RTE_LOG(ERR, PMD, "Failed to stop txq %d\n", queue_id);
521 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
527 * DPDK callback to start the device.
530 * Pointer to Ethernet device structure.
533 * 0 on success, negative errno value on failure.
536 mrvl_dev_start(struct rte_eth_dev *dev)
538 struct mrvl_priv *priv = dev->data->dev_private;
539 char match[MRVL_MATCH_LEN];
540 int ret = 0, i, def_init_size;
542 snprintf(match, sizeof(match), "ppio-%d:%d",
543 priv->pp_id, priv->ppio_id);
544 priv->ppio_params.match = match;
547 * Calculate the minimum bpool size for refill feature as follows:
548 * 2 default burst sizes multiply by number of rx queues.
549 * If the bpool size will be below this value, new buffers will
550 * be added to the pool.
552 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
554 /* In case initial bpool size configured in queues setup is
555 * smaller than minimum size add more buffers
557 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
558 if (priv->bpool_init_size < def_init_size) {
559 int buffs_to_add = def_init_size - priv->bpool_init_size;
561 priv->bpool_init_size += buffs_to_add;
562 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
564 RTE_LOG(ERR, PMD, "Failed to add buffers to bpool\n");
568 * Calculate the maximum bpool size for refill feature as follows:
569 * maximum number of descriptors in rx queue multiply by number
570 * of rx queues plus minimum bpool size.
571 * In case the bpool size will exceed this value, superfluous buffers
574 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
575 priv->bpool_min_size;
577 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
579 RTE_LOG(ERR, PMD, "Failed to init ppio\n");
584 * In case there are some some stale uc/mc mac addresses flush them
585 * here. It cannot be done during mrvl_dev_close() as port information
586 * is already gone at that point (due to pp2_ppio_deinit() in
589 if (!priv->uc_mc_flushed) {
590 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
593 "Failed to flush uc/mc filter list\n");
596 priv->uc_mc_flushed = 1;
599 if (!priv->vlan_flushed) {
600 ret = pp2_ppio_flush_vlan(priv->ppio);
602 RTE_LOG(ERR, PMD, "Failed to flush vlan list\n");
605 * once pp2_ppio_flush_vlan() is supported jump to out
609 priv->vlan_flushed = 1;
612 /* For default QoS config, don't start classifier. */
614 ret = mrvl_start_qos_mapping(priv);
616 RTE_LOG(ERR, PMD, "Failed to setup QoS mapping\n");
621 ret = mrvl_dev_set_link_up(dev);
623 RTE_LOG(ERR, PMD, "Failed to set link up\n");
627 /* start tx queues */
628 for (i = 0; i < dev->data->nb_tx_queues; i++) {
629 struct mrvl_txq *txq = dev->data->tx_queues[i];
631 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
633 if (!txq->tx_deferred_start)
637 * All txqs are started by default. Stop them
638 * so that tx_deferred_start works as expected.
640 ret = mrvl_tx_queue_stop(dev, i);
647 RTE_LOG(ERR, PMD, "Failed to start device\n");
648 pp2_ppio_deinit(priv->ppio);
653 * Flush receive queues.
656 * Pointer to Ethernet device structure.
659 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
663 RTE_LOG(INFO, PMD, "Flushing rx queues\n");
664 for (i = 0; i < dev->data->nb_rx_queues; i++) {
668 struct mrvl_rxq *q = dev->data->rx_queues[i];
669 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
671 num = MRVL_PP2_RXD_MAX;
672 ret = pp2_ppio_recv(q->priv->ppio,
673 q->priv->rxq_map[q->queue_id].tc,
674 q->priv->rxq_map[q->queue_id].inq,
675 descs, (uint16_t *)&num);
676 } while (ret == 0 && num);
681 * Flush transmit shadow queues.
684 * Pointer to Ethernet device structure.
687 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
690 struct mrvl_txq *txq;
692 RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
693 for (i = 0; i < dev->data->nb_tx_queues; i++) {
694 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
696 for (j = 0; j < RTE_MAX_LCORE; j++) {
697 struct mrvl_shadow_txq *sq;
702 sq = &txq->shadow_txqs[j];
703 mrvl_free_sent_buffers(txq->priv->ppio,
704 hifs[j], j, sq, txq->queue_id, 1);
705 while (sq->tail != sq->head) {
706 uint64_t addr = cookie_addr_high |
707 sq->ent[sq->tail].buff.cookie;
709 (struct rte_mbuf *)addr);
710 sq->tail = (sq->tail + 1) &
711 MRVL_PP2_TX_SHADOWQ_MASK;
713 memset(sq, 0, sizeof(*sq));
719 * Flush hardware bpool (buffer-pool).
722 * Pointer to Ethernet device structure.
725 mrvl_flush_bpool(struct rte_eth_dev *dev)
727 struct mrvl_priv *priv = dev->data->dev_private;
731 unsigned int core_id = rte_lcore_id();
733 if (core_id == LCORE_ID_ANY)
736 hif = mrvl_get_hif(priv, core_id);
738 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
740 RTE_LOG(ERR, PMD, "Failed to get bpool buffers number\n");
745 struct pp2_buff_inf inf;
748 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
752 addr = cookie_addr_high | inf.cookie;
753 rte_pktmbuf_free((struct rte_mbuf *)addr);
758 * DPDK callback to stop the device.
761 * Pointer to Ethernet device structure.
764 mrvl_dev_stop(struct rte_eth_dev *dev)
766 struct mrvl_priv *priv = dev->data->dev_private;
768 mrvl_dev_set_link_down(dev);
769 mrvl_flush_rx_queues(dev);
770 mrvl_flush_tx_shadow_queues(dev);
772 pp2_cls_tbl_deinit(priv->cls_tbl);
773 priv->cls_tbl = NULL;
776 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
777 priv->qos_tbl = NULL;
780 pp2_ppio_deinit(priv->ppio);
783 /* policer must be released after ppio deinitialization */
785 pp2_cls_plcr_deinit(priv->policer);
786 priv->policer = NULL;
791 * DPDK callback to close the device.
794 * Pointer to Ethernet device structure.
797 mrvl_dev_close(struct rte_eth_dev *dev)
799 struct mrvl_priv *priv = dev->data->dev_private;
802 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
803 struct pp2_ppio_tc_params *tc_params =
804 &priv->ppio_params.inqs_params.tcs_params[i];
806 if (tc_params->inqs_params) {
807 rte_free(tc_params->inqs_params);
808 tc_params->inqs_params = NULL;
812 mrvl_flush_bpool(dev);
816 * DPDK callback to retrieve physical link information.
819 * Pointer to Ethernet device structure.
820 * @param wait_to_complete
821 * Wait for request completion (ignored).
824 * 0 on success, negative error value otherwise.
827 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
831 * once MUSDK provides necessary API use it here
833 struct mrvl_priv *priv = dev->data->dev_private;
834 struct ethtool_cmd edata;
836 int ret, fd, link_up;
841 edata.cmd = ETHTOOL_GSET;
843 strcpy(req.ifr_name, dev->data->name);
844 req.ifr_data = (void *)&edata;
846 fd = socket(AF_INET, SOCK_DGRAM, 0);
850 ret = ioctl(fd, SIOCETHTOOL, &req);
858 switch (ethtool_cmd_speed(&edata)) {
860 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
863 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
866 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
869 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
872 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
875 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
876 ETH_LINK_HALF_DUPLEX;
877 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
879 pp2_ppio_get_link_state(priv->ppio, &link_up);
880 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
886 * DPDK callback to enable promiscuous mode.
889 * Pointer to Ethernet device structure.
892 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
894 struct mrvl_priv *priv = dev->data->dev_private;
903 ret = pp2_ppio_set_promisc(priv->ppio, 1);
905 RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
909 * DPDK callback to enable allmulti mode.
912 * Pointer to Ethernet device structure.
915 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
917 struct mrvl_priv *priv = dev->data->dev_private;
926 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
928 RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
932 * DPDK callback to disable promiscuous mode.
935 * Pointer to Ethernet device structure.
938 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
940 struct mrvl_priv *priv = dev->data->dev_private;
946 ret = pp2_ppio_set_promisc(priv->ppio, 0);
948 RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
952 * DPDK callback to disable allmulticast mode.
955 * Pointer to Ethernet device structure.
958 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
960 struct mrvl_priv *priv = dev->data->dev_private;
966 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
968 RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
972 * DPDK callback to remove a MAC address.
975 * Pointer to Ethernet device structure.
980 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
982 struct mrvl_priv *priv = dev->data->dev_private;
983 char buf[ETHER_ADDR_FMT_SIZE];
992 ret = pp2_ppio_remove_mac_addr(priv->ppio,
993 dev->data->mac_addrs[index].addr_bytes);
995 ether_format_addr(buf, sizeof(buf),
996 &dev->data->mac_addrs[index]);
997 RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
1002 * DPDK callback to add a MAC address.
1005 * Pointer to Ethernet device structure.
1007 * MAC address to register.
1009 * MAC address index.
1011 * VMDq pool index to associate address with (unused).
1014 * 0 on success, negative error value otherwise.
1017 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1018 uint32_t index, uint32_t vmdq __rte_unused)
1020 struct mrvl_priv *priv = dev->data->dev_private;
1021 char buf[ETHER_ADDR_FMT_SIZE];
1028 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
1035 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
1036 * parameter uc_filter_max. Maximum number of mc addresses is then
1037 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
1040 * If more than uc_filter_max uc addresses were added to filter list
1041 * then NIC will switch to promiscuous mode automatically.
1043 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
1044 * were added to filter list then NIC will switch to all-multicast mode
1047 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1049 ether_format_addr(buf, sizeof(buf), mac_addr);
1050 RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
1058 * DPDK callback to set the primary MAC address.
1061 * Pointer to Ethernet device structure.
1063 * MAC address to register.
1066 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
1068 struct mrvl_priv *priv = dev->data->dev_private;
1077 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1079 char buf[ETHER_ADDR_FMT_SIZE];
1080 ether_format_addr(buf, sizeof(buf), mac_addr);
1081 RTE_LOG(ERR, PMD, "Failed to set mac to %s\n", buf);
1086 * DPDK callback to get device statistics.
1089 * Pointer to Ethernet device structure.
1091 * Stats structure output buffer.
1094 * 0 on success, negative error value otherwise.
1097 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1099 struct mrvl_priv *priv = dev->data->dev_private;
1100 struct pp2_ppio_statistics ppio_stats;
1101 uint64_t drop_mac = 0;
1102 unsigned int i, idx, ret;
1107 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1108 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1109 struct pp2_ppio_inq_statistics rx_stats;
1114 idx = rxq->queue_id;
1115 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1117 "rx queue %d stats out of range (0 - %d)\n",
1118 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1122 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1123 priv->rxq_map[idx].tc,
1124 priv->rxq_map[idx].inq,
1126 if (unlikely(ret)) {
1128 "Failed to update rx queue %d stats\n", idx);
1132 stats->q_ibytes[idx] = rxq->bytes_recv;
1133 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1134 stats->q_errors[idx] = rx_stats.drop_early +
1135 rx_stats.drop_fullq +
1138 stats->ibytes += rxq->bytes_recv;
1139 drop_mac += rxq->drop_mac;
1142 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1143 struct mrvl_txq *txq = dev->data->tx_queues[i];
1144 struct pp2_ppio_outq_statistics tx_stats;
1149 idx = txq->queue_id;
1150 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1152 "tx queue %d stats out of range (0 - %d)\n",
1153 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1156 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1158 if (unlikely(ret)) {
1160 "Failed to update tx queue %d stats\n", idx);
1164 stats->q_opackets[idx] = tx_stats.deq_desc;
1165 stats->q_obytes[idx] = txq->bytes_sent;
1166 stats->obytes += txq->bytes_sent;
1169 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1170 if (unlikely(ret)) {
1171 RTE_LOG(ERR, PMD, "Failed to update port statistics\n");
1175 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1176 stats->opackets += ppio_stats.tx_packets;
1177 stats->imissed += ppio_stats.rx_fullq_dropped +
1178 ppio_stats.rx_bm_dropped +
1179 ppio_stats.rx_early_dropped +
1180 ppio_stats.rx_fifo_dropped +
1181 ppio_stats.rx_cls_dropped;
1182 stats->ierrors = drop_mac;
1188 * DPDK callback to clear device statistics.
1191 * Pointer to Ethernet device structure.
1194 mrvl_stats_reset(struct rte_eth_dev *dev)
1196 struct mrvl_priv *priv = dev->data->dev_private;
1202 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1203 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1205 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1206 priv->rxq_map[i].inq, NULL, 1);
1207 rxq->bytes_recv = 0;
1211 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1212 struct mrvl_txq *txq = dev->data->tx_queues[i];
1214 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1215 txq->bytes_sent = 0;
1218 pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1222 * DPDK callback to get extended statistics.
1225 * Pointer to Ethernet device structure.
1227 * Pointer to xstats table.
1229 * Number of entries in xstats table.
1231 * Negative value on error, number of read xstats otherwise.
1234 mrvl_xstats_get(struct rte_eth_dev *dev,
1235 struct rte_eth_xstat *stats, unsigned int n)
1237 struct mrvl_priv *priv = dev->data->dev_private;
1238 struct pp2_ppio_statistics ppio_stats;
1244 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1245 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1248 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1249 val = *(uint32_t *)((uint8_t *)&ppio_stats +
1250 mrvl_xstats_tbl[i].offset);
1251 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1252 val = *(uint64_t *)((uint8_t *)&ppio_stats +
1253 mrvl_xstats_tbl[i].offset);
1258 stats[i].value = val;
1265 * DPDK callback to reset extended statistics.
1268 * Pointer to Ethernet device structure.
1271 mrvl_xstats_reset(struct rte_eth_dev *dev)
1273 mrvl_stats_reset(dev);
1277 * DPDK callback to get extended statistics names.
1279 * @param dev (unused)
1280 * Pointer to Ethernet device structure.
1281 * @param xstats_names
1282 * Pointer to xstats names table.
1284 * Size of the xstats names table.
1286 * Number of read names.
1289 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1290 struct rte_eth_xstat_name *xstats_names,
1296 return RTE_DIM(mrvl_xstats_tbl);
1298 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1299 snprintf(xstats_names[i].name, RTE_ETH_XSTATS_NAME_SIZE, "%s",
1300 mrvl_xstats_tbl[i].name);
1306 * DPDK callback to get information about the device.
1309 * Pointer to Ethernet device structure (unused).
1311 * Info structure output buffer.
1314 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1315 struct rte_eth_dev_info *info)
1317 info->speed_capa = ETH_LINK_SPEED_10M |
1318 ETH_LINK_SPEED_100M |
1322 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1323 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1324 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1326 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1327 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1328 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1330 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1331 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1332 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1334 info->rx_offload_capa = MRVL_RX_OFFLOADS;
1335 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1337 info->tx_offload_capa = MRVL_TX_OFFLOADS;
1338 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1340 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1341 ETH_RSS_NONFRAG_IPV4_TCP |
1342 ETH_RSS_NONFRAG_IPV4_UDP;
1344 /* By default packets are dropped if no descriptors are available */
1345 info->default_rxconf.rx_drop_en = 1;
1346 info->default_rxconf.offloads = DEV_RX_OFFLOAD_CRC_STRIP;
1348 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1352 * Return supported packet types.
1355 * Pointer to Ethernet device structure (unused).
1358 * Const pointer to the table with supported packet types.
1360 static const uint32_t *
1361 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1363 static const uint32_t ptypes[] = {
1366 RTE_PTYPE_L3_IPV4_EXT,
1367 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1369 RTE_PTYPE_L3_IPV6_EXT,
1370 RTE_PTYPE_L2_ETHER_ARP,
1379 * DPDK callback to get information about specific receive queue.
1382 * Pointer to Ethernet device structure.
1383 * @param rx_queue_id
1384 * Receive queue index.
1386 * Receive queue information structure.
1388 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1389 struct rte_eth_rxq_info *qinfo)
1391 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1392 struct mrvl_priv *priv = dev->data->dev_private;
1393 int inq = priv->rxq_map[rx_queue_id].inq;
1394 int tc = priv->rxq_map[rx_queue_id].tc;
1395 struct pp2_ppio_tc_params *tc_params =
1396 &priv->ppio_params.inqs_params.tcs_params[tc];
1399 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1403 * DPDK callback to get information about specific transmit queue.
1406 * Pointer to Ethernet device structure.
1407 * @param tx_queue_id
1408 * Transmit queue index.
1410 * Transmit queue information structure.
1412 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1413 struct rte_eth_txq_info *qinfo)
1415 struct mrvl_priv *priv = dev->data->dev_private;
1416 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1419 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1420 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1424 * DPDK callback to Configure a VLAN filter.
1427 * Pointer to Ethernet device structure.
1429 * VLAN ID to filter.
1434 * 0 on success, negative error value otherwise.
1437 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1439 struct mrvl_priv *priv = dev->data->dev_private;
1447 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1448 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1452 * Release buffers to hardware bpool (buffer-pool)
1455 * Receive queue pointer.
1457 * Number of buffers to release to bpool.
1460 * 0 on success, negative error value otherwise.
1463 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1465 struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
1466 struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
1468 unsigned int core_id;
1469 struct pp2_hif *hif;
1470 struct pp2_bpool *bpool;
1472 core_id = rte_lcore_id();
1473 if (core_id == LCORE_ID_ANY)
1476 hif = mrvl_get_hif(rxq->priv, core_id);
1480 bpool = rxq->priv->bpool;
1482 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1486 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1488 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1490 for (i = 0; i < num; i++) {
1491 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1492 != cookie_addr_high) {
1494 "mbuf virtual addr high 0x%lx out of range\n",
1495 (uint64_t)mbufs[i] >> 32);
1499 entries[i].buff.addr =
1500 rte_mbuf_data_iova_default(mbufs[i]);
1501 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1502 entries[i].bpool = bpool;
1505 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1506 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1513 for (; i < num; i++)
1514 rte_pktmbuf_free(mbufs[i]);
1520 * Check whether requested rx queue offloads match port offloads.
1523 * dev Pointer to the device.
1525 * requested Bitmap of the requested offloads.
1528 * 1 if requested offloads are okay, 0 otherwise.
1531 mrvl_rx_queue_offloads_okay(struct rte_eth_dev *dev, uint64_t requested)
1533 uint64_t mandatory = dev->data->dev_conf.rxmode.offloads;
1534 uint64_t supported = MRVL_RX_OFFLOADS;
1535 uint64_t unsupported = requested & ~supported;
1536 uint64_t missing = mandatory & ~requested;
1539 RTE_LOG(ERR, PMD, "Some Rx offloads are not supported. "
1540 "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n",
1541 requested, supported);
1546 RTE_LOG(ERR, PMD, "Some Rx offloads are missing. "
1547 "Requested 0x%" PRIx64 " missing 0x%" PRIx64 ".\n",
1548 requested, missing);
1556 * DPDK callback to configure the receive queue.
1559 * Pointer to Ethernet device structure.
1563 * Number of descriptors to configure in queue.
1565 * NUMA socket on which memory must be allocated.
1567 * Thresholds parameters.
1569 * Memory pool for buffer allocations.
1572 * 0 on success, negative error value otherwise.
1575 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1576 unsigned int socket,
1577 const struct rte_eth_rxconf *conf,
1578 struct rte_mempool *mp)
1580 struct mrvl_priv *priv = dev->data->dev_private;
1581 struct mrvl_rxq *rxq;
1583 max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1586 if (!mrvl_rx_queue_offloads_okay(dev, conf->offloads))
1589 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1591 * Unknown TC mapping, mapping will not have a correct queue.
1593 RTE_LOG(ERR, PMD, "Unknown TC mapping for queue %hu eth%hhu\n",
1594 idx, priv->ppio_id);
1598 min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1599 MRVL_PKT_EFFEC_OFFS;
1600 if (min_size < max_rx_pkt_len) {
1602 "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.\n",
1603 max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1604 MRVL_PKT_EFFEC_OFFS,
1609 if (dev->data->rx_queues[idx]) {
1610 rte_free(dev->data->rx_queues[idx]);
1611 dev->data->rx_queues[idx] = NULL;
1614 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1620 rxq->cksum_enabled =
1621 dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1622 rxq->queue_id = idx;
1623 rxq->port_id = dev->data->port_id;
1624 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1626 tc = priv->rxq_map[rxq->queue_id].tc,
1627 inq = priv->rxq_map[rxq->queue_id].inq;
1628 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1631 ret = mrvl_fill_bpool(rxq, desc);
1637 priv->bpool_init_size += desc;
1639 dev->data->rx_queues[idx] = rxq;
1645 * DPDK callback to release the receive queue.
1648 * Generic receive queue pointer.
1651 mrvl_rx_queue_release(void *rxq)
1653 struct mrvl_rxq *q = rxq;
1654 struct pp2_ppio_tc_params *tc_params;
1655 int i, num, tc, inq;
1656 struct pp2_hif *hif;
1657 unsigned int core_id = rte_lcore_id();
1659 if (core_id == LCORE_ID_ANY)
1662 hif = mrvl_get_hif(q->priv, core_id);
1667 tc = q->priv->rxq_map[q->queue_id].tc;
1668 inq = q->priv->rxq_map[q->queue_id].inq;
1669 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1670 num = tc_params->inqs_params[inq].size;
1671 for (i = 0; i < num; i++) {
1672 struct pp2_buff_inf inf;
1675 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1676 addr = cookie_addr_high | inf.cookie;
1677 rte_pktmbuf_free((struct rte_mbuf *)addr);
1684 * Check whether requested tx queue offloads match port offloads.
1687 * dev Pointer to the device.
1689 * requested Bitmap of the requested offloads.
1692 * 1 if requested offloads are okay, 0 otherwise.
1695 mrvl_tx_queue_offloads_okay(struct rte_eth_dev *dev, uint64_t requested)
1697 uint64_t mandatory = dev->data->dev_conf.txmode.offloads;
1698 uint64_t supported = MRVL_TX_OFFLOADS;
1699 uint64_t unsupported = requested & ~supported;
1700 uint64_t missing = mandatory & ~requested;
1703 RTE_LOG(ERR, PMD, "Some Tx offloads are not supported. "
1704 "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n",
1705 requested, supported);
1710 RTE_LOG(ERR, PMD, "Some Tx offloads are missing. "
1711 "Requested 0x%" PRIx64 " missing 0x%" PRIx64 ".\n",
1712 requested, missing);
1720 * DPDK callback to configure the transmit queue.
1723 * Pointer to Ethernet device structure.
1725 * Transmit queue index.
1727 * Number of descriptors to configure in the queue.
1729 * NUMA socket on which memory must be allocated.
1731 * Tx queue configuration parameters.
1734 * 0 on success, negative error value otherwise.
1737 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1738 unsigned int socket,
1739 const struct rte_eth_txconf *conf)
1741 struct mrvl_priv *priv = dev->data->dev_private;
1742 struct mrvl_txq *txq;
1744 if (!mrvl_tx_queue_offloads_okay(dev, conf->offloads))
1747 if (dev->data->tx_queues[idx]) {
1748 rte_free(dev->data->tx_queues[idx]);
1749 dev->data->tx_queues[idx] = NULL;
1752 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1757 txq->queue_id = idx;
1758 txq->port_id = dev->data->port_id;
1759 txq->tx_deferred_start = conf->tx_deferred_start;
1760 dev->data->tx_queues[idx] = txq;
1762 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1768 * DPDK callback to release the transmit queue.
1771 * Generic transmit queue pointer.
1774 mrvl_tx_queue_release(void *txq)
1776 struct mrvl_txq *q = txq;
1785 * DPDK callback to get flow control configuration.
1788 * Pointer to Ethernet device structure.
1790 * Pointer to the flow control configuration.
1793 * 0 on success, negative error value otherwise.
1796 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1798 struct mrvl_priv *priv = dev->data->dev_private;
1804 ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
1806 RTE_LOG(ERR, PMD, "Failed to read rx pause state\n");
1810 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
1816 * DPDK callback to set flow control configuration.
1819 * Pointer to Ethernet device structure.
1821 * Pointer to the flow control configuration.
1824 * 0 on success, negative error value otherwise.
1827 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1829 struct mrvl_priv *priv = dev->data->dev_private;
1834 if (fc_conf->high_water ||
1835 fc_conf->low_water ||
1836 fc_conf->pause_time ||
1837 fc_conf->mac_ctrl_frame_fwd ||
1839 RTE_LOG(ERR, PMD, "Flowctrl parameter is not supported\n");
1844 if (fc_conf->mode == RTE_FC_NONE ||
1845 fc_conf->mode == RTE_FC_RX_PAUSE) {
1848 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1;
1849 ret = pp2_ppio_set_rx_pause(priv->ppio, en);
1852 "Failed to change flowctrl on RX side\n");
1861 * Update RSS hash configuration
1864 * Pointer to Ethernet device structure.
1866 * Pointer to RSS configuration.
1869 * 0 on success, negative error value otherwise.
1872 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1873 struct rte_eth_rss_conf *rss_conf)
1875 struct mrvl_priv *priv = dev->data->dev_private;
1880 return mrvl_configure_rss(priv, rss_conf);
1884 * DPDK callback to get RSS hash configuration.
1887 * Pointer to Ethernet device structure.
1889 * Pointer to RSS configuration.
1895 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1896 struct rte_eth_rss_conf *rss_conf)
1898 struct mrvl_priv *priv = dev->data->dev_private;
1899 enum pp2_ppio_hash_type hash_type =
1900 priv->ppio_params.inqs_params.hash_type;
1902 rss_conf->rss_key = NULL;
1904 if (hash_type == PP2_PPIO_HASH_T_NONE)
1905 rss_conf->rss_hf = 0;
1906 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1907 rss_conf->rss_hf = ETH_RSS_IPV4;
1908 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1909 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1910 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1911 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1917 * DPDK callback to get rte_flow callbacks.
1920 * Pointer to the device structure.
1924 * Flow filter operation.
1926 * Pointer to pass the flow ops.
1929 * 0 on success, negative error value otherwise.
1932 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
1933 enum rte_filter_type filter_type,
1934 enum rte_filter_op filter_op, void *arg)
1936 switch (filter_type) {
1937 case RTE_ETH_FILTER_GENERIC:
1938 if (filter_op != RTE_ETH_FILTER_GET)
1940 *(const void **)arg = &mrvl_flow_ops;
1943 RTE_LOG(WARNING, PMD, "Filter type (%d) not supported",
1949 static const struct eth_dev_ops mrvl_ops = {
1950 .dev_configure = mrvl_dev_configure,
1951 .dev_start = mrvl_dev_start,
1952 .dev_stop = mrvl_dev_stop,
1953 .dev_set_link_up = mrvl_dev_set_link_up,
1954 .dev_set_link_down = mrvl_dev_set_link_down,
1955 .dev_close = mrvl_dev_close,
1956 .link_update = mrvl_link_update,
1957 .promiscuous_enable = mrvl_promiscuous_enable,
1958 .allmulticast_enable = mrvl_allmulticast_enable,
1959 .promiscuous_disable = mrvl_promiscuous_disable,
1960 .allmulticast_disable = mrvl_allmulticast_disable,
1961 .mac_addr_remove = mrvl_mac_addr_remove,
1962 .mac_addr_add = mrvl_mac_addr_add,
1963 .mac_addr_set = mrvl_mac_addr_set,
1964 .mtu_set = mrvl_mtu_set,
1965 .stats_get = mrvl_stats_get,
1966 .stats_reset = mrvl_stats_reset,
1967 .xstats_get = mrvl_xstats_get,
1968 .xstats_reset = mrvl_xstats_reset,
1969 .xstats_get_names = mrvl_xstats_get_names,
1970 .dev_infos_get = mrvl_dev_infos_get,
1971 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1972 .rxq_info_get = mrvl_rxq_info_get,
1973 .txq_info_get = mrvl_txq_info_get,
1974 .vlan_filter_set = mrvl_vlan_filter_set,
1975 .tx_queue_start = mrvl_tx_queue_start,
1976 .tx_queue_stop = mrvl_tx_queue_stop,
1977 .rx_queue_setup = mrvl_rx_queue_setup,
1978 .rx_queue_release = mrvl_rx_queue_release,
1979 .tx_queue_setup = mrvl_tx_queue_setup,
1980 .tx_queue_release = mrvl_tx_queue_release,
1981 .flow_ctrl_get = mrvl_flow_ctrl_get,
1982 .flow_ctrl_set = mrvl_flow_ctrl_set,
1983 .rss_hash_update = mrvl_rss_hash_update,
1984 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1985 .filter_ctrl = mrvl_eth_filter_ctrl,
1989 * Return packet type information and l3/l4 offsets.
1992 * Pointer to the received packet descriptor.
1999 * Packet type information.
2001 static inline uint64_t
2002 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
2003 uint8_t *l3_offset, uint8_t *l4_offset)
2005 enum pp2_inq_l3_type l3_type;
2006 enum pp2_inq_l4_type l4_type;
2007 uint64_t packet_type;
2009 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
2010 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
2012 packet_type = RTE_PTYPE_L2_ETHER;
2015 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
2016 packet_type |= RTE_PTYPE_L3_IPV4;
2018 case PP2_INQ_L3_TYPE_IPV4_OK:
2019 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
2021 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
2022 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
2024 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
2025 packet_type |= RTE_PTYPE_L3_IPV6;
2027 case PP2_INQ_L3_TYPE_IPV6_EXT:
2028 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
2030 case PP2_INQ_L3_TYPE_ARP:
2031 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
2033 * In case of ARP l4_offset is set to wrong value.
2034 * Set it to proper one so that later on mbuf->l3_len can be
2035 * calculated subtracting l4_offset and l3_offset.
2037 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
2040 RTE_LOG(DEBUG, PMD, "Failed to recognise l3 packet type\n");
2045 case PP2_INQ_L4_TYPE_TCP:
2046 packet_type |= RTE_PTYPE_L4_TCP;
2048 case PP2_INQ_L4_TYPE_UDP:
2049 packet_type |= RTE_PTYPE_L4_UDP;
2052 RTE_LOG(DEBUG, PMD, "Failed to recognise l4 packet type\n");
2060 * Get offload information from the received packet descriptor.
2063 * Pointer to the received packet descriptor.
2066 * Mbuf offload flags.
2068 static inline uint64_t
2069 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
2072 enum pp2_inq_desc_status status;
2074 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
2075 if (unlikely(status != PP2_DESC_ERR_OK))
2076 flags = PKT_RX_IP_CKSUM_BAD;
2078 flags = PKT_RX_IP_CKSUM_GOOD;
2080 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
2081 if (unlikely(status != PP2_DESC_ERR_OK))
2082 flags |= PKT_RX_L4_CKSUM_BAD;
2084 flags |= PKT_RX_L4_CKSUM_GOOD;
2090 * DPDK callback for receive.
2093 * Generic pointer to the receive queue.
2095 * Array to store received packets.
2097 * Maximum number of packets in array.
2100 * Number of packets successfully received.
2103 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2105 struct mrvl_rxq *q = rxq;
2106 struct pp2_ppio_desc descs[nb_pkts];
2107 struct pp2_bpool *bpool;
2108 int i, ret, rx_done = 0;
2110 struct pp2_hif *hif;
2111 unsigned int core_id = rte_lcore_id();
2113 hif = mrvl_get_hif(q->priv, core_id);
2115 if (unlikely(!q->priv->ppio || !hif))
2118 bpool = q->priv->bpool;
2120 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2121 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2122 if (unlikely(ret < 0)) {
2123 RTE_LOG(ERR, PMD, "Failed to receive packets\n");
2126 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2128 for (i = 0; i < nb_pkts; i++) {
2129 struct rte_mbuf *mbuf;
2130 uint8_t l3_offset, l4_offset;
2131 enum pp2_inq_desc_status status;
2134 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2135 struct pp2_ppio_desc *pref_desc;
2138 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2139 pref_addr = cookie_addr_high |
2140 pp2_ppio_inq_desc_get_cookie(pref_desc);
2141 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2142 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2145 addr = cookie_addr_high |
2146 pp2_ppio_inq_desc_get_cookie(&descs[i]);
2147 mbuf = (struct rte_mbuf *)addr;
2148 rte_pktmbuf_reset(mbuf);
2150 /* drop packet in case of mac, overrun or resource error */
2151 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2152 if (unlikely(status != PP2_DESC_ERR_OK)) {
2153 struct pp2_buff_inf binf = {
2154 .addr = rte_mbuf_data_iova_default(mbuf),
2155 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
2158 pp2_bpool_put_buff(hif, bpool, &binf);
2159 mrvl_port_bpool_size
2160 [bpool->pp2_id][bpool->id][core_id]++;
2165 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2166 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2167 mbuf->data_len = mbuf->pkt_len;
2168 mbuf->port = q->port_id;
2170 mrvl_desc_to_packet_type_and_offset(&descs[i],
2173 mbuf->l2_len = l3_offset;
2174 mbuf->l3_len = l4_offset - l3_offset;
2176 if (likely(q->cksum_enabled))
2177 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
2179 rx_pkts[rx_done++] = mbuf;
2180 q->bytes_recv += mbuf->pkt_len;
2183 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2184 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2186 if (unlikely(num <= q->priv->bpool_min_size ||
2187 (!rx_done && num < q->priv->bpool_init_size))) {
2188 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
2190 RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
2191 } else if (unlikely(num > q->priv->bpool_max_size)) {
2193 int pkt_to_remove = num - q->priv->bpool_init_size;
2194 struct rte_mbuf *mbuf;
2195 struct pp2_buff_inf buff;
2198 "\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
2199 bpool->pp2_id, q->priv->ppio->port_id,
2200 bpool->id, pkt_to_remove, num,
2201 q->priv->bpool_init_size);
2203 for (i = 0; i < pkt_to_remove; i++) {
2204 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2207 mbuf = (struct rte_mbuf *)
2208 (cookie_addr_high | buff.cookie);
2209 rte_pktmbuf_free(mbuf);
2211 mrvl_port_bpool_size
2212 [bpool->pp2_id][bpool->id][core_id] -= i;
2214 rte_spinlock_unlock(&q->priv->lock);
2221 * Prepare offload information.
2225 * @param packet_type
2226 * Packet type bitfield.
2228 * Pointer to the pp2_ouq_l3_type structure.
2230 * Pointer to the pp2_outq_l4_type structure.
2231 * @param gen_l3_cksum
2232 * Will be set to 1 in case l3 checksum is computed.
2234 * Will be set to 1 in case l4 checksum is computed.
2237 * 0 on success, negative error value otherwise.
2240 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
2241 enum pp2_outq_l3_type *l3_type,
2242 enum pp2_outq_l4_type *l4_type,
2247 * Based on ol_flags prepare information
2248 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
2251 if (ol_flags & PKT_TX_IPV4) {
2252 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2253 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
2254 } else if (ol_flags & PKT_TX_IPV6) {
2255 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2256 /* no checksum for ipv6 header */
2259 /* if something different then stop processing */
2263 ol_flags &= PKT_TX_L4_MASK;
2264 if ((packet_type & RTE_PTYPE_L4_TCP) &&
2265 ol_flags == PKT_TX_TCP_CKSUM) {
2266 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2268 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
2269 ol_flags == PKT_TX_UDP_CKSUM) {
2270 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2273 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2274 /* no checksum for other type */
2282 * Release already sent buffers to bpool (buffer-pool).
2285 * Pointer to the port structure.
2287 * Pointer to the MUSDK hardware interface.
2289 * Pointer to the shadow queue.
2293 * Force releasing packets.
2296 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2297 unsigned int core_id, struct mrvl_shadow_txq *sq,
2300 struct buff_release_entry *entry;
2301 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2304 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2306 sq->num_to_release += nb_done;
2308 if (likely(!force &&
2309 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2312 nb_done = sq->num_to_release;
2313 sq->num_to_release = 0;
2315 for (i = 0; i < nb_done; i++) {
2316 entry = &sq->ent[sq->tail + num];
2317 if (unlikely(!entry->buff.addr)) {
2319 "Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
2320 sq->tail, (u64)entry->buff.cookie,
2321 (u64)entry->buff.addr);
2326 if (unlikely(!entry->bpool)) {
2327 struct rte_mbuf *mbuf;
2329 mbuf = (struct rte_mbuf *)
2330 (cookie_addr_high | entry->buff.cookie);
2331 rte_pktmbuf_free(mbuf);
2336 mrvl_port_bpool_size
2337 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2339 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2344 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2346 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2353 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2354 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2360 * DPDK callback for transmit.
2363 * Generic pointer transmit queue.
2365 * Packets to transmit.
2367 * Number of packets in array.
2370 * Number of packets successfully transmitted.
2373 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2375 struct mrvl_txq *q = txq;
2376 struct mrvl_shadow_txq *sq;
2377 struct pp2_hif *hif;
2378 struct pp2_ppio_desc descs[nb_pkts];
2379 unsigned int core_id = rte_lcore_id();
2380 int i, ret, bytes_sent = 0;
2381 uint16_t num, sq_free_size;
2384 hif = mrvl_get_hif(q->priv, core_id);
2385 sq = &q->shadow_txqs[core_id];
2387 if (unlikely(!q->priv->ppio || !hif))
2391 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2392 sq, q->queue_id, 0);
2394 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2395 if (unlikely(nb_pkts > sq_free_size)) {
2397 "No room in shadow queue for %d packets! %d packets will be sent.\n",
2398 nb_pkts, sq_free_size);
2399 nb_pkts = sq_free_size;
2402 for (i = 0; i < nb_pkts; i++) {
2403 struct rte_mbuf *mbuf = tx_pkts[i];
2404 int gen_l3_cksum, gen_l4_cksum;
2405 enum pp2_outq_l3_type l3_type;
2406 enum pp2_outq_l4_type l4_type;
2408 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2409 struct rte_mbuf *pref_pkt_hdr;
2411 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2412 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2413 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2416 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
2417 sq->ent[sq->head].buff.addr =
2418 rte_mbuf_data_iova_default(mbuf);
2419 sq->ent[sq->head].bpool =
2420 (unlikely(mbuf->port >= RTE_MAX_ETHPORTS ||
2421 mbuf->refcnt > 1)) ? NULL :
2422 mrvl_port_to_bpool_lookup[mbuf->port];
2423 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
2426 pp2_ppio_outq_desc_reset(&descs[i]);
2427 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
2428 rte_pktmbuf_iova(mbuf));
2429 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
2430 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
2431 rte_pktmbuf_pkt_len(mbuf));
2433 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2435 * in case unsupported ol_flags were passed
2436 * do not update descriptor offload information
2438 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2439 &l3_type, &l4_type, &gen_l3_cksum,
2444 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2446 mbuf->l2_len + mbuf->l3_len,
2447 gen_l3_cksum, gen_l4_cksum);
2451 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2452 /* number of packets that were not sent */
2453 if (unlikely(num > nb_pkts)) {
2454 for (i = nb_pkts; i < num; i++) {
2455 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2456 MRVL_PP2_TX_SHADOWQ_MASK;
2457 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2459 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2461 sq->size -= num - nb_pkts;
2464 q->bytes_sent += bytes_sent;
2470 * Initialize packet processor.
2473 * 0 on success, negative error value otherwise.
2478 struct pp2_init_params init_params;
2480 memset(&init_params, 0, sizeof(init_params));
2481 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2482 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2483 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2485 return pp2_init(&init_params);
2489 * Deinitialize packet processor.
2492 * 0 on success, negative error value otherwise.
2495 mrvl_deinit_pp2(void)
2501 * Create private device structure.
2504 * Pointer to the port name passed in the initialization parameters.
2507 * Pointer to the newly allocated private device structure.
2509 static struct mrvl_priv *
2510 mrvl_priv_create(const char *dev_name)
2512 struct pp2_bpool_params bpool_params;
2513 char match[MRVL_MATCH_LEN];
2514 struct mrvl_priv *priv;
2517 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2521 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2522 &priv->pp_id, &priv->ppio_id);
2526 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2527 PP2_BPOOL_NUM_POOLS);
2530 priv->bpool_bit = bpool_bit;
2532 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2534 memset(&bpool_params, 0, sizeof(bpool_params));
2535 bpool_params.match = match;
2536 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2537 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2539 goto out_clear_bpool_bit;
2541 priv->ppio_params.type = PP2_PPIO_T_NIC;
2542 rte_spinlock_init(&priv->lock);
2545 out_clear_bpool_bit:
2546 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2553 * Create device representing Ethernet port.
2556 * Pointer to the port's name.
2559 * 0 on success, negative error value otherwise.
2562 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2564 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2565 struct rte_eth_dev *eth_dev;
2566 struct mrvl_priv *priv;
2569 eth_dev = rte_eth_dev_allocate(name);
2573 priv = mrvl_priv_create(name);
2579 eth_dev->data->mac_addrs =
2580 rte_zmalloc("mac_addrs",
2581 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2582 if (!eth_dev->data->mac_addrs) {
2583 RTE_LOG(ERR, PMD, "Failed to allocate space for eth addrs\n");
2588 memset(&req, 0, sizeof(req));
2589 strcpy(req.ifr_name, name);
2590 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2594 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2595 req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2597 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2598 eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2599 eth_dev->data->kdrv = RTE_KDRV_NONE;
2600 eth_dev->data->dev_private = priv;
2601 eth_dev->device = &vdev->device;
2602 eth_dev->dev_ops = &mrvl_ops;
2606 rte_free(eth_dev->data->mac_addrs);
2608 rte_eth_dev_release_port(eth_dev);
2616 * Cleanup previously created device representing Ethernet port.
2619 * Pointer to the port name.
2622 mrvl_eth_dev_destroy(const char *name)
2624 struct rte_eth_dev *eth_dev;
2625 struct mrvl_priv *priv;
2627 eth_dev = rte_eth_dev_allocated(name);
2631 priv = eth_dev->data->dev_private;
2632 pp2_bpool_deinit(priv->bpool);
2633 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2635 rte_free(eth_dev->data->mac_addrs);
2636 rte_eth_dev_release_port(eth_dev);
2640 * Callback used by rte_kvargs_process() during argument parsing.
2643 * Pointer to the parsed key (unused).
2645 * Pointer to the parsed value.
2647 * Pointer to the extra arguments which contains address of the
2648 * table of pointers to parsed interface names.
2654 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2657 struct mrvl_ifnames *ifnames = extra_args;
2659 ifnames->names[ifnames->idx++] = value;
2665 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2668 mrvl_deinit_hifs(void)
2672 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2674 pp2_hif_deinit(hifs[i]);
2676 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2677 memset(hifs, 0, sizeof(hifs));
2681 * DPDK callback to register the virtual device.
2684 * Pointer to the virtual device.
2687 * 0 on success, negative error value otherwise.
2690 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2692 struct rte_kvargs *kvlist;
2693 struct mrvl_ifnames ifnames;
2695 uint32_t i, ifnum, cfgnum;
2698 params = rte_vdev_device_args(vdev);
2702 kvlist = rte_kvargs_parse(params, valid_args);
2706 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2707 if (ifnum > RTE_DIM(ifnames.names))
2708 goto out_free_kvlist;
2711 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2712 mrvl_get_ifnames, &ifnames);
2716 * The below system initialization should be done only once,
2717 * on the first provided configuration file
2719 if (!mrvl_qos_cfg) {
2720 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2721 RTE_LOG(INFO, PMD, "Parsing config file!\n");
2723 RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n");
2724 goto out_free_kvlist;
2725 } else if (cfgnum == 1) {
2726 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2727 mrvl_get_qoscfg, &mrvl_qos_cfg);
2734 RTE_LOG(INFO, PMD, "Perform MUSDK initializations\n");
2736 * ret == -EEXIST is correct, it means DMA
2737 * has been already initialized (by another PMD).
2739 ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
2742 goto out_free_kvlist;
2745 "DMA memory has been already initialized by a different driver.\n");
2748 ret = mrvl_init_pp2();
2750 RTE_LOG(ERR, PMD, "Failed to init PP!\n");
2751 goto out_deinit_dma;
2754 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2755 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
2757 mrvl_lcore_first = RTE_MAX_LCORE;
2758 mrvl_lcore_last = 0;
2761 for (i = 0; i < ifnum; i++) {
2762 RTE_LOG(INFO, PMD, "Creating %s\n", ifnames.names[i]);
2763 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2767 mrvl_dev_num += ifnum;
2769 rte_kvargs_free(kvlist);
2774 mrvl_eth_dev_destroy(ifnames.names[i]);
2776 if (mrvl_dev_num == 0)
2779 if (mrvl_dev_num == 0)
2780 mv_sys_dma_mem_destroy();
2782 rte_kvargs_free(kvlist);
2788 * DPDK callback to remove virtual device.
2791 * Pointer to the removed virtual device.
2794 * 0 on success, negative error value otherwise.
2797 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2802 name = rte_vdev_device_name(vdev);
2806 RTE_LOG(INFO, PMD, "Removing %s\n", name);
2808 for (i = 0; i < rte_eth_dev_count(); i++) {
2809 char ifname[RTE_ETH_NAME_MAX_LEN];
2811 rte_eth_dev_get_name_by_port(i, ifname);
2812 mrvl_eth_dev_destroy(ifname);
2816 if (mrvl_dev_num == 0) {
2817 RTE_LOG(INFO, PMD, "Perform MUSDK deinit\n");
2820 mv_sys_dma_mem_destroy();
2826 static struct rte_vdev_driver pmd_mrvl_drv = {
2827 .probe = rte_pmd_mrvl_probe,
2828 .remove = rte_pmd_mrvl_remove,
2831 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
2832 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);